WO2013020471A1 - Transistor bipolaire à jonction et procédé de fabrication d'une structure hybride bipolaire et semi-conducteur complémentaire à l'oxyde de métal - Google Patents

Transistor bipolaire à jonction et procédé de fabrication d'une structure hybride bipolaire et semi-conducteur complémentaire à l'oxyde de métal Download PDF

Info

Publication number
WO2013020471A1
WO2013020471A1 PCT/CN2012/079457 CN2012079457W WO2013020471A1 WO 2013020471 A1 WO2013020471 A1 WO 2013020471A1 CN 2012079457 W CN2012079457 W CN 2012079457W WO 2013020471 A1 WO2013020471 A1 WO 2013020471A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
region
type
fabricating
junction transistor
Prior art date
Application number
PCT/CN2012/079457
Other languages
English (en)
Chinese (zh)
Inventor
青云
胡金节
李月影
胡勇海
Original Assignee
无锡华润上华半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润上华半导体有限公司 filed Critical 无锡华润上华半导体有限公司
Publication of WO2013020471A1 publication Critical patent/WO2013020471A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

Definitions

  • the present invention relates to a method for fabricating a bipolar junction transistor and a bipolar-complementary metal oxide semiconductor hybrid structure, and more particularly to a bipolar junction transistor having a polysilicon emitter and a bipolar-complementary metal oxide semiconductor hybrid structure Production method.
  • BiCMOS Bipolar-complementary metal oxide semiconductor hybrid structure
  • CMOS complementary metal-oxide semiconductor
  • Bipolar Junction Transistor (Bipolar Junction Transistor; The emitter region of BJT) is formed by diffusion annealing after implanting impurities in a specific region of single crystal silicon by a photolithographic plate. Usually, this process is realized simultaneously with the implantation of the source and the drain of the CMOS transistor.
  • the current process for fabricating a polysilicon emitter transistor is to first etch the window of the emitter region by dry etching, and then clean it with a mixed solution of NH 3 : H 2 O 2 :H 2 O, followed by low temperature chemical vapor deposition of polysilicon, and then Impurities are implanted thereon and annealed to form an emitter junction.
  • the disadvantages of this approach are:
  • the emitter junction formed by the implantation of the source and the drain of the CMOS tube and the annealing thereof has a relatively large junction depth and a high surface concentration
  • the emitter junction formed by the implantation of the source and drain of the CMOS transistor and its annealing is easily limited when adjusting the device parameters, and also affects the CMOS device;
  • an object of the present invention is to provide a BJT fabrication method capable of obtaining a shallower emitter junction and achieving a higher concentration of silicon surface in the emitter region.
  • Another object of the present invention is to provide a In the BiCMOS process, the BJT emitter can be fabricated separately from the source and drain of the CMOS.
  • a BJT production method includes the steps of:
  • the bipolar junction transistor is an NPN transistor
  • the semiconductor substrate is a P-type substrate.
  • the method includes:
  • Step (1) implanting N-type ions on the P-type substrate to form an N-type buried layer, and forming an N-type epitaxial layer on the N-type buried layer;
  • the first ion is an N-type ion
  • the sinking region is an N-type sinking region
  • the second ion is a P-type ion
  • the base region is a P-type base region
  • the N is The sinking zone is connected with the N-type buried layer to form a collector region.
  • the P-type substrate is one of silicon, germanium, germanium silicon compound or organic compound semiconductor material.
  • the N-type ion is a strontium ion
  • the cesium ion implantation dose is 1 ⁇ 10 15 /cm 2
  • the implantation energy is 40KeV.
  • the N-type epitaxial layer has a thickness of 1 to 1.5 ⁇ m and a resistivity of 2.0 ⁇ •cm.
  • the isolation region has a trench depth of 0.4 to 0.8 ⁇ m.
  • the bipolar junction transistor is a PNP transistor
  • the semiconductor substrate is an N-type substrate.
  • the method includes:
  • step (1) P-type ions are implanted on the N-type substrate to form a P-type buried layer, and a P-type epitaxial layer is formed on the P-type buried layer;
  • the first ion is a P-type ion
  • the sinking region is a P-type sinking region
  • the second ion is an N-type ion
  • the base region is an N-type base region
  • the P-type sinking region is connected with the P-type buried layer to form a collector region.
  • the silicon oxide layer has a thickness of 100 to 150 angstroms.
  • the silicon oxide layer is fabricated by a thermal oxidation process or a chemical vapor deposition process.
  • the anti-corrosion layer is one of Alpha-type polysilicon, silicon nitride or tetraethyl orthosilicate.
  • the anti-corrosion layer is an Alpha-type polysilicon layer
  • the Alpha-type polysilicon layer has a thickness of 750 to 850 angstroms.
  • the anti-corrosion layer is an Alpha-type polysilicon layer
  • the Alpha-type polysilicon layer is fabricated by one of low pressure chemical vapor deposition or atmospheric pressure chemical vapor deposition.
  • the Alpha type polycrystalline silicon is deposited at a temperature of 500 ° C to 550 ° C.
  • the silicon oxide layer in the emission region window has a thickness of 60 to 100 angstroms.
  • the polysilicon layer in the step (6) is fabricated by a chemical vapor deposition process.
  • a method of fabricating a bipolar-complementary metal oxide semiconductor hybrid structure comprising fabricating a bipolar junction transistor portion on a substrate and fabricating a complementary metal oxide semiconductor portion, wherein the bipolar
  • the junction transistor is fabricated by the method described above.
  • the BJT obtained by the above method has a two-step etching method, the first step of dry etching, using silicon dioxide as a retention layer, and does not cause damage to the surface of the single crystal silicon;
  • the etching method uses Alpha-type polysilicon as a barrier layer, which reduces the lateral corrosion amount of the silicon dioxide layer in the wet etching, and obtains a relatively good window morphology. Therefore, when the emitter region is implanted and diffused by polysilicon, a better surface concentration can be obtained, and the small current degradation of the BJT is improved.
  • the ion implantation and annealing processes of the BJT emitter region can be performed separately, independent of the ionic source and drain ion implantation and annealing processes, which greatly improves the design flexibility of the device.
  • FIG. 1 is a general flow chart of a BJT fabrication method of the present invention.
  • FIGS. 2A to 2F are schematic cross-sectional views corresponding to the process of the BJT manufacturing method in the embodiment of the present invention.
  • FIG. 3 is a flow chart showing the fabrication of a BJT emitter region in a BiCMOS process in accordance with an embodiment of the present invention.
  • the present invention proposes a method for fabricating a BJT, which enables the BJT to form a relatively good window shape when forming an emitter.
  • the BJT fabrication method proposed by the present invention can be used, and the ion implantation and annealing processes are separately performed from the ion implantation and annealing processes of the CMOS source and drain when the emitter is fabricated, thereby improving BJT and CMOS. Design flexibility.
  • FIG. 1 is a flow chart of a BJT manufacturing method of the present invention. As shown, the method of making a BJT includes the steps of:
  • S11 providing a semiconductor substrate, performing ion implantation on the semiconductor substrate to form a buried region, and forming an epitaxial layer on the buried region.
  • S12 forming an active region and an isolation region on the epitaxial layer by using a shallow trench isolation process (STI), and performing first ion implantation and second ion implantation on a portion of the active regions to inject an active region of the first ion Forming a sinking region, the active region implanting the second ions forms a base region, wherein the sinking region is connected to the buried region and forms a collector region together with the sinking region;
  • STI shallow trench isolation process
  • S14 exposing and etching the emitter window on the photoresist layer above the base region by using a mask. Then, the photoresist layer is used as a mask, the silicon oxide layer is used as a retention layer, and the anti-corrosion layer is dry-etched to form an emission region window on the anti-corrosion layer.
  • S16 depositing a polysilicon layer on the surface of the anti-corrosion layer and the surface of the epitaxial layer exposed in the window of the emissive region, performing ion implantation and diffusion annealing on the polysilicon layer, and performing a stripping process to remove the polysilicon layer outside the emitter region, The anti-corrosion layer and the silicon oxide layer are etched away and eventually form an emitter.
  • the manufacturing method mentioned in the present invention will be specifically described below in a specific embodiment. It should be noted that since the main key point of the present invention is the formation process of the emitter region, in order to more clearly express the gist of the invention, some of the previous process levels associated therewith are briefly described herein. There are many specific processes at these levels, and here is an example of a process commonly used in the industry. In addition, since the tubes of the BJT have two kinds of NPN and PNP, the following process characteristics are required. We only use the NPN tube as an example, and the PNP type BJT tube can be obtained according to the method of the present invention.
  • FIGS. 2A to 2F are schematic cross-sectional views showing a process of a BJT manufacturing method according to an embodiment of the present invention, and the same reference numerals are used to refer to the same parts throughout the drawings; however, for convenience of explanation, the cross-sectional view showing the structure of the device is not practical.
  • the scale is proportionally scaled locally. The emphasis is on the gist of the invention. In addition, the actual three-dimensional dimensions of length, width and depth should be included in the actual production. A process for improving BJT degradation of the present invention will now be described with reference to Figs. 2A to 2F.
  • a P-type substrate 100 is provided, which may be made of one of silicon, germanium or germanium silicon compounds, and an organic compound semiconductor material.
  • a silicon material is used as the p-type substrate 100. Crystal orientation of the substrate 100 ⁇ 100> The resistivity is 15 ⁇ 25 ohm•cm.
  • the substrate 100 is subjected to an ion implantation process, and the implanted ions are N-type ions, and the N buried region 101 is formed.
  • the ion implantation process specifically includes: forming a silicon oxide layer on the substrate 100, forming a silicon nitride layer on the silicon oxide layer, and spin-coating the photoresist layer on the silicon nitride layer.
  • the photoresist layer is exposed and etched using a mask to form a buried window pattern on the photoresist layer.
  • the buried window pattern is transferred onto the silicon nitride layer and the silicon oxide layer, and the substrate 100 is exposed under the buried window.
  • the portion of the substrate 100 exposed to the buried layer is subjected to N ion implantation, and the implanted N-type ions are erbium ions, and the dose of the implanted ions is 1 ⁇ 10 15 /cm 2 and the energy is about 40 KeV.
  • the photoresist layer, the silicon nitride layer, and the silicon oxide layer are removed.
  • the coating process and the removal process of the above-mentioned photoresist layer, silicon nitride layer and silicon oxide layer are all commonly used in the industry, and will not be described here.
  • an N-type epitaxial layer 102 is formed on the N buried region 101 by epitaxial growth, and the N-type epitaxial layer 102 has a thickness of about 1.3 ⁇ m and a resistivity of 2.0 ohm•cm.
  • the active region 110 and the isolation region 120 are then formed on the epitaxial layer 102 using shallow trench isolation (STI), wherein the isolation region 120 has a groove depth of about 0.6 um.
  • STI shallow trench isolation
  • N-type ion implantation and P-type ion implantation are respectively performed on a portion of the active region 110 in the N-type epitaxial layer 102, and an active region of the N-type ions is implanted to form an N sinking region (SINK) 111.
  • the active region implanted with P-type ions forms a P-base region 112.
  • the NSINK region 111 is in communication with the N buried region 101 to form a collector region of the BJT.
  • the implantation process of N ions and P ions is the same as the ion implantation process described above, including at least one photolithography process and corresponding layering and de-layering processes, and thus will not be described again.
  • a 250 angstrom layer of silicon dioxide layer 130 is formed over the N-type epitaxial layer 102, and then an anti-corrosion layer of about 800 angstroms is grown by chemical vapor deposition.
  • the anti-corrosion layer is specifically Alpha-type polysilicon 140. It is worth noting that when the BJT fabrication method of the present invention is used in a BiCMOS process, the two layer films are also used for the formation of a CMOS gate, so the specific thickness parameters and process conditions need to be determined according to CMOS, and not Limited to the numerical range above.
  • the emitter window 150 is formed by dry etching.
  • the method for forming the silicon dioxide layer 130 is a conventional thermal oxidation process or a chemical vapor deposition process.
  • a thermal oxidation process is preferably used.
  • the specific process can refer to the existing thermal oxidation process formation method, and is no longer here. Narration.
  • the method for specifically forming the Alpha-type polysilicon 140 is a chemical vapor deposition method, and the chemical vapor deposition method may be one of low pressure chemical vapor deposition (LPCVD) and atmospheric pressure chemical vapor deposition (APCVD), and it is particularly pointed out that when When the deposition temperature of the Alpha-type polysilicon 140 layer is performed at 500 ° C - 550 ° C, the formed Alpha-type polycrystalline silicon has a small lattice feature, and can better shield the hydrofluoric acid solution for the subsequent wet etching process. The effect is to ensure the quality of the shape of the silicon dioxide layer 130 layer which is corroded.
  • LPCVD low pressure chemical vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • the anti-corrosion layer can also be replaced with a higher quality film, such as silicon nitride, Tetraethyl orthosilicate (TEOS) and the like.
  • TEOS Tetraethyl orthosilicate
  • the thickness thereof should not be thin. If it is too thin, the subsequent hydrofluoric acid solution may penetrate the oxide layer under the barrier layer.
  • the step of specifically forming the region of the emitter region window 150 includes: spin-coating a photoresist layer (not shown) on the Alpha-type polysilicon 140 layer, and defining an emitter region on the Alpha-type polysilicon 140 after the exposure and development process using the mask.
  • the pattern of the window 150 using the photoresist layer as a mask, patterning the pattern to the Alpha-type polysilicon 140 along the emitter window 150, etching the emitter window 150 by dry etching, and the gas menu for the specific dry etching It is defined according to the film thickness of the actual Alpha-type polysilicon 140, but the amount of over-etching (OE) thereof cannot be too large, and it must stay on the silicon dioxide layer 130 under the Alpha-type polysilicon 140, preferably retaining 60-100 angstroms of residual Silicon oxide layer 130. Due to the anisotropy of the dry etching, there is only an etching effect in the etching direction, so that the sidewall of the emitter window 150 formed by this step is relatively even and flat.
  • the silicon dioxide layer 130 remaining under the region of the emitter region window 150 is washed with a certain proportion of hydrofluoric acid solution for a certain period of time, and the emitter region window 150 is transferred downward into the silicon dioxide layer 130.
  • a new emitter window 151 is exposed and the surface of the single crystal silicon of Pbase 112 is exposed. It is particularly important to point out here that the proportion and time of the etching solution are critical, mainly determined by the thickness of the residual silicon dioxide layer 130 below the region of the emitter window 150. If the concentration of the solution is too large, the corrosion rate is too fast, resulting in a shape of 151.
  • the silicon dioxide layer 130 in the region where the new emitter window 151 is located is severely corroded laterally, that is, the undercut is too large, and the time is too short, which leads to residual silicon dioxide layer. 130 corrosion is not clean. These can affect the subsequent polysilicon fill.
  • the residual silicon dioxide layer 130 can be cleaned without causing too much lateral corrosion, and the BJT small current degradation is significantly improved.
  • a polysilicon layer 160 of about 1700 angstroms is grown by chemical vapor deposition on the polysilicon 140 and the surface of the emitter window 151.
  • the characteristic of the polysilicon layer 160 is that the diffusion speed of the impurity in the inside is fast, so that the impurity in the emissive region to be implanted into the polysilicon can reach the surface of the single crystal faster, thereby obtaining a better surface concentration of the emitter region and improving the BJT small current degradation.
  • the thickness and process of the polysilicon layer 160 is also based on the gate of the CMOS portion.
  • the requirements for polysilicon are determined and are not limited to the values mentioned above.
  • P-type ions are implanted on the 160.
  • the P-type ions are generally arsenic, and the energy dose thereof is mainly selected according to the thickness of the polysilicon and the electrical requirements of the BJT.
  • the specific ion implantation process reference may be made to the above ion implantation method, which will not be described herein.
  • the polysilicon 160 is annealed to diffuse ions in the portion of the polysilicon 160 located in the emitter region 151 to the underlying single crystal silicon surface.
  • Polysilicon 160, Alpha-type polysilicon 140, and silicon dioxide layer 130 other than the emitter region are then removed by dry etching.
  • the specific removal method comprises: spin coating a photoresist layer on the polysilicon layer 160, exposing the photoresist layer by using a mask, and developing and etching away the photoresist layer except the emitter region.
  • the polysilicon layer 160, the Alpha-type polysilicon 140, and the silicon dioxide layer 130 are etched away by a dry etching method to form a basic shape of the emitter region, and finally removed in the emitter region 150.
  • the upper photoresist is exposed to expose the portion of the polysilicon layer 160.
  • the actual remaining polysilicon 160 is larger than the emissive region, which is mainly determined by the lithography engraving, that is, the design rule of the process size, and has nothing to do with the gist of the present invention.
  • the process of fabricating the BJT is mainly the processes of ohmic contact implantation and lead wire of the collector and the base of the NSENKK111 and Pbase112 regions, and these processes can be existing processes, so they will not be described here.
  • the BJT obtained by the above method has a two-step etching method, the first step of dry etching, using silicon dioxide as a retention layer, and does not cause damage to the surface of the single crystal silicon;
  • the etching method uses Alpha-type polysilicon as a barrier layer, which reduces the lateral corrosion amount of the silicon dioxide layer in the wet etching, and obtains a relatively good window morphology. Therefore, when the emitter region is implanted and diffused by polysilicon, a better surface concentration can be obtained, and the small current degradation of the BJT is improved.
  • CMOS portion and fabricating a BJT portion are simultaneously performed.
  • ion implantation and annealing processes of polysilicon in the emitter region are The source and drain ion implantation and annealing processes of CMOS are performed simultaneously, but the process requirements for ion implantation of the source and drain of CMOS are different from those of the BJT emitter region, resulting in a BJT emitter region.
  • the junction depth is large and the surface ion concentration is too small.
  • the emitter of the BJT is separately formed from the source and drain of the CMOS by using the BJT fabrication method described above, thereby obtaining a BJT emitter having a good window shape, a shallow junction depth, and a large surface concentration. And because it is made separately, the design flexibility of each device is greatly improved. specifically:
  • a portion of the active region is defined as a BJT region, and a portion of the active region is defined as a CMOS region.
  • doping different ions, namely ion implantation process forming the SINK region and the base region of the BJT, and the source and drain regions of the CMOS.
  • the launch area is started on the Base area of the BJT.
  • the fabrication steps of the emitter region are as shown in FIG. 3, as shown in the figure:
  • S24 Exposing and etching the emitter window on the photoresist layer above the Base region by using a mask. Then, the photoresist layer is used as a mask, and the silicon oxide layer is used as a retention layer, and the Alpha-type polysilicon is dry-etched to form an emission region window on the Alpha-type polysilicon.
  • S26 depositing a polysilicon layer on the surface of the Alpha-type polysilicon layer and the surface of the single crystal silicon exposed in the window of the emission region, and performing ion implantation and diffusion annealing on the polysilicon layer.
  • step S23 the formed silicon dioxide layer and the Alpha-type polysilicon layer are also applied to the gate dielectric layer of the CMOS portion at the same time, so the process parameters of the two layers are determined according to the actual needs of the CMOS.
  • the polysilicon layer deposited in step S26 is also applied to the gate fabrication of the CMOS portion, so the process parameters of the polysilicon layer are determined according to the actual needs of the CMOS.
  • steps S24-S25 only the etching of the emitter window of the BJT portion is performed.
  • step S26 the ion implantation and annealing process for the polysilicon is only used to fabricate the emitter of the BJT portion.
  • the ion implantation in this step is covered by the silicon dioxide layer and the Alpha-type polysilicon layer in the CMOS region, so The source and drain regions of the CMOS do not cause ion implantation.
  • step S27 the emitter of the BJT and the gate of the CMOS are simultaneously etched using a mask.
  • the parameters of the ion implantation and annealing process can be designed for the characteristics of the BJT emitter, thereby A better junction depth and surface ion concentration are obtained. It not only improves the BJT small current degradation in the BiCMOS process, but also greatly improves the design flexibility of the entire device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention porte sur un transistor bipolaire à jonction (BJT) et sur un procédé de fabrication d'un BiCMOS. Le BJT comporte un émetteur en polysilicium. Un procédé de gravure en deux étapes est utilisé lorsque l'émetteur est fabriqué. La première étape est une gravure au plasma à l'aide de dioxyde de silicium en tant que couche résiduelle, de façon à éviter un endommagement à la surface du silicium microcristallin. La seconde étape est une gravure humide à l'aide d'un polysilicium de type Alpha en tant que couche barrière, de façon à réduire une corrosion latérale pour la couche de dioxyde de silicium dans la gravure humide. Au moyen de la forme de fenêtre obtenue, une dégradation à petit courant du BJT est réduite.
PCT/CN2012/079457 2011-08-05 2012-07-31 Transistor bipolaire à jonction et procédé de fabrication d'une structure hybride bipolaire et semi-conducteur complémentaire à l'oxyde de métal WO2013020471A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201110224765XA CN102915975A (zh) 2011-08-05 2011-08-05 一种BJT以及BiCMOS的制作方法
CN201110224765.X 2011-08-05

Publications (1)

Publication Number Publication Date
WO2013020471A1 true WO2013020471A1 (fr) 2013-02-14

Family

ID=47614290

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/079457 WO2013020471A1 (fr) 2011-08-05 2012-07-31 Transistor bipolaire à jonction et procédé de fabrication d'une structure hybride bipolaire et semi-conducteur complémentaire à l'oxyde de métal

Country Status (2)

Country Link
CN (1) CN102915975A (fr)
WO (1) WO2013020471A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108458820A (zh) * 2018-03-16 2018-08-28 广东和宇传感器有限公司 一种单片硅基微压传感器及其制作方法
CN114093936A (zh) * 2021-09-28 2022-02-25 重庆中科渝芯电子有限公司 一种亚微米多晶硅发射极双极结型晶体管及其制造方法
CN114783872A (zh) * 2022-05-30 2022-07-22 福建福顺微电子有限公司 一种双向可控硅的制作方法及双向可控硅

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097506B (zh) * 2014-04-29 2018-11-27 无锡华润上华科技有限公司 多晶硅发射极垂直npn晶体管的制造方法
CN106981421B (zh) * 2016-01-19 2020-07-14 北大方正集团有限公司 三极管基区的制作方法
CN112825301B (zh) * 2019-11-21 2022-08-12 东南大学 绝缘栅双极型晶体管器件及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6159870A (ja) * 1984-08-31 1986-03-27 Fujitsu Ltd 半導体装置の製造方法
US5147809A (en) * 1991-02-21 1992-09-15 Samsung Electronics Co., Ltd. Method of producing a bipolar transistor with a laterally graded emitter (LGE) employing a refill method of polycrystalline silicon
US20070202642A1 (en) * 2006-02-24 2007-08-30 Nanda Arun K Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method
CN101877313A (zh) * 2009-04-29 2010-11-03 上海华虹Nec电子有限公司 存储器器件中隧穿氧化层形成的方法
CN101944484A (zh) * 2009-07-09 2011-01-12 上海华虹Nec电子有限公司 一种改善发射极窗口侧向开口的方法
CN102129991A (zh) * 2010-01-18 2011-07-20 上海华虹Nec电子有限公司 改善SiGe工艺中发射极窗口图形形成的方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101126933B1 (ko) * 2008-09-02 2012-03-20 주식회사 동부하이텍 폴리에미터형 바이폴라 트랜지스터, ｂｃｄ 소자, 폴리에미터형 바이폴라 트랜지스터의 제조 방법 및 ｂｃｄ 소자의 제조 방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6159870A (ja) * 1984-08-31 1986-03-27 Fujitsu Ltd 半導体装置の製造方法
US5147809A (en) * 1991-02-21 1992-09-15 Samsung Electronics Co., Ltd. Method of producing a bipolar transistor with a laterally graded emitter (LGE) employing a refill method of polycrystalline silicon
US20070202642A1 (en) * 2006-02-24 2007-08-30 Nanda Arun K Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method
CN101877313A (zh) * 2009-04-29 2010-11-03 上海华虹Nec电子有限公司 存储器器件中隧穿氧化层形成的方法
CN101944484A (zh) * 2009-07-09 2011-01-12 上海华虹Nec电子有限公司 一种改善发射极窗口侧向开口的方法
CN102129991A (zh) * 2010-01-18 2011-07-20 上海华虹Nec电子有限公司 改善SiGe工艺中发射极窗口图形形成的方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108458820A (zh) * 2018-03-16 2018-08-28 广东和宇传感器有限公司 一种单片硅基微压传感器及其制作方法
CN114093936A (zh) * 2021-09-28 2022-02-25 重庆中科渝芯电子有限公司 一种亚微米多晶硅发射极双极结型晶体管及其制造方法
CN114093936B (zh) * 2021-09-28 2024-02-09 重庆中科渝芯电子有限公司 一种亚微米多晶硅发射极双极结型晶体管及其制造方法
CN114783872A (zh) * 2022-05-30 2022-07-22 福建福顺微电子有限公司 一种双向可控硅的制作方法及双向可控硅

Also Published As

Publication number Publication date
CN102915975A (zh) 2013-02-06

Similar Documents

Publication Publication Date Title
WO2013020471A1 (fr) Transistor bipolaire à jonction et procédé de fabrication d'une structure hybride bipolaire et semi-conducteur complémentaire à l'oxyde de métal
US7785974B2 (en) Methods of employing a thin oxide mask for high dose implants
US9812445B2 (en) Bipolar junction transistor device having base epitaxy region on etched opening in DARC layer
US10062767B2 (en) Memory cell and fabrication method thereof
US6342428B1 (en) Method for a consistent shallow trench etch profile
US20220157993A1 (en) Flash memory device
US20090050980A1 (en) Method of forming a semiconductor device with source/drain nitrogen implant, and related device
US6475922B1 (en) Hard mask process to control etch profiles in a gate stack
TW521347B (en) Method for controlling an opening width in a semiconductor device and related structure
JP2887076B2 (ja) 半導体ｍｏｓトランジスタの製造方法
CN100517577C (zh) 半导体器件的栅极制造方法
CN101207026B (zh) 半导体器件的栅极形成方法
KR20050071156A (ko) 반도체 소자의 게이트 스페이서형성방법
KR100629606B1 (ko) 고전압 소자 영역의 게이트 산화막 질 개선방법
US20050020043A1 (en) Methods for reducing cell pitch in semiconductor devices
KR100503746B1 (ko) 반도체 소자의 제조방법
TWI833266B (zh) 半導體裝置與其製造方法
CN107452629B (zh) 功率半导体器件及其制造方法
KR20000043917A (ko) 플래쉬 메모리 소자의 제조 방법
KR100670539B1 (ko) 단결정 실리콘 성장 방식을 이용한 씨모스 이미지센서제조 방법
KR100628624B1 (ko) 바이폴라 트랜지스터 및 그 제조 방법
KR20010008564A (ko) 반도체장치의 트랜지스터 제조방법
CN110931492A (zh) Nor闪存的集成工艺方法
KR100532739B1 (ko) 반도체의 게이트 스페이서 형성 방법
KR100480919B1 (ko) 반도체 소자의 소자분리막 형성방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12821576

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12821576

Country of ref document: EP

Kind code of ref document: A1