WO2013006672A3 - Programmable patch architecture for rom - Google Patents

Programmable patch architecture for rom Download PDF

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Publication number
WO2013006672A3
WO2013006672A3 PCT/US2012/045501 US2012045501W WO2013006672A3 WO 2013006672 A3 WO2013006672 A3 WO 2013006672A3 US 2012045501 W US2012045501 W US 2012045501W WO 2013006672 A3 WO2013006672 A3 WO 2013006672A3
Authority
WO
WIPO (PCT)
Prior art keywords
storage medium
address
rom
host cpu
patch information
Prior art date
Application number
PCT/US2012/045501
Other languages
French (fr)
Other versions
WO2013006672A2 (en
Inventor
Vishal V. Varma
Kamal J. Koshy
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to KR1020147002616A priority Critical patent/KR101574512B1/en
Priority to EP12808115.5A priority patent/EP2729880A2/en
Publication of WO2013006672A2 publication Critical patent/WO2013006672A2/en
Publication of WO2013006672A3 publication Critical patent/WO2013006672A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/328—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)
  • Debugging And Monitoring (AREA)

Abstract

A system according to one embodiment includes a host central processing unit (CPU); a first storage medium configured to be in communication with the host CPU and to store information associated with at least one address; a second storage medium configured to be in communication with the host CPU, to store patch information associated with the at least one address of the first storage medium; and selection circuitry configured to, in response to a fetch instruction from the host CPU, select the patch information from the second storage medium if the fetch instruction contains a destination address that matches the at least one address associated with the patch information.
PCT/US2012/045501 2011-07-06 2012-07-05 Programmable patch architecture for rom WO2013006672A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020147002616A KR101574512B1 (en) 2011-07-06 2012-07-05 Programmable patch architecture for rom
EP12808115.5A EP2729880A2 (en) 2011-07-06 2012-07-05 Programmable patch architecture for rom

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/177,328 2011-07-06
US13/177,328 US20130013849A1 (en) 2011-07-06 2011-07-06 Programmable Patch Architecture for ROM

Publications (2)

Publication Number Publication Date
WO2013006672A2 WO2013006672A2 (en) 2013-01-10
WO2013006672A3 true WO2013006672A3 (en) 2013-03-14

Family

ID=47437680

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2012/045501 WO2013006672A2 (en) 2011-07-06 2012-07-05 Programmable patch architecture for rom

Country Status (4)

Country Link
US (1) US20130013849A1 (en)
EP (1) EP2729880A2 (en)
KR (1) KR101574512B1 (en)
WO (1) WO2013006672A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150242213A1 (en) * 2014-02-23 2015-08-27 Qualcomm Incorporated System and method for modification of coded instructions in read-only memory using one-time programmable memory
GB2551574B (en) * 2016-06-24 2019-11-27 Advanced Risc Mach Ltd An apparatus and method for generating and processing a trace stream indicative of instruction execution by processing circuitry
US11354117B2 (en) 2016-07-13 2022-06-07 Oracle International Corporation Adaptable patching mechanism for mixed memory systems
US10740029B2 (en) * 2017-11-28 2020-08-11 Advanced Micro Devices, Inc. Expandable buffer for memory transactions
US10725699B2 (en) 2017-12-08 2020-07-28 Sandisk Technologies Llc Microcontroller instruction memory architecture for non-volatile memory
KR20210046418A (en) 2019-10-18 2021-04-28 삼성전자주식회사 Semiconductor device inclduing secure patchable rom and pathc method thereof
EP4012554B1 (en) * 2020-01-17 2023-10-18 Shenzhen Goodix Technology Co., Ltd. Chip patching method and chip

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100717110B1 (en) * 2006-02-21 2007-05-10 삼성전자주식회사 Rom data patch circuit, embedded system including the same and method of patching rom data
US20080112205A1 (en) * 2006-10-30 2008-05-15 Via Telecom Co., Ltd. Circuit and method for patching for program ROM
KR20090101771A (en) * 2008-03-24 2009-09-29 삼성전자주식회사 Crum for image forming apparatus, image forming apparatus including the same and authentication method using the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6766449B2 (en) * 2000-12-28 2004-07-20 Intel Corporation Method and apparatus for dynamic processor configuration by limiting a processor array pointer
US20030018842A1 (en) * 2001-07-19 2003-01-23 Donald Harbin Interrupt controller
US7596721B1 (en) * 2004-01-09 2009-09-29 Maxtor Corporation Methods and structure for patching embedded firmware
GB0424424D0 (en) * 2004-11-04 2004-12-08 St Microelectronics Belgium Nv A code patching device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100717110B1 (en) * 2006-02-21 2007-05-10 삼성전자주식회사 Rom data patch circuit, embedded system including the same and method of patching rom data
US20070220374A1 (en) * 2006-02-21 2007-09-20 Dong-Hee Han ROM Data Patch Circuit, Embedded System Including the Same and Method of Patching ROM Data
US20080112205A1 (en) * 2006-10-30 2008-05-15 Via Telecom Co., Ltd. Circuit and method for patching for program ROM
KR20090101771A (en) * 2008-03-24 2009-09-29 삼성전자주식회사 Crum for image forming apparatus, image forming apparatus including the same and authentication method using the same

Also Published As

Publication number Publication date
US20130013849A1 (en) 2013-01-10
EP2729880A2 (en) 2014-05-14
KR20140034294A (en) 2014-03-19
KR101574512B1 (en) 2015-12-07
WO2013006672A2 (en) 2013-01-10

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