WO2012168051A1 - Regulated current source and method for providing a regulated output current - Google Patents

Regulated current source and method for providing a regulated output current Download PDF

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Publication number
WO2012168051A1
WO2012168051A1 PCT/EP2012/059262 EP2012059262W WO2012168051A1 WO 2012168051 A1 WO2012168051 A1 WO 2012168051A1 EP 2012059262 W EP2012059262 W EP 2012059262W WO 2012168051 A1 WO2012168051 A1 WO 2012168051A1
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WO
WIPO (PCT)
Prior art keywords
output
current source
signal
regulation
loop
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Ceased
Application number
PCT/EP2012/059262
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French (fr)
Inventor
Pramod Singnurkar
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Ams Osram AG
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Ams AG
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Publication of WO2012168051A1 publication Critical patent/WO2012168051A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H03F3/45192—Folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45695—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedforward means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H03F3/45748—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit
    • H03F3/45753—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit using switching means, e.g. sample and hold
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H03F3/45757—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedforward circuit
    • H03F3/45762—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedforward circuit using switching means, e.g. sample and hold
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/345—Current stabilisation; Maintaining constant current

Definitions

  • the present invention is related to a regulated current source and to a method for providing a regulated output current .
  • Current sources are commonly used for several different applications, for instance to drive lightening diodes of a backlight panel in a TV.
  • the number of such current sources to control lightning diodes has constantly increased for such applications.
  • the need to reduce the overall size, costs and complexity of those current sources has increased as well.
  • An aspect of the invention is related to a regulated current source comprising controllable output means coupled to a supply terminal and to an output terminal to provide a respective output current.
  • a first regulation loop comprises first comparing means to provide a control signal to the controllable output means in response to a feedback signal and a reference signal. As such, the first regulation loop may regulate the output current to a specific value in response to the reference signal.
  • the regulated current source may comprise a first switch between the controllable output means and output of the first comparing means.
  • An offset cancellation loop having second comparing means is coupled with its input to the output of the first comparing means to provide an offset cancellation signal to the first comparing means.
  • a unity gain buffer is coupled to a node between the first switch and the controllable output means and is selectively switchable arranged in parallel to the first switch.
  • the present invention proposes two loops to control an output current, whereby the first regulation loop provides a regulation for the output current while the second loop acts to cancel any offset generated in the first
  • the first switch of a regulated current source is adapted to be closed during a regulation cycle of the first regulation loop.
  • the regulated current source controls the first switch between an open state and a closed state.
  • the regulation loop provides a regulated output current.
  • the offset cancellation loop is adapted to provide the offset cancellation signal during a refresh cycle of the first regulation loop.
  • the unity gain buffer is adapted to be operated between the refresh cycle and the regulation cycle. Such operation may be controlled by the regulated current source. Due to the operation of the gain buffer between the refresh cycle and the regulation cycle, the output of the first comparing means and the control input are at the same potential at the start of the regulation cycle.
  • the regulated current source is operated in three different consecutive cycles.
  • the first regulation loop is active and provides a respective control signal such as a controllable output means.
  • a refresh cycle follows the regulation cycle consecutively.
  • the offset such as a controllable output means
  • the cancellation loop is active to evaluate an offset of the first regulation loop. In response to an evaluated offset, the offset cancellation loop provides a respective
  • cancellation signal to the first regulation loop.
  • Said cancellation signal may be used in the regulation cycle.
  • the unity gain buffer is operated.
  • the gain buffer equalizes the signal at the node between the first switch and the controllable output means to a signal between the output of the first regulation loop and the first switch. As a result, any glitches during transition from the refresh cycle to the regulation cycle are significantly reduced .
  • the first comparing means comprise a differential operational amplifier, wherein at least one output is coupled to the first switch.
  • the second comparing means may also comprise a differential amplifier coupled with its input via respective switches to the output of the first comparing means and with its output to a supply of the first comparing means.
  • comparing means provide a cancellation signal, that cancellation signal being the supply signal for the first comparing means .
  • the second comparing means may comprise at least one capacitor coupled between one of the inputs and the respective switch.
  • the capacitor provides a signal storage to the offset cancellation loop.
  • a capacitor may be coupled to the supply terminal and the node.
  • the unity gain buffer may be adapted to mirror a signal at the node to the output of the first regulation loop between the refresh cycle and the regulation cycle .
  • FIG. 2 shows a time signal diagram for several control signals applied to the embodiment of FIG. 1 during operation
  • FIG. 3 shows an embodiment of a unity gain buffer to be implemented in the embodiment of FIG. 1 in
  • FIG. 4 shows an embodiment of an operational amplifier according to the present invention
  • FIG. 5 illustrates an embodiment of an operational
  • FIG. 6 shows a known regulated current source.
  • FIG. 6 shows a regulated current source comprising several regulation loops with different bandwidths to provide a respective output current lout.
  • the known regulated current source includes a first regulation loop LI having a low bandwidth, a first offset cancellation loop L2 with a medium bandwidth, and a second offset cancellation loop L3 with a high bandwidth.
  • the second offset cancellation loop L3 is used to cancel any offset of an operational amplifier A2 in the first offset cancellation loop.
  • the first regulation loop LI comprises a comparator Al with its output coupled to a current output transistor Mp .
  • the current output transistor is connected between the supply terminal Vbat and an output terminal for providing the output current lout.
  • a feedback is coupled between power transistor Mp and the inverting input for operational amplifier Al, thereby implementing the first regulation loop.
  • the operational amplifier Al compares the feedback signal with a reference signal Vref applied to its non-inverting input and provides a respective control signal to the gate of output transistor Mp .
  • three other operational amplifiers A2, A3 and A4 are used.
  • the operational amplifier A2 forming a portion of the first cancellation loop L2 also requires its own offset cancellation loop implemented by the second offset cancellation loop L3 and the operational amplifier A3.
  • several switches are arranged in the regulated current source. The current source itself is operated by a clock signal.
  • Capacitor CI thereby stores voltage equal two a reference signal VrefO, as operational amplifier A3 of the second offset cancellation loop L3 provides a respective supply signal to operational amplifier A2.
  • switches SB and SI are open, while switches S2 and Sa are closed.
  • the output signal of operational amplifier A2 now with a significantly reduced offset due to the offset cancellation loop L3 provides a control signal to the inverting input of operational amplifier A4 and capacitor C2.
  • operational amplifier A2 receives the reference signal Vref at its non-inverting input and the feedback signal from the main regulation loop LI at its inverting input signal.
  • capacitor C2 stores a voltage equal to reference voltage Vrefl, as operational amplifier A4 provides the offset cancellation signal for operational amplifier Al in the main loop. If regulation loop LI is active,
  • operational amplifier Al will have a balanced offset signal over a number of clock cycles.
  • offset cancellation loop L3 requires a high bandwidth than offset cancellation loop L2.
  • the main regulation loop LI requires a lower bandwidth compared to the first cancellation loop. This poses a bandwidth limit.
  • an offset cancellation is only achieved if the main regulation loop LI is stable. During transience, no offset cancellation may exist.
  • FIG. 1 illustrates an embodiment of the proposed principle of a regulated current source.
  • regulated current source according to FIG. 1 comprises a main regulation loop LI as indicated, and an offset cancellation loop L2.
  • the main regulation loop comprises an operational amplifier Al which is implemented as a fully differential operational amplifier.
  • the non-inverting output of the operational amplifier Al providing output signal outp is coupled via a first switch SI to the gate of the output transistor Mp providing the output current lout.
  • a feedback node for feedback signal Vfb is coupled via switch SC to the inverting input of
  • amplifier Al is connected via switch SD to a reference signal Vref.
  • the two inputs of amplifier Al are also connected via switches Sa and Sb to a common mode reference Vc .
  • switches Sa and Sb are operated in a specific mode as it will be explained in greater detail below.
  • the offset cancellation loop comprises an operational amplifier A2 with an inverting and non-inverting input.
  • the inverting input is connected via switch Sp to the non- inverting output outp of operational amplifier Al .
  • the non- inverting input is coupled via switch Sn to the inverting output outn of operational amplifier Al .
  • capacitances CI and C2 are connected between the inputs of amplifier Al and the respective switches. They are used to store respective signals applied to operational amplifier A2 during operation of the circuit.
  • the output of operational amplifier A2 providing output signals icp and icn are
  • a unity gain buffer is substantially arranged in parallel to switch SI.
  • the unity gain buffer is coupled to a first node Vs between the gate of transistor Mp and switch SI and with a second node via switch Se to the non-inverting output of operational amplifier Al .
  • node Vs is connected via capacitor C to supply terminal Vbat .
  • Switch S2 for selectively activating or deactivating the regulated current source is arranged in parallel to capacitor C.
  • FIG. 2 illustrates a time-signal diagram of several signals applied to the embodiment of the regulated current source according to FIG. 1.
  • the regulated current source is operated in consecutive sequential cycles, namely regulation cycle, refresh cycle, and equalizer cycle.
  • switches SI, S2, Se, Sc and Sd are open, while switches Sa, Sb, Sn and Sp are closed.
  • Common mode voltage signal Vcm is both applied to the non-inverting and to the inverting input of operational amplifier A2 of the main regulation loop. If there is no internal offset voltage in operational amplifier Al, the difference between the output signals outp and outn must be zero as well. If there is any offset, said offset will result in a difference applied to operational amplifier A2 of the offset cancellation loop.
  • the offset cancellation loop provides output signals icp and icn to cancel the offset signal in amplifier Al .
  • the switches Sa, Sb, Sn and Sp are open and the current source starts the regulation cycle by closing switch SI, Sc and Sd.
  • Reference signal Vref is now applied to operational amplifier Al .
  • a first refresh cycle switches SI, S2, Se, Sc and Sd are open, while switches Sa, Sb, Sn and Sp
  • the operational amplifier provides an output signal outp applied to power transistor Mp to drive the transistor.
  • the transistor provides the respective regulated output current lout.
  • any offset in operational amplifier Al is cancelled by the offset cancellation loop L2.
  • the second refresh cycle and any refresh cycle afterwards are immediately followed by an equalizer cycle.
  • switch SI remains open, switches Sa, Sb, Sn and Sp are opened as well.
  • Switch Se coupling the unity gain buffer to the output of operational amplifier Al is now closed as well as switches Sc and Sd.
  • the operational amplifier compares the feedback signal Vfb with the reference signal and provides an output signal outp to the still open switch SI.
  • the unity gain buffer now arranged in parallel to switch SI has the purpose of equalizing a signal at node VS with the signal outp provided by operational amplifier Al .
  • any potential at node VS is equal to the potential at the output of operational amplifier Al .
  • Closing switch SI with the beginning of the next regulation cycle will therefore not provoke any spike on the output current lout.
  • the output current lout is given by the output current during the last regulation cycle. This is achieved by the unity gain buffer arranged in parallel to switch SI and capacitor C connected between node VS and supply terminal Vbat.
  • the regulation cycle may be much longer than the following refresh and equalizer cycle.
  • the equalizer cycle may be only a few per cent of the refresh cycle sufficient to equalize the signal at node VS with the output signal outp of operational amplifier Al .
  • the regulation cycle may be in the range of a few hundred ys up to a few
  • FIG. 3 illustrates a unity gain buffer to be used in the regulated current source according to the present invention.
  • the unity gain buffer equalizes signal Vs applied to gate terminal of transistor Ml to output signal Ve .
  • signal Vs is basically mirrored via transistors Ml, M2, M3 and M4 to the respective output terminal.
  • the current Icnl given by current source II flowing through transistor Ml, M5 and M9 is mirrored into transistor M10, Mil and M12. If the transistors M9 to M12 carry equal currents, the respective gate-to-source voltages of transistors Ml, M2, M3 and M4 are equal as well.
  • the output signal Ve the output signal
  • transistors M3 and M7 respectively.
  • FIG. 3 provides an output signal Ve equal to node Vs without loading the node Vs itself. This feature is important for a continuous output current lout.
  • the equalizer according to FIG. 3 smoothly transfers the original value of signal at node VS to the operational output terminal of amplifier Al without loading the node VS itself.
  • both signals are equal and after switch SI is closed, no spike or signal transient in the control signal applied to gate terminal of transistor Mp takes place.
  • the voltage to voltage amplifier comprises an input portion including a differential amplifier with transistors M21 and M22 as well as an output portion with nodes 11 and 12 for providing output voltage signals outp and outn.
  • a supply terminal provides the supply voltage to transistors M23 and M24 in the output path, which are connected to transistors M25 and M26, respectively.
  • a node between transistor M23 and M25 is coupled to transistor M22 of the differential amplifier.
  • a node between transistors M24 and M26 is connected to
  • transistor M21 of the differential amplifier The gates of transistors M23 and M24 are coupled to output node 12.
  • the feedback signal and the reference signal are applied to the respective input terminals inn or inp, respectively.
  • the amplifier provides a current to the output path and to the respective nodes.
  • FIG. 5 illustrates an embodiment of a voltage to current amplifier used in the offset cancellation loop.
  • the amplifier comprises a differential amplifier including transistors M41 and M42. At the gate of transistor M41, the voltage signal VC1 generated by capacitor CI in the embodiment of FIG. 1 is applied, too. Accordingly, the gate of transistor M42
  • Transistor M43 is connected in series to transistor M41 and coupled with its gate to node 21.
  • Transistor M44 is coupled with its gate to node 23.
  • Nodes 21 and 23 are the output nodes of the differential amplifier and connected to the gates of current output transistors M45 and M46.
  • the output transistors M45 and M46 provide respective output currents icn and icp to nodes Vj 2 and Vjl, respectively .

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  • Physics & Mathematics (AREA)
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Abstract

A regulated current source comprises a controllable output means (Mp) and a first regulation loop with a first comparing means to provide a control signal to the controllable output means. A first switch is arranged between the controllable output means and an output of the first comparing means. The current source also comprises an offset cancellation loop having second comparing means coupled with its input to the output of the first comparing means. A unity gain buffer is coupled to a node between the first switch and the controllable output means and selectively switchable arranged in parallel to the first switch.

Description

Description
Regulated current source and method for providing a regulated output current
The present invention is related to a regulated current source and to a method for providing a regulated output current . Current sources are commonly used for several different applications, for instance to drive lightening diodes of a backlight panel in a TV. The number of such current sources to control lightning diodes has constantly increased for such applications. As a consequence, the need to reduce the overall size, costs and complexity of those current sources has increased as well.
This and other needs are taken into account by the current independent claims. Further embodiments and different aspects of the invention are a subject matter of the dependent claims .
An aspect of the invention is related to a regulated current source comprising controllable output means coupled to a supply terminal and to an output terminal to provide a respective output current. A first regulation loop comprises first comparing means to provide a control signal to the controllable output means in response to a feedback signal and a reference signal. As such, the first regulation loop may regulate the output current to a specific value in response to the reference signal. Further, the regulated current source may comprise a first switch between the controllable output means and output of the first comparing means. An offset cancellation loop having second comparing means is coupled with its input to the output of the first comparing means to provide an offset cancellation signal to the first comparing means. A unity gain buffer is coupled to a node between the first switch and the controllable output means and is selectively switchable arranged in parallel to the first switch.
To this extent, the present invention proposes two loops to control an output current, whereby the first regulation loop provides a regulation for the output current while the second loop acts to cancel any offset generated in the first
regulation loop. The unity gain buffer offers offset
cancellation prior to signal application and operation of the regulation loop. As a result, there is no limitation of bandwidth compared to known implementations.
In an aspect, the first switch of a regulated current source is adapted to be closed during a regulation cycle of the first regulation loop. For example, the regulated current source controls the first switch between an open state and a closed state. During the regulation cycle, the first
regulation loop provides a regulated output current. The offset cancellation loop is adapted to provide the offset cancellation signal during a refresh cycle of the first regulation loop. Finally, the unity gain buffer is adapted to be operated between the refresh cycle and the regulation cycle. Such operation may be controlled by the regulated current source. Due to the operation of the gain buffer between the refresh cycle and the regulation cycle, the output of the first comparing means and the control input are at the same potential at the start of the regulation cycle. In accordance with the present invention, the regulated current source is operated in three different consecutive cycles. During a regulation cycle, the first regulation loop is active and provides a respective control signal such as a controllable output means. To reduce an offset in the first regulation loop, a refresh cycle follows the regulation cycle consecutively. During the refresh cycle, the offset
cancellation loop is active to evaluate an offset of the first regulation loop. In response to an evaluated offset, the offset cancellation loop provides a respective
cancellation signal to the first regulation loop. Said cancellation signal may be used in the regulation cycle.
After the refresh cycle and before the following regulation cycle, the unity gain buffer is operated.
The gain buffer equalizes the signal at the node between the first switch and the controllable output means to a signal between the output of the first regulation loop and the first switch. As a result, any glitches during transition from the refresh cycle to the regulation cycle are significantly reduced .
In an aspect of the present invention, the first comparing means comprise a differential operational amplifier, wherein at least one output is coupled to the first switch. The second comparing means may also comprise a differential amplifier coupled with its input via respective switches to the output of the first comparing means and with its output to a supply of the first comparing means.
In accordance with the present invention, the second
comparing means provide a cancellation signal, that cancellation signal being the supply signal for the first comparing means .
In a further aspect, the second comparing means may comprise at least one capacitor coupled between one of the inputs and the respective switch. The capacitor provides a signal storage to the offset cancellation loop.
To further reduce any glitches, particularly with respect to a ground potential, a capacitor may be coupled to the supply terminal and the node.
In another aspect, the unity gain buffer may be adapted to mirror a signal at the node to the output of the first regulation loop between the refresh cycle and the regulation cycle .
Further aspects and principles of the present invention are now illustrated in greater detail with respect to the accompanying drawings, in which: llustrates a first embodiment of the present invention ;
FIG. 2 shows a time signal diagram for several control signals applied to the embodiment of FIG. 1 during operation;
FIG. 3 shows an embodiment of a unity gain buffer to be implemented in the embodiment of FIG. 1 in
accordance with the present invention; FIG. 4 shows an embodiment of an operational amplifier according to the present invention;
FIG. 5 illustrates an embodiment of an operational
amplifier in the offset cancellation loop in accordance with the present invention;
FIG. 6 shows a known regulated current source. FIG. 6 shows a regulated current source comprising several regulation loops with different bandwidths to provide a respective output current lout. The known regulated current source includes a first regulation loop LI having a low bandwidth, a first offset cancellation loop L2 with a medium bandwidth, and a second offset cancellation loop L3 with a high bandwidth. The second offset cancellation loop L3 is used to cancel any offset of an operational amplifier A2 in the first offset cancellation loop. The first regulation loop LI comprises a comparator Al with its output coupled to a current output transistor Mp . The current output transistor is connected between the supply terminal Vbat and an output terminal for providing the output current lout. A feedback is coupled between power transistor Mp and the inverting input for operational amplifier Al, thereby implementing the first regulation loop.
The operational amplifier Al compares the feedback signal with a reference signal Vref applied to its non-inverting input and provides a respective control signal to the gate of output transistor Mp . To cancel any offset of the operational amplifier Al, three other operational amplifiers A2, A3 and A4 are used. The operational amplifier A2 forming a portion of the first cancellation loop L2 also requires its own offset cancellation loop implemented by the second offset cancellation loop L3 and the operational amplifier A3. For offset cancellation as well as for regulation, several switches are arranged in the regulated current source. The current source itself is operated by a clock signal.
In a first switching phase of the clock, the switches Sa between the inverting and non-inverting input of operation amplifier A2 and SI are closed. Capacitor CI thereby stores voltage equal two a reference signal VrefO, as operational amplifier A3 of the second offset cancellation loop L3 provides a respective supply signal to operational amplifier A2.
In a second phase of the clock signal, switches SB and SI are open, while switches S2 and Sa are closed. During this phase, the output signal of operational amplifier A2 now with a significantly reduced offset due to the offset cancellation loop L3 provides a control signal to the inverting input of operational amplifier A4 and capacitor C2. At the same time, operational amplifier A2 receives the reference signal Vref at its non-inverting input and the feedback signal from the main regulation loop LI at its inverting input signal.
In steady state, capacitor C2 stores a voltage equal to reference voltage Vrefl, as operational amplifier A4 provides the offset cancellation signal for operational amplifier Al in the main loop. If regulation loop LI is active,
operational amplifier Al will have a balanced offset signal over a number of clock cycles. To provide the respective stability of all regulation and offset cancellation loops, offset cancellation loop L3 requires a high bandwidth than offset cancellation loop L2. At the same time, the main regulation loop LI requires a lower bandwidth compared to the first cancellation loop. This poses a bandwidth limit.
Further to this limitation, an offset cancellation is only achieved if the main regulation loop LI is stable. During transience, no offset cancellation may exist.
To this extent, FIG. 1 illustrates an embodiment of the proposed principle of a regulated current source. The
regulated current source according to FIG. 1 comprises a main regulation loop LI as indicated, and an offset cancellation loop L2.
The main regulation loop comprises an operational amplifier Al which is implemented as a fully differential operational amplifier. The non-inverting output of the operational amplifier Al providing output signal outp is coupled via a first switch SI to the gate of the output transistor Mp providing the output current lout. Between resistor Rs and output transistor Mp, a feedback node for feedback signal Vfb is coupled via switch SC to the inverting input of
operational amplifier Al . The non-inverting input of
amplifier Al is connected via switch SD to a reference signal Vref. The two inputs of amplifier Al are also connected via switches Sa and Sb to a common mode reference Vc . The
switches Sa and Sb are operated in a specific mode as it will be explained in greater detail below. The common mode
reference Vc could be the same as Vbat . The offset cancellation loop comprises an operational amplifier A2 with an inverting and non-inverting input. The inverting input is connected via switch Sp to the non- inverting output outp of operational amplifier Al . The non- inverting input is coupled via switch Sn to the inverting output outn of operational amplifier Al . Further,
capacitances CI and C2 are connected between the inputs of amplifier Al and the respective switches. They are used to store respective signals applied to operational amplifier A2 during operation of the circuit. The output of operational amplifier A2 providing output signals icp and icn are
connected to respective supply terminals of operational amplifier Al . To provide an offset cancellation and reduce any spikes during operation of the regulated current source, a unity gain buffer is substantially arranged in parallel to switch SI. Particularly, the unity gain buffer is coupled to a first node Vs between the gate of transistor Mp and switch SI and with a second node via switch Se to the non-inverting output of operational amplifier Al .
Finally, node Vs is connected via capacitor C to supply terminal Vbat . Switch S2 for selectively activating or deactivating the regulated current source is arranged in parallel to capacitor C.
FIG. 2 illustrates a time-signal diagram of several signals applied to the embodiment of the regulated current source according to FIG. 1.
The regulated current source is operated in consecutive sequential cycles, namely regulation cycle, refresh cycle, and equalizer cycle. Starting with a first refresh cycle, switches SI, S2, Se, Sc and Sd are open, while switches Sa, Sb, Sn and Sp are closed. Common mode voltage signal Vcm is both applied to the non-inverting and to the inverting input of operational amplifier A2 of the main regulation loop. If there is no internal offset voltage in operational amplifier Al, the difference between the output signals outp and outn must be zero as well. If there is any offset, said offset will result in a difference applied to operational amplifier A2 of the offset cancellation loop. In response to any offset signal provided by operational amplifier Al, the offset cancellation loop provides output signals icp and icn to cancel the offset signal in amplifier Al . After the first refresh cycle, the switches Sa, Sb, Sn and Sp are open and the current source starts the regulation cycle by closing switch SI, Sc and Sd. Reference signal Vref is now applied to operational amplifier Al . In response to a
comparison between the feedback signal Vfb and the reference signal Vref, the operational amplifier provides an output signal outp applied to power transistor Mp to drive the transistor. The transistor provides the respective regulated output current lout. After the regulation cycle is finished, the second refresh cycle starts by opening switch SI, Sc and Sd, thereby
separating the feedback signal Vfb as well as the reference signal Vref from the respective input terminals of
operational amplifier Al . Similar to the first refresh cycle, any offset in operational amplifier Al is cancelled by the offset cancellation loop L2. The second refresh cycle and any refresh cycle afterwards are immediately followed by an equalizer cycle. For this purpose, switch SI remains open, switches Sa, Sb, Sn and Sp are opened as well. Switch Se coupling the unity gain buffer to the output of operational amplifier Al is now closed as well as switches Sc and Sd. The operational amplifier compares the feedback signal Vfb with the reference signal and provides an output signal outp to the still open switch SI. The unity gain buffer now arranged in parallel to switch SI has the purpose of equalizing a signal at node VS with the signal outp provided by operational amplifier Al . After the
equalization process at the end of the equalizer cycle, any potential at node VS is equal to the potential at the output of operational amplifier Al . Closing switch SI with the beginning of the next regulation cycle will therefore not provoke any spike on the output current lout.
Further, during the refresh and the equalizer cycle, the output current lout is given by the output current during the last regulation cycle. This is achieved by the unity gain buffer arranged in parallel to switch SI and capacitor C connected between node VS and supply terminal Vbat.
During the regulation cycle, switch SI is closed and the feedback signal Vfb regulated to the reference signal Vref by the main regulation loop and the amplifier Al . The current output lout is given by lout = (Vbat Vref) /Rs wherein Rs is the resistance value in the resistor connected between supply terminal Vbat and output transistor Mp . In the refresh cycle following the regulation cycle, the operational amplifier A2 of the offset cancellation loop generates, if necessary, the supply signals icp and icn such that output signal outp is regulated to output signal outn of operational amplifier Al . During this phase, both capacitors CI and C2 are charged to a value of outp = outn. The output current lout stays to the value at the end of the previous regulation cycle. In the following equalizer cycle, just before the next regulation cycle, the output node outp of operational
amplifier Al is equalized to the voltage at node VS. This equalization process assures that the voltage at VS and the control signal of operational amplifier Al in the following regulation cycle are at the same potential before the start of the regulation cycle.
As such, the regulation cycle may be much longer than the following refresh and equalizer cycle. The equalizer cycle may be only a few per cent of the refresh cycle sufficient to equalize the signal at node VS with the output signal outp of operational amplifier Al . For example, the regulation cycle may be in the range of a few hundred ys up to a few
milliseconds, while the refresh cycle is about a few μ- seconds. The equalizer cycle is only a few hundred
nanoseconds long, and sufficiently long enough to obtain equalization of the potential on both sides of switch SI.
FIG. 3 illustrates a unity gain buffer to be used in the regulated current source according to the present invention. The unity gain buffer equalizes signal Vs applied to gate terminal of transistor Ml to output signal Ve . For this purpose, signal Vs is basically mirrored via transistors Ml, M2, M3 and M4 to the respective output terminal. The current Icnl given by current source II flowing through transistor Ml, M5 and M9 is mirrored into transistor M10, Mil and M12. If the transistors M9 to M12 carry equal currents, the respective gate-to-source voltages of transistors Ml, M2, M3 and M4 are equal as well. Hence, the output signal Ve
provided at a node between transistor M8 and M12 and also applied to gate of transistor M4 is equal to input signal Vs. The current flowing through M2 and M6 is mirrored to
transistors M3 and M7, respectively.
The embodiment of FIG. 3 provides an output signal Ve equal to node Vs without loading the node Vs itself. This feature is important for a continuous output current lout.
As a result, the equalizer according to FIG. 3 smoothly transfers the original value of signal at node VS to the operational output terminal of amplifier Al without loading the node VS itself. At the end of the equalizer cycle, both signals are equal and after switch SI is closed, no spike or signal transient in the control signal applied to gate terminal of transistor Mp takes place.
An embodiment of an operational amplifier to be used for the main regulation loop is illustrated in FIG. 4. The voltage to voltage amplifier comprises an input portion including a differential amplifier with transistors M21 and M22 as well as an output portion with nodes 11 and 12 for providing output voltage signals outp and outn. A supply terminal provides the supply voltage to transistors M23 and M24 in the output path, which are connected to transistors M25 and M26, respectively. A node between transistor M23 and M25 is coupled to transistor M22 of the differential amplifier. A node between transistors M24 and M26 is connected to
transistor M21 of the differential amplifier. The gates of transistors M23 and M24 are coupled to output node 12. In operation of the amplifier according to FIG. 4, the feedback signal and the reference signal are applied to the respective input terminals inn or inp, respectively. The amplifier provides a current to the output path and to the respective nodes.
To cancel an existing offset of the operational amplifier in FIG. 4, additional current is subtracted or added at nodes Vj 1 and Vj2, respectively. These nodes are arranged between transistors M23, M25 and M24, M26. The added or subtracted current cancels any offset in the output signals outp, outn of the differential amplifier.
FIG. 5 illustrates an embodiment of a voltage to current amplifier used in the offset cancellation loop. The amplifier comprises a differential amplifier including transistors M41 and M42. At the gate of transistor M41, the voltage signal VC1 generated by capacitor CI in the embodiment of FIG. 1 is applied, too. Accordingly, the gate of transistor M42
receives signal VC2 originated from capacitor C2. Transistor M43 is connected in series to transistor M41 and coupled with its gate to node 21. Transistor M44 is coupled with its gate to node 23. Nodes 21 and 23 are the output nodes of the differential amplifier and connected to the gates of current output transistors M45 and M46. Depending on the signals VC2, VC1 applied to the gates of the differential amplifier transistors, the output transistors M45 and M46 provide respective output currents icn and icp to nodes Vj 2 and Vjl, respectively .

Claims

Patent claims
A regulated current source, comprising:
controllable output means (Mp) , coupled to a supply terminal and to an output terminal to provide an output current (lout) ;
a first regulation loop comprising first comparing means (Al) to provide a control signal to the controllable output means (Mp) in response to a feedback signal (Vfb) and a reference signal (Vref) ;
a first switch (SI) between the controllable output means (Mp) and an output of the first comparing means (Al); an offset cancellation loop having second comparing means
(A2) coupled with its input to the output of the first comparing means (Al) to provide an offset cancellation signal to the first comparing means (Al)
a unity gain buffer coupled to a node (Vs) between the first switch (SI) and the controllable output means (Mp) and selectively switchable arranged in parallel to the first switch (SI) .
The current source of claim 1, wherein
the current source is adapted to close the first switch (SI) during a regulation cycle of the first regulation loop;
the offset cancellation loop is adapted to provide the offset cancellation signal during a refresh cycle of the first regulation loop;
the current source is adapted to operate the unity gain buffer between the refresh cycle and the regulation cycle
3. The current source according to any of claims 1 to 2, wherein the first comparing means comprise a differential operational amplifier (Al), wherein one output is coupled to the first switch (SI) .
4. The current source according to any of claims 1 to 3,
wherein the second comparing means comprise a differential amplifier (A2), coupled with its inputs via respective switches (Sp, Sn) to the output of the first comparing means (Al) and with its output to a supply of the first comparing means .
5. The current source according to any of claims 1 to 4,
wherein the second comparing means comprise at least one capacitor (CI, C2) coupled between one of the inputs and the respective switch (Sp, Sn) .
6. The current source according to any of claims 1 to 5,
further comprising a capacitor (C) coupled to the supply terminal and the node (Vs) .
7. The current source according to any of claims 1 to 6,
further comprising switching means (Sa, Sb) coupled to a common reference and to the input of the first regulation loop, the switching means (Sa, Sb) to be operated, in particular to be closed, during the refresh cycle.
8. The current source according to any of claims 1 to 7,
wherein the unity gain buffer is adapted to mirror a signal at the node (Vs) to the output of the first
regulation loop between the refresh cycle and the
regulation cycle.
9. Method for operating a regulated current source, the regulated current source having an output device (Mp) and a regulation loop (LI) comprising a comparator (Al), the method comprising:
- regulating an output current by comparing a feedback
signal (Vfb) with a reference signal to provide a current control signal in response thereto;
evaluating an offset in the evaluation loop;
applying an offset cancellation signal to the regulation loop in response to evaluating the offset;
equalizing a potential on a control input of the output device (Mp) to an output of the comparator before
regulating an output current.
10. The method according to claim 9, wherein the step of
evaluating an offset is done in a first time period, the step of equalizing a potential is done in a subsequent second time period and the steps of regulating an output current and applying an offset cancellation signal are done in a subsequent third time period.
11. The method of claim 10, wherein the first, second and third time period are cyclically repeated, wherein the third time period is longer than the first time period and the first time period is longer than the second time period .
PCT/EP2012/059262 2011-06-09 2012-05-18 Regulated current source and method for providing a regulated output current Ceased WO2012168051A1 (en)

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