WO2012158632A1 - Improved compound semiconductor growth using ion implantation - Google Patents

Improved compound semiconductor growth using ion implantation Download PDF

Info

Publication number
WO2012158632A1
WO2012158632A1 PCT/US2012/037811 US2012037811W WO2012158632A1 WO 2012158632 A1 WO2012158632 A1 WO 2012158632A1 US 2012037811 W US2012037811 W US 2012037811W WO 2012158632 A1 WO2012158632 A1 WO 2012158632A1
Authority
WO
WIPO (PCT)
Prior art keywords
workpiece
implanted regions
compound semiconductor
implanted
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2012/037811
Other languages
French (fr)
Inventor
Morgan D. Evans
Simon Ruffell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Varian Semiconductor Equipment Associates Inc
Original Assignee
Varian Semiconductor Equipment Associates Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Varian Semiconductor Equipment Associates Inc filed Critical Varian Semiconductor Equipment Associates Inc
Publication of WO2012158632A1 publication Critical patent/WO2012158632A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2921—Materials being crystalline insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/276—Lateral overgrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3416—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/206—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group III-V semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/12—Diffusion of dopants within, into or out of semiconductor bodies or layers between a solid phase and a gaseous phase
    • H10P32/1204—Diffusion of dopants within, into or out of semiconductor bodies or layers between a solid phase and a gaseous phase from a plasma phase

Definitions

  • This invention relates to ion implantation and, more particularly, to ion implantation to improve the quality of a layer grown on a workpiece.
  • Ion implantation is a standard technique for introducing material into a workpiece.
  • a desired implant material is ionized in an ion source, the ions are accelerated to form an ion beam of prescribed energy, and the ion beam is directed at the surface of the workpiece, The energetic ions in the ion beam penetrate into the bulk of the workpiece material and affect both the surface and depth of the workpiece material under certain conditions.
  • Gallium nitride is a material commonly grown on workpieces. GaN is becoming more important for use in light-emitting diodes (LEDs), power transistors, and solid state lasers. The ability to grow high-quality GaN is one limiting factor to improving the quality and lowering the cost of these devices.
  • One method of improving the quality of epitaxialiy-grown GaN is known as epitaxial layer overgrowth (ELOG). For ELOG, a layer of GaN is gro wn, hard mask windows of SiO? or Si x N Y are deposited, and then the high- quality GaN is grown.
  • deposition of the hard mask requires removal of the workpiece from the MOCVD tool and then reintroduction of the workpiece to the MOCVD tool after a lithography step, photoresist application, deposition, and photoresist removal. This particular process is cumbersome and costly. Repeated ELOG sequences add even more cost.
  • ELOG of GaN on silicon, sapphire, SiC, AiN, GaN, or other workpieces can be accomplished using implantation instead of Si0 2 or Si x N y deposition.
  • photoresist was used to mask part of the silicon workpiece and implantation was performed on the unmasked areas. GaN grew laterally over the implanted areas. However, this process is still fairly complex, The use of photoresist adds extra steps, which increases manufacturing costs. What is needed is a faster, less complex, and lower cost method of growing high-quality compound semiconductor layers.
  • a method of workpiece processing comprises implanting a first plurality of implanted regions in a workpiece with a first species.
  • a compound semiconductor is grown on the workpiece after the implanting.
  • the compound semiconductor growth is reduced on the first plurality of implanted regions compared to between the first plurality of implanted regions.
  • At least one device is formed between the first plurality of implanted regions.
  • a method of workpiece processing comprises implanting a second plurality of regions in a workpiece.
  • a compound semiconductor is grown on the workpiece after the implanting.
  • the compound semiconductor growth is increased on the plurality of implanted regions compared to between the plurality of implanted regions,
  • a method of workpiece processing comprises implanting a periphery of a workpiece, A compound semiconductor is grown on the workpiece after the implanting. The growth is reduced on the periphery.
  • FIG, 1 is a cross-sectional side view of a first embodiment of implantation into a workpiece
  • FIG. 2 is a cross-sectional side view of a second embodiment of implantation into a workpiece
  • FIG. 3 is a cross-sectional side view of a third embodiment of implantation into a workpiece
  • FIG. 4 is a cross-sectional side view of a fourth embodiment of implantation into a workpiece
  • FIG . 5 is a top perspective view of a fifth embodiment of implantation into a workpiece
  • FIG. 6 is a cross-sectional side view of a sixth embodiment of implantation into a workpiece
  • FIG, 7 is a top perspective view of a seventh embodiment of an implanted workpiece
  • FIG. 8 is a cross-sectional side vie w of an eighth embodiment of an implanted workpiece
  • FIG. 9 is a perspective view of a ninth embodiment of an implanted workpiece
  • FIG. 10 is a top perspective view of a tenth embodiment of an implanted workpiece
  • FIG. 1 1 is a block diagram of a plasma processing apparatus having a plasma sheath modifier
  • FIG. 12 is a side view of an embodiment of selective ion implantation.
  • the embodiments are described herein in connection with formation of a compound semiconductor such as GaN, but these embodiments also may be used with other III/V compound semiconductors, Ii/Vi compound semiconductors, or other materials known to a person skilled in the art, While specific types of implanters are disclosed, other ion implantation systems known to those skilled in the art that can focus an ion beam or that can implant particular regions of a workpiece with or without a mask on the workpiece may he used in the embodiments described herein. While LEDs are specifically disclosed, other devices also may benefit from the embodiments described herein.
  • the workpieces herein may be silicon, sapphire, AIM, GaN, other compound semiconductors, or other materials and include a coating or other layers in some instances. Any implant dimensions are exemplary and other dimensions are possible. Thus, the invention is not limited to the specific embodiments described below,
  • FIG. 1 is a cross-sectional side view of a first embodiment of implantation into a workpiece,
  • a blanket implant is performed over the entire surface of the workpiece 100 using the ions 1 02 (illustrated by the arrows).
  • the implanted region 109 is formed in the workpiece 100.
  • the devices 1 Q4A-104C. which may be GaN or some other compound semiconductor, are then grown on top of this workpiece 100 after the implantation is completed.
  • the devices 104 A- KMC are shown with doited lines in FIG. 1 because these devices 104A-104C were not formed prior to the blanket implant.
  • These devices 104A-104C may have a width 105 of approximately 300 ⁇ in one embodiment, though these devices 104A-104C may be between 100 ⁇ to 3000 ⁇ in dimension. Of course, other dimensions are possible, A distance 106 of approximately 100 um may separate each pair of devices 104A-104C in one instance. The distance 106 also may be between 10 um to 300 um or other distances known to those skilled in the art.
  • the blanket implant that forms the implanted region 109 improves compound semiconductor growth, such as the growth of GaN.
  • This blanket implant can be combined with a selective or patterned implant, as seen separately in other embodiments herein.
  • the blanket implant and patterned implants can be performed in either order.
  • One possible mechanism that causes the improved growth is that the implant changes the stoichiometry on the surface of the workpiece 100 or relieves the lattice mismatch between the workpiece 100 and the compound semiconductor. Stoichiometry is changed by either adding particular elements through implantation or by preferential sputtering of the elements from the workpiece.
  • FIG. 2 is a cross-sectional side view of a second embodiment of implantation into a workpiece.
  • the workpiece 100 is implanted using ions 102 in the implanted regions 103A-103C.
  • Devices 104A-104C are formed on the implanted regions 103A-103C during a later processing step. These devices 104A-104C may have a width 105 of approximately 300 urn and may be separated by a distance 106 of approximately 100 ⁇ , though other dimensions are possible.
  • a plasma processing apparatus having a plasma sheath modifier such as that illustrated in FIGs. 1 1-12, or other systems may be used to perform this selective implantation.
  • parts of the workpiece 100 are not implanted, such as the distance 106 between implanted regions 103A-103C.
  • the implanted regions 103A-1 G3C improve compound semiconductor growth on the workpiece 100 or make the compound semiconductor grow at an increased rate, Some compound semiconductor growth may occur between the implanted regions 103A-103C in one instance, but it may occur at a rate less than the growth on the implanted regions 103A-103C.
  • FIG. 3 is a cross-sectional side view of a third embodiment of implantation into a workpiece.
  • the ions 102 only implant the implanted regions i lOA-l 10F, Thus, these implanted regions 1 lOA-11 OF are smaller than a dimension of the devices 104A-104C.
  • the implanted regions 1 lOA-1 1 OF may have a width 111 of approximately 20 ⁇ while the devices 104A-104C may have a width 105 of approximately 300 ⁇ , though other dimensions are possible.
  • a plasma processing apparatus having a plasma sheath modifier, such as that illustrated in FIGs. 1 1-12, or other systems may be used to perform this selective implantation. Such a selective implantation may improve ELOG and the plasma sheath modifier, such as that illustrated in FIGs. 1 1-12, or other systems may be used to perform this selective implantation. Such a selective implantation may improve ELOG and the plasma sheath modifier, such as that illustrated in FIGs. 1 1-12, or other systems may be used to
  • subsequently-grown compound semiconductor may be of higher quality. This also may enable ELOG within a single device.
  • the implanted regions 1 1 OA- 1 IOC can improve, reduce, or prevent compound semiconductor growth on the workpiece 100. Thus, the compound semiconductor growth may be at a slower rate over the implanted regions 11 OA- 1 IOC in one instance.
  • One possible mechanism that reduces or prevents compound semiconductor growth is that the compound semiconductor will preferentially deposit on a crystalline portion of the workpiece 100 compared to an amorphous portion of the workpiece 100, An implant may cause amorphization of the workpiece 100.
  • Another possible mechanism that reduces or prevents compound semiconductor growth relates to using a species that interferes with the nucleation of the compound semiconductor. F, CI, C, or metals may have this effect.
  • F, CI, C, or metals may have this effect.
  • FIG. 4 is a cross-sectional side view of a fourth embodiment of implantation into a workpiece.
  • a blanket implant of the entire workpiece 100 is performed. but a proximity mask 1 12 positioned above or a distance from the workpieee 100 is used to block a portion of the ions 102, Thus, the apertures 113 in the proximity mask 112 correspond with the desired implanted regions 103A-103C.
  • the devices 104A-1G4C may have a width 105 of approximately 300 ⁇ and may be separated by a distance 106 of approximately 100 ⁇ , though other dimensions are possible, The distance 106 may not correspond exactly with the dimensions of the proximity mask 112 and the width 105 may not correspond exactly with the dimensions of the aperture 113 due to the angles of the ions 102.
  • the implanted regions 103A-103C may correspond with the location of the devices 104A- 104C that are formed during later processing steps.
  • a beamline ion implanter, plasma doping implanter, or other plasma system may be used with the proximity mask 112,
  • FIG. 5 is a cross-sectional side view of a fifth embodiment of implantation into a workpieee.
  • the apertures 113 in the proximity mask 1 12 are configured such that the ions 102 implant only a portion of the areas under the devices 104 A- 104C during the blanket implant of the workpieee 100.
  • these implanted regions 1 lOA-110F are smaller than a dimension of the devices 104A-104C.
  • the implanted regions 1 lOA-1 IGF may have a width 1 11 of approximately 20 ⁇ while the devices 104A-104C may have a width 105 of approximately 300 ⁇ , though other dimensions are possible.
  • the width 111 may not correspond exactly with the dimensions of the aperture 113 due to the angles of the ions 102.
  • a beamline ion implanter, plasma doping implanter, or other plasma system may be used with the proximity mask.
  • FIG. 6 is a cross-sectional side view of a sixth embodiment of implantation into a workpieee.
  • the regions between the devices 104A-104C are implanted.
  • the ions 102 form the implanted regions 114A-1 14D, These implanted regions 114A- 1 14D may prevent or reduce GaN growth between the devices 104A-104C during formation of these devices 104A-104C.
  • a patterned implant of the ions 102 is illustrated, a proximity mask also may be used. This may be combined with a blanket implant (to increase or reduce GaN growth) or other embodiments disclosed herein.
  • the compound semiconductor is grown on the surface of the workpieee 100, but this growth may be at a reduced rate over the implanted regions 1 14A-114D compared to between the implanted regions 114A-1 14D. In another embodiment, compound semiconductor growth over the implanted regions 114A-1 14D is prevented but growth between the implanted regions 1 14A-114D still occurs,
  • FIG . 7 is a top perspective view of a seventh embodiment of an implanted workpieee.
  • multiple implant steps are performed.
  • a series of lines are implanted in the workpieee to form the implanted regions 1 15A-1 15D, which may be similar to the implant illustrated in FIG. 6 that forms the implanted regions 114A-114D.
  • the workplace 100 is then rotated, for example, 90" and a second series of lines are implanted in the workpiece 100 to form the implanted regions 116A-116D (which are shaded in FIG, 7).
  • other rotation amounts such as 60°, are possible.
  • implanted regions 1 15A- 1 15D and implanted regions 116A-116D overlap, "islands” or “blocks” (represented by the spaces i 17) that may not he implanted are surrounded by implanied “streets” (represented by the implanted regions 1 15A-I 15D and implanted regions 116A-116D).
  • the implanted regions 115A-U 5D and implanted regions 1 16A-I 16D may prevent or reduce growth of the , compound semiconductor.
  • the crystal regions will meet within such a region 117, as represented by the X within each region 117. While the X is illustrated, there may be variation due to non-uniform deposition and the actual pattern of the crystal regions may vary.
  • the defects are reduced and localized in the compound semiconductor, which leads to a higher quality layer of a compound semiconductor, such as GaN.
  • the spaces 117 may have a dimension 119 of approximately 100 to 500 ⁇ .
  • the implanted regions 115A-115D or implanted regions 1 16A-116D may have a width 118 of approximately 10 to 100 ⁇ , Of course, other dimensions are possible.
  • the whole surface of the workpiece 100 is implanted.
  • the implanted regions 115A-1 15D and implanted regions 116A-116D may be implanted with, for example, Ar and the spaces 117 may be implanted with, for example, N.
  • Other embodiments or combination of species is possible. This may be performed using either two or more patterned implants or using a blanket implant (as illustrated in FIG, 1) to implant the spaces 117 with one or more patterned implant to form the implanted regions 115A-1 15D and implanted regions 1 16A-1 16D.
  • a blanket N implant can be combined with two patterned Ar implants to form the structure shown in FIG. 7. The workpiece 100 is rotated between these two Ar implants.
  • the quality and growth rate of epitaxially-grown GaN on sapphire can be controlled by selection of the implant species. For example, N, Al, or O enhance GaN growth on sapphire while Ar prevents or reduces GaN growth on sapphire. Implanting Al, N, or O can change the stoichiometry on the surface of the sapphire workpiece. For example, i f GaN is grown on a sapphire workpiece, the N implant will add N to the sapphire workpiece surface. A1N may have a better match to GaN than sapphire in terms of lattice constant or size.
  • Implanting Ar may change the stoichiometry by preferential sputtering of Al over the O on the sapphire surface, for example. High doses of some species, such as doses above
  • 1E17 cm -2 may prevent or reduce compound semiconductor growth if amorphization occurs on the workpiece. Smaller ions, such as H or He, also may prevent or reduce compound semiconductor growth if amorphization occurs. A dose smaller than 1E17 cm -2 may be used to amorphize a workpiece and prevent or reduce compound semiconductor growth with other noble gases larger than Ar.
  • two sapphire workpieces were implanted at 40 keV and lE17cm -2 using Ar and N, respectively. GaN successively grew on the N-implanted workpiece, while Ar caused pitting in the GaN growth.
  • the dose or either N or Ar may be optimized for improved GaN growth or reduction in growth. For example, an N dose below approximately 1E1.7 cm -2 may improve GaN growth.
  • other species besides N or Ar may be used, P, As, or other species also may enhance GaN growth.
  • Other noble gases, H, O, A1, C, or other species also may prevent or reduce GaN growth.
  • noble gases such as Ar, Xe, and Kr may prevent growth of GaN .
  • O or N may form Sii ⁇ or SiN regions in a silicon workpiece during an anneal, which also may prevent growth of GaN. These species also may have similar effects on other workpiece materials or with other compound semiconductors,
  • Compound semiconductor growth, such as GaN growth, on a silicon workpiece also may be enhanced by implanting C or Ge, This may form SiC or SiGe during an anneal. These SiC or SiGe regions modify the lattice parameter of the silicon and may allow better lattice matching to the GaN.
  • Effects on the surface of the workpiece also may enhance, reduce, or prevent growth of a compound semiconductor
  • a 0,5 keV Ar implant into a silicon workpiece with a dose of 5E16 cm -2 has been shown to sputter approximately 100 ran away from the workpiece.
  • this is further increased when using a focused beam because the sputter yield may increase as the angle of incidence of the ions increases toward 60 degrees. This may produce a textured workpiece.
  • this surface topography modification also may affect, the growth of the compound
  • the textured surface caused by sputtering will enhance compound semiconductor growth on the workpiece.
  • FIG. 8 is a cross-sectional side view of an eighth embodiment of an implanted workpiece.
  • the workpiece 100 which also may include a blanket buffer layer (not illustrated), is implanted using a proximity mask or patterned implant as previously described,
  • the implanted regions 114A-1 14C and implanted regions 1 lOA-110D are designed to reduce or prevent GaN growth.
  • These implanted regions 1 14A-114C and implanted regions 1 10A- 110D may be implanted with Ar.
  • a compound semiconductor, such as GaN is grown between these implanted areas to form devices 104A and 104B, which may be LEDs. Defect lines or voids 120 form above the implanted regions 11 OA-1 10D.
  • FIG. 9 is a perspective view of a ninth embodiment of an implanted workplace. This embodiment may correspond to the embodiment illustrated in FIG. 8.
  • the workpiece 100 is implanted.
  • the implanted regions 3 14, of which only one is pointed out in FIG. 9, separate multiple spaces 1 17.
  • the compound semiconductor preferentially grows in the spaces 117 between the implanted regions 114 because the implanted regions 114 are configured to reduce or prevent growth of a compound semiconductor.
  • At least one space 117 has at least one implanted regions 110, of which only one is pointed out in FIG. 9.
  • the implanted regions 1 14 and 1 10 are configured to reduce or prevent growth of GaN.
  • the spaces J 17 may be implanted in one instance to improve growth of GaN.
  • other implant patterns are possible from that illustrated in FIG. 9,
  • FIG. 10 is a top perspective view of a tenth embodiment of an implanted workpiece.
  • the periphery 121 (shaded in FIG. 10) of the workpiece 100 is implanted to reduce or prevent compound semiconductor growth.
  • GaN or another compound semiconductor may grow thicker or at a faster rate at this periphery 121 than in the center 122.
  • the lattice constant of, for example, GaN may be smaller than that of the sapphire or silicon in a workpiece 100.
  • the GaN deposits under significant strain at the center 122 of the workpiece 100.
  • the GaN deposits more freely or is less constrained and forms an initial layer more quickly.
  • GaN gallium arsphide
  • additional Ga and N atoms deposit more freely on the GaN at the periphery 123 of the workpiece 100 than filling the center 122 of the workpiece 100.
  • This forms a thicker outer layer of GaN on the workpiece 100.
  • This effect may disappear when a sufficiently thick layer of GaN, such as greater than approximately 100 nm, is formed on the entire surface of the workpiece 100, but the workpiece 100 may stiil have an uneven layer of GaN due to the initial GaN growth at the periphery 121 .
  • the resulting thicker GaN at the periphery 123 may lead to cracking because of the increased stresses caused by the difference in thickness.
  • the implant at the periphery 321 is configured to reduce compound semiconductor growth so that this compound semiconductor growth is equal on both the periphery 123 and center 322. This results in a workpiece 100 having a compound semiconductor layer with an approximately equal or uniform thickness.
  • the implant at the periphery 121 is configured to totally prevent compound semiconductor growth on the periphery 121.
  • the workpiece 100 is rotated 360° under a fixed ion beam that has a width of the implanted area at the periphery 121.
  • the periphery 121 that is implanted has a width of
  • This implant into the periphery 123 may be combined with other implants, such as the resulting implanted workpiece 100 of FIG.
  • the workplaces may have a blanket implant performed across the entire surface of the workpiece prior to the patterned implant. This may be have a different dose, energy, or species from a pattenied implant. The blanket implant may improve compound semiconductor growth.
  • the compound semiconductor may be grown in a plasma cluster tool. This may be the same tool where the implants were performed or it may be operatively linked to the tool where the implants were performed. Vacuum may not be broken around the workpiece if the tools are operatively linked, which reduces oxide layers, contamination of workpieces, and increases throughput. Ion beam assisted deposition (IBAD) also may assist in GaN growth.
  • IBAD Ion beam assisted deposition
  • FIG. 11 is a block diagram of a plasma processing apparatus having a plasma sheath modifier.
  • the plasma 140 is generated as is known in the art.
  • This plasma 140 is generally a quasi-neutral collection of ions and electrons.
  • the ions typically have a positive charge while the electrons have a negative charge.
  • the plasma 140 may have an electric field of, for example, approximately 0 V/cm in the bulk of the plasma 140.
  • ions 102 from the plasma 140 are attracted toward a workpiece 100. These ions 102 may be attracted with sufficient energy to be implanted into the workpiece 100.
  • the plasma 140 is bounded by a region proximate the workpiece 100 referred to as a plasma sheath 242.
  • the plasma sheath 242 is a region that has fewer electrons than the plasma 140. Hence, the differences between the negative and positive charges cause a sheath potential in the plasma sheath 242. The light emission from this plasma sheath 242 is less intense than the plasma 140 because fewer electrons are present and, hence, few excitation-relaxation collisions occur. Thus, the plasma sheath 242 is sometimes referred to as "dark space.”
  • the plasma sheath modifier 101 is configured to modify an electric field within the plasma sheath 242 to control a shape of a boundary 241 between the plasma 140 and the plasma sheath 242. Accordingly, ions 102 that are attracted from the plasma 140 across the plasma sheath 242 may strike the workpiece 100 at a large range of incident angles.
  • This plasma sheath modifier 101 may be referred to as, for example, a focusing plate or sheath engineering plate.
  • the plasma sheath modifier 101 includes a pair of panels 212 and 214 defining an aperture there between having a horizontal spacing (G).
  • the panels 212 and 214 may be an insulator, semiconductor, or conductor. In other embodiments, the plasma sheath modifier 101 may include only one panel or more than two panels.
  • the panels 212 and 214 may be a pair of sheets having a thin, flat shape. In other embodiments, the panels 212 and 214 may be other shapes such as tube-shaped, wedge-shaped, and/or have a beveled edge proximate the aperture.
  • the panels 212 and 214 also may be positioned a vertical spacing (Z) above the plane 151 defined by the front surface of the workpiece 100. In one embodiment the vertical spacing (Z) may be about 1.0 to 10.0 mm.
  • Ions 102 may be attracted from the plasma 140 across the plasma sheath 242 by different mechanisms.
  • the workpiece 100 is biased to attract ions 102 from the plasma 140 across the plasma sheath 242.
  • a plasma source thai generates the plasma 140 and walls surrounding the plasma 140 are biased positively and the workpiece 100 may be grounded.
  • the biasing may be pulsed in one particular embodiment.
  • electric or magnetic fields are used to attract ions 102 from the plasma 140 toward the workpiece 100.
  • the plasma sheath modifier 101 modifies the electric field within the plasma sheath 242 to control a shape of the boundary 241 between the plasma 140 and the plasma sheath 242,
  • the boundary 241 between the plasma 140 and the plasma sheath 242 may have a convex shape relative to the plane 151 in one instance.
  • the ions 102 are attracted across the plasma sheath 242 through the aperture between the panels 212 and 214 at a large range of incident angles.
  • ions 102 following trajectory path 271 may strike the workpiece 100 at an angle of +0 ° relative to the plane 151.
  • Ions 102 following trajectory path 270 may strike the workpiece 100 at about an angle of 0 ° relative to the same plane 151.
  • Ions 102 following trajectory path 269 may strike the workpiece 100 an angle of relative to the plane 151. Accordingly, the range of incident angles may be between + ⁇ " and -8° centered about 0°. In addition, some ion trajectories paths such as paths 269 and 271 may cross each other. Depending on a number of factors including, but not limited to, the horizontal spacing (G) between the panels 212 and 214, the vertical spacing (Z) of the panels 212 and 214 above the plane 151, the dielectric constant of the panels 212 and 214, or other process parameters of the plasma 140, the range of incident angles ( ⁇ ) may be between +60° and -60° centered about 0".
  • FIG. 12 is a side view of an embodiment of selective ion implantation, implanted regions 103 are formed in the workpiece 100 using the ions 102.
  • the workpiece 100 is scanned with respect to the plasma sheath modifier 101 or ions 102, as illustrated by the arrow 108. This may involve moving the plasma sheath modifier 101 , workpiece 100, or both. The scanning may be in one dimension or two dimensions.
  • the workpiece 100 is biased when the ions 102 implant the implanted regions 103.
  • the bias scheme is adjusted to produce the desired pattern of implanted regions 103.
  • the workpiece 100 is not biased when the ions 102 would implant between the implanted regions 103.
  • the implanted regions 303 may be formed without a mask or photoresist layer on the workplace 100. Alignment, lithography, or photoresist removal steps may be eliminated.
  • the location of the implanted regions 103 may be carefully controlled because spacing of the implanted regions 103 may affect growth of the GaN or another compound semiconductor during ELOG. This spacing may be optimized for the improved compound semiconductor growth.
  • the dose rate and focus of the ions i 02 can be varied to form the implanted regions 103.
  • the ions 102 may be switched on and off to form the implanted regions 103, the dose of the ion 102 may be adjusted to reduce implantation between the implanted regions 103, or the ions 102 may be focused when implanting the implanted regions 103. if the ions 102 are focused when implanting the implanted regions 103, the ions 102 may be less focused over other parts of the workpiece 100, which reduces implantation between the implanted regions 103.

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Vapour Deposition (AREA)
  • Led Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)

Abstract

A workpiece is implanted to affect growth of a compound semiconductor, such as GaN, implanted regions of a workpiece increase, reduce, or prevent growth of this compound semiconductor. Combinations of implants may be performed to cause increased growth in certain regions of the workpiece, such as between regions where growth is reduced. Growth also may be reduced or prevented at the periphery of the workpiece.

Description

IMPROVED COMPOUND SEMICONDUCTOR GROWTH USING ION
IMPLANTATION
FIELD
This invention relates to ion implantation and, more particularly, to ion implantation to improve the quality of a layer grown on a workpiece.
BACKGROUND
Ion implantation is a standard technique for introducing material into a workpiece. A desired implant material is ionized in an ion source, the ions are accelerated to form an ion beam of prescribed energy, and the ion beam is directed at the surface of the workpiece, The energetic ions in the ion beam penetrate into the bulk of the workpiece material and affect both the surface and depth of the workpiece material under certain conditions.
Gallium nitride (GaN) is a material commonly grown on workpieces. GaN is becoming more important for use in light-emitting diodes (LEDs), power transistors, and solid state lasers. The ability to grow high-quality GaN is one limiting factor to improving the quality and lowering the cost of these devices. One method of improving the quality of epitaxialiy-grown GaN is known as epitaxial layer overgrowth (ELOG). For ELOG, a layer of GaN is gro wn, hard mask windows of SiO? or SixNY are deposited, and then the high- quality GaN is grown. In some instances, deposition of the hard mask requires removal of the workpiece from the MOCVD tool and then reintroduction of the workpiece to the MOCVD tool after a lithography step, photoresist application, deposition, and photoresist removal. This particular process is cumbersome and costly. Repeated ELOG sequences add even more cost.
ELOG of GaN on silicon, sapphire, SiC, AiN, GaN, or other workpieces can be accomplished using implantation instead of Si02 or SixNy deposition, Previously, photoresist was used to mask part of the silicon workpiece and implantation was performed on the unmasked areas. GaN grew laterally over the implanted areas. However, this process is still fairly complex, The use of photoresist adds extra steps, which increases manufacturing costs. What is needed is a faster, less complex, and lower cost method of growing high-quality compound semiconductor layers.
SUMMARY
According to a first aspect of the invention, a method of workpiece processing is provided. The method comprises implanting a first plurality of implanted regions in a workpiece with a first species. A compound semiconductor is grown on the workpiece after the implanting. The compound semiconductor growth is reduced on the first plurality of implanted regions compared to between the first plurality of implanted regions. At least one device is formed between the first plurality of implanted regions.
According to a second aspect of the invention, a method of workpiece processing is provided. The method comprises implanting a second plurality of regions in a workpiece. A compound semiconductor is grown on the workpiece after the implanting. The compound semiconductor growth is increased on the plurality of implanted regions compared to between the plurality of implanted regions,
According to a third aspect of the invention, a method of workpiece processing is provided, The method comprises implanting a periphery of a workpiece, A compound semiconductor is grown on the workpiece after the implanting. The growth is reduced on the periphery.
BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the present disclosure, reference is made to the accompanying drawings, which are incorporated herein by reference and in which:
FIG, 1 is a cross-sectional side view of a first embodiment of implantation into a workpiece;
FIG. 2 is a cross-sectional side view of a second embodiment of implantation into a workpiece;
FIG. 3 is a cross-sectional side view of a third embodiment of implantation into a workpiece;
FIG. 4 is a cross-sectional side view of a fourth embodiment of implantation into a workpiece;
FIG . 5 is a top perspective view of a fifth embodiment of implantation into a workpiece;
FIG. 6 is a cross-sectional side view of a sixth embodiment of implantation into a workpiece;
FIG, 7 is a top perspective view of a seventh embodiment of an implanted workpiece; FIG. 8 is a cross-sectional side vie w of an eighth embodiment of an implanted workpiece;
FIG. 9 is a perspective view of a ninth embodiment of an implanted workpiece; FIG. 10 is a top perspective view of a tenth embodiment of an implanted workpiece; FIG. 1 1 is a block diagram of a plasma processing apparatus having a plasma sheath modifier; and
FIG. 12 is a side view of an embodiment of selective ion implantation. DETAILED DESCRIPTION
The embodiments are described herein in connection with formation of a compound semiconductor such as GaN, but these embodiments also may be used with other III/V compound semiconductors, Ii/Vi compound semiconductors, or other materials known to a person skilled in the art, While specific types of implanters are disclosed, other ion implantation systems known to those skilled in the art that can focus an ion beam or that can implant particular regions of a workpiece with or without a mask on the workpiece may he used in the embodiments described herein. While LEDs are specifically disclosed, other devices also may benefit from the embodiments described herein. The workpieces herein may be silicon, sapphire, AIM, GaN, other compound semiconductors, or other materials and include a coating or other layers in some instances. Any implant dimensions are exemplary and other dimensions are possible. Thus, the invention is not limited to the specific embodiments described below,
FIG. 1 is a cross-sectional side view of a first embodiment of implantation into a workpiece, In this embodiment, a blanket implant is performed over the entire surface of the workpiece 100 using the ions 1 02 (illustrated by the arrows). The implanted region 109 is formed in the workpiece 100. The devices 1 Q4A-104C. which may be GaN or some other compound semiconductor, are then grown on top of this workpiece 100 after the implantation is completed. The devices 104 A- KMC are shown with doited lines in FIG. 1 because these devices 104A-104C were not formed prior to the blanket implant. These devices 104A-104C may have a width 105 of approximately 300 μηι in one embodiment, though these devices 104A-104C may be between 100 μηι to 3000 μηι in dimension. Of course, other dimensions are possible, A distance 106 of approximately 100 um may separate each pair of devices 104A-104C in one instance. The distance 106 also may be between 10 um to 300 um or other distances known to those skilled in the art.
The blanket implant that forms the implanted region 109 improves compound semiconductor growth, such as the growth of GaN. This blanket implant can be combined with a selective or patterned implant, as seen separately in other embodiments herein. The blanket implant and patterned implants can be performed in either order. One possible mechanism that causes the improved growth is that the implant changes the stoichiometry on the surface of the workpiece 100 or relieves the lattice mismatch between the workpiece 100 and the compound semiconductor. Stoichiometry is changed by either adding particular elements through implantation or by preferential sputtering of the elements from the workpiece. For example, preferentially sputtering Ai or O in a sapphire workpiece 100, depending on implant species, energy, angle, and dose, may affect the stoichiometry of the workpiece 100. Of course, other mechanisms are possible. FIG. 2 is a cross-sectional side view of a second embodiment of implantation into a workpiece. in this embodiment, the workpiece 100 is implanted using ions 102 in the implanted regions 103A-103C. Devices 104A-104C are formed on the implanted regions 103A-103C during a later processing step. These devices 104A-104C may have a width 105 of approximately 300 urn and may be separated by a distance 106 of approximately 100 μτη, though other dimensions are possible. A plasma processing apparatus having a plasma sheath modifier, such as that illustrated in FIGs. 1 1-12, or other systems may be used to perform this selective implantation. Thus, parts of the workpiece 100 are not implanted, such as the distance 106 between implanted regions 103A-103C. The implanted regions 103A-1 G3C improve compound semiconductor growth on the workpiece 100 or make the compound semiconductor grow at an increased rate, Some compound semiconductor growth may occur between the implanted regions 103A-103C in one instance, but it may occur at a rate less than the growth on the implanted regions 103A-103C.
FIG. 3 is a cross-sectional side view of a third embodiment of implantation into a workpiece. In this embodiment, only a portion of the areas under the devices 104A-104C are implanted. The ions 102 only implant the implanted regions i lOA-l 10F, Thus, these implanted regions 1 lOA-11 OF are smaller than a dimension of the devices 104A-104C. For example, the implanted regions 1 lOA-1 1 OF may have a width 111 of approximately 20 μηι while the devices 104A-104C may have a width 105 of approximately 300 μηι, though other dimensions are possible. Again, a plasma processing apparatus having a plasma sheath modifier, such as that illustrated in FIGs. 1 1-12, or other systems may be used to perform this selective implantation. Such a selective implantation may improve ELOG and the
subsequently-grown compound semiconductor may be of higher quality. This also may enable ELOG within a single device. The implanted regions 1 1 OA- 1 IOC can improve, reduce, or prevent compound semiconductor growth on the workpiece 100. Thus, the compound semiconductor growth may be at a slower rate over the implanted regions 11 OA- 1 IOC in one instance.
One possible mechanism that reduces or prevents compound semiconductor growth is that the compound semiconductor will preferentially deposit on a crystalline portion of the workpiece 100 compared to an amorphous portion of the workpiece 100, An implant may cause amorphization of the workpiece 100. Another possible mechanism that reduces or prevents compound semiconductor growth relates to using a species that interferes with the nucleation of the compound semiconductor. F, CI, C, or metals may have this effect. Of course, other mechanisms are possible,
FIG. 4 is a cross-sectional side view of a fourth embodiment of implantation into a workpiece. In this embodiment, a blanket implant of the entire workpiece 100 is performed. but a proximity mask 1 12 positioned above or a distance from the workpieee 100 is used to block a portion of the ions 102, Thus, the apertures 113 in the proximity mask 112 correspond with the desired implanted regions 103A-103C. The devices 104A-1G4C may have a width 105 of approximately 300 μτη and may be separated by a distance 106 of approximately 100 μηι, though other dimensions are possible, The distance 106 may not correspond exactly with the dimensions of the proximity mask 112 and the width 105 may not correspond exactly with the dimensions of the aperture 113 due to the angles of the ions 102. The implanted regions 103A-103C may correspond with the location of the devices 104A- 104C that are formed during later processing steps. A beamline ion implanter, plasma doping implanter, or other plasma system may be used with the proximity mask 112,
FIG. 5 is a cross-sectional side view of a fifth embodiment of implantation into a workpieee. In this embodiment, the apertures 113 in the proximity mask 1 12 are configured such that the ions 102 implant only a portion of the areas under the devices 104 A- 104C during the blanket implant of the workpieee 100. Thus, these implanted regions 1 lOA-110F are smaller than a dimension of the devices 104A-104C. For example, the implanted regions 1 lOA-1 IGF may have a width 1 11 of approximately 20 μιη while the devices 104A-104C may have a width 105 of approximately 300 μτη, though other dimensions are possible. The width 111 may not correspond exactly with the dimensions of the aperture 113 due to the angles of the ions 102. A beamline ion implanter, plasma doping implanter, or other plasma system may be used with the proximity mask.
FIG. 6 is a cross-sectional side view of a sixth embodiment of implantation into a workpieee. In this embodiment, the regions between the devices 104A-104C are implanted. Thus, the ions 102 form the implanted regions 114A-1 14D, These implanted regions 114A- 1 14D may prevent or reduce GaN growth between the devices 104A-104C during formation of these devices 104A-104C. While a patterned implant of the ions 102 is illustrated, a proximity mask also may be used. This may be combined with a blanket implant (to increase or reduce GaN growth) or other embodiments disclosed herein. In one embodiment, the compound semiconductor is grown on the surface of the workpieee 100, but this growth may be at a reduced rate over the implanted regions 1 14A-114D compared to between the implanted regions 114A-1 14D. In another embodiment, compound semiconductor growth over the implanted regions 114A-1 14D is prevented but growth between the implanted regions 1 14A-114D still occurs,
FIG . 7 is a top perspective view of a seventh embodiment of an implanted workpieee. In this particular embodiment, multiple implant steps are performed. First, a series of lines are implanted in the workpieee to form the implanted regions 1 15A-1 15D, which may be similar to the implant illustrated in FIG. 6 that forms the implanted regions 114A-114D. The workplace 100 is then rotated, for example, 90" and a second series of lines are implanted in the workpiece 100 to form the implanted regions 116A-116D (which are shaded in FIG, 7). Of course, other rotation amounts, such as 60°, are possible. These implanted regions 1 15A- 1 15D and implanted regions 116A-116D overlap, "islands" or "blocks" (represented by the spaces i 17) that may not he implanted are surrounded by implanied "streets" (represented by the implanted regions 1 15A-I 15D and implanted regions 116A-116D). The implanted regions 115A-U 5D and implanted regions 1 16A-I 16D may prevent or reduce growth of the , compound semiconductor. During compound semiconductor growth, the crystal regions will meet within such a region 117, as represented by the X within each region 117. While the X is illustrated, there may be variation due to non-uniform deposition and the actual pattern of the crystal regions may vary. The defects are reduced and localized in the compound semiconductor, which leads to a higher quality layer of a compound semiconductor, such as GaN. The spaces 117 may have a dimension 119 of approximately 100 to 500 μηι. The implanted regions 115A-115D or implanted regions 1 16A-116D may have a width 118 of approximately 10 to 100 μπι, Of course, other dimensions are possible.
In one particular embodiment, the whole surface of the workpiece 100 is implanted. The implanted regions 115A-1 15D and implanted regions 116A-116D may be implanted with, for example, Ar and the spaces 117 may be implanted with, for example, N. Other embodiments or combination of species is possible. This may be performed using either two or more patterned implants or using a blanket implant (as illustrated in FIG, 1) to implant the spaces 117 with one or more patterned implant to form the implanted regions 115A-1 15D and implanted regions 1 16A-1 16D. For example, a blanket N implant can be combined with two patterned Ar implants to form the structure shown in FIG. 7. The workpiece 100 is rotated between these two Ar implants.
The quality and growth rate of epitaxially-grown GaN on sapphire can be controlled by selection of the implant species. For example, N, Al, or O enhance GaN growth on sapphire while Ar prevents or reduces GaN growth on sapphire. Implanting Al, N, or O can change the stoichiometry on the surface of the sapphire workpiece. For example, i f GaN is grown on a sapphire workpiece, the N implant will add N to the sapphire workpiece surface. A1N may have a better match to GaN than sapphire in terms of lattice constant or size.
Implanting Ar may change the stoichiometry by preferential sputtering of Al over the O on the sapphire surface, for example. High doses of some species, such as doses above
1E17 cm-2 may prevent or reduce compound semiconductor growth if amorphization occurs on the workpiece. Smaller ions, such as H or He, also may prevent or reduce compound semiconductor growth if amorphization occurs. A dose smaller than 1E17 cm-2 may be used to amorphize a workpiece and prevent or reduce compound semiconductor growth with other noble gases larger than Ar.
In one instance, two sapphire workpieces were implanted at 40 keV and lE17cm-2 using Ar and N, respectively. GaN successively grew on the N-implanted workpiece, while Ar caused pitting in the GaN growth. The dose or either N or Ar may be optimized for improved GaN growth or reduction in growth. For example, an N dose below approximately 1E1.7 cm-2 may improve GaN growth. Of course, other species besides N or Ar may be used, P, As, or other species also may enhance GaN growth. Other noble gases, H, O, A1, C, or other species also may prevent or reduce GaN growth. For silicon workpieces, noble gases such as Ar, Xe, and Kr may prevent growth of GaN . O or N may form Siiな or SiN regions in a silicon workpiece during an anneal, which also may prevent growth of GaN. These species also may have similar effects on other workpiece materials or with other compound semiconductors,
Compound semiconductor growth, such as GaN growth, on a silicon workpiece also may be enhanced by implanting C or Ge, This may form SiC or SiGe during an anneal. These SiC or SiGe regions modify the lattice parameter of the silicon and may allow better lattice matching to the GaN.
Effects on the surface of the workpiece also may enhance, reduce, or prevent growth of a compound semiconductor, For example, a 0,5 keV Ar implant into a silicon workpiece with a dose of 5E16 cm-2 has been shown to sputter approximately 100 ran away from the workpiece. Thus, this is further increased when using a focused beam because the sputter yield may increase as the angle of incidence of the ions increases toward 60 degrees. This may produce a textured workpiece. Besides the chemical effects from the ion implantation, this surface topography modification also may affect, the growth of the compound
semiconductor. In one instance, the textured surface caused by sputtering will enhance compound semiconductor growth on the workpiece.
FIG. 8 is a cross-sectional side view of an eighth embodiment of an implanted workpiece. The workpiece 100, which also may include a blanket buffer layer (not illustrated), is implanted using a proximity mask or patterned implant as previously described, The implanted regions 114A-1 14C and implanted regions 1 lOA-110D are designed to reduce or prevent GaN growth. These implanted regions 1 14A-114C and implanted regions 1 10A- 110D may be implanted with Ar. A compound semiconductor, such as GaN, is grown between these implanted areas to form devices 104A and 104B, which may be LEDs. Defect lines or voids 120 form above the implanted regions 11 OA-1 10D. These may encourage ELOG to occur within the individual devices 104 A and I04B. Selective area growth (SAG) may occur between the devices 104 A and 104B. FIG. 9 is a perspective view of a ninth embodiment of an implanted workplace. This embodiment may correspond to the embodiment illustrated in FIG. 8. The workpiece 100 is implanted. The implanted regions 3 14, of which only one is pointed out in FIG. 9, separate multiple spaces 1 17. The compound semiconductor preferentially grows in the spaces 117 between the implanted regions 114 because the implanted regions 114 are configured to reduce or prevent growth of a compound semiconductor. At least one space 117 has at least one implanted regions 110, of which only one is pointed out in FIG. 9. The implanted regions 1 14 and 1 10 are configured to reduce or prevent growth of GaN. The spaces J 17 may be implanted in one instance to improve growth of GaN. Of course, other implant patterns are possible from that illustrated in FIG. 9,
FIG. 10 is a top perspective view of a tenth embodiment of an implanted workpiece. The periphery 121 (shaded in FIG. 10) of the workpiece 100 is implanted to reduce or prevent compound semiconductor growth. During a growth process, GaN or another compound semiconductor may grow thicker or at a faster rate at this periphery 121 than in the center 122. The lattice constant of, for example, GaN may be smaller than that of the sapphire or silicon in a workpiece 100. Thus, the GaN deposits under significant strain at the center 122 of the workpiece 100. At the periphery 321 of the workpiece 100, the GaN deposits more freely or is less constrained and forms an initial layer more quickly. Once the GaN is deposited, additional Ga and N atoms deposit more freely on the GaN at the periphery 123 of the workpiece 100 than filling the center 122 of the workpiece 100. This forms a thicker outer layer of GaN on the workpiece 100. This effect may disappear when a sufficiently thick layer of GaN, such as greater than approximately 100 nm, is formed on the entire surface of the workpiece 100, but the workpiece 100 may stiil have an uneven layer of GaN due to the initial GaN growth at the periphery 121 .
The resulting thicker GaN at the periphery 123 may lead to cracking because of the increased stresses caused by the difference in thickness. The implant at the periphery 321 is configured to reduce compound semiconductor growth so that this compound semiconductor growth is equal on both the periphery 123 and center 322. This results in a workpiece 100 having a compound semiconductor layer with an approximately equal or uniform thickness. Or, alternatively, the implant at the periphery 121 is configured to totally prevent compound semiconductor growth on the periphery 121. In one particular embodiment the workpiece 100 is rotated 360° under a fixed ion beam that has a width of the implanted area at the periphery 121. In one instance, the periphery 121 that is implanted has a width of
approximate 5 mm, though other dimensions are possible. This implant into the periphery 123 may be combined with other implants, such as the resulting implanted workpiece 100 of FIG. In one particular embodiment, the workplaces may have a blanket implant performed across the entire surface of the workpiece prior to the patterned implant. This may be have a different dose, energy, or species from a pattenied implant. The blanket implant may improve compound semiconductor growth.
In an alternate embodiment, the compound semiconductor may be grown in a plasma cluster tool. This may be the same tool where the implants were performed or it may be operatively linked to the tool where the implants were performed. Vacuum may not be broken around the workpiece if the tools are operatively linked, which reduces oxide layers, contamination of workpieces, and increases throughput. Ion beam assisted deposition (IBAD) also may assist in GaN growth.
FIG. 11 is a block diagram of a plasma processing apparatus having a plasma sheath modifier. The plasma 140 is generated as is known in the art. This plasma 140 is generally a quasi-neutral collection of ions and electrons. The ions typically have a positive charge while the electrons have a negative charge. The plasma 140 may have an electric field of, for example, approximately 0 V/cm in the bulk of the plasma 140. In a system containing the plasma 140, ions 102 from the plasma 140 are attracted toward a workpiece 100. These ions 102 may be attracted with sufficient energy to be implanted into the workpiece 100. The plasma 140 is bounded by a region proximate the workpiece 100 referred to as a plasma sheath 242. The plasma sheath 242 is a region that has fewer electrons than the plasma 140. Hence, the differences between the negative and positive charges cause a sheath potential in the plasma sheath 242. The light emission from this plasma sheath 242 is less intense than the plasma 140 because fewer electrons are present and, hence, few excitation-relaxation collisions occur. Thus, the plasma sheath 242 is sometimes referred to as "dark space."
The plasma sheath modifier 101 is configured to modify an electric field within the plasma sheath 242 to control a shape of a boundary 241 between the plasma 140 and the plasma sheath 242. Accordingly, ions 102 that are attracted from the plasma 140 across the plasma sheath 242 may strike the workpiece 100 at a large range of incident angles. This plasma sheath modifier 101 may be referred to as, for example, a focusing plate or sheath engineering plate.
In the embodiment of FIG. 11 , the plasma sheath modifier 101 includes a pair of panels 212 and 214 defining an aperture there between having a horizontal spacing (G). The panels 212 and 214 may be an insulator, semiconductor, or conductor. In other embodiments, the plasma sheath modifier 101 may include only one panel or more than two panels. The panels 212 and 214 may be a pair of sheets having a thin, flat shape. In other embodiments, the panels 212 and 214 may be other shapes such as tube-shaped, wedge-shaped, and/or have a beveled edge proximate the aperture. The panels 212 and 214 also may be positioned a vertical spacing (Z) above the plane 151 defined by the front surface of the workpiece 100. In one embodiment the vertical spacing (Z) may be about 1.0 to 10.0 mm.
Ions 102 may be attracted from the plasma 140 across the plasma sheath 242 by different mechanisms. In one instance, the workpiece 100 is biased to attract ions 102 from the plasma 140 across the plasma sheath 242. in another instance, a plasma source thai generates the plasma 140 and walls surrounding the plasma 140 are biased positively and the workpiece 100 may be grounded. The biasing may be pulsed in one particular embodiment. In yet another instance, electric or magnetic fields are used to attract ions 102 from the plasma 140 toward the workpiece 100.
Advantageously, the plasma sheath modifier 101 modifies the electric field within the plasma sheath 242 to control a shape of the boundary 241 between the plasma 140 and the plasma sheath 242, The boundary 241 between the plasma 140 and the plasma sheath 242 may have a convex shape relative to the plane 151 in one instance. When the workpiece 100 is biased, for example, the ions 102 are attracted across the plasma sheath 242 through the aperture between the panels 212 and 214 at a large range of incident angles. For instance, ions 102 following trajectory path 271 may strike the workpiece 100 at an angle of +0° relative to the plane 151. Ions 102 following trajectory path 270 may strike the workpiece 100 at about an angle of 0° relative to the same plane 151. Ions 102 following trajectory path 269 may strike the workpiece 100 an angle of relative to the plane 151. Accordingly, the range of incident angles may be between +Θ" and -8° centered about 0°. In addition, some ion trajectories paths such as paths 269 and 271 may cross each other. Depending on a number of factors including, but not limited to, the horizontal spacing (G) between the panels 212 and 214, the vertical spacing (Z) of the panels 212 and 214 above the plane 151, the dielectric constant of the panels 212 and 214, or other process parameters of the plasma 140, the range of incident angles (Θ) may be between +60° and -60° centered about 0".
FIG. 12 is a side view of an embodiment of selective ion implantation, implanted regions 103 are formed in the workpiece 100 using the ions 102. The workpiece 100 is scanned with respect to the plasma sheath modifier 101 or ions 102, as illustrated by the arrow 108. This may involve moving the plasma sheath modifier 101 , workpiece 100, or both. The scanning may be in one dimension or two dimensions. In one particular embodiment, the workpiece 100 is biased when the ions 102 implant the implanted regions 103. The bias scheme is adjusted to produce the desired pattern of implanted regions 103. Thus, the workpiece 100 is not biased when the ions 102 would implant between the implanted regions 103. This eliminates or reduces ions 102 from impacting between the implanted regions 103, In this manner, the implanted regions 303 may be formed without a mask or photoresist layer on the workplace 100. Alignment, lithography, or photoresist removal steps may be eliminated.
The location of the implanted regions 103 may be carefully controlled because spacing of the implanted regions 103 may affect growth of the GaN or another compound semiconductor during ELOG. This spacing may be optimized for the improved compound semiconductor growth.
The dose rate and focus of the ions i 02 can be varied to form the implanted regions 103. if the workpiece 100 is scanned, then the ions 102 may be switched on and off to form the implanted regions 103, the dose of the ion 102 may be adjusted to reduce implantation between the implanted regions 103, or the ions 102 may be focused when implanting the implanted regions 103. if the ions 102 are focused when implanting the implanted regions 103, the ions 102 may be less focused over other parts of the workpiece 100, which reduces implantation between the implanted regions 103.
The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. These other
embodiments and modifications are intended to fall within the scope of the present disclosure. Furthermore, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth befow should be construed in view of the full breadth and spirit, of the present disclosure as described herein.

Claims

What is claimed is:
1. A method of workpiece processing comprising:
implanting a first plurality of implanted regions in a workpiece with a first species; and
growing a compound semiconductor on said workpiece after said implanting, wherein said compound semiconductor growth is reduced on said first plurality of implanted regions compared to between said first plurality of implanted regions, wherein at least one device is formed between said first plurality of implanted regions.
2. The method of claim 1, wherein said first plurality of implanted regions form a grid and said compound semiconductor grows preferentially in spaces between said first plurality of implanted regions.
3. The method of claim 1, further comprising implanting a second plurality of
implanted regions in said workpiece, wherein each of said second plurality of implanted regions is between said first plurality of implanted regions.
4. The method of claim 1 , further comprising implanting a periphery of said
workpiece, wherein said growing is reduced on said periphery.
5. The method of claim 4, wherein said growing is reduced to zero on said periphery.
6. A method of workpiece processing comprising:
implanting a plurality of implanted regions in a workpiece; and
growing a compound semiconductor on said workpiece after said implanting, wherein said compound semiconductor growth is increased on said plurality of implanted regions compared to between said plurality of implanted regions.
7. The method of claim 6, wherein further comprising implanting a second plurality of implanted regions in said workpiece, wherein each of said plura lity of implanted regions is between said second plurality of implanted regions.
8. The method of claim 7, wherein said second plurality' of implanted regions form a grid and said compound semiconductor grows preferentially on said plurality of implanted regions between said second plurality of implanted regions,
9. The method of claim 6, further comprising implanting a periphery of said
workpiece, wherein said growing is reduced on said periphery.
10. The method of claim 9, wherein said growing is reduced to zero on said periphery.
11. The method of claim 6, wherein said implanting textures a surface of said
workpiece on said plurality' of implanted regions,
12. A method of workpiece processing comprising:
implanting a periphery of a workpiece; and
growing a compound semiconductor on said workpiece after said implanting, wherein said growing is reduced on said periphery.
13. The method of claim 12, wherein said growing is reduced to zero on said periphery.
14. The method of claim 12, wherein said growing on said periphery is reduced to be approximately equal to growing at a center of said workpiece whereby a thickness of said compound semiconductor is approximately equal across said workpiece.
15. The method of claim 12, wherein said implanting comprises rotating said
workpiece with respect to an ion beam during said implanting, whereby said ion beam only implants said periphery.
16. The method of claim 12, wherein further comprising implanting a first plurality of regions in said workpiece, wherein said compound semiconductor growth is reduced on said first plurality of implanted regions compared to between said first plurality of implanted regions.
17. The method of claim 16, wherein said first plurality of regions form a grid and said compound semiconductor grows preferentially in spaces between said first plurality of regions.
18. The method of claim 16, further comprising implanting a second plurality of
regions in said workpiece, wherein each of said second plurality of regions is between said first plurality of regions.
PCT/US2012/037811 2011-05-13 2012-05-14 Improved compound semiconductor growth using ion implantation Ceased WO2012158632A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201161486032P 2011-05-13 2011-05-13
US61/486,032 2011-05-13
US13/470,015 US9023722B2 (en) 2011-05-13 2012-05-11 Compound semiconductor growth using ion implantation
US13/470,015 2012-05-11

Publications (1)

Publication Number Publication Date
WO2012158632A1 true WO2012158632A1 (en) 2012-11-22

Family

ID=47142133

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2012/037811 Ceased WO2012158632A1 (en) 2011-05-13 2012-05-14 Improved compound semiconductor growth using ion implantation

Country Status (3)

Country Link
US (1) US9023722B2 (en)
TW (1) TW201250796A (en)
WO (1) WO2012158632A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9023722B2 (en) * 2011-05-13 2015-05-05 Varian Semiconductor Equipment Associates, Inc. Compound semiconductor growth using ion implantation
US20140367693A1 (en) * 2013-06-14 2014-12-18 Epistar Corporation Light-emitting device and the manufacturing method thereof
CN105102695B (en) * 2013-12-18 2018-06-12 日本碍子株式会社 Composite substrate and function element

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100323508A1 (en) * 2009-06-23 2010-12-23 Solar Implant Technologies Inc. Plasma grid implant system for use in solar cell fabrications

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10209506A (en) * 1997-01-24 1998-08-07 Rohm Co Ltd Manufacturing method of semiconductor light emitting device
US20050263854A1 (en) * 1998-10-23 2005-12-01 Shelton Bryan S Thick laser-scribed GaN-on-sapphire optoelectronic devices
WO2002013245A1 (en) * 2000-08-04 2002-02-14 The Regents Of The University Of California Method of controlling stress in gallium nitride films deposited on substrates
JP2002203806A (en) * 2000-10-31 2002-07-19 Toshiba Corp Method of manufacturing semiconductor device, stencil mask and method of manufacturing the same
US7105865B2 (en) * 2001-09-19 2006-09-12 Sumitomo Electric Industries, Ltd. AlxInyGa1−x−yN mixture crystal substrate
DE102004063691B4 (en) * 2004-05-10 2019-01-17 Hynix Semiconductor Inc. Method for implanting ions in a semiconductor device
US20060258128A1 (en) * 2005-03-09 2006-11-16 Peter Nunan Methods and apparatus for enabling multiple process steps on a single substrate
JP2006339534A (en) * 2005-06-03 2006-12-14 Sony Corp Light emitting diode, light emitting diode manufacturing method, light emitting diode backlight, light emitting diode illumination device, light emitting diode display, and electronic device
KR20060127743A (en) * 2005-06-06 2006-12-13 스미토모덴키고교가부시키가이샤 Nitride Semiconductor Substrate and Manufacturing Method Thereof
KR100699889B1 (en) * 2005-12-29 2007-03-28 삼성전자주식회사 Method for manufacturing semiconductor device with variable ion implantation conditions
US20100330787A1 (en) * 2006-08-18 2010-12-30 Piero Sferlazzo Apparatus and method for ultra-shallow implantation in a semiconductor device
US7528391B2 (en) * 2006-12-22 2009-05-05 Varian Semiconductor Equipment Associates, Inc. Techniques for reducing contamination during ion implantation
JP2008166660A (en) * 2007-01-05 2008-07-17 Matsushita Electric Ind Co Ltd Semiconductor manufacturing equipment
CA2641016A1 (en) * 2007-10-24 2009-04-24 Sumitomo Electric Industries, Ltd. Semi-insulating nitride semiconductor substrate and method of manufacturing the same, nitride semiconductor epitaxial substrate, and field-effect transistor
US20090317937A1 (en) * 2008-06-20 2009-12-24 Atul Gupta Maskless Doping Technique for Solar Cells
KR100988126B1 (en) * 2008-09-18 2010-10-18 고려대학교 산학협력단 Method for forming nitride semiconductor through ion implantation and light emitting diode manufactured using same
JP5311112B2 (en) * 2008-11-12 2013-10-09 日新イオン機器株式会社 Ion implantation method and ion implantation apparatus
US8330128B2 (en) * 2009-04-17 2012-12-11 Varian Semiconductor Equipment Associates, Inc. Implant mask with moveable hinged mask segments
US8101927B2 (en) * 2009-06-08 2012-01-24 Varian Semiconductor Equipment Associates, Inc. Masking apparatus for an ion implanter
US8173527B2 (en) * 2009-10-19 2012-05-08 Varian Semiconductor Equipment Associates, Inc. Stepped masking for patterned implantation
US8698104B2 (en) * 2009-11-09 2014-04-15 Varian Semiconductor Equipment Associates, Inc. System and method for handling multiple workpieces for matrix configuration processing
US20110143527A1 (en) * 2009-12-14 2011-06-16 Varian Semiconductor Equipment Associates, Inc. Techniques for generating uniform ion beam
US8187979B2 (en) * 2009-12-23 2012-05-29 Varian Semiconductor Equipment Associates, Inc. Workpiece patterning with plasma sheath modulation
US8592230B2 (en) * 2010-04-22 2013-11-26 Varian Semiconductor Equipment Associates, Inc. Method for patterning a substrate using ion assisted selective depostion
US9023722B2 (en) * 2011-05-13 2015-05-05 Varian Semiconductor Equipment Associates, Inc. Compound semiconductor growth using ion implantation
US8835287B2 (en) * 2011-05-13 2014-09-16 Varian Semiconductor Equipment Associates, Inc. Method of implanting a workpiece to improve growth of a compound semiconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100323508A1 (en) * 2009-06-23 2010-12-23 Solar Implant Technologies Inc. Plasma grid implant system for use in solar cell fabrications

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BUMJOON KIM ET AL: "Epitaxial Lateral Overgrowth of GaN on Si (111) Substrates Using High-dose, N<+> Ion Implantation", CHEMICAL VAPOR DEPOSITION, WILEY-VCH VERLAG, WEINHEIM, DE, vol. 16, no. 1-3, 1 January 2010 (2010-01-01), pages 80 - 84, XP002678344, ISSN: 0948-1907, DOI: DOI:10.1002/CVDE.200906807 *

Also Published As

Publication number Publication date
US9023722B2 (en) 2015-05-05
US20120289031A1 (en) 2012-11-15
TW201250796A (en) 2012-12-16

Similar Documents

Publication Publication Date Title
TWI620233B (en) Method and apparatus for selective deposition
US8906727B2 (en) Heteroepitaxial growth using ion implantation
JP6450675B2 (en) Method for forming a multilayer substrate structure
TW201246367A (en) Method of etching a workpiece
JP2013514673A5 (en)
JP2022531362A (en) Backside physical gas phase deposition methods and equipment
US20120309180A1 (en) Method of forming a retrograde material profile using ion implantation
CN107039251B (en) DC ion implantation for solid phase epitaxial regrowth in solar cell fabrication
US9023722B2 (en) Compound semiconductor growth using ion implantation
US8163635B2 (en) Manufacturing method of semiconductor device
KR20120003494A (en) Formation of elevated sources / drains on modified thin films implanted with cold and / or molecular carbon
US8481340B2 (en) Method for preparing a light-emitting device using gas cluster ion beam processing
US8835287B2 (en) Method of implanting a workpiece to improve growth of a compound semiconductor
KR101366745B1 (en) Method of manufacturing solar cell including crystallizing process for large area using electron beam for p-type silicon thin film formed by physical vapor deposition and solar cell manufactured by the same
KR100936869B1 (en) Nitride semiconductor device and its manufacturing method
US8969181B2 (en) Method for epitaxial layer overgrowth
US20110300696A1 (en) Method for damage-free junction formation
US9437432B1 (en) Self-compensating oxide layer
Yanagisawa et al. Effects of Ga ion irradiation on growth of GaN on SiN substrates by electron cyclotron resonance-assisted molecular beam epitaxy
TW201234429A (en) Method of doping
JP2002118064A (en) Crystal growth method of semiconductor at low temperature

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12723783

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12723783

Country of ref document: EP

Kind code of ref document: A1