WO2012153655A1 - Esd protection device - Google Patents

Esd protection device Download PDF

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Publication number
WO2012153655A1
WO2012153655A1 PCT/JP2012/061342 JP2012061342W WO2012153655A1 WO 2012153655 A1 WO2012153655 A1 WO 2012153655A1 JP 2012061342 W JP2012061342 W JP 2012061342W WO 2012153655 A1 WO2012153655 A1 WO 2012153655A1
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Prior art keywords
conductor
discharge
layer
esd protection
protection device
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PCT/JP2012/061342
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French (fr)
Japanese (ja)
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山本隼也
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株式会社村田製作所
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Publication of WO2012153655A1 publication Critical patent/WO2012153655A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01TSPARK GAPS; OVERVOLTAGE ARRESTERS USING SPARK GAPS; SPARKING PLUGS; CORONA DEVICES; GENERATING IONS TO BE INTRODUCED INTO NON-ENCLOSED GASES
    • H01T4/00Overvoltage arresters using spark gaps
    • H01T4/08Overvoltage arresters using spark gaps structurally associated with protected apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F17/0006Printed inductances
    • H01F17/0013Printed inductances with stacked layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01TSPARK GAPS; OVERVOLTAGE ARRESTERS USING SPARK GAPS; SPARKING PLUGS; CORONA DEVICES; GENERATING IONS TO BE INTRODUCED INTO NON-ENCLOSED GASES
    • H01T1/00Details of spark gaps
    • H01T1/14Means structurally associated with spark gap for protecting it against overload or for disconnecting it in case of failure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01TSPARK GAPS; OVERVOLTAGE ARRESTERS USING SPARK GAPS; SPARKING PLUGS; CORONA DEVICES; GENERATING IONS TO BE INTRODUCED INTO NON-ENCLOSED GASES
    • H01T4/00Overvoltage arresters using spark gaps
    • H01T4/10Overvoltage arresters using spark gaps having a single gap or a plurality of gaps in parallel
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00Screening of apparatus or components against electric or magnetic fields
    • H05K9/0067Devices for protecting against damage from electrostatic discharge

Definitions

  • the present invention relates to an ESD protection device that protects electronic equipment from generated static electricity.
  • Patent Document 1 discloses a static electricity countermeasure component suitable for a high frequency circuit.
  • FIG. 1 is a diagram schematically showing the configuration of an anti-static component described in Patent Document 1.
  • the antistatic component shown in FIG. 1 is configured by laminating and integrating a varistor layer 100 and inductor layers 110 and 120 on which conductors are formed. By electrically connecting the conductors of each layer, a varistor and an inductor connected in parallel are provided between the signal line of the device circuit and the ground, and another inductor is connected in series to the signal line of the device circuit. A circuit will be constructed.
  • an electrostatic pulse can be bypassed to the ground by the inductor, and at the same time, a high frequency component that cannot be removed by the inductor can be absorbed by the varistor.
  • the inductor connected in series with the signal line suppresses the application of the high-frequency component of the electrostatic pulse to the electrical circuit of the device, and has the effect of promoting the absorption of the high-frequency component by the ground-side varistor. The voltage applied to the electric circuit can be suppressed.
  • the conductor pattern of each layer is connected to the conductor formed in the inductor layers 110 and 120 by the via conductors 130, 131, 132, and 133.
  • 132 and 133 may be broken by the heat of surge current due to static electricity.
  • the via conductors 130, 131, 132, 133 break, it becomes impossible to reliably protect the electronic components connected to the subsequent stage of the antistatic components from static electricity.
  • an object of the present invention is to provide an ESD protection element that can reliably protect an electronic component connected to a subsequent stage from static electricity.
  • the present invention provides an ESD protection device comprising: a laminate in which a plurality of insulator base layers are laminated; and a first side conductor, a second side conductor, and a third side conductor provided on a side surface of the laminate.
  • the laminated body includes an input / output conductor formed with a signal input conductor conducting to the first side conductor, a signal output conductor conducting to the second side conductor, and a ground conductor conducting to the third side conductor.
  • a conductor forming layer, a discharge part forming layer in which a discharge part conducting to each of the first side conductor and the third side conductor, and an inductor pattern conducting the first side conductor and the second side conductor are configured. And an inductor layer.
  • the discharge part of the discharge part formation layer is connected to the signal input conductor and the ground conductor of the input / output conductor formation layer via the first side conductor and the third side conductor.
  • the inductor pattern of the inductor layer is connected to the signal input conductor and the signal output conductor of the input / output conductor formation layer via the first side conductor and the second side conductor.
  • the discharge part of the discharge part forming layer may be a varistor or a discharge gap.
  • the inductor pattern prevents a high-frequency component of a surge flowing from the signal input conductor to the signal output conductor, it is possible to suppress static electricity from flowing to the subsequent electronic component connected to the signal output conductor. Thereby, the latter electronic component can be protected from static electricity.
  • the discharge part of the discharge part forming layer has a first discharge conductor and a second discharge conductor facing each other with a gap therebetween, and the first discharge conductor is the first discharge conductor. It is preferable that the first side conductor is conductive and the second discharge conductor is conductive to the third side conductor.
  • the input / output conductor formation layer, the discharge portion formation layer, and the inductor layer are preferably laminated in this order.
  • the discharge portion forming layer is laminated near the input / output conductor forming layer.
  • an unnecessary inductance component is likely to be generated between the input conductor and the discharge portion. Since this inductance component exists in the previous stage of the discharge part, the high frequency component contained in the surge is blocked by the inductance component, the discharge start voltage of the discharge part is increased, and the discharge performance is lowered. For this reason, by stacking the discharge portion forming layer near the input / output conductor forming layer, unnecessary inductance components can be reduced, and more effective electrostatic discharge can be performed.
  • the ESD protection device includes a cavity in a portion facing each other with an interval between the first discharge conductor and the second discharge conductor at the interface between the input / output conductor formation layer and the discharge portion formation layer. May be provided.
  • the ESD protection device further includes an auxiliary electrode provided on the discharge part forming layer for connecting the first discharge conductor and the second discharge conductor, and the auxiliary electrode is coated with an insulating material-coated metal particle.
  • the semiconductor particle may be composed of a dispersion of semiconductor particles.
  • the inductor pattern may be formed in a meander shape.
  • the inductor can be configured with one insulator layer, it is not necessary to stack the insulator layer to configure the inductor, and the ESD protection device can be configured with a smaller number of interlayer connections. Further, since the first and second discharge electrodes are directly connected to the side conductors and it is not necessary to use via conductors, the reliability against surge is high.
  • the inductor layer includes a plurality of insulator layers on which conductor patterns are formed, and the conductor pattern formed on the insulator layer is located in a via hole of the insulator layer.
  • a multilayer inductor formed by direct interlayer connection to the conductor pattern of the insulator layer may be used.
  • conductor patterns formed in different insulator layers are directly connected to each other (bare connection).
  • bare connection When the conductive patterns of each layer are connected to each other with via conductors, a conductive paste having a different particle size or resin component from the conductive paste used for the conductive pattern is used.
  • the via conductor is generally formed in a separate process from the conductor pattern, the via conductor and the conductor pattern are not completely the same material, and the resistance of the connection portion varies. As a result, the discharge characteristics of the ESD protection device may fluctuate and reliability may be impaired. In the case of direct connection between conductor patterns using the bare connection, it is possible to prevent the discharge characteristics of the ESD protection device from deteriorating.
  • the via conductor for connecting the conductor pattern formed in each layer becomes unnecessary by using the bare connection, the deterioration of the discharge characteristics of the ESD protection device due to the formation of the via conductor is avoided. be able to.
  • An ESD protection device is used to protect an IC (Integrated Circuit) built in an electronic device such as a mobile phone from electrostatic discharge such as a surge.
  • the ESD protection device is provided between the signal line and the ground. For example, when static electricity generated when a charged user touches an electronic device is applied to a signal line, the subsequent IC is protected by guiding a voltage due to the static electricity to the ground side.
  • FIG. 2 is an external view of the ESD protection device according to the first embodiment.
  • the ESD protection device 1 includes a sintered body (laminated body) 2 having a substantially rectangular parallelepiped shape.
  • the sintered body 2 is formed by laminating a plurality of plate-shaped ceramic green sheets having a conductor pattern formed on the surface in the thickness direction and then sintering.
  • the ceramic green sheet becomes an insulator layer and constitutes the sintered body 2.
  • an input side conductor (first side conductor) 3, an output side conductor (second side conductor) 4 and a ground side conductor (third side conductor) 5 are provided in contact with each other. It has been.
  • the input side surface conductor 3 is provided so as to cover one side surface having a minimum area among the six surfaces of the sintered body 2 and a part of four surfaces adjacent thereto in a cap shape.
  • the output side conductor 4 and the ground side conductor 5 are respectively provided at the corners of the side surface facing the side surface of the sintered body 2 provided with the input side conductor 3.
  • the input side conductor 3, the output side conductor 4, and the ground side conductor 5 are electrically connected to the conductor pattern formed on each insulating substrate constituting the sintered body 2, respectively. That is, the ESD protection device 1 according to the present embodiment is configured such that the conductor pattern formed on each ceramic substrate is directly conducted by the input side conductor 3, the output side conductor 4, and the ground side conductor 5.
  • the via conductor and the conductor pattern are not completely the same material because the conductive paste having a different particle size or resin component is used or because the manufacturing process is different.
  • the connection resistance between the via conductor and the conductor pattern varies.
  • the via conductor may be broken by electrostatic discharge, which may impair the reliability of the ESD protection device 1.
  • the configuration in which the conductor pattern is directly conducted by the input side conductor 3, the output side conductor 4, and the ground side conductor 5 can prevent the reliability of the ESD protection device 1 from being lowered by eliminating the need for the via conductor. .
  • FIG. 3A, 3B, and 3C are schematic plan views of ceramic substrates constituting the sintered body 2.
  • FIG. 3D is a cross-sectional view at a substantially central portion of the short side of each layer. 2, assuming that the thickness direction of the sintered body 2 is the vertical direction, FIGS. 3A, 3B, and 3C show a state seen from the lower side of the sintered body 2.
  • 3A is an input / output conductor forming layer 21 that is the lowest layer of the sintered body 2
  • FIG. 3B is a discharge portion forming layer 22 that is an intermediate layer of the sintered body 2
  • FIG. 3D shows a sectional view of the sintered body 2.
  • the input / output conductor formation layer 21 is a layer for forming an input / output of a signal to the ESD protection device 1 and a ground conductor. As shown in FIG. 3A, a rectangular signal input conductor 211, a signal output conductor 212, and a ground conductor 213 are formed on the input / output conductor formation layer 21.
  • the signal input conductor 211 is connected to a signal line and serves as an input terminal for inputting a signal to the ESD protection device 1.
  • the signal input conductor 211 is formed such that one long side coincides with one short side of the input / output conductor forming layer 21.
  • the signal input conductor 211 is electrically connected to the input side conductor 3.
  • the signal output conductor 212 is connected to a signal line and serves as an output terminal for outputting a signal from the ESD protection device 1.
  • the signal output conductor 212 is formed at one corner of the short side opposite to the signal input conductor 211.
  • the signal output conductor 212 is electrically connected to the output side conductor 4.
  • the ground conductor 213 serves as a terminal for connecting the ESD protection device 1 to the ground.
  • the ground conductor 213 is formed at the other corner of the short side opposite to the signal input conductor 211.
  • the ground conductor 213 is electrically connected to the ground side conductor 5.
  • the discharge part forming layer 22 is a layer in which a discharge part for discharging static electricity is formed. As shown in FIG. 3B, the discharge conductors 221 and 222 are formed on the discharge portion forming layer 22 so as to face each other with a gap of 30 ⁇ m, for example.
  • the discharge conductor 221 is electrically connected to the input side conductor 3 provided on the sintered body 2. Accordingly, the discharge conductor 221 is electrically connected to the signal input conductor 211 of the input / output conductor forming layer 21 through the input side conductor 3.
  • the discharge conductor 222 is electrically connected to the output side conductor 4 provided on the sintered body 2. Accordingly, the discharge conductor 222 is electrically connected to the ground conductor 213 of the input / output conductor forming layer 21 through the ground side conductor 5.
  • a conductor pattern 231 is formed in a meander shape on the inductor layer 23, and the conductor is composed of the conductor pattern 231.
  • One end of the conductor pattern 231 is electrically connected to the input side conductor 3 and the other end is electrically connected to the output side conductor 4. Therefore, the conductor pattern 231 is electrically connected to the signal input conductor 211 and the signal output conductor 212 of the input / output conductor forming layer 21 via the input side conductor 3 and the output side conductor 4.
  • a cavity 224 is provided between the discharge part forming layer 22 and the input / output conductor forming layer 21. A portion of the cavity 224 that faces the gap between the first discharge conductor 221 and the second discharge conductor 222 is exposed. Since the cavity 224 is provided, air discharge can be generated to stabilize the ESD discharge characteristics.
  • An auxiliary electrode 223 is provided on the discharge portion forming layer 22 so as to connect the first discharge conductor 221 and the second discharge conductor 222.
  • the auxiliary electrode 223 is made of a dispersion of insulating material-coated metal particles and semiconductor particles. With the auxiliary electrode 223, the discharge start voltage can be adjusted to an appropriate voltage.
  • the auxiliary electrodes 223 made of the insulating material coated metal particles 225 and the semiconductor particles 226 are dispersed in the glass-like material 227, and more creepage is formed, so that the ESD discharge characteristics are stable.
  • a BAS material mainly composed of Ba, Al and Si is mixed so as to have a predetermined composition, calcined and pulverized to obtain a ceramic powder.
  • a ceramic green sheet is obtained by molding a slurry comprising ceramic powder, an organic solvent, a binder and a plasticizer by a doctor blade method.
  • a conductive paste is obtained by stirring and mixing 80% by weight of Cu particles having an average particle size of 2 ⁇ m, a binder, and an organic solvent.
  • a metal particle is prepared by adhering Al2O3 powder having an average particle size of several nm to several tens of nm to the surface of Cu particles having an average particle size of 4 ⁇ m.
  • the metal particles are mixed with SiC powder having an average particle diameter of 1 ⁇ m, a binder resin, and a solvent to obtain an auxiliary electrode paste.
  • a resin paste made of polyethylene terephthalate (PET) and an organic solvent is prepared as a burnout material for forming the cavity 224.
  • the ceramic green sheets to be the input / output conductor forming layer 21 are laminated, and the conductive paste to be the inductor layer 23 is printed on the surface.
  • the ceramic green sheet to be the discharge portion forming layer 22 is laminated thereon, and the auxiliary electrode forming paste to be the auxiliary electrode 223 is applied thereon.
  • the conductive paste to be the first and second discharge conductors 221 and 222 is printed. Further, the resin paste that becomes the cavity 224 is applied.
  • a ceramic green sheet to be the input / output conductor forming layer 21 is laminated on the upper surface, and the whole is pressure-bonded in the thickness direction. In this way, a laminate is prepared. Thereafter, the laminate is cut by pressing to obtain an ESD protection device piece.
  • a conductive paste to be used as the input side conductor 3, the output side conductor 4, and the ground side conductor 5 is applied.
  • it is fired in a nitrogen atmosphere, and an ESD protection device is obtained in which the opposing portions of the first and second discharge conductors 221 and 222 are exposed in a cavity formed by burning out the resin paste.
  • the ceramic green sheet used as the input / output conductor forming layer 21, the discharge part forming layer 22, and the input / output conductor forming layer 21 may be either a single layer or a plurality of layers.
  • FIG. 4A and 4B are diagrams showing an equivalent circuit of the ESD protection device 1.
  • FIG. The signal input conductor 211 of the ESD protection device 1 is connected to the signal line 10 for inputting a signal, and the signal output conductor 212 is connected to the signal line 11 for outputting a signal.
  • the ground conductor 213 is connected to the ground.
  • the signal input conductor 211 is connected to the signal output conductor 212 via the input side conductor 3, the conductor pattern 231 of the inductor layer 23 constituting the inductor L, and the output side conductor 4.
  • the signal input conductor 211 is connected to the ground conductor 213 via the input side conductor 3, the discharge conductors 221 and 222 of the discharge portion forming layer 22, and the ground side conductor 5.
  • the signal input conductor 211 to which the input signal line 10 is connected is connected via the inductor L to the signal output conductor 212 to which the output signal line 11 is connected.
  • the signal input conductor 211 is connected to the ground via the discharge conductors 221 and 222.
  • the ESD protection device 1 prevents a voltage due to static electricity from being applied to the subsequent IC connected to the signal line 11 and protects the subsequent IC from static electricity.
  • the IC connected to the subsequent stage of the ESD protection device 1 can be protected from static electricity.
  • the conductor patterns of the ceramic substrates constituting the sintered body 2 are conducted by the side conductors 3, 4, and 5.
  • the discharge part forming layer 22 is stacked near the input / output conductor forming layer 21, but when the discharge part forming layer 22 and the inductor layer 23 are stacked in the opposite order, FIG. As shown, an unnecessary inductance component LS is easily generated between the signal input conductor 211 and the discharge conductor 221. The high frequency component is blocked by the inductance component LS, and the discharge performance by the discharge conductors 221 and 222 is lowered. Since the ESD protection device does not discharge, static electricity flows to the subsequent stage. For this reason, by laminating the discharge part forming layer 22 near the input / output conductor forming layer 21, it is possible to eliminate the influence of the inductance component LS on the discharge of static electricity and perform more effective discharge of static electricity.
  • the inductor L of the inductor layer is configured by a linear conductor pattern formed in a meander shape.
  • the inductor layer 23 is formed of a plurality of layers, and the inductor L is a multilayer inductor. This is different from the first embodiment. Only the differences will be described below.
  • FIG. 5 is a schematic plan view of each ceramic substrate constituting the inductor layer.
  • FIG. 5 is a bottom view of each ceramic substrate when the inductor layer is viewed from below.
  • FIG. 6 is a side sectional view of the inductor layer according to the second embodiment.
  • the inductor layer 6 is formed by laminating a first ceramic substrate 61, a second ceramic substrate 62, a third ceramic substrate 63, and a fourth ceramic substrate 64.
  • the first ceramic substrate 61 shown in FIG. 5A is the uppermost layer of the inductor layer, and a linear conductor pattern 611 extends from one short side of the first ceramic substrate 61 along the long side.
  • the conductor pattern 611 is formed by being wound clockwise from the outside toward the inside center (hereinafter referred to as point A) so as to be parallel to each side of the first ceramic substrate 61.
  • the second ceramic substrate 62 shown in FIG. 5B is laminated below the first ceramic substrate 61.
  • a linear conductor pattern 621 is clocked outward from a position coincident with the point A of the first ceramic substrate 61 in the thickness direction so as to be parallel to each side of the second ceramic substrate 62. It is formed by winding in the direction.
  • the position of the outer end portion of the conductor pattern 621 is defined as B point.
  • the third ceramic substrate 63 shown in FIG. 5C is laminated below the second ceramic substrate 62.
  • a linear conductor pattern 631 is clocked inward from a position coincident with the point B of the second ceramic substrate 62 in the thickness direction so as to be parallel to each side of the third ceramic substrate 63. It is formed by winding in the direction.
  • the position of the outer end portion of the conductor pattern 631 is defined as a C point.
  • the fourth ceramic substrate 64 shown in FIG. 5D is laminated below the third ceramic substrate 63.
  • a linear conductor pattern 641 is clocked outward from a position coincident with the point C of the third ceramic substrate 63 in the thickness direction so as to be parallel to each side of the fourth ceramic substrate 64. It is wound in the direction and extends to one short side of the fourth ceramic substrate 64.
  • the conductor pattern 611 of the first ceramic substrate 61 is electrically connected to the input side conductor 3. Further, the conductor pattern 641 of the fourth ceramic substrate 64 is electrically connected to the output side conductor 4. Furthermore, the conductor patterns 611, 621, 631, 641 of the ceramic substrates 61, 62, 63, 64 are connected by bare connection at points A, B, and C.
  • a via hole penetrating is formed by a method such as piercing by irradiating a carbon dioxide laser, and then the via hole is filled with a conductive paste simultaneously with the printing of the conductor pattern. That is, the conductive pattern and the via connection portion are formed in the same one process.
  • An ESD protection device is manufactured by laminating a plurality of ceramic green sheets after being filled with the conductive paste, followed by pressure bonding and firing. For this reason, the variation in resistance value of the connection part of the conductor pattern between different layers is smaller than that in the case where the printing of the conductive pattern and the filling of the via hole are formed in separate processes.
  • via conductors that electrically connect conductor patterns between layers different from those of the ceramic substrate are formed in different processes, so even if the same conductive paste is used, they are not completely the same material.
  • a conductive paste for forming a via conductor is selected to have a good filling property
  • a conductive paste for forming a conductor pattern is selected to have a good printability.
  • the connection between the conductor pattern and the via conductor in the ESD protection device 1 is a connection between different materials, and the resistance value of the connection portion is likely to vary. For this reason, the dispersion
  • the conductor pattern and the bare connection portion are made of the same material, so that the resistance value of the connection portion is substantially uniform. It is possible to prevent the reliability of the ESD protection device 1 from being lowered.
  • ESD protection device 1 has been described above, the specific configuration and the like can be appropriately changed in design, and the functions and effects described in the above-described embodiments are the most preferable functions and effects resulting from the present invention. The effects are merely listed, and the operations and effects of the present invention are not limited to those described in the above-described embodiment.
  • a capacitor layer may be further laminated on the sintered body 2 of the ESD protection device 1.
  • 7A and 7B show an equivalent circuit of the ESD protection device 1 when capacitor layers are stacked.
  • the capacitor layer is a ceramic substrate in which the capacitor C is constituted by a conductor pattern formed on the surface.
  • the input / output layer, the discharge layer, the inductor layer, and the capacitor layer are stacked in this order, and one end of the conductor pattern constituting the capacitor C is connected to the output side conductor 4 and the other end is connected to the ground side conductor 5.
  • the inductor L in the inductor layer and the capacitor C in the capacitor layer constitute a low-pass filter.
  • the low-pass filter used in the high-frequency circuit can be incorporated in the ESD protection device 1.
  • the area for mounting the low-pass filter element becomes unnecessary, and the circuit area can be reduced.
  • the input / output layer, the discharge layer, the capacitor layer, and the inductor layer are stacked in this order, and one end of the conductor pattern constituting the capacitor C is connected to the input side conductor 3 and the other end is connected to the output side conductor 4.
  • one end of the inductor L is connected to the output side conductor 4 and the other end is connected to the ground side conductor 5.
  • the inductor L in the inductor layer and the capacitor C in the capacitor layer constitute a high-pass filter.
  • the input and output are cut off in a DC manner by the capacitor C, so that the surge energy to the circuit connected to the subsequent stage of the ESD protection device 1 can be sufficiently suppressed.
  • 1-ESD protection device 2-sintered body (laminated body) 21-Input / output conductor forming layer 22-Discharge portion forming layer 23-Inductor layer 3-Input side conductor (first side conductor) 211—Signal input conductor 212—Signal output conductor 213—Ground conductors 221, 222—Discharge conductor (discharge section, first discharge conductor, second discharge conductor) 223-auxiliary electrode 224-cavity 225-insulating material coated metal particle 226-semiconductor particle 227-glass-like substance 4-side conductor for output (second side conductor) 5-side conductor for ground (third side conductor)

Abstract

An input side-surface conductor, an output side-surface conductor, and a ground side-surface conductor are disposed on the side surface of a sintered body having an I/O conductor-forming layer (21), a discharge section-forming layer (22), and an inductor layer (23) layered therein. A signal input conductor (211) which conducts to the input side-surface conductor, a signal output conductor which conducts to the output side-surface conductor, and a ground conductor (213) which conducts to the ground side-surface conductor are formed in the I/O conductor-forming layer (21). Discharge conductors (221, 222) are formed in the discharge section-forming layer (22) as discharge units that conduct to the input side-surface conductor and the ground side-surface conductor. A conductor pattern (231) that configures an inductor is formed in the inductor layer (23) and conducts to the input side-surface conductor and the output side-surface conductor. As a result, an ESD protection element capable of reliably protecting electrical components connected at a latter stage from static electricity is provided.

Description

ESD保護デバイスESD protection device
 本発明は、発生した静電気から電子機器を保護するESD保護デバイスに関する。 The present invention relates to an ESD protection device that protects electronic equipment from generated static electricity.
 近年、携帯電話等の電子機器に用いられる電子部品は、静電気に対して脆弱な構造であり、静電気放電(ESD: Electro-Static-Discharge)によって破壊されたり、誤動作が発生したりするなどの影響を受けることがある。そこで、特許文献1には、高周波回路に適した静電気対策部品が開示されている。 In recent years, electronic parts used in electronic devices such as mobile phones have a structure that is vulnerable to static electricity, and they are damaged by electrostatic discharge (ESD) or are affected by malfunctions. May receive. Thus, Patent Document 1 discloses a static electricity countermeasure component suitable for a high frequency circuit.
 図1は特許文献1に記載の静電気対策部品の構成を模式的に示す図である。図1に示す静電気対策部品は、導体が形成されたバリスタ層100及びインダクタ層110,120が積層一体化されて構成されている。各層の導体が電気的に接続されることにより、並列接続されたバリスタとインダクタとが機器回路の信号ラインおよびグランド間に設けられ、さらに別のインダクタが機器回路の信号ラインに直列に接続された回路が構成されることとなる。 FIG. 1 is a diagram schematically showing the configuration of an anti-static component described in Patent Document 1. In FIG. The antistatic component shown in FIG. 1 is configured by laminating and integrating a varistor layer 100 and inductor layers 110 and 120 on which conductors are formed. By electrically connecting the conductors of each layer, a varistor and an inductor connected in parallel are provided between the signal line of the device circuit and the ground, and another inductor is connected in series to the signal line of the device circuit. A circuit will be constructed.
 並列接続されたバリスタとインダクタとにより、静電気パルスをインダクタによってグランドにバイパスさせると同時にインダクタで除去しきれない高周波成分をバリスタにより吸収することができる。さらに、信号ラインに直列に接続したインダクタにより、静電気パルスの高周波成分が機器の電気回路に印加されるのを抑制し、グランド側のバリスタによる高周波成分の吸収を促進する作用を有し、機器の電気回路に印加される電圧を抑制することができる。 By using a varistor and an inductor connected in parallel, an electrostatic pulse can be bypassed to the ground by the inductor, and at the same time, a high frequency component that cannot be removed by the inductor can be absorbed by the varistor. Furthermore, the inductor connected in series with the signal line suppresses the application of the high-frequency component of the electrostatic pulse to the electrical circuit of the device, and has the effect of promoting the absorption of the high-frequency component by the ground-side varistor. The voltage applied to the electric circuit can be suppressed.
特開2004-281893号公報JP 2004-281893 A
 特許文献1に記載の静電気対策部品は、インダクタ層110,120に形成された導体をビア導体130,131,132,133により各層の導体パターンを接続しているが、このビア導体130,131,132,133は、静電気によるサージ電流の熱により破断するおそれがある。ビア導体130,131,132,133が破断した場合、静電気対策部品の後段に接続される電子部品を静電気から確実に保護できなくなる。 In the anti-static component described in Patent Document 1, the conductor pattern of each layer is connected to the conductor formed in the inductor layers 110 and 120 by the via conductors 130, 131, 132, and 133. 132 and 133 may be broken by the heat of surge current due to static electricity. When the via conductors 130, 131, 132, 133 break, it becomes impossible to reliably protect the electronic components connected to the subsequent stage of the antistatic components from static electricity.
 そこで、本発明の目的は、後段に接続される電子部品を静電気から確実に保護することができるESD保護素子を提供することにある。 Therefore, an object of the present invention is to provide an ESD protection element that can reliably protect an electronic component connected to a subsequent stage from static electricity.
 本発明は、複数の絶縁体基層が積層されてなる積層体と、前記積層体の側面に設けられた第1側面導体、第2側面導体および第3側面導体と、を備えるESD保護デバイスにおいて、前記積層体は、前記第1側面導体に導通する信号入力用導体、前記第2側面導体に導通する信号出力用導体、および前記第3側面導体に導通するグランド用導体が形成された入出力用導体形成層と、前記第1側面導体および前記第3側面導体それぞれに導通する放電部が形成された放電部形成層と、前記第1側面導体および前記第2側面導体を導通するインダクタパターンが構成されているインダクタ層と、を有している。 The present invention provides an ESD protection device comprising: a laminate in which a plurality of insulator base layers are laminated; and a first side conductor, a second side conductor, and a third side conductor provided on a side surface of the laminate. The laminated body includes an input / output conductor formed with a signal input conductor conducting to the first side conductor, a signal output conductor conducting to the second side conductor, and a ground conductor conducting to the third side conductor. A conductor forming layer, a discharge part forming layer in which a discharge part conducting to each of the first side conductor and the third side conductor, and an inductor pattern conducting the first side conductor and the second side conductor are configured. And an inductor layer.
 この構成では、放電部形成層の放電部は第1側面導体および第3側面導体を介して、入出力用導体形成層の信号入力用導体およびグランド用導体に接続している。また、インダクタ層のインダクタパターンは、第1側面導体および第2側面導体を介して、入出力用導体形成層の信号入力用導体および信号出力用導体に接続している。なお、放電部形成層の放電部はバリスタであってもよいし、放電ギャップを用いたものであってもよい。 In this configuration, the discharge part of the discharge part formation layer is connected to the signal input conductor and the ground conductor of the input / output conductor formation layer via the first side conductor and the third side conductor. The inductor pattern of the inductor layer is connected to the signal input conductor and the signal output conductor of the input / output conductor formation layer via the first side conductor and the second side conductor. The discharge part of the discharge part forming layer may be a varistor or a discharge gap.
 これにより、入出力用導体形成層の信号入力用導体から静電気による高電圧が印加された場合、放電部で放電が起こり、サージがグランド側に導かれる。また、インダクタパターンにより、信号入力用導体から信号出力用導体に流れるサージの高周波成分が阻止されるため、信号出力用導体に接続される後段の電子部品に静電気が流れることを抑制できる。これにより、後段の電子部品を静電気から保護することができる。 Thus, when a high voltage due to static electricity is applied from the signal input conductor of the input / output conductor forming layer, discharge occurs in the discharge section, and the surge is guided to the ground side. In addition, since the inductor pattern prevents a high-frequency component of a surge flowing from the signal input conductor to the signal output conductor, it is possible to suppress static electricity from flowing to the subsequent electronic component connected to the signal output conductor. Thereby, the latter electronic component can be protected from static electricity.
 本発明に係るESD保護デバイスにおいて、前記放電部形成層の放電部は、間隔を隔てて互いに対向しあっている第1放電導体および第2放電導体を有し、前記第1放電導体は前記第1側面導体に導通し、前記第2放電導体は前記第3側面導体に導通していることが好ましい。 In the ESD protection device according to the present invention, the discharge part of the discharge part forming layer has a first discharge conductor and a second discharge conductor facing each other with a gap therebetween, and the first discharge conductor is the first discharge conductor. It is preferable that the first side conductor is conductive and the second discharge conductor is conductive to the third side conductor.
 この構成では、信号入力用導体とグランド用導体との間に放電ギャップが設けられる構成となるため、通常動作時には信号入力用導体とグランド用導体とが接続されずに、信号がグランド側に導かれることがない。また、静電気が加わると、放電し、信号入力用導体からグランド用導体へとサージが流れ込み後段へ流れないため、後段の電子部品を保護することができる。この放電ギャップを用いるESD保護デバイスは小型であるため、例えばバリスタを用いた場合との対比において、ESD保護デバイスを小型化できる。 In this configuration, since a discharge gap is provided between the signal input conductor and the ground conductor, the signal input conductor and the ground conductor are not connected during normal operation, and the signal is guided to the ground side. There will be no damage. Further, when static electricity is applied, it discharges and a surge flows from the signal input conductor to the ground conductor and does not flow to the subsequent stage, so that it is possible to protect the subsequent electronic components. Since the ESD protection device using this discharge gap is small, for example, the ESD protection device can be downsized in comparison with the case where a varistor is used.
 本発明に係るESD保護デバイスにおいて、前記入出力用導体形成層、前記放電部形成層およびインダクタ層の順に積層されてなることが好ましい。 In the ESD protection device according to the present invention, the input / output conductor formation layer, the discharge portion formation layer, and the inductor layer are preferably laminated in this order.
 この構成では、放電部形成層を入出力用導体形成層の近くに積層している。放電部形成層とインダクタ層とを逆順に積層した場合、入力用導体と放電部との間に不要なインダクタンス成分が発生し易い。放電部の前段にこのインダクタンス成分が存在するためサージに含まれる高周波成分がインダクタンス成分により遮断され、放電部の放電開始電圧を高くなり放電性能が低下する。このため、放電部形成層を入出力用導体形成層の近くに積層することで不要なインダクタンス成分を低減し、より効果的な静電気の放電を行うことができる。 In this configuration, the discharge portion forming layer is laminated near the input / output conductor forming layer. When the discharge portion forming layer and the inductor layer are laminated in reverse order, an unnecessary inductance component is likely to be generated between the input conductor and the discharge portion. Since this inductance component exists in the previous stage of the discharge part, the high frequency component contained in the surge is blocked by the inductance component, the discharge start voltage of the discharge part is increased, and the discharge performance is lowered. For this reason, by stacking the discharge portion forming layer near the input / output conductor forming layer, unnecessary inductance components can be reduced, and more effective electrostatic discharge can be performed.
 本発明に係るESD保護デバイスは、前記入出力用導体形成層と前記放電部形成層間の界面の前記第1放電導体と、第2放電導体の間隔を隔てて互いに対向しあっている部分に空洞が設けられている構成でもよい。 The ESD protection device according to the present invention includes a cavity in a portion facing each other with an interval between the first discharge conductor and the second discharge conductor at the interface between the input / output conductor formation layer and the discharge portion formation layer. May be provided.
 この構成では、気中放電を発生させてESD放電特性を安定化することができる。 In this configuration, air discharge can be generated to stabilize the ESD discharge characteristics.
 本発明に係るESD保護デバイスは、前記第1放電導体と前記第2放電導体とを接続する、前記放電部形成層に設けられた補助電極をさらに備え、該補助電極は絶縁性材料コート金属粒子および半導体粒子の分散体からなる構成でもよい。 The ESD protection device according to the present invention further includes an auxiliary electrode provided on the discharge part forming layer for connecting the first discharge conductor and the second discharge conductor, and the auxiliary electrode is coated with an insulating material-coated metal particle. Alternatively, the semiconductor particle may be composed of a dispersion of semiconductor particles.
 この構成では、より多くの沿面が形成されるのでESD放電特性を安定化することができ、放電特性をさらに安定化できる。 In this configuration, since more creepage surfaces are formed, the ESD discharge characteristics can be stabilized, and the discharge characteristics can be further stabilized.
 本発明に係るESD保護デバイスにおいて、前記インダクタパターンはミアンダ状に形成されていてもよい。 In the ESD protection device according to the present invention, the inductor pattern may be formed in a meander shape.
 この構成では、一の絶縁体層によりインダクタを構成できるため、インダクタを構成するために絶縁体層を積層する必要がなく、より少ない層間接続数によりESD保護デバイスを構成できる。また、第1,第2放電電極が側面導体に直接接続され、ビア導体を用いる必要がないので、サージに対する信頼性が高い。 In this configuration, since the inductor can be configured with one insulator layer, it is not necessary to stack the insulator layer to configure the inductor, and the ESD protection device can be configured with a smaller number of interlayer connections. Further, since the first and second discharge electrodes are directly connected to the side conductors and it is not necessary to use via conductors, the reliability against surge is high.
 本発明に係るESD保護デバイスにおいて、前記インダクタ層は、導体パターンが形成された絶縁体層が複数積層され、前記絶縁体層に形成された前記導体パターンが絶縁体層のビア穴内に位置する下層の絶縁体層の導体パターンに直接層間接続されて形成された積層インダクタである構成でもよい。 In the ESD protection device according to the present invention, the inductor layer includes a plurality of insulator layers on which conductor patterns are formed, and the conductor pattern formed on the insulator layer is located in a via hole of the insulator layer. A multilayer inductor formed by direct interlayer connection to the conductor pattern of the insulator layer may be used.
 この構成では、異なる絶縁体層に形成される導体パターンを直接層間接続(ベア接続)している。ビア導体で各層の導体パターンを層間接続する場合、導体パターンに用いる導電性ペーストとは粒径が異なったり樹脂成分が異なったりする導電性ペーストが用いられる。また、ビア導体は一般的には導体パターンとは別工程で形成されることから、ビア導体と導体パターンとは完全に材質が同一ではなく、接続部分の抵抗にばらつきが生じる。その結果、ESD保護デバイスの放電特性が変動し信頼性が損なうおそれがある。ベア接続を用いた相間を跨いだ導体パターン間の直接接続の場合、ESD保護デバイスの放電特性が低下することを防止できる。 In this configuration, conductor patterns formed in different insulator layers are directly connected to each other (bare connection). When the conductive patterns of each layer are connected to each other with via conductors, a conductive paste having a different particle size or resin component from the conductive paste used for the conductive pattern is used. Further, since the via conductor is generally formed in a separate process from the conductor pattern, the via conductor and the conductor pattern are not completely the same material, and the resistance of the connection portion varies. As a result, the discharge characteristics of the ESD protection device may fluctuate and reliability may be impaired. In the case of direct connection between conductor patterns using the bare connection, it is possible to prevent the discharge characteristics of the ESD protection device from deteriorating.
 また、ビア導体で各層の導体パターンを接続する場合、ビア導体を形成する工程で、ビア導体となる導電性ペーストが不足するとビア導体部分が欠損し、ビア導体内に隙間が形成されてしまうが、ベア接続を採用することで、斯かる問題を回避できる。 Also, when connecting the conductor patterns of each layer with via conductors, if the conductive paste that becomes the via conductor is insufficient in the step of forming the via conductor, the via conductor portion is lost and a gap is formed in the via conductor. By adopting bare connection, such a problem can be avoided.
 本発明によれば、ベア接続を用いることにより各層に形成された導体パターンを接続するためのビア導体が不要となるため、ビア導体の形成に起因するESD保護デバイスの放電特性の劣化を回避することができる。 According to the present invention, since the via conductor for connecting the conductor pattern formed in each layer becomes unnecessary by using the bare connection, the deterioration of the discharge characteristics of the ESD protection device due to the formation of the via conductor is avoided. be able to.
特許文献1に記載の静電気対策部品の構成を模式的に示す図The figure which shows typically the structure of the static electricity countermeasure component of patent document 1 実施形態1に係るESD保護デバイスの外観図External view of ESD protection device according to Embodiment 1 焼結体を構成する各セラミック基板の概略平面図Schematic plan view of each ceramic substrate constituting the sintered body 焼結体を構成する各セラミック基板の概略平面図Schematic plan view of each ceramic substrate constituting the sintered body 焼結体を構成する各セラミック基板の概略平面図Schematic plan view of each ceramic substrate constituting the sintered body 各層の短辺の略中央部における断面図Sectional view at the approximate center of the short side of each layer ESD保護デバイスの等価回路を示す図Diagram showing equivalent circuit of ESD protection device ESD保護デバイスの等価回路を示す図Diagram showing equivalent circuit of ESD protection device インダクタ層を構成する各セラミック基板の概略平面図Schematic plan view of each ceramic substrate constituting the inductor layer 実施形態2に係るインダクタ層の側面断面図Side surface sectional drawing of the inductor layer which concerns on Embodiment 2. FIG. キャパシタ層を積層させた場合のESD保護デバイスの等価回路Equivalent circuit of ESD protection device when capacitor layers are stacked キャパシタ層を積層させた場合のESD保護デバイスの等価回路Equivalent circuit of ESD protection device when capacitor layers are stacked
 以下に説明する実施形態に係るESD保護デバイスは、携帯電話機等の電子機器に内蔵されるIC(Integrated Circuit)をサージのような静電気放電から保護するために用いられる。ESD保護デバイスは、信号ラインとグランド間に設けられる。例えば、帯電したユーザが電子機器に接触したときに発生する静電気が信号ラインに加わると、その静電気による電圧をグランド側に導くことにより、後段のICを保護する。 An ESD protection device according to an embodiment described below is used to protect an IC (Integrated Circuit) built in an electronic device such as a mobile phone from electrostatic discharge such as a surge. The ESD protection device is provided between the signal line and the ground. For example, when static electricity generated when a charged user touches an electronic device is applied to a signal line, the subsequent IC is protected by guiding a voltage due to the static electricity to the ground side.
(実施形態1)
 図2は実施形態1に係るESD保護デバイスの外観図である。ESD保護デバイス1は、略直方体形状の焼結体(積層体)2を備えている。焼結体2は、表面に導体パターンが形成された板状の複数のセラミックグリーンシートが厚み方向に積層された後、焼結されて形成されている。セラミックグリーンシートは、絶縁体層になり焼結体2を構成する。
(Embodiment 1)
FIG. 2 is an external view of the ESD protection device according to the first embodiment. The ESD protection device 1 includes a sintered body (laminated body) 2 having a substantially rectangular parallelepiped shape. The sintered body 2 is formed by laminating a plurality of plate-shaped ceramic green sheets having a conductor pattern formed on the surface in the thickness direction and then sintering. The ceramic green sheet becomes an insulator layer and constitutes the sintered body 2.
 焼結体2の外側には、入力用側面導体(第1側面導体)3、出力用側面導体(第2側面導体)4およびグランド用側面導体(第3側面導体)5が互いに非接触に設けられている。入力用側面導体3は、焼結体2の六面のなかで、最小面積となる一の側面と、それに隣接する四つの面の一部とをキャップ状に覆うよう設けられている。出力用側面導体4およびグランド用側面導体5は、入力用側面導体3が設けられた焼結体2の側面に対向する側面の角部にそれぞれ設けられている。 Outside the sintered body 2, an input side conductor (first side conductor) 3, an output side conductor (second side conductor) 4 and a ground side conductor (third side conductor) 5 are provided in contact with each other. It has been. The input side surface conductor 3 is provided so as to cover one side surface having a minimum area among the six surfaces of the sintered body 2 and a part of four surfaces adjacent thereto in a cap shape. The output side conductor 4 and the ground side conductor 5 are respectively provided at the corners of the side surface facing the side surface of the sintered body 2 provided with the input side conductor 3.
 入力用側面導体3、出力用側面導体4およびグランド用側面導体5は、それぞれ焼結体2を構成する各絶縁性基板に形成された導体パターンを導通している。すなわち、本実施形態に係るESD保護デバイス1は、各セラミック基板に形成される導体パターンを入力用側面導体3、出力用側面導体4およびグランド用側面導体5で直接導通する構成となっている。 The input side conductor 3, the output side conductor 4, and the ground side conductor 5 are electrically connected to the conductor pattern formed on each insulating substrate constituting the sintered body 2, respectively. That is, the ESD protection device 1 according to the present embodiment is configured such that the conductor pattern formed on each ceramic substrate is directly conducted by the input side conductor 3, the output side conductor 4, and the ground side conductor 5.
 例えば導体パターンの接続にビア導体を用いた場合、ビア導体と導体パターンとは、粒径または樹脂成分の異なる導電性ペーストを用いるため、又は製造工程が異なるため、完全に材質が同一ではなく、ビア導体と導体パターンとの接続抵抗にばらつきが生じる。このため、ビア導体が静電気放電によって破断される場合があり、ESD保護デバイス1に対する信頼性を損なうおそれがある。導体パターンを入力用側面導体3、出力用側面導体4およびグランド用側面導体5で直接導通する構成は、ビア導体を不要とすることで、ESD保護デバイス1に対する信頼性が低下することを防止できる。 For example, when a via conductor is used for connection of the conductor pattern, the via conductor and the conductor pattern are not completely the same material because the conductive paste having a different particle size or resin component is used or because the manufacturing process is different. The connection resistance between the via conductor and the conductor pattern varies. For this reason, the via conductor may be broken by electrostatic discharge, which may impair the reliability of the ESD protection device 1. The configuration in which the conductor pattern is directly conducted by the input side conductor 3, the output side conductor 4, and the ground side conductor 5 can prevent the reliability of the ESD protection device 1 from being lowered by eliminating the need for the via conductor. .
 また、ビア導体を形成する一般的な工程ではビア導体部分に欠損が生じることがあり、斯かる欠損が原因により積層したセラミック基板の焼結時に破断が発生することがあるが、ビア導体を不要とすることで、破断の問題を回避することができる。 In addition, in the general process of forming via conductors, there may be defects in the via conductors, which may cause breakage during sintering of the laminated ceramic substrate. By doing so, the problem of breakage can be avoided.
 図3A、図3Bおよび図3Cは焼結体2を構成する各セラミック基板の概略平面図である。図3Dは、各層の短辺の略中央部における断面図である。図2において、焼結体2の厚み方向を上下方向とすると、図3A、図3Bおよび図3Cは焼結体2の下方向から見た状態を示している。図3Aは焼結体2の最下層となる入出力用導体形成層21、図3Bは焼結体2の中間層となる放電部形成層22、図3Cは焼結体2の示す最上層となるインダクタ層23、図3Dは焼結体2の断面図をそれぞれ示している。 3A, 3B, and 3C are schematic plan views of ceramic substrates constituting the sintered body 2. FIG. FIG. 3D is a cross-sectional view at a substantially central portion of the short side of each layer. 2, assuming that the thickness direction of the sintered body 2 is the vertical direction, FIGS. 3A, 3B, and 3C show a state seen from the lower side of the sintered body 2. 3A is an input / output conductor forming layer 21 that is the lowest layer of the sintered body 2, FIG. 3B is a discharge portion forming layer 22 that is an intermediate layer of the sintered body 2, and FIG. FIG. 3D shows a sectional view of the sintered body 2.
 入出力用導体形成層21は、ESD保護デバイス1への信号の入出力、およびグランド用導体を形成するための層である。入出力用導体形成層21には、図3Aに示すように、長方形状の信号入力用導体211、信号出力用導体212およびグランド用導体213が形成されている。 The input / output conductor formation layer 21 is a layer for forming an input / output of a signal to the ESD protection device 1 and a ground conductor. As shown in FIG. 3A, a rectangular signal input conductor 211, a signal output conductor 212, and a ground conductor 213 are formed on the input / output conductor formation layer 21.
 信号入力用導体211は、信号ラインが接続され、ESD保護デバイス1へ信号を入力する入力端子となる。この信号入力用導体211は、一の長辺が入出力用導体形成層21の一の短辺に一致するよう形成されている。信号入力用導体211は入力用側面導体3と導通している。 The signal input conductor 211 is connected to a signal line and serves as an input terminal for inputting a signal to the ESD protection device 1. The signal input conductor 211 is formed such that one long side coincides with one short side of the input / output conductor forming layer 21. The signal input conductor 211 is electrically connected to the input side conductor 3.
 信号出力用導体212は、信号ラインが接続され、ESD保護デバイス1から信号を出力する出力端子となる。この信号出力用導体212は、信号入力用導体211とは逆側の短辺の一方の角部に形成されている。信号出力用導体212は、出力用側面導体4と導通している。 The signal output conductor 212 is connected to a signal line and serves as an output terminal for outputting a signal from the ESD protection device 1. The signal output conductor 212 is formed at one corner of the short side opposite to the signal input conductor 211. The signal output conductor 212 is electrically connected to the output side conductor 4.
 グランド用導体213は、ESD保護デバイス1をグランドに接続するための端子となる。グランド用導体213は、信号入力用導体211とは逆側の短辺の他方の角部に形成されている。グランド用導体213は、グランド用側面導体5と導通している。 The ground conductor 213 serves as a terminal for connecting the ESD protection device 1 to the ground. The ground conductor 213 is formed at the other corner of the short side opposite to the signal input conductor 211. The ground conductor 213 is electrically connected to the ground side conductor 5.
 放電部形成層22は、静電気を放電する放電部が形成された層である。放電部形成層22には、図3Bに示すように、放電部として放電導体221,222を例えば30μmのギャップを介して対向するように形成されている。放電導体221は、焼結体2に設けられる入力用側面導体3と導通している。従って、放電導体221は、入力用側面導体3を介して入出力用導体形成層21の信号入力用導体211と導通している。 The discharge part forming layer 22 is a layer in which a discharge part for discharging static electricity is formed. As shown in FIG. 3B, the discharge conductors 221 and 222 are formed on the discharge portion forming layer 22 so as to face each other with a gap of 30 μm, for example. The discharge conductor 221 is electrically connected to the input side conductor 3 provided on the sintered body 2. Accordingly, the discharge conductor 221 is electrically connected to the signal input conductor 211 of the input / output conductor forming layer 21 through the input side conductor 3.
 また、放電導体222は、焼結体2に設けられる出力用側面導体4と導通している。従って、放電導体222は、グランド用側面導体5を介して入出力用導体形成層21のグランド用導体213と導通している。 The discharge conductor 222 is electrically connected to the output side conductor 4 provided on the sintered body 2. Accordingly, the discharge conductor 222 is electrically connected to the ground conductor 213 of the input / output conductor forming layer 21 through the ground side conductor 5.
 インダクタ層23には、図3Cに示すように、ミアンダ状に導体パターン231が形成されており、斯かる導体パターン231によりインダクタが構成されている。導体パターン231の一端は入力用側面導体3と導通し、他端は出力用側面導体4と導通している。従って、導体パターン231は、入力用側面導体3および出力用側面導体4を介して、入出力用導体形成層21の信号入力用導体211および信号出力用導体212と導通している。 As shown in FIG. 3C, a conductor pattern 231 is formed in a meander shape on the inductor layer 23, and the conductor is composed of the conductor pattern 231. One end of the conductor pattern 231 is electrically connected to the input side conductor 3 and the other end is electrically connected to the output side conductor 4. Therefore, the conductor pattern 231 is electrically connected to the signal input conductor 211 and the signal output conductor 212 of the input / output conductor forming layer 21 via the input side conductor 3 and the output side conductor 4.
 放電部形成層22と入出力用導体形成層21の間には、図3Dに示すように、空洞224が設けられている。空洞224内に第1放電導体221と、第2放電導体222のギャップを隔てて対向する部分が露出している。空洞224を設けたので、気中放電を発生させてESD放電特性を安定化することができる。 As shown in FIG. 3D, a cavity 224 is provided between the discharge part forming layer 22 and the input / output conductor forming layer 21. A portion of the cavity 224 that faces the gap between the first discharge conductor 221 and the second discharge conductor 222 is exposed. Since the cavity 224 is provided, air discharge can be generated to stabilize the ESD discharge characteristics.
 第1放電導体221と、第2放電導体222とを接続するように、放電部形成層22に補助電極223が設けられている。補助電極223は絶縁性材料コート金属粒子および半導体粒子の分散体からなる。補助電極223により、放電開始電圧を、適度な電圧に調整することができる。絶縁材料コート金属粒子225と半導体粒子226とからなる補助電極223がガラス様物質227中に分散配置されており、より多くの沿面が形成されるのでESD放電特性は安定したものになる。 An auxiliary electrode 223 is provided on the discharge portion forming layer 22 so as to connect the first discharge conductor 221 and the second discharge conductor 222. The auxiliary electrode 223 is made of a dispersion of insulating material-coated metal particles and semiconductor particles. With the auxiliary electrode 223, the discharge start voltage can be adjusted to an appropriate voltage. The auxiliary electrodes 223 made of the insulating material coated metal particles 225 and the semiconductor particles 226 are dispersed in the glass-like material 227, and more creepage is formed, so that the ESD discharge characteristics are stable.
 以下に、焼結体2の製造方法を説明する。Ba,AlおよびSiを主体とするBAS材を所定の組成となるように混合し、仮焼、粉砕してセラミック粉末を得る。セラミック粉末と、有機溶媒、バインダー及び可塑剤からなるスラリーをドクターブレード法で成形してセラミックグリーンシートを得る。平均粒形2μmのCu粒子80重量%と、バインダーと、有機溶剤とを撹拌、混合し導電性ペーストを得る。 Below, the manufacturing method of the sintered compact 2 is demonstrated. A BAS material mainly composed of Ba, Al and Si is mixed so as to have a predetermined composition, calcined and pulverized to obtain a ceramic powder. A ceramic green sheet is obtained by molding a slurry comprising ceramic powder, an organic solvent, a binder and a plasticizer by a doctor blade method. A conductive paste is obtained by stirring and mixing 80% by weight of Cu particles having an average particle size of 2 μm, a binder, and an organic solvent.
 平均粒径4μmのCu粒子の表面に平均粒径数nm~数十nmのAl2O3粉末を付着させてなる、金属粒子を用意する。この金属粒子に平均粒径1μmのSiC粉末、バインダー樹脂及び溶剤を混合し、補助電極用ペーストを得る。 A metal particle is prepared by adhering Al2O3 powder having an average particle size of several nm to several tens of nm to the surface of Cu particles having an average particle size of 4 μm. The metal particles are mixed with SiC powder having an average particle diameter of 1 μm, a binder resin, and a solvent to obtain an auxiliary electrode paste.
 空洞224を形成する焼失性材料として、ポリエチレンテルフタレート(PET)と有機溶剤からなる樹脂ペーストを用意する。入出力用導体形成層21となる上記のセラミックグリーンシートを積層し、表面にインダクタ層23となる上記導電性ペーストを印刷する。その上に放電部形成層22となる上記のセラミックグリーンシートを積層し、その上に、補助電極223となる上記補助電極形成用ペーストを塗布する。 A resin paste made of polyethylene terephthalate (PET) and an organic solvent is prepared as a burnout material for forming the cavity 224. The ceramic green sheets to be the input / output conductor forming layer 21 are laminated, and the conductive paste to be the inductor layer 23 is printed on the surface. The ceramic green sheet to be the discharge portion forming layer 22 is laminated thereon, and the auxiliary electrode forming paste to be the auxiliary electrode 223 is applied thereon.
 しかるのち、第1,第2放電導体221,222となる上記導電性ペーストを印刷する。さらに、空洞224となる上記樹脂ペーストを塗布する。上面に入出力用導体形成層21となるセラミックグリーンシートを積層し、全体を厚み方向に圧着する。このようにして積層体を用意する。しかるのち、押し切りにより上記積層体を切断し、ESD保護デバイス個片を得る。 Thereafter, the conductive paste to be the first and second discharge conductors 221 and 222 is printed. Further, the resin paste that becomes the cavity 224 is applied. A ceramic green sheet to be the input / output conductor forming layer 21 is laminated on the upper surface, and the whole is pressure-bonded in the thickness direction. In this way, a laminate is prepared. Thereafter, the laminate is cut by pressing to obtain an ESD protection device piece.
 次に、入力用側面導体3、出力用側面導体4およびグランド用側面導体5となる導電性ペーストを塗布する。次に、窒素雰囲気中で焼成し、樹脂ペーストが焼失して形成された空洞内に第1、第2放電導体221,222の対向部分が露出したESD保護デバイスを得る。 Next, a conductive paste to be used as the input side conductor 3, the output side conductor 4, and the ground side conductor 5 is applied. Next, it is fired in a nitrogen atmosphere, and an ESD protection device is obtained in which the opposing portions of the first and second discharge conductors 221 and 222 are exposed in a cavity formed by burning out the resin paste.
 なお、入出力用導体形成層21、放電部形成層22および入出力用導体形成層21となるセラミックグリーンシートは単層と複数層のいずれであってもよい。 The ceramic green sheet used as the input / output conductor forming layer 21, the discharge part forming layer 22, and the input / output conductor forming layer 21 may be either a single layer or a plurality of layers.
 図4Aおよび図4BはESD保護デバイス1の等価回路を示す図である。ESD保護デバイス1の信号入力用導体211には、信号を入力する信号ライン10が接続され、信号出力用導体212には信号を出力する信号ライン11が接続される。また、グランド用導体213はグランドに接続される。 4A and 4B are diagrams showing an equivalent circuit of the ESD protection device 1. FIG. The signal input conductor 211 of the ESD protection device 1 is connected to the signal line 10 for inputting a signal, and the signal output conductor 212 is connected to the signal line 11 for outputting a signal. The ground conductor 213 is connected to the ground.
 信号入力用導体211は、入力用側面導体3、およびインダクタLを構成するインダクタ層23の導体パターン231、および出力用側面導体4を介して、信号出力用導体212に接続している。また、信号入力用導体211は、入力用側面導体3、放電部形成層22の放電導体221,222、およびグランド用側面導体5を介してグランド用導体213に接続されている。 The signal input conductor 211 is connected to the signal output conductor 212 via the input side conductor 3, the conductor pattern 231 of the inductor layer 23 constituting the inductor L, and the output side conductor 4. The signal input conductor 211 is connected to the ground conductor 213 via the input side conductor 3, the discharge conductors 221 and 222 of the discharge portion forming layer 22, and the ground side conductor 5.
 換言すれば、入力用の信号ライン10が接続される信号入力用導体211は、インダクタLを介して、出力用の信号ライン11が接続される信号出力用導体212に接続されている。また、信号入力用導体211は、放電導体221,222を介してグランドに接続されている。 In other words, the signal input conductor 211 to which the input signal line 10 is connected is connected via the inductor L to the signal output conductor 212 to which the output signal line 11 is connected. The signal input conductor 211 is connected to the ground via the discharge conductors 221 and 222.
 図4Aに示す回路において、平時に信号ライン10から信号が入力されても、放電導体221,222は高い抵抗を持っているため、信号が放電導体221,222を介してグランド側に流れることはない。この場合、信号ライン10から入力される信号は、インダクタLを介して信号出力用導体212に流れ、信号ライン11から出力される。 In the circuit shown in FIG. 4A, even if a signal is input from the signal line 10 during normal times, the discharge conductors 221 and 222 have a high resistance, so that the signal does not flow to the ground side through the discharge conductors 221 and 222. Absent. In this case, a signal input from the signal line 10 flows to the signal output conductor 212 via the inductor L and is output from the signal line 11.
 一方、信号ライン10に静電気が加わり、過大な電圧が信号ライン10上に加わると、放電導体221,222間で放電が起こり、サージがグランド側に導かれる。また、インダクタLは高周波成分を通さないため、サージの高周波成分が信号ライン10から信号ライン11へ流れるのを抑制している。これにより、ESD保護デバイス1は、信号ライン11に接続される後段のICに静電気による電圧が印加されることを防ぎ、後段のICを静電気から保護する。 On the other hand, when static electricity is applied to the signal line 10 and an excessive voltage is applied to the signal line 10, a discharge occurs between the discharge conductors 221, 222, and a surge is guided to the ground side. Further, since the inductor L does not pass the high frequency component, the high frequency component of the surge is suppressed from flowing from the signal line 10 to the signal line 11. As a result, the ESD protection device 1 prevents a voltage due to static electricity from being applied to the subsequent IC connected to the signal line 11 and protects the subsequent IC from static electricity.
 以上説明したように、本実施形態では、ESD保護デバイス1の後段に接続されるICを静電気から保護することができる。このESD保護デバイス1は、焼結体2を構成する各セラミック基板の導体パターンを、側面導体3,4,5により導通している。 As described above, in this embodiment, the IC connected to the subsequent stage of the ESD protection device 1 can be protected from static electricity. In the ESD protection device 1, the conductor patterns of the ceramic substrates constituting the sintered body 2 are conducted by the side conductors 3, 4, and 5.
 これにより、発生する静電気の高電圧によりビア導体が破断し、ESD保護デバイス1が機能しなくなることを防止することができる。 Thereby, it is possible to prevent the via conductor from being broken by the high voltage of the generated static electricity and the ESD protection device 1 from functioning.
 また、焼結体2において、放電部形成層22を入出力用導体形成層21の近くに積層しているが、放電部形成層22とインダクタ層23とを反対順に積層した場合、図4Bに示すように、信号入力用導体211と放電導体221との間に不要なインダクタンス成分LSが発生し易い。高周波成分がインダクタンス成分LSにより遮断され、放電導体221,222による放電性能が低下する。ESD保護デバイスが放電しないため、後段に静電気が流れてしまう。このため、放電部形成層22を入出力用導体形成層21の近くに積層することで、インダクタンス成分LSによる静電気の放電への影響を無くし、より効果的な静電気の放電を行うことができる。 Further, in the sintered body 2, the discharge part forming layer 22 is stacked near the input / output conductor forming layer 21, but when the discharge part forming layer 22 and the inductor layer 23 are stacked in the opposite order, FIG. As shown, an unnecessary inductance component LS is easily generated between the signal input conductor 211 and the discharge conductor 221. The high frequency component is blocked by the inductance component LS, and the discharge performance by the discharge conductors 221 and 222 is lowered. Since the ESD protection device does not discharge, static electricity flows to the subsequent stage. For this reason, by laminating the discharge part forming layer 22 near the input / output conductor forming layer 21, it is possible to eliminate the influence of the inductance component LS on the discharge of static electricity and perform more effective discharge of static electricity.
(実施形態2)
 実施形態1では、ミアンダ状に形成した線状の導体パターンによりインダクタ層のインダクタLを構成しているが、実施形態2では、インダクタ層23を複数層から形成し、インダクタLを積層インダクタとしている点で実施形態1と相違する。以下、相違点についてのみ説明する。
(Embodiment 2)
In the first embodiment, the inductor L of the inductor layer is configured by a linear conductor pattern formed in a meander shape. However, in the second embodiment, the inductor layer 23 is formed of a plurality of layers, and the inductor L is a multilayer inductor. This is different from the first embodiment. Only the differences will be described below.
 図5は、インダクタ層を構成する各セラミック基板の概略平面図である。図5は、インダクタ層を下方向から見たみた各セラミック基板の下面図である。図6は、実施形態2に係るインダクタ層の側面断面図である。 FIG. 5 is a schematic plan view of each ceramic substrate constituting the inductor layer. FIG. 5 is a bottom view of each ceramic substrate when the inductor layer is viewed from below. FIG. 6 is a side sectional view of the inductor layer according to the second embodiment.
 インダクタ層6は、第1セラミック基板61、第2セラミック基板62、第3セラミック基板63および第4セラミック基板64が積層されて構成されている。 The inductor layer 6 is formed by laminating a first ceramic substrate 61, a second ceramic substrate 62, a third ceramic substrate 63, and a fourth ceramic substrate 64.
 図5(a)に示す第1セラミック基板61は、インダクタ層の最上層となり、線状の導体パターン611が第1セラミック基板61の一の短辺から長辺に沿って延びている。この導体パターン611は、第1セラミック基板61の各辺に平行となるよう、外側から内側中心(以下、A点という)に向かって時計方向に巻回して形成されている。 The first ceramic substrate 61 shown in FIG. 5A is the uppermost layer of the inductor layer, and a linear conductor pattern 611 extends from one short side of the first ceramic substrate 61 along the long side. The conductor pattern 611 is formed by being wound clockwise from the outside toward the inside center (hereinafter referred to as point A) so as to be parallel to each side of the first ceramic substrate 61.
 図5(b)に示す第2セラミック基板62は、第1セラミック基板61の下方に積層されている。第2セラミック基板62には線状の導体パターン621が、第2セラミック基板62の各辺に平行となるよう、第1セラミック基板61のA点と厚み方向に一致する位置から外側に向かって時計方向に巻回して形成されている。以下、導体パターン621の外側の端部の位置をB点とする。 The second ceramic substrate 62 shown in FIG. 5B is laminated below the first ceramic substrate 61. On the second ceramic substrate 62, a linear conductor pattern 621 is clocked outward from a position coincident with the point A of the first ceramic substrate 61 in the thickness direction so as to be parallel to each side of the second ceramic substrate 62. It is formed by winding in the direction. Hereinafter, the position of the outer end portion of the conductor pattern 621 is defined as B point.
 図5(c)に示す第3セラミック基板63は、第2セラミック基板62の下方に積層されている。第3セラミック基板63には線状の導体パターン631が、第3セラミック基板63の各辺に平行となるよう、第2セラミック基板62のB点と厚み方向に一致する位置から内側に向かって時計方向に巻回して形成されている。以下、導体パターン631の外側の端部の位置をC点とする。 The third ceramic substrate 63 shown in FIG. 5C is laminated below the second ceramic substrate 62. On the third ceramic substrate 63, a linear conductor pattern 631 is clocked inward from a position coincident with the point B of the second ceramic substrate 62 in the thickness direction so as to be parallel to each side of the third ceramic substrate 63. It is formed by winding in the direction. Hereinafter, the position of the outer end portion of the conductor pattern 631 is defined as a C point.
 図5(d)に示す第4セラミック基板64は、第3セラミック基板63の下方に積層されている。第4セラミック基板64には線状の導体パターン641が、第4セラミック基板64の各辺に平行となるよう、第3セラミック基板63のC点と厚み方向に一致する位置から外側に向かって時計方向に巻回し、第4セラミック基板64の一の短辺まで延びて形成されている。 The fourth ceramic substrate 64 shown in FIG. 5D is laminated below the third ceramic substrate 63. On the fourth ceramic substrate 64, a linear conductor pattern 641 is clocked outward from a position coincident with the point C of the third ceramic substrate 63 in the thickness direction so as to be parallel to each side of the fourth ceramic substrate 64. It is wound in the direction and extends to one short side of the fourth ceramic substrate 64.
 第1セラミック基板61の導体パターン611は入力用側面導体3と導通している。また、第4セラミック基板64の導体パターン641は出力用側面導体4と導通している。さらに各セラミック基板61,62,63,64の導体パターン611,621,631,641は、各A点、B点およびC点においてベア接続により接続されている。 The conductor pattern 611 of the first ceramic substrate 61 is electrically connected to the input side conductor 3. Further, the conductor pattern 641 of the fourth ceramic substrate 64 is electrically connected to the output side conductor 4. Furthermore, the conductor patterns 611, 621, 631, 641 of the ceramic substrates 61, 62, 63, 64 are connected by bare connection at points A, B, and C.
 各セラミック基板となるセラミックグリーンシートには、貫通するビア穴が炭酸ガスレーザを照射して穿孔するなどの方法により形成され、その後、導体パターンの印刷と同時にビア穴に導電性ペーストが充填される。すなわち、導電パターンおよびビア接続部分は同じ一の工程で形成される。上記導電性ペーストを充填した後にセラミックグリーンシートを複数枚積層し圧着および焼成することによりESD保護デバイスを製造する。このため、異なる層間の導体パターンの接続部分の抵抗値のばらつきは、導電パターンの印刷と、ビア穴への充填とを別工程で形成した場合に比べて小さくなる。 In the ceramic green sheet to be each ceramic substrate, a via hole penetrating is formed by a method such as piercing by irradiating a carbon dioxide laser, and then the via hole is filled with a conductive paste simultaneously with the printing of the conductor pattern. That is, the conductive pattern and the via connection portion are formed in the same one process. An ESD protection device is manufactured by laminating a plurality of ceramic green sheets after being filled with the conductive paste, followed by pressure bonding and firing. For this reason, the variation in resistance value of the connection part of the conductor pattern between different layers is smaller than that in the case where the printing of the conductive pattern and the filling of the via hole are formed in separate processes.
 通常は、セラミック基板の導体パターンと異なる層間の導体パターンを電気的に接続するビア導体とはそれぞれ別工程で形成されるため、同一の導電性ペーストを用いても完全に同じ材質ではなくなる。また、通常は、ビア導体形成用導電性ペーストは充填性の良いものが選ばれ、導体パターン形成用導電性ペーストは印刷性のよいものが選ばれる。このため、ESD保護デバイス1における導体パターンとビア導体との接続は、異種材質同士の接続となり、接続部分の抵抗値が変動しやすくなる。このため、ESD保護デバイス1の放電特性のばらつきが大きくなり、ESD保護デバイス1に対する信頼性が低下するおそれがある。 Usually, via conductors that electrically connect conductor patterns between layers different from those of the ceramic substrate are formed in different processes, so even if the same conductive paste is used, they are not completely the same material. In general, a conductive paste for forming a via conductor is selected to have a good filling property, and a conductive paste for forming a conductor pattern is selected to have a good printability. For this reason, the connection between the conductor pattern and the via conductor in the ESD protection device 1 is a connection between different materials, and the resistance value of the connection portion is likely to vary. For this reason, the dispersion | variation in the discharge characteristic of the ESD protection device 1 becomes large, and there exists a possibility that the reliability with respect to the ESD protection device 1 may fall.
 そこで、本実施形態2のように、導体パターンとベア接続部分とを同じ一工程で形成することで、導体パターンとベア接続部分とは同じ材質となるため、接続部分の抵抗値を略均一にすることができ、ESD保護デバイス1に対する信頼性が低下することを防止することができる。 Therefore, as in the second embodiment, by forming the conductor pattern and the bare connection portion in the same process, the conductor pattern and the bare connection portion are made of the same material, so that the resistance value of the connection portion is substantially uniform. It is possible to prevent the reliability of the ESD protection device 1 from being lowered.
 以上、本発明に係るESD保護デバイス1について説明したが、具体的構成などは、適宜設計変更可能であり、上述の実施形態に記載された作用及び効果は、本発明から生じる最も好適な作用及び効果を列挙したに過ぎず、本発明による作用及び効果は、上述の実施形態に記載されたものに限定されるものではない。 Although the ESD protection device 1 according to the present invention has been described above, the specific configuration and the like can be appropriately changed in design, and the functions and effects described in the above-described embodiments are the most preferable functions and effects resulting from the present invention. The effects are merely listed, and the operations and effects of the present invention are not limited to those described in the above-described embodiment.
 例えば、ESD保護デバイス1の焼結体2に、キャパシタ層をさらに積層させるようにしてもよい。図7Aおよび図7Bはキャパシタ層を積層させた場合のESD保護デバイス1の等価回路を示す。キャパシタ層とは、表面に形成する導体パターンによりキャパシタCが構成されるセラミック基板である。 For example, a capacitor layer may be further laminated on the sintered body 2 of the ESD protection device 1. 7A and 7B show an equivalent circuit of the ESD protection device 1 when capacitor layers are stacked. The capacitor layer is a ceramic substrate in which the capacitor C is constituted by a conductor pattern formed on the surface.
 例えば、入出力層、放電層、インダクタ層およびキャパシタ層の順に積層させ、キャパシタCを構成する導体パターンの一端を出力用側面導体4に接続し、他端をグランド用側面導体5に接続する構成とする。この場合、図7Aに示すように、インダクタ層のインダクタLと、キャパシタ層のキャパシタCとにより、ローパスフィルタが構成される。 For example, the input / output layer, the discharge layer, the inductor layer, and the capacitor layer are stacked in this order, and one end of the conductor pattern constituting the capacitor C is connected to the output side conductor 4 and the other end is connected to the ground side conductor 5. And In this case, as shown in FIG. 7A, the inductor L in the inductor layer and the capacitor C in the capacitor layer constitute a low-pass filter.
 ローパスフィルタをESD保護デバイス1に構成することで、高周波回路で用いられるローパスフィルタをESD保護デバイス1内に組み込むことができる。これにより、ローパスフィルタの素子を実装する面積が不要となり、回路面積を小さくすることができる。 By configuring the low-pass filter in the ESD protection device 1, the low-pass filter used in the high-frequency circuit can be incorporated in the ESD protection device 1. As a result, the area for mounting the low-pass filter element becomes unnecessary, and the circuit area can be reduced.
 また、例えば、入出力層、放電層、キャパシタ層およびインダクタ層の順に積層させ、キャパシタCを構成する導体パターンの一端を入力用側面導体3に接続し、他端を出力用側面導体4に接続し、さらに、インダクタLの一端を出力用側面導体4に接続し、他端をグランド用側面導体5に接続する構成とする。この場合、図7Bに示すように、インダクタ層のインダクタLと、キャパシタ層のキャパシタCとにより、ハイパスフィルタが構成される。 Further, for example, the input / output layer, the discharge layer, the capacitor layer, and the inductor layer are stacked in this order, and one end of the conductor pattern constituting the capacitor C is connected to the input side conductor 3 and the other end is connected to the output side conductor 4. In addition, one end of the inductor L is connected to the output side conductor 4 and the other end is connected to the ground side conductor 5. In this case, as shown in FIG. 7B, the inductor L in the inductor layer and the capacitor C in the capacitor layer constitute a high-pass filter.
 ハイパスフィルタを設けることで、入出力間がキャパシタCにより直流的に遮断されるため、ESD保護デバイス1の後段に接続される回路へのサージエネルギーを充分に抑制できる。 By providing a high-pass filter, the input and output are cut off in a DC manner by the capacitor C, so that the surge energy to the circuit connected to the subsequent stage of the ESD protection device 1 can be sufficiently suppressed.
1-ESD保護デバイス
2-焼結体(積層体)
21-入出力用導体形成層
22-放電部形成層
23-インダクタ層
3-入力用側面導体(第1側面導体)
211-信号入力用導体
212-信号出力用導体
213-グランド用導体
221,222-放電導体(放電部、第1放電導体、第2放電導体)
223-補助電極
224-空洞
225-絶縁材料コート金属粒子
226-半導体粒子
227-ガラス様物質
4-出力用側面導体(第2側面導体)
5-グランド用側面導体(第3側面導体)
1-ESD protection device 2-sintered body (laminated body)
21-Input / output conductor forming layer 22-Discharge portion forming layer 23-Inductor layer 3-Input side conductor (first side conductor)
211—Signal input conductor 212—Signal output conductor 213— Ground conductors 221, 222—Discharge conductor (discharge section, first discharge conductor, second discharge conductor)
223-auxiliary electrode 224-cavity 225-insulating material coated metal particle 226-semiconductor particle 227-glass-like substance 4-side conductor for output (second side conductor)
5-side conductor for ground (third side conductor)

Claims (7)

  1.  複数の絶縁体基層が積層されてなる積層体と、
     前記積層体の側面に設けられた第1側面導体、第2側面導体および第3側面導体と、
     を備えるESD保護デバイスにおいて、
     前記積層体は、
     前記第1側面導体に導通する信号入力用導体、前記第2側面導体に導通する信号出力用導体、および前記第3側面導体に導通するグランド用導体が形成された入出力用導体形成層と、
     前記第1側面導体および前記第3側面導体それぞれに導通する放電部が形成された放電部形成層と、
     前記第1側面導体および前記第2側面導体を導通するインダクタパターンが構成されているインダクタ層と、
     を有しているESD保護デバイス。
    A laminate formed by laminating a plurality of insulator base layers;
    A first side conductor, a second side conductor and a third side conductor provided on the side surface of the laminate;
    In an ESD protection device comprising:
    The laminate is
    An input / output conductor forming layer in which a signal input conductor conducting to the first side conductor, a signal output conductor conducting to the second side conductor, and a ground conductor conducting to the third side conductor;
    A discharge part forming layer in which a discharge part conducting to each of the first side conductor and the third side conductor is formed;
    An inductor layer in which an inductor pattern that conducts the first side conductor and the second side conductor is formed;
    An ESD protection device.
  2.  前記放電部形成層の放電部は、
     間隔を隔てて互いに対向しあっている第1放電導体および第2放電導体を有し、
     前記第1放電導体は前記第1側面導体に導通し、前記第2放電導体は前記第3側面導体に導通している、請求項1に記載のESD保護デバイス。
    The discharge part of the discharge part forming layer is
    Having a first discharge conductor and a second discharge conductor facing each other at an interval;
    The ESD protection device according to claim 1, wherein the first discharge conductor is electrically connected to the first side conductor, and the second discharge conductor is electrically connected to the third side conductor.
  3.  前記積層体は、前記入出力用導体形成層、前記放電部形成層およびインダクタ層の順に積層されてなる、請求項1又は2に記載のESD保護デバイス。 3. The ESD protection device according to claim 1, wherein the multilayer body is formed by laminating the input / output conductor formation layer, the discharge portion formation layer, and the inductor layer in this order.
  4.  前記入出力用導体形成層と前記放電部形成層間の界面の前記第1放電導体と、第2放電導体の間隔を隔てて互いに対向しあっている部分に空洞が設けられている、請求項2又は3に記載のESD保護デバイス。 The cavity is provided in the part which has mutually opposed the said 1st discharge conductor of the interface between the said input / output conductor formation layer and the said discharge part formation layer, and the 2nd discharge conductor. Or the ESD protection device according to 3.
  5.  前記第1放電導体と前記第2放電導体とを接続する、前記放電部形成層に設けられた補助電極をさらに備え、
     該補助電極は絶縁性材料コート金属粒子および半導体粒子の分散体からなる、請求項2から4の何れか一つに記載のESD保護デバイス。
    An auxiliary electrode provided on the discharge portion forming layer for connecting the first discharge conductor and the second discharge conductor;
    The ESD protection device according to any one of claims 2 to 4, wherein the auxiliary electrode is made of a dispersion of insulating material-coated metal particles and semiconductor particles.
  6.  前記インダクタパターンはミアンダ状に形成されている、請求項1から5の何れか一つに記載のESD保護デバイス。 The ESD protection device according to any one of claims 1 to 5, wherein the inductor pattern is formed in a meander shape.
  7.  前記インダクタ層は、導体パターンが形成された絶縁体層が複数積層され、前記絶縁体層に形成された前記導体パターンが絶縁体層のビア穴内に位置する下層の絶縁体層の導体パターンに直接層間接続されて形成された積層インダクタである、請求項1から6の何れか一つに記載のESD保護デバイス。 The inductor layer is formed by laminating a plurality of insulator layers on which a conductor pattern is formed, and the conductor pattern formed on the insulator layer is directly on the conductor pattern of the lower insulator layer located in the via hole of the insulator layer. The ESD protection device according to any one of claims 1 to 6, wherein the ESD protection device is a multilayer inductor formed by interlayer connection.
PCT/JP2012/061342 2011-05-10 2012-04-27 Esd protection device WO2012153655A1 (en)

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JPH0443889U (en) * 1990-08-14 1992-04-14
JP2003123936A (en) * 2001-10-16 2003-04-25 Matsushita Electric Ind Co Ltd Electronic part and method of manufacturing the same
JP2005260137A (en) * 2004-03-15 2005-09-22 Matsushita Electric Ind Co Ltd Antistatic electricity component
JP2006294724A (en) * 2005-04-07 2006-10-26 Matsushita Electric Ind Co Ltd Composite electronic component and its manufacturing method
WO2009098944A1 (en) * 2008-02-05 2009-08-13 Murata Manufacturing Co., Ltd. Esd protection device

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JPH0443889U (en) * 1990-08-14 1992-04-14
JP2003123936A (en) * 2001-10-16 2003-04-25 Matsushita Electric Ind Co Ltd Electronic part and method of manufacturing the same
JP2005260137A (en) * 2004-03-15 2005-09-22 Matsushita Electric Ind Co Ltd Antistatic electricity component
JP2006294724A (en) * 2005-04-07 2006-10-26 Matsushita Electric Ind Co Ltd Composite electronic component and its manufacturing method
WO2009098944A1 (en) * 2008-02-05 2009-08-13 Murata Manufacturing Co., Ltd. Esd protection device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015138932A (en) * 2014-01-24 2015-07-30 Tdk株式会社 Static electricity protection component

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