WO2012147962A1

WO2012147962A1 - Liquid crystal display device

Info

Publication number: WO2012147962A1
Application number: PCT/JP2012/061472
Authority: WO
Inventors: 孝司上野
Original assignee: シャープ株式会社
Priority date: 2011-04-28
Filing date: 2012-04-27
Publication date: 2012-11-01
Also published as: WO2012147962A8

Abstract

This liquid crystal display device is provided with first and second scan signal lines formed in a display part, first and second wires formed in a non-display part, and a scan signal line driving circuit. The first and second wires are formed in different layers, the scan signal line driving circuit is connected to the first scan signal line via the first wire and connected to the second scan signal line via the second wire, the time constant of the first wire is smaller than the time constant of the second wire, and a first scan pulse outputted from the scan signal line driving circuit to the first wire includes a first inclined section at the termination thereof ranging from an active level to a non-active level. The display quality of the liquid crystal display device is improved by the abovementioned configuration.

Description

Liquid crystal display

The present invention relates to a liquid crystal display device.

In a liquid crystal display device in which a plurality of scanning signal lines of a display portion and a scanning signal line driving circuit (gate driver) are connected via a plurality of wirings formed in the non-display portion, the non-display portion is reduced (narrowed). For the purpose of (framed), a configuration has been proposed in which these wirings are arranged in two layers (three-dimensionally arranged).

JP-A-9-127540

In the above configuration, the inventor determines the time constant of the first wiring arranged on one of the two layers (product of parasitic capacitance and parasitic resistance) and the time constant of the second wiring arranged on the other (parasitic capacitance and parasitic resistance). The waveform of the scanning pulse supplied to the scanning signal line connected to the first wiring and the scanning pulse supplied to the scanning signal line connected to the second wiring are different, and the display portion has a horizontal stripe shape. We found a problem that unevenness is likely to appear.

An object of the present invention is to improve the display quality of a liquid crystal display device that performs three-dimensional wiring in a non-display portion.

The liquid crystal display device includes first and second scanning signal lines formed in a display portion, first and second wirings formed in a non-display portion, and a scanning signal line driving circuit. Two wirings are formed in different layers, and the scanning signal line driving circuit is connected to the first scanning signal line through the first wiring and is connected to the second scanning signal line through the second wiring, The time constant of the first wiring is smaller than the time constant of the second wiring, and the first scanning pulse output from the scanning signal line driving circuit to the first wiring is first at the end from the active level to the inactive level. An inclined portion is included.

In this way, by providing the first inclined portion in the first scanning pulse output to the first wiring having a small time constant, the first scanning pulse and the second scanning pulse (scanning output to the second wiring having a large time constant). Pulse) when each of them is supplied to the first and second scanning signal lines via the first and second wirings, the pull-in voltage associated with the deactivation of the first scanning pulse and the deactivation of the second scanning pulse. Thus, the difference from the pull-in voltage associated with can be reduced. Thereby, horizontal stripe-shaped display unevenness can be suppressed and display quality can be improved.

According to the present invention, it is possible to improve the display quality of a liquid crystal display device that performs three-dimensional wiring in a non-display portion.

1 is a schematic diagram illustrating a configuration of a liquid crystal display device of Example 1. FIG. 2 is a cross-sectional view of the liquid crystal panel of Example 1. FIG. 3 is a schematic diagram illustrating a pixel configuration of the liquid crystal display device of Example 1. FIG. 3 is a plan view of a liquid crystal panel of Example 1. FIG. FIG. 6 is a cross-sectional view taken along the line Y-Y ′ of FIG. 5. 3 is an equivalent circuit diagram illustrating a pixel configuration of the liquid crystal panel of Example 1. FIG. It is a schematic diagram which shows the conventional scanning pulse. FIG. 3 is a schematic diagram illustrating scanning pulses of the liquid crystal display device according to the first embodiment. 3 is a schematic diagram illustrating a configuration of a gate driver according to Embodiment 1. FIG. 10 is a timing chart showing the operation of the gate driver of FIG. 9. FIG. 3 is a schematic diagram illustrating another configuration of the gate driver according to the first embodiment. It is a table | surface which shows an example of a register | resistor. 12 is a timing chart illustrating an operation of the gate driver of FIG. 11. 12 is a timing chart showing another operation of the gate driver of FIG. 11. 15 is a table showing an example of register input in FIG. 14. 12 is a timing chart showing still another operation of the gate driver of FIG. 17 is a table showing an example of register input in FIG. 16. 12 is a timing chart showing still another operation of the gate driver of FIG. FIG. 19 is a table showing an example of register input in FIG. 18. FIG. It is a schematic diagram which shows the example of input of each scanning pulse. FIG. 6 is a schematic diagram illustrating a scan pulse setting method (previous two lines) in the first embodiment. FIG. 3 is a schematic diagram illustrating a scan pulse setting method (rear two lines) in the first embodiment. FIG. 6 is a schematic diagram illustrating an example of setting each scanning pulse in the first embodiment. 6 is a schematic diagram illustrating an example of pixel writing polarity (H line inversion) in Embodiment 1. FIG. FIG. 6 is a schematic diagram illustrating an example of pixel writing polarity in Example 1 (vertical 1 dot horizontal 1 dot inversion). FIG. 6 is a schematic diagram illustrating an example of pixel writing polarity in Example 1 (vertical 2 dots, horizontal 1 dot inversion). 6 is a schematic diagram illustrating an example of pixel writing polarity (V-line inversion) in Embodiment 1. FIG. FIG. 6 is a schematic diagram illustrating a configuration of a gate driver according to a second embodiment. FIG. 29 is a timing chart showing an operation of the gate driver of FIG. 28. FIG. FIG. 10 is a schematic diagram illustrating another configuration of the gate driver according to the second embodiment. FIG. 31 is a timing chart showing an operation of the gate driver of FIG. 30. FIG. FIG. 31 is a timing chart showing still another operation of the gate driver of FIG. 30. FIG. FIG. 31 is a timing chart showing still another operation of the gate driver of FIG. 30. FIG. 6 is a schematic diagram illustrating a configuration of a liquid crystal display device of Example 3. FIG. FIG. 6 is a schematic diagram illustrating a pixel configuration and a scan pulse input configuration of a liquid crystal display device of Example 3. FIG. 9 is a schematic diagram illustrating a scan pulse setting method (previous two lines) in Example 3. FIG. 10 is a schematic diagram illustrating a scan pulse setting method (rear two lines) in the third embodiment. FIG. 10 is a schematic diagram illustrating an example of pixel writing polarity (H line inversion) in Example 3. FIG. 6 is a schematic diagram illustrating an example of pixel writing polarity in Example 3 (vertical 1 dot horizontal 1 dot inversion). FIG. 10 is a schematic diagram illustrating an example of pixel writing polarity in Example 3 (vertical 2 dots, horizontal 1 dot inversion). FIG. 10 is a schematic diagram illustrating an example of pixel writing polarity in Example 3 (V-line inversion). It is a schematic diagram which shows one structural example of this liquid crystal display device.

The embodiment of the present invention will be described with reference to FIGS. 1 to 42 as follows. In the description of the liquid crystal display device, the term “column direction (the direction perpendicular to the column direction is the row direction)” is used for convenience of description. The “column direction” may be the vertical direction or the horizontal direction.

[Example 1]
FIG. 1 is a schematic diagram illustrating the configuration of the liquid crystal display device according to the first embodiment. As shown in FIG. 1, the liquid crystal display device 1 includes a liquid crystal panel 2, a driver 5 in which a scanning signal line driving circuit and a data signal line driving circuit are integrated on one chip, and a display control circuit 4. The liquid crystal panel 2 is driven by a driver 5, and the driver 5 is controlled by a display control circuit 4. The liquid crystal panel 2 includes an active matrix substrate, a counter substrate (for example, a color filter substrate), and a liquid crystal layer disposed between the two substrates, and a plurality of subpixels are provided in a matrix on the display unit. The non-display portion is provided with four wirings Ha (first wiring), Hb (third wiring), Hc (second wiring), and Hd (fourth wiring).

Each sub-pixel includes a pixel electrode formed on the active matrix substrate, a counter electrode formed on the counter substrate, and a liquid crystal layer between the pixel electrode and the corresponding electrode, and has a plurality of primary colors (for example, red, green, and blue). Display one. The pixel electrode of each subpixel is connected to a data signal line through a transistor, and this transistor is connected to a scanning signal line. Note that the data signal lines extend in the column direction, and the scanning signal lines extend in the row direction.

One pixel is composed of three sub-pixels arranged in the column direction (scanning direction) that display different primary colors (triple scan method). For example, the pixel P in FIG. 1 includes R (red) sub-pixels, G (green) sub-pixels, and B (blue) sub-pixels arranged in the column direction. Driven by the signal line D and the scanning signal line Ga (first scanning signal line), the G sub-pixel is driven by the data signal line D and the scanning signal line Gb (third scanning signal line), and the B sub-pixel is Driven by the data signal line D and the scanning signal line Gc (second scanning signal line). Further, the sub pixel (R) adjacent to the downstream side of the B sub pixel in the scanning direction is driven by the data signal line D and the scanning signal line Gd (fourth scanning signal line). The scanning signal lines Ga to Gd are arranged in this order along the scanning direction.

A plurality of sub-pixels arranged in the row direction (a plurality of sub-pixels included in the same row) are driven by the same scanning signal line and display the same primary color. For example, a plurality of subpixels included in the same row as the R subpixel of the pixel P are driven by the scanning signal line Ga to display R. A plurality of sub-pixels included in the same row as the G sub-pixel of the pixel P are driven by the scanning signal line Gb to display R. A plurality of sub-pixels included in the same row as the B sub-pixel of the pixel P are driven by the scanning signal line Gc to display B.

The scanning signal line Ga is connected to the driver 5 via the wiring Ha, the scanning signal line Gb is connected to the driver 5 via the wiring Hb, and the scanning signal line Gc is connected to the driver 5 via the wiring Hc. The scanning signal line Gd is connected to the driver 5 via the wiring Hd, and the scanning pulse output from the driver 5 is supplied to the scanning signal lines Ga to Gd via the wirings Ha to Hd. The display unit of the liquid crystal panel 2 has a rectangular shape surrounded by the first and second short sides E1 and E2 and the four sides of the first and second long sides, and the wirings Ha and Hc have the first short side E1. The wirings Hb and Hd pass through the outside of the second short side E2.

FIG. 2 is a cross-sectional view showing the structure of the active matrix substrate in region X (region surrounded by oblique lines) in FIG. As shown in FIG. 2, a wiring Ha is formed on a transparent substrate (glass substrate) 30 (on the gate layer GL), a gate insulating film 21 is formed so as to cover the wiring Ha, and a source insulating film 21 is formed on the gate insulating film 21 (source A wiring Hc is formed on the layer SL, an inorganic interlayer insulating film 25 is formed so as to cover the wiring Hc, and a thicker organic interlayer insulating film 26 is formed on the inorganic interlayer insulating film 25. Although not shown, the wiring Hb is formed in the same layer (gate layer GL) as the wiring Ha, and the wiring Hd is formed in the same layer (source layer SL) as the wiring Hc. FIG. 3 shows a corresponding primary color, a formation layer (GL or SL) of a connected wiring, and a via area (outside of the first short side E1 or outside of the second short side E2) for each subpixel row. Let me show you. Thus, by forming the wirings Ha to Hd in two layers (GL and SL), the non-display portion can be reduced (narrow frame).

FIG. 4 is a plan view of a portion corresponding to the pixel P (see FIG. 1) of the active matrix substrate. As shown in FIG. 4, the pixel electrode 17a of the R sub-pixel, the pixel electrode 17b of the G sub-pixel, and the pixel electrode 17c of the B sub-pixel are arranged in the scanning direction along the data signal line D. A scanning signal line Ga is disposed between the electrode 17a and the pixel electrode 17b, and a scanning signal line Gb is disposed between the pixel electrode 17b and the pixel electrode 17c. A part of the scanning signal line Ga is a gate electrode of the transistor 12, the source electrode 7 of the transistor 12 is connected to the data signal line D, the drain electrode 8 of the transistor 12 is connected to the drain extraction electrode 27, and the drain extraction The electrode 27 is connected to the pixel electrode 17 a through the contact hole 11. Further, the capacitor electrode 127 formed in the same layer as the data signal line D is connected to the pixel electrode 17a through the contact hole 111, and the capacitor electrode 127 and the storage capacitor wiring 18 overlap with each other through the gate insulating film. . 5 is a cross-sectional view taken along the line Y-Y 'of FIG. As shown in FIG. 5, the scanning signal line Ga and the storage capacitor line 18 are formed on the transparent substrate (glass substrate) 30, and the gate insulating film 21 is formed so as to cover the scanning signal line Ga and the storage capacitor line 18. A data signal line D and a drain lead electrode 27 are formed on the gate insulating film 21, an inorganic interlayer insulating film 25 is formed so as to cover the data signal line D and the drain lead electrode 27, and on the inorganic interlayer insulating film 25, A thicker organic interlayer insulating film 26 is formed, and a pixel electrode 17 a is formed on the organic interlayer insulating film 26. In the contact hole 11 portion, the inorganic interlayer insulating film 25 and the organic interlayer insulating film 26 are removed, so that the pixel electrode 17a and the drain lead electrode 27 are in contact with each other.

FIG. 6A is an equivalent circuit diagram of the R subpixel and the B subpixel of the pixel P (see FIG. 1). In the R subpixel, a liquid crystal capacitor CLC is formed between the pixel electrode 17a and the counter electrode COM, a storage (storage) capacitor CCS is formed between the pixel electrode 17a and the storage capacitor wiring 18, and the pixel electrode 17a A parasitic capacitance Cgd is formed between the scanning signal line Ga connected to the wiring Ha. The parasitic capacitance Cgd is generated, for example, in an overlapping portion between the scanning signal line Ga and the drain electrode 8 and the drain extraction electrode 27 in FIGS. FIG. 6B is an equivalent circuit diagram of the B subpixel of the pixel P (see FIG. 1). In the sub-pixel B, a liquid crystal capacitor CLC ′ is formed between the pixel electrode 17c and the counter electrode COM, and a storage (storage) capacitor CCS ′ is formed between the pixel electrode 17c and the storage capacitor wiring 18, and the pixel electrode A parasitic capacitance Cgd ′ is formed between 17c and the scanning signal line Gc connected to the wiring Hc.

Here, the potential V (17a) of the pixel electrode 17a is drawn due to the parasitic capacitance Cgd when the transistor 12 is OFF (at the fall of the scanning pulse GPa supplied to the scanning signal line Ga). The potential V (17c) of 17c is drawn due to the parasitic capacitance Cgd 'when the transistor 12' is OFF (at the fall of the scanning pulse GPc supplied to the scanning signal line Gc). When the scanning pulse GPa output to Ha and the scanning pulse GPc output from the driver 5 to the wiring Hc have the same rectangular shape (inactive potential VGL <potential of the counter electrode VCOM <active potential VGH) as shown in FIG. Even if the parasitic capacitance Cgd = parasitic capacitance Cgd ′, the pull-in voltage Δva generated in the pixel electrode 17a is generated in the pixel electrode 17c. Is considerably larger than the actual voltage Δvc, it has been found to be a horizontal-striped display unevenness. This is because the time constant of the wiring Ha (connected to the scanning signal line Ga) formed in the gate layer is the time constant of the wiring Hc (connected to the scanning signal line Gc) formed in the metal layer (parasitic capacitance and parasitic resistance). 7 (b), the scanning pulse gpa supplied to the scanning signal line Ga rises more steeply than the scanning pulse gpc supplied to the scanning signal line Gc. Because it goes down.

Therefore, in the liquid crystal display device according to the first embodiment, as shown in FIG. 8, the end of the scanning pulse GPa output from the driver 5 to the wiring Ha (portion from the active level to the inactive level) and the output from the driver 5 to the wiring Hc. An inclined portion K is provided at each end (portion from the active level to the inactive level) of the scanning pulse GPc to be performed.

As a result, the difference between the pull-in voltage Δva generated in the pixel electrode 17a and the pull-in voltage Δvc generated in the pixel electrode 17c can be reduced (see FIG. 8), and the above-described horizontal stripe-shaped display unevenness can be suppressed. it can. Note that the end of the scanning pulse GPb output from the driver 5 to the wiring Hb and the end of the scanning pulse GPd output from the driver 5 to the wiring Hd are each provided with an inclined portion having the same shape as the end of the scanning pulses GPa and GPc. .

FIG. 9 shows a configuration example of the driver 5 that generates the scanning pulses GPa to GPd including the inclined portion at the end in this way. 9 includes a timing controller Tcon, an inverter INV, a P-channel transistor Tp, an N-channel transistor Tn, a gate circuit GC including a shift register (not shown), a level shifter LS, and a potential of VGH. A power source and a power source having a potential of VGL. The plurality of output ends of the gate circuit GC are connected to the corresponding wirings Ha to Hd, the output end of the level shifter LS is connected to the input end of the inverter INV, and the output end of the inverter INV is the gate terminal of the transistor Tp and the transistor Tn Connected to the gate terminal, the node Nx is connected to the node Ny via the transistor Tp, and the node Nx is connected to one end of the resistor Rx provided outside the driver 5 and provided outside the driver 5. The other end of the resistor Rx is grounded via the transistor Tn, and the node Ny is connected to the output end of a DC-DC converter (not shown) and provided outside the driver 5. It is grounded via the capacitor Cy. The potential Vi of the node Nx is supplied to the gate circuit GC, the potential VGH is supplied to the node Ny, the potential VGL is supplied to the gate circuit GC, and the gate clock GCK and the gate start pulse GSP are supplied from the timing controller Tcon to the gate circuit GC. And the slope clock SLCK is supplied from the timing controller Tcon to the level shifter LS.

FIG. 10 is a timing chart showing the operation of the driver 5 of FIG. Each of the gate clock GCK and the slope clock SLCK is composed of the first to fourth periods (the first to third periods are “H” and the fourth period is “L”), and the third period ( H)) and the fourth period (L) of the slope clock SLCK. When the slope clock SLCK is in the first to third periods (H), the transistor Tp in FIG. 9 is turned on, the transistor Tn is turned off, the potential Vi = VGH supplied to the gate circuit GC, and the capacitor Cx is also charged to VGH. Is done. When the slope clock SLCK is in the fourth period (L), the transistor Tp in FIG. 9 is turned off, the transistor Tn is turned on, the capacitor Cx is discharged through the resistor Rx and the transistor Tn, and the potential supplied to the gate circuit GC Vi gradually decreases from VGH to a predetermined potential higher than VGL over the fourth period (slowly decreases during the fourth period).

Each stage of the gate circuit GC corresponds to one scanning signal line (wiring), and takes in the gate clock GCK in accordance with the inactivation (falling) of the output (or gate start pulse GSP) of the previous stage, With the activation (rise) of the output of the subsequent stage, the capture of the gate clock GCK is terminated, and Vi is output to the corresponding wiring only during the period when the captured gate clock GCK is “H”, and the other (captured GCK VGL is output to the corresponding wiring during a period when “L” is “L” and when GCK is not captured. As a result, scan pulses GPa to GPd as shown in FIG. 10 are output to the wirings Ha to Hd.
Another configuration example of the driver 5 is shown in FIG. The driver 5 in FIG. 11 includes a timing controller Tcon, a slope destination potential setting circuit SVC, a slope amount setting circuit SRC, a slope clock generation circuit SGC, a slope switch circuit SSC, a gate circuit GC including a shift register, A VGL power source, a potential VSS power source, a potential AVDD power source, a potential VDD power source, a potential VCl power source, and a potential VGH power source (VGL <VSS <VDD <VCl <AVDD <VGH). Note that VGH is a gate ON voltage, AVDD is a source analog voltage, VCI is a driver input voltage (for example, 3.3 V), VDD is a logic voltage inside the chip, VSS is GND, and VGL is a gate OFF voltage.

A plurality of output ends of the gate circuit GC are connected to the corresponding wirings Ha to Hd, a gate clock GCK and a gate start pulse GSP are supplied from the timing controller Tcon to the gate circuit GC, and a gate is supplied from the timing controller Tcon to the slope clock generation circuit SGC. The clock GCK is supplied, and the potential VGL is supplied to the gate circuit GC.

The slope clock generation circuit SGC sets the slope width according to the input data D0 to D5 to the register RE1 (see FIG. 12A), and further generates the slope clock SLCK using the gate clock GCK. The slope clock SLCK is supplied to the slope switch circuit SSC.

The slope destination potential setting circuit SVC has a node N1, and the node N1 is used as a power source of potential VSS, potential AVDD, potential VDD, or potential VCl according to input data D0 to D1 to the register RE2. Connect (see FIG. 12B).
The slope switch circuit SSC has nodes N2 to N4, and this node N2 is connected to one of the nodes N3 and N4 according to the slope clock SLCK. The node N3 is connected to the power supply of the potential VGH, and the node N4 is connected to the node N1 via the slope amount setting circuit SRC. The slope amount setting circuit SRC is a variable resistor, and is set to a resistance value corresponding to the input data D0 to D3 to the register RE3. More specifically, the number of transistors corresponding to the input data is turned on, and resistors equal to the number of turned on transistors are connected in parallel. That is, as the number of ON transistors increases, the resistance decreases and the slope becomes steeper (see FIG. 12C). Then, the potential Vi of the node N2 is supplied to the gate circuit GC.

FIG. 13 is a timing chart showing the operation of the driver 5 of FIG. Each of the gate clock GCK and the slope clock SLCK is composed of the first to fourth periods (the first to third periods are “H” and the fourth period is “L”), and the third period ( H)) and the fourth period (L) of the slope clock SLCK. When the slope clock SLCK is in the first to third periods (H), the node N2 and the node N3 of the slope switch circuit SSC are connected, and the potential Vi = VGH supplied to the gate circuit GC. When the slope clock SLCK is in the fourth period (L), the node N2 and the node N4 of the slope switch circuit SSC are connected, and the potential Vi supplied to the gate circuit GC is changed from VGH to the slope destination potential setting circuit SVC. The voltage gradually decreases to the set potential (any one of VSS, AVDD, VDD, VCl, and potential VGH). The inclination (potential decrease amount per unit time) is set by the slope amount setting circuit SRC, and becomes steep (inclination increases) as the resistance value of the slope amount setting circuit SRC decreases.

Each stage of the gate circuit GC corresponds to one scanning signal line (wiring), and takes in the gate clock GCK in accordance with the inactivation (falling) of the output (or gate start pulse GSP) of the previous stage, With the activation (rise) of the output of the subsequent stage, the capture of the gate clock GCK is terminated, and Vi is output to the corresponding wiring only during the period when the captured gate clock GCK is “H”, and the other (captured GCK VGL is output to the corresponding wiring during a period when “L” is “L” and when GCK is not captured. As a result, scan pulses GPa to GPd as shown in FIG. 13 are output to the wirings Ha to Hd.

In FIG. 13, the scanning pulses GPa to GPd output to the wirings Ha to Hd have the same waveform, but the present invention is not limited to this. For example, as shown in FIGS. 14 and 15, the input data D0 to D5 to the register RE1 of the slope clock generation circuit SGC (see FIG. 11) is periodically exchanged to output to the wirings Ha and Hb (small time constant). The slopes of the scanning pulses GPa and GPb are made the same as the slopes of the slopes of the scanning pulses GPa and GPb and the slopes of the slopes of the scanning pulses GPc and GPd output to the wirings Hc and Hd (large time constant). Can be made larger than the width of the inclined portion of the scan pulses GPc and GPd.

Further, as shown in FIGS. 16 and 17, the input data D0 to D3 to the register RE3 of the slope amount setting circuit SRC (see FIG. 11) are periodically switched to output to the wirings Ha and Hb (small time constant). The slopes of the scan pulses GPa and GPb are made the same with the widths of the slopes of the scan pulses GPa and GPb and the widths of the slopes of the scan pulses GPc and GPd output to the wires Hc and Hd (large time constant) Can be made larger than the inclination of the inclined portion of the scanning pulses GPc and GPd.

Further, as shown in FIGS. 18 and 19, the input data D0 to D5 to the register RE1 of the slope clock generation circuit SGC (see FIG. 11) are periodically switched to output to the wirings Ha and Hb (small time constant). The scan pulse GPa / GPb is provided with an inclined portion, and the scan pulse GPc / GPd output to the wirings Hc / Hd (large time constant) is not provided with an inclined portion (the end is substantially the time axis with respect to the time axis). Vertical).

In the above embodiment, as shown in FIG. 20, the scanning pulse GPa is supplied to the scanning signal line Ga corresponding to the R (red) sub-pixel row via the GL wiring (Ha) on the left of the display unit, and the scanning pulse GPb Is supplied to the scanning signal line Gb corresponding to the G (green) sub-pixel row via the GL wiring (Hb) on the right side of the display unit, and the scanning pulse GPc is transmitted to the B ( The scanning signal line Gc corresponding to the sub-pixel row of blue) is supplied to the scanning signal line Gc, and the scanning pulse GPd is supplied to the scanning signal line Gd corresponding to the sub-pixel row of R (red) via the SL wiring (Hd) on the right of the display unit. The shape of the end of the scanning pulses GPa to GPd can be set as follows, for example.

First, as shown in FIG. 21, the input data to the register RE3 of the slope amount setting circuit SRC (see FIG. 11) is D1, and the subpixel row (k is a natural number 4k−3) connected to the left GL wiring. The predetermined gradation (for example, halftone) is displayed on the second sub-pixel row), and the luminance is measured with the other sub-pixel row being displayed in black, and the result is set as a specified value. Next, the input data to the register RE3 is set to D1, and the predetermined gradation is displayed on the sub-pixel row (4k-2nd sub-pixel row) connected to the GL wiring on the right side of the display section, and another sub-pixel row is displayed. The luminance is measured with black display, and if it is different from the specified value, the input data to the register RE3 is changed to D2, and the measured value is adjusted to the specified value. Further, as shown in FIG. 22, the input data to the register RE3 is set to D1, and the predetermined gradation is displayed on the sub-pixel row (4k-1th sub-pixel row) connected to the SL wiring on the left side of the display unit. At the same time, the luminance is measured with the other sub-pixel row displayed in black, and if it is different from the specified value, the input data to the register RE3 is changed to D3, and the measured value is adjusted to the specified value. Finally, the input data to the register RE3 is set to D1, and the predetermined gradation is displayed on the sub-pixel row (4kth sub-pixel row) connected to the SL wiring on the right side of the display portion, and the other sub-pixel rows are black. The brightness is measured as a display, and if it is different from the specified value, the input data to the register RE3 is changed to D4, and the measured value is adjusted to the specified value.

Thus, when the time constant of the GL wiring on the left side of the display portion <the time constant of the GL wiring on the right side of the display portion <the time constant of the SL wiring on the left side of the display portion <the time constant of the SL wiring on the right side of the display portion The terminal shapes of GPa to GPd can be set as shown in FIG. 23, for example.

In FIGS. 21 and 22, measurement and register settings are performed for the (4k-3) th, (4k-2) th, (4k-1), and 4kth subpixel rows, but the present invention is not limited to this. When the left and right wiring widths are equal or when it is necessary to shorten the process, for example, measurement and register setting are performed only for the (4k-3) th and (4k-1) th subpixel rows, and (4k-2) The register setting of the first subpixel row is the same as the (4k-3) th subpixel row, and the register setting of the (4k-1) th subpixel row is the same as the (4k-1) th subpixel row. You can also.

24 to 27 are schematic diagrams illustrating examples of the polarity of the signal potential written to each sub-pixel. FIG. 24 shows a three-gate line inversion method, in which the signal potential supplied to each data signal line is inverted every 3H (horizontal scanning period) and applied to one of the two data signal lines adjacent to the same horizontal scanning period. The polarity of the signal potential supplied is the same as the polarity of the signal potential supplied to the other. FIG. 25 shows a vertical one-dot horizontal one-dot inversion method, in which the signal potential supplied to each data signal line is inverted every 1H (horizontal scanning period), and two data signal lines adjacent to the same horizontal scanning period. The polarity of the signal potential supplied to one of the two is opposite to the polarity of the signal potential supplied to the other. FIG. 26 shows a vertical 2 dot horizontal 1 dot inversion method, in which the signal potential supplied to each data signal line is inverted every 2H (horizontal scanning period), and two data signal lines adjacent to the same horizontal scanning period. The polarity of the signal potential supplied to one of the two is opposite to the polarity of the signal potential supplied to the other. FIG. 27 shows a source line inversion method in which the signal potential supplied to each data signal line is inverted every 1V (vertical scanning period) and supplied to one of two data signal lines adjacent to the same horizontal scanning period. The polarity of the signal potential applied is opposite to the polarity of the signal potential supplied to the other.
[Example 2]
In the configuration in which three sub-pixels constituting one pixel are arranged in the column direction (scanning direction), the number of scanning signal lines to be scanned increases (three times that in the configuration in which three sub-pixels are arranged in the row direction). Insufficient charge of the pixel electrode is likely to occur (especially when it is assumed to be used at a low temperature such as an in-vehicle liquid crystal display device). In order to solve this problem, precharge is effective.

Therefore, when the polarity of the signal potential written to each sub-pixel is, for example, FIG. 25, the driver 5 can be configured as shown in FIG. 28 and operated as shown in FIG. In the configuration of FIG. 28, the gate circuit GC of FIG. 11 is provided with a shift register using a D flip-flop and an AND circuit corresponding to each stage of the shift register. The gate clock GCK from the timing controller Tcon is input to the CK terminal of each D flip-flop, and the D terminal of each D flip-flop is connected to the Q (output) terminal in the previous stage, and the Q (output terminal) is in the subsequent stage. Connected to the D terminal. The AND of the output of each D flip-flop and the gate clock GCK is input to the output circuit OC, and the potential Vi and the potential VGL of the node N2 are supplied to the output circuit OC. For example, the Q terminal of the D flip-flop Fa corresponding to the wiring Ha is connected to the D terminal of the D flip-flop Fb corresponding to the wiring Hb, and the Q terminal of the D flip-flop Fb corresponds to the D flip-flop Fc corresponding to the wiring Hc. The output of the D flip-flop Fa and the gate clock GCK are input to the AND circuit Aa, and the output of the D flip-flop Fb and the gate clock GCK are input to the AND circuit Ab. The output APa of the circuit Aa and the output APb of the AND circuit Ab are input to the output circuit OC. The gate start pulse GSP is input to the D terminal of the first stage D flip-flop.

In FIG. 29, each of the gate clock GCK and the slope clock SLCK is composed of the first to fourth periods (the first to third periods are “H” and the fourth period is “L”). The third period (H)) and the fourth period (L) of the slope clock SLCK overlap. In addition, the gate start pulse GSP becomes active twice, the first time is synchronized with a certain cycle of the gate clock GCK (becomes active in the first to fourth periods), and the second is the next of this GCK cycle. Synchronized with the next cycle.

When the slope clock SLCK is in the first to third periods (H), the node N2 and the node N3 of the slope switch circuit SSC are connected, and the potential Vi = VGH supplied to the output circuit OC. When the slope clock SLCK is in the fourth period (L), the node N2 and the node N4 of the slope switch circuit SSC are connected, and the potential Vi supplied to the output circuit OC is set from VGH by the slope destination potential setting circuit SVC. Gradually decrease to the applied potential (VSS, AVDD, VDD, and VCl). The inclination (potential decrease amount per unit time) is set by the slope amount setting circuit SRC, and becomes steep (inclination increases) as the resistance value of the slope amount setting circuit SRC decreases.

Each D flip-flop transfers the input of the D terminal to the Q terminal when the gate clock signal GCK rises from “L” to “H”. That is, the output Q of the own stage is activated (rises) at the same time as the output Q of the previous stage is deactivated (falls), and is inactive at the same time as the output Q of the next stage is activated (rises). (Fall down). Then, the output of the AND circuit to which the output Q and GCK of its own stage are input is input to the output circuit OC, and the output circuit OC applies Vi to the corresponding wiring only during the period when the output of the AND circuit is “H”. VGL is output to the corresponding wiring in other cases (period in which the output of the AND circuit of the own stage is “L”). Accordingly, as shown in FIG. 29, scanning pulses GPa to GPd that are activated twice at intervals are output to the wirings Ha to Hd, and the scanning signal lines Ga to Gd are signals corresponding to two lines before. It is precharged by the potential (the same polarity as the signal potential of the main charge). Thereby, the problem of insufficient charging of the pixel electrode can be solved.

If the polarity of the signal potential written to each sub-pixel is, for example, FIG. 27, the driver 5 can be configured as shown in FIG. 30 and operated as shown in FIG. In the configuration of FIG. 30, the gate circuit GC of FIG. 11 is provided with a two-stage shift register using D flip-flops, and an AND circuit corresponding to each stage of the shift register, and the gate circuit GC is supplied from the timing controller Tcon. The gate clocks GCK1 and GCK2 and the gate start pulses GSP1 and GSP2 are supplied to the slope clock generation circuit SGC. In the gate circuit GC, the tag gate clock GCK1 is input to the CK terminal of the odd-numbered D flip-flop, the tag gate clock GCK2 is input to the CK terminal of the even-numbered D flip-flop, The D terminal is connected to the Q (output) terminal of the previous odd-numbered stage, the Q (output terminal) is connected to the D terminal of the next odd-numbered stage, and the even-numbered D flip-flop is The D terminal is connected to the Q (output) terminal of the previous even numbered stage, and the Q (output terminal) is connected to the D terminal of the next even numbered stage. The AND of the odd-stage D flip-flop and the gate clock GCK1 is input to the output circuit OC, and the AND of the even-stage D flip-flop and the gate clock GCK2 is input to the output circuit OC. The potential Vi and the potential VGL of the node N2 are supplied to the OC. For example, the Q terminal of the D flip-flop Fa corresponding to the wiring Ha is connected to the D terminal of the D flip-flop Fc corresponding to the wiring Hc, and the Q terminal of the D flip-flop Fb is connected to the D flip-flop Fd corresponding to the wiring Hd. The output of the D flip-flop Fa and the gate clock GCK1 are input to the AND circuit Aa, and the output of the D flip-flop Fb and the gate clock GCK2 are input to the AND circuit Ab. The output APa of the circuit Aa and the output APb of the AND circuit Ab are input to the output circuit OC. The gate start pulse GSP1 is input to the D terminal of the first stage D flip-flop F0, and the gate start pulse GSP2 is input to the D terminal of the second stage D flip-flop F0 '.

In FIG. 31, each of the gate clocks GCK1 and GCK2 consists of the first to sixth periods (the first to fifth periods are “H” and the sixth period is “L”), and the sixth period ( L) and the third period (H) of GCK2 overlap. The slope clock SLCK consists of the first to third periods (the first and second periods are “H” and the third period is “L”). The sixth period (L) of GCK1 and the slope clock SLCK The first period (H) overlaps. The gate start pulse GSP is activated once in synchronization with a certain cycle of GCK1.

When the slope clock SLCK is in the first to second periods (H), the node N2 and the node N3 of the slope switch circuit SSC are connected, and the potential Vi = VGH supplied to the output circuit OC. When the slope clock SLCK is in the third period (L), the node N2 and the node N4 of the slope switch circuit SSC are connected, and the potential Vi supplied to the output circuit OC is set from VGH by the slope destination potential setting circuit SVC. The voltage is gradually decreased to the set potential (any one of VSS, AVDD, VDD, VCl, and potential VGH). The inclination (potential decrease amount per unit time) is set by the slope amount setting circuit SRC, and becomes steep (inclination increases) as the resistance value of the slope amount setting circuit SRC decreases.

When the gate clock signal GCK1 rises from “L” to “H”, the odd-numbered D flip-flop shifts the input of the D terminal to the Q terminal, and the even-numbered D flip-flop has the gate clock signal GCK2 of “L”. When rising from "" to "H", the input of the D terminal is transferred to the Q terminal. That is, the output Q of the own stage is activated (rises) before the output Q of the previous stage is deactivated (falls), and deactivates after the output Q of the next stage is activated (rises). (Fall down). Then, the output of the AND circuit to which the output Q of its own stage and GCK1 or GCK2 are input is input to the output circuit OC. The output circuit OC corresponds to Vi only during the period when the output of the AND circuit is “H”. VGL is output to the corresponding wiring in other cases (period in which the output of the AND circuit of the own stage is “L”). As a result, the scan pulses GPa to GPd, in which the scan pulse of the own stage overlaps the scan pulse of the previous stage, are output to the wirings Ha to Hd, respectively, and the scan signal lines Ga to Gd correspond to the previous line. Is precharged by the signal potential (the same polarity as the signal potential of the main charge). Thereby, the problem of insufficient charging of the pixel electrode can be solved.

In FIG. 31, the scanning pulses GPa to GPd output to the wirings Ha to Hd have the same waveform, but the present invention is not limited to this. For example, as shown in FIGS. 32 and 15, the input data D0 to D5 to the register RE1 of the slope clock generation circuit SGC (see FIG. 11) are periodically switched to output to the wirings Ha and Hb (small time constant). The slopes of the scanning pulses GPa and GPb are made the same as the slopes of the slopes of the scanning pulses GPa and GPb and the slopes of the slopes of the scanning pulses GPc and GPd output to the wirings Hc and Hd (large time constant). Can be made larger than the width of the inclined portion of the scan pulses GPc and GPd.

Further, as shown in FIGS. 33 and 17, the input data D0 to D3 to the register RE3 of the slope amount setting circuit SRC (see FIG. 11) are periodically switched, and output to the wirings Ha and Hb (small time constant). The slopes of the scan pulses GPa and GPb are made the same with the widths of the slopes of the scan pulses GPa and GPb and the widths of the slopes of the scan pulses GPc and GPd output to the wires Hc and Hd (large time constant). Can be made larger than the inclination of the inclined portion of the scanning pulses GPc and GPd.

Example 3
In the above embodiment, the three sub-pixels constituting one pixel are arranged in the column direction (scanning direction), but the present invention is not limited to this. As shown in FIG. 34, these three sub-pixels are arranged in the column direction (perpendicular to the scanning direction). As shown in FIG. 35, the scan pulse GPa is supplied to the scan signal line Ga corresponding to the first sub-pixel row via the SL wiring (Ha) on the left side of the display unit, and the scan pulse GPb is displayed on the display unit. The scanning signal GPc is supplied to the scanning signal line Gb corresponding to the second sub-pixel row via the right SL wiring (Hb), and the scanning pulse GPc corresponds to the third sub-pixel row via the GL wiring (Hc) on the left of the display unit. The scanning signal GPc may be supplied to the scanning signal line Gc, and the scanning pulse GPd may be supplied to the scanning signal line Gd corresponding to the fourth sub-pixel row via the GL wiring (Hd) on the right side of the display unit.

In this case, the end shape of the scanning pulses GPa to GPd can be set as follows, for example. First, as shown in FIG. 36, the input data to the register RE3 of the slope amount setting circuit SRC (see FIG. 11) is D1, and the sub-pixel row (k is a natural number 4k−3) connected to the left GL wiring. The predetermined gradation (for example, halftone) is displayed on the second sub-pixel row), and the luminance is measured with the other sub-pixel row being displayed in black, and the result is set as a specified value. Next, the input data to the register RE3 is set to D1, and the predetermined gradation is displayed on the sub-pixel row (4k-2nd sub-pixel row) connected to the GL wiring on the right side of the display section, and another sub-pixel row is displayed. The luminance is measured with black display, and if it is different from the specified value, the input data to the register RE3 is changed to D2, and the measured value is adjusted to the specified value. Further, as shown in FIG. 37, the input data to the register RE3 is set to D1, and the predetermined gradation is displayed on the sub-pixel row (4k-1th sub-pixel row) connected to the SL wiring on the left side of the display unit. At the same time, the luminance is measured with the other sub-pixel row displayed in black, and if it is different from the specified value, the input data to the register RE3 is changed to D3, and the measured value is adjusted to the specified value. Finally, the input data to the register RE3 is set to D1, and the predetermined gradation is displayed on the sub-pixel row (4kth sub-pixel row) connected to the SL wiring on the right side of the display portion, and the other sub-pixel rows are black. The brightness is measured as a display, and if it is different from the specified value, the input data to the register RE3 is changed to D4, and the measured value is adjusted to the specified value. By so doing, it is possible to generate an optimum scanning pulse for each sub-pixel row, and it is possible to further suppress horizontal stripe-like display unevenness. In FIGS. 36 and 37, measurement and register setting are performed for the (4k-3) th, (4k-2) th, (4k-1), and 4kth subpixel rows, but the present invention is not limited to this. When the left and right wiring widths are equal or when it is necessary to shorten the process, for example, measurement and register setting are performed only for the (4k-3) th and (4k-1) th subpixel rows, and (4k-2) The register setting of the first subpixel row is the same as the (4k-3) th subpixel row, and the register setting of the (4k-1) th subpixel row is the same as the (4k-1) th subpixel row. You can also.

38 to 41 are schematic diagrams showing examples of the polarity of the signal potential written to each sub-pixel in the configuration of FIGS. FIG. 38 shows a one-gate line inversion method in which the signal potential supplied to each data signal line is inverted every 3H (horizontal scanning period) and is applied to one of two data signal lines adjacent to the same horizontal scanning period. The polarity of the signal potential supplied is the same as the polarity of the signal potential supplied to the other. FIG. 39 shows a vertical 1-dot horizontal 1-dot inversion method, in which the signal potential supplied to each data signal line is inverted every 1H (horizontal scanning period), and two data signal lines adjacent to the same horizontal scanning period. The polarity of the signal potential supplied to one of the two is opposite to the polarity of the signal potential supplied to the other. FIG. 40 shows a vertical 2 dot horizontal 1 dot inversion method, in which the signal potential supplied to each data signal line is inverted every 2H (horizontal scanning period), and two data signal lines adjacent to the same horizontal scanning period are displayed. The polarity of the signal potential supplied to one of the two is opposite to the polarity of the signal potential supplied to the other. FIG. 41 shows a source line inversion method in which the signal potential supplied to each data signal line is inverted every 1V (vertical scanning period) and supplied to one of two data signal lines adjacent to the same horizontal scanning period. The polarity of the signal potential applied is opposite to the polarity of the signal potential supplied to the other.

When precharging is performed with the configuration of FIGS. 38 and 39, it is desirable to operate the driver of FIG. 28 as shown in FIG. When precharging is performed with the configuration of FIG. 41, it is desirable to operate the driver of FIG. 30 as shown in FIGS.
In the present liquid crystal panel, as shown in FIG. 42, the primary colors of the sub-pixels are four colors of red (R), green (G), blue (B), and Y (yellow). Is connected to the wiring passing through the outside of the first short side E1, and the scanning signal line corresponding to the yellow subpixel is formed in the gate layer GL. The scanning signal line corresponding to the red sub-pixel is connected to the wiring passing through the outside of the short side E2, and connected to the wiring passing through the outside of the first short side E1 to the blue sub-pixel. The corresponding scanning signal line may be formed in the source layer SL and connected to the wiring passing through the outside of the second short side E2. In this way, in the entire display unit, sub-pixels of the same color (particularly G or Y) are connected to wiring on the same layer and the same side (with respect to the display unit) via the scanning signal lines. It is easy to set the waveform of the scan pulse output to the wiring.

In the present liquid crystal display device, the second scanning pulse output from the scanning signal line driving circuit to the second wiring may include a second inclined portion at the end from the active level to the inactive level. .

In the present liquid crystal display device, the first inclined portion and the second inclined portion may have the same shape.

In the present liquid crystal display device, the inclination of the first inclined portion and the inclination of the second inclined portion may be the same, and the width of the first inclined portion may be larger than the width of the second inclined portion.

In the present liquid crystal display device, the width of the first inclined portion and the width of the second inclined portion may be the same, and the inclination of the first inclined portion may be steeper than the inclination of the second inclined portion.

In the present liquid crystal display device, the second scanning pulse output from the scanning signal line driving circuit to the second wiring has a configuration in which the end from the active level to the inactive level is substantially perpendicular to the time axis. It can also be.

The liquid crystal display device includes a first pixel electrode, a first data signal line, and a first transistor, and the first scanning signal line, the first data signal line, and the first pixel electrode are connected to the first transistor. It can also be set as the structure which is.

In the present liquid crystal display device, one pixel is composed of a plurality of sub-pixels arranged in the column direction with the extending direction of the first scanning signal line as the row direction, and one of the plurality of sub-pixels includes the first pixel electrode. May be included.

In the present liquid crystal display device, each sub-pixel controlled by the first scanning signal line may be configured to have the same color.

In the present liquid crystal display device, one of the first and second wirings may be formed in the same layer as the first data signal line, and the other may be formed in the same layer as the first and second scanning signal lines. it can.

The present liquid crystal display device may be configured such that n is a natural number and the first scanning signal line is supplied with a precharge pulse before n horizontal scanning periods during which the first scanning pulse is supplied.

In the present liquid crystal display device, the polarity of the signal potential output from the first data signal line may be inverted every n horizontal scanning periods.

The liquid crystal display device includes third and fourth scanning signal lines formed in the display unit and third and fourth wirings formed in the non-display unit, and the display unit includes the first and second short lines. The third wiring is formed in the same layer as the first wiring, the fourth wiring is formed in the same layer as the second wiring, and the scanning signal line is surrounded by four sides of the side and the first and second long sides. The drive circuit is connected to the third scanning signal line through the third wiring, and is connected to the fourth scanning signal line through the fourth wiring. The first and second wirings are outside the first short side. The third and fourth wirings can also be configured to pass through the outside of the second short side.

In the present liquid crystal display device, the first scanning signal line, the third scanning signal line, the second scanning signal line, and the fourth scanning signal line may be arranged in the column direction in this order.

In the present liquid crystal display device, the second to fourth scanning pulses are output from the scanning signal line driving circuit to the second to fourth wirings, respectively, and the time constant of the third wiring is smaller than the time constant of the fourth wiring. The third scan pulse may include a third inclined portion at the end from the active level to the inactive level.

The present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on common general technical knowledge and those obtained by combining them are also included in the embodiments of the present invention.

The present invention is suitable for a liquid crystal display device that performs three-dimensional wiring in a non-display portion.

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 5 Driver Ga-Gd Scan signal line Ha-Hd Wiring D Data signal line P Pixel GPa-GPd Scan pulse Inclination part Ks

Claims

First and second scanning signal lines formed in the display portion, first and second wirings formed in the non-display portion, and a scanning signal line drive circuit,
The first and second wirings are formed in different layers;
The scanning signal line driving circuit is connected to the first scanning signal line via the first wiring, and is connected to the second scanning signal line via the second wiring,
The time constant of the first wiring is smaller than the time constant of the second wiring,
The liquid crystal display device, wherein the first scanning pulse output from the scanning signal line driving circuit to the first wiring includes a first inclined portion at the end from the active level to the inactive level.
2. The liquid crystal display device according to claim 1, wherein the second scanning pulse output from the scanning signal line driving circuit to the second wiring includes a second inclined portion at a terminal end from the active level to the inactive level.
3. The liquid crystal display device according to claim 2, wherein the first inclined portion and the second inclined portion have the same shape.
3. The liquid crystal display device according to claim 2, wherein the inclination of the first inclined portion is the same as that of the second inclined portion, and the width of the first inclined portion is larger than the width of the second inclined portion.
3. The liquid crystal display device according to claim 2, wherein the width of the first inclined portion is the same as the width of the second inclined portion, and the inclination of the first inclined portion is steeper than the inclination of the second inclined portion.
2. The liquid crystal display according to claim 1, wherein the second scanning pulse output from the scanning signal line driving circuit to the second wiring has a terminal end from the active level to the inactive level substantially perpendicular to the time axis. apparatus.
A first pixel electrode, a first data signal line, and a first transistor;
2. The liquid crystal display device according to claim 1, wherein the first scanning signal line, the first data signal line, and the first pixel electrode are connected to a first transistor.
The extending direction of the first scanning signal line is a row direction, and one pixel is composed of a plurality of sub-pixels arranged in the column direction,
The liquid crystal display device according to claim 7, wherein the first pixel electrode is included in one of the plurality of sub-pixels.
The liquid crystal display device according to claim 8, wherein the sub-pixels controlled by the first scanning signal line have the same color.
8. The liquid crystal display device according to claim 7, wherein one of the first and second wirings is formed in the same layer as the first data signal line, and the other is formed in the same layer as the first and second scanning signal lines.
Let n be a natural number
8. The liquid crystal display device according to claim 7, wherein a precharge pulse is supplied to the first scanning signal line before n horizontal scanning periods during which the first scanning pulse is supplied.
12. The liquid crystal display device according to claim 11, wherein the polarity of the signal potential output from the first data signal line is inverted every n horizontal scanning periods.
Third and fourth scanning signal lines formed in the display unit, and third and fourth wirings formed in the non-display unit,
The display unit is surrounded by four sides of the first and second short sides and the first and second long sides,
The third wiring is formed in the same layer as the first wiring, the fourth wiring is formed in the same layer as the second wiring,
The scanning signal line driving circuit is connected to the third scanning signal line through the third wiring, and is connected to the fourth scanning signal line through the fourth wiring.
2. The liquid crystal display device according to claim 1, wherein the first and second wirings pass through the outside of the first short side, and the third and fourth wirings pass through the outside of the second short side.
14. The liquid crystal display device according to claim 13, wherein the first scanning signal line, the third scanning signal line, the second scanning signal line, and the fourth scanning signal line are arranged in the column direction in this order.
Second to fourth scanning pulses are output from the scanning signal line driving circuit to the second to fourth wirings,
The time constant of the third wiring is smaller than the time constant of the fourth wiring,
14. The liquid crystal display device according to claim 13, wherein the third scanning pulse includes a third inclined portion at a terminal end from the active level to the inactive level.