WO2012139559A1 - Verfahren zum speichern einer sicherheitsrelevanten dateneinheit - Google Patents
Verfahren zum speichern einer sicherheitsrelevanten dateneinheit Download PDFInfo
- Publication number
- WO2012139559A1 WO2012139559A1 PCT/DE2012/100082 DE2012100082W WO2012139559A1 WO 2012139559 A1 WO2012139559 A1 WO 2012139559A1 DE 2012100082 W DE2012100082 W DE 2012100082W WO 2012139559 A1 WO2012139559 A1 WO 2012139559A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- memory area
- data unit
- var
- const
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operations
- G06F11/1479—Generic software techniques for error detection or fault masking
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operations
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
- G06F11/141—Saving, restoring, recovering or retrying at machine instruction level for bus or memory accesses
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Definitions
- the invention relates to a method for storing a security-relevant data unit according to the preamble of claim 1 and to a corresponding memory unit.
- a memory unit in particular for security-relevant data, is designed such that the stored data content is maintained during the operation of the memory unit, ie it is neither lost randomly nor overwritten by uncontrolled write accesses.
- a failure of individual cells of the memory unit can never be completely ruled out and take also microcontroller, for example, due to external disturbances, such as temperature influences, electromagnetic interference or overvoltages, uncontrolled operating conditions, which can lead to unintentional write accesses.
- memory protection units ie memory monitoring units
- memory monitoring units can be done in terms of hardware such monitoring, but this is correspondingly expensive and expensive.
- a method for storing data units, in particular security-relevant data units should be designed so that such errors are at least recognized and avoided as far as possible.
- DE 10 2006 055 964 A1 describes a method and a device for data backup in which the identical data are stored in two different memory systems and hash values are formed and compared.
- the object of the present invention is therefore to provide a suitable method and a corresponding memory unit.
- An essential idea of the invention is that a memory area with a memory content which is not variable at least in normal memory operation is provided in the memory area for the security-relevant data before and / or after the memory area of the data unit.
- a data unit always forms a contiguous set of at least 1 bit, preferably also 1 byte or several bytes of the security-relevant data to be stored, whereby the length of the data unit and the number of data units are irrelevant for the invention.
- the memory area with a memory content which is not variable in normal memory operation is described with a predetermined constant value, this memory area preferably consisting of at least 2 bits with diverging bit values.
- this memory content is immutable, for example by a write access to this memory area is excluded by appropriate addressing in an address register of the microcontroller. If it is a volatile memory (RAM) is in a separate memory operation normal configuration operation, for example, when commissioning the microcontroller exceptionally this memory area with the predetermined constant value described, but is ensured by the program flow that this configuration process of the normal Storage operation is carried out separately.
- RAM volatile memory
- Fig.2-4 various embodiments of the method according to the invention
- FIG. 1 shows a memory unit 1 with a memory area 1 .2 bordered by a dashed line, in which the security-critical data units are stored.
- the memory unit can also have non-protected memory areas 1 .1 or unused memory areas 1 .3, i. the method can only be applied to those memory areas in which particularly safety-critical data units are stored.
- FIGS. 2A to 2C now show the different variants of the embodiments.
- a memory area (const) having a memory content which is not variable in normal memory operation hereinafter referred to as constant memory content.
- FIG. 2B after the data unit to be protected (var n ), a memory area (const) having a constant memory content is described.
- FIG. 3 now shows a particularly preferred development in which a data unit is stored in a first memory area (var n ) and additionally at least in a second memory area (copy var n ) and at least one intermediate area with at least one of the first and second memory areas normal memory operation is not variable memory content (const) is provided.
- var n first memory area
- copy var n second memory area
- at least one intermediate area with at least one of the first and second memory areas normal memory operation is not variable memory content (const) is provided.
- the first memory area this therefore corresponds to the variant according to FIG. 2B, for the second memory area with the copy (copy var n ) of the data unit of the variant according to FIG. 2A.
- Such a designed memory area can, of course, be surrounded on the outside again by memory areas with a constant memory content, although this would considerably increase the required memory requirement.
- the storage of the binary inverse value of this data unit is also included here as a copy of the data unit in the first storage area and is to be understood as a possible embodiment of this method, since a comparison of the two storage areas and a recognition of a deviation is also directly possible in this case.
- FIG. 2C Another particular embodiment is outlined in FIG.
- the memory area (const A) in front of the data unit (var n ) and the memory area (const B) after the memory area with data unit (var n ) are each described with a non-variable storage capacity at least in normal memory operation, the two immutable memory contents (const A + const B) differ from each other.
- This thus represents a modification of the embodiment according to FIG. 2C, but can certainly also be combined with the embodiment according to FIG.
- both the memory area of the data unit (var n ) and the surrounding memory area with non-variable memory content (const) are checked for changes and the data unit (var n ) is accepted as unchanged only if the surrounding memory area is unchanged with non-variable memory contents.
- checksums are formed and, in addition to the data unit (var n ), at least one surrounding memory area is also included in the checksum.
- the switch state (which is a 100 ohm or 400 ohm resistor, which is to be measured depending on the switch position) is measured via the AD converter of the microcontroller and on the other hand via a measuring unit in the ASIC.
- Both measurement and Ausnceroutinen are implemented in the microcontroller, wherein in the routine, in which the switch resistance is measured with the A / D converter of the microcontroller, the mechanisms described are implemented.
- the switch resistance value is here kept in two identical variables, both of which are described after measurement with the same value.
- the double held reading is used to enable or disable an external logic signal on the ZündASIC.
- the identity of the double-held measured value is checked, but also the integrity of the constants surrounding it. If a discrepancy is detected before switching the logic signal whose state is not changed and if a discrepancy at check after the switching of the logic signal turns out, then the switching is withdrawn and brought to the previous state.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
Abstract
Description
Claims
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE112012001265T DE112012001265A5 (de) | 2011-04-13 | 2012-03-30 | Verfahren zum Speichern einer sicherheitsrelevanten Dateneinheit |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE201110016974 DE102011016974A1 (de) | 2011-04-13 | 2011-04-13 | Verfahren zum Speichern einer sicherheitsrelevanten Dateneinheit |
| DE102011016974.1 | 2011-04-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2012139559A1 true WO2012139559A1 (de) | 2012-10-18 |
Family
ID=46025288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/DE2012/100082 Ceased WO2012139559A1 (de) | 2011-04-13 | 2012-03-30 | Verfahren zum speichern einer sicherheitsrelevanten dateneinheit |
Country Status (2)
| Country | Link |
|---|---|
| DE (2) | DE102011016974A1 (de) |
| WO (1) | WO2012139559A1 (de) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040158775A1 (en) * | 2003-01-28 | 2004-08-12 | Renesas Technology Corp. | Nonvolatile memory |
| EP1505504A2 (de) * | 2003-08-04 | 2005-02-09 | Hitachi, Ltd. | Fernkopiersystem |
| DE102006055964A1 (de) | 2006-11-24 | 2008-05-29 | Bdt-Solutions Gmbh | Verfahren und Vorrichtung zur Datensicherung |
| US20080276065A1 (en) * | 2007-05-03 | 2008-11-06 | Samsung Electronics Co., Ltd. | Method of partitioning storage area of recording medium and recording medium using the method, and method of accessing recording medium and recording device using the method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7143314B2 (en) * | 2003-10-01 | 2006-11-28 | General Motors Corporation | Method and apparatus for ensuring integrity of critical RAM variables |
| DE102006010820A1 (de) * | 2006-03-07 | 2007-09-13 | Micronas Gmbh | Fehlerkorrektur- und Fehlererfassungs-Verfahren zum Auslesen von gespeicherten Informationsdaten und Speichersteuereinrichtung dafür |
| DE102007043083A1 (de) * | 2007-09-10 | 2009-03-12 | Continental Automotive Gmbh | Verfahren und Vorrichtung zum Codieren von Datenworten |
| US8645792B2 (en) * | 2008-12-16 | 2014-02-04 | Micron Technology, Inc. | Memory with guard value dependent error correction |
-
2011
- 2011-04-13 DE DE201110016974 patent/DE102011016974A1/de not_active Withdrawn
-
2012
- 2012-03-30 WO PCT/DE2012/100082 patent/WO2012139559A1/de not_active Ceased
- 2012-03-30 DE DE112012001265T patent/DE112012001265A5/de not_active Ceased
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040158775A1 (en) * | 2003-01-28 | 2004-08-12 | Renesas Technology Corp. | Nonvolatile memory |
| EP1505504A2 (de) * | 2003-08-04 | 2005-02-09 | Hitachi, Ltd. | Fernkopiersystem |
| DE102006055964A1 (de) | 2006-11-24 | 2008-05-29 | Bdt-Solutions Gmbh | Verfahren und Vorrichtung zur Datensicherung |
| US20080276065A1 (en) * | 2007-05-03 | 2008-11-06 | Samsung Electronics Co., Ltd. | Method of partitioning storage area of recording medium and recording medium using the method, and method of accessing recording medium and recording device using the method |
Also Published As
| Publication number | Publication date |
|---|---|
| DE112012001265A5 (de) | 2013-12-19 |
| DE102011016974A1 (de) | 2012-11-15 |
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