WO2012125162A1 - Memory cell having closed curve structure - Google Patents
Memory cell having closed curve structure Download PDFInfo
- Publication number
- WO2012125162A1 WO2012125162A1 PCT/US2011/028537 US2011028537W WO2012125162A1 WO 2012125162 A1 WO2012125162 A1 WO 2012125162A1 US 2011028537 W US2011028537 W US 2011028537W WO 2012125162 A1 WO2012125162 A1 WO 2012125162A1
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- WIPO (PCT)
- Prior art keywords
- channel
- floating gate
- eprom
- rectangular
- cell
- Prior art date
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- 238000007667 floating Methods 0.000 claims abstract description 162
- 238000000034 method Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000000969 carrier Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 description 21
- 238000010586 diagram Methods 0.000 description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 239000000758 substrate Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 239000002784 hot electron Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 201000009310 astigmatism Diseases 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 101100004188 Arabidopsis thaliana BARD1 gene Proteins 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/015—Ink jet characterised by the jet generation process
- B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
- B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
- B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
- B41J2/04541—Specific driving circuit
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/015—Ink jet characterised by the jet generation process
- B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
- B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
- B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
- B41J2/04586—Control methods or devices therefor, e.g. driver circuits, control circuits controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Definitions
- PROM Programmable read-only memory
- a PROM chip includes a grid of metal conductors forming rows and columns. Each row/column intersection includes a conductive fuse that provides one bit of memory.
- a relatively high current is selectively routed to the fuse to cause the fuse to burn out. Intersections where fuses remain are one logic value and intersections where fuses are burned out are the other logic value.
- NMOS N-channel metal-oxide semiconductor
- fuses are programmed in substantially the same way, where fuses are selectively burned out to program a bit.
- programming chips in this way has some drawbacks. If a chip is improperly programmed, there is no way to fix it and the chip must be discarded. Also, fuses are relatively large and can be unreliable. In addition, fuses can damage the orifice layer of the inkjet during programming and after a fuse burns out metal debris from the fuse can be drawn into the ink and cause blockage in the inkjet pen, resulting in poor quality printing.
- EPROM EPROM devices
- EPROM devices include a conductive grid of rows and columns, but they do not include fuses. Instead, a memory cell is located at each row/column intersection.
- Each memory cell includes a transistor structure and two gates that are separated from each other by a thin dielectric layer.
- One of the gates is a floating gate and the other is a control gate or input gate.
- the floating gate In an unprogrammed memory cell, the floating gate has no charge, which causes the threshold voltage to be low.
- the floating gate In a programmed memory cell, the floating gate is charged with electrons and the threshold voltage is higher.
- a programming voltage e.g. 10 to 16 volts
- This programming voltage draws excited electrons to the floating gate, thereby increasing the threshold voltage.
- a memory cell having a lower threshold voltage is one logic value and a memory cell having a higher threshold voltage is the other logic value.
- Figure 1 is a diagram illustrating one example of an EPRO cell that stores one bit of information.
- Figure 2 is a diagram illustrating one example of an EPROM array.
- Figure 3 is a diagram illustrating one example of the layers in an EPROM chip.
- Figure 4 is a diagram illustrating one example of an EPROM cell that uses the layers of the EPROM chip of Figure 3.
- Figure 5 is a top-view diagram illustrating one example of an EPROM cell that includes a circular floating gate and a circular channel.
- Figure 6 is a top-view diagram illustrating one example of an EPROM cell that includes a floating gate having multiple straight sides and rounded corners, and a channel having multiple straight sides and rounded corners.
- Figure 7 is a top-view diagram illustrating one example of an EPROM cell that includes a floating gate having multiple straight sides, a rounded top, and a rounded bottom, and a channel having multiple straight sides, a rounded top, and a rounded bottom.
- Figure 8 is a top-view diagram illustrating one example of an EPROM cell that includes a rectangular floating gate and a rectangular channel.
- Figure 9 is a graph illustrating EPROM resistance ratios of EPROM cells having circular floating gates and channels, and EPROM cells having
- Figure 10 is a graph illustrating unprogrammed resistance ratios for circular and rectangular EPROM cells.
- Figure 11 is a graph illustrating programmed resistance ratios for circular and rectangular EPROM cells.
- Figure 12 is a graph illustrating unprogrammed resistance ratios for circular and rectangular EPROM cells fabricated in another suitable process.
- Figure 13 is a graph illustrating programmed resistance ratios for circular and rectangular EPROM cells fabricated in the other suitable process.
- Figure 1 is a diagram illustrating one example of an EPROM cell 20 that stores one bit of information.
- EPROM cell 20 does not include a fuse and provides a number of advantages over an NMOS fused bit.
- EPROM cells such as EPROM cell 20, can be used to eliminate fuses in systems, such as ink jet printhead systems.
- EPROM cell 20 includes a semiconductor substrate 22 having a source 24, a drain 26, and a channel 28, where channel 28 is situated between source 24 and drain 26.
- a floating gate 30 is situated over channel 28 and an input gate 32, also referred to as control gate 32, is situated over floating gate 30.
- Source 24 includes an N+ doped region and drain 26 includes an N+ doped region.
- Channel 28 is a p doped region situated between the N+ doped regions of source 24 and drain 26.
- Control gate 32 is capacitively coupled to floating gate 30 via a dielectric material 34 that is situated between control gate 32 and floating gate 30. A voltage at control gate 32 is coupled to floating gate 30. Another layer of dielectric material 36 is disposed between floating gate 30 and substrate 22 over channel 28.
- This high voltage bias on drain 26 generates energetic "hot” carriers or electrons.
- a positive voltage bias between control gate 32 and drain 26 pulls some of these hot electrons onto floating gate 30.
- the threshold voltage of EPROM cell 20 i.e., the voltage required to cause channel 28 to conduct current, increases. If enough electrons are pulled onto floating gate 30, the threshold voltage increases to a level above a specified threshold voltage and EPROM cell 20 blocks current at the specified threshold voltage level, which changes the logic state of EPROM cell 20 from one logic value to the other logic value.
- EPROM cell 20 is programmed via hot carrier injection onto floating gate 30.
- a sensor (not shown) is used to detect the state of EPROM cell 20.
- Figure 2 is a diagram illustrating one example of an EPROM array 40 including EPROM cells 42 arranged in rows and columns.
- each of the EPROM cells 42 is similar to EPROM cell 20 of Figure 1.
- Each of the EPROM cells 42 includes a control gate 44, a drain 46, and a source 48.
- Control gates 44 are electrically coupled to input voltage Vin at 50.
- Drains 46 are electrically coupled together and to series resistor 52 via drain line 54, including drain lines 54a and 54b. The other side of series resistor 52 is electrically coupled to input voltage Vin at 50.
- Sources 48 are electrically coupled to the drains of row transistors 56, where the sources of row transistors 56 are electrically coupled to the drains of column transistors 58a and 58b via column lines 60a and 60b.
- the sources of column transistors 58a and 58b are electrically coupled to references at 62a and 62b, such as ground.
- Row transistors 56 and column transistors 58a and 58b provide selection of EPROM cells 42 for programming and reading.
- Row lines 64a and 64b are electrically coupled to the gates of row transistors 56.
- Row line 64a provides row signal ROW1 at 64a to the gates of row transistors 56 in one row and row line 64b provides row signal ROW2 at 64b to the gates of row transistors 56 in another row.
- the sources of row transistors 56 in a given column are electrically coupled together and to the drain of one of the column transistors 58a and 58b that corresponds to the given column.
- the gates of each column transistor 58a and 58b are electrically coupled to a voltage source via column select lines (not shown).
- Each of the EPROM cells 42 is programmed by applying a voltage pulse to the control gate 44 and drain 46 of the EPROM cell 42, across drain 46 to source 48 of the EPROM cell 42. This provides hot carriers or electrons to floating gate 66.
- the time required for programming is a function of at least the floating gate voltage, the quantity of hot electrons drawn to the floating gate, the threshold voltage needed, and the thickness of gate oxide between the substrate and the floating gate.
- control gate 44 is coupled to drain 46 via resistor 52 to limit the breakdown current.
- resistor 52 has a resistance of 100 ohms.
- the programming voltage across drain 46 to source 48 is close to the breakdown voltage of the EPROM cell 42, where the breakdown voltage is the voltage at which the EPROM cell 42 begins to conduct with its control gate 44 below the threshold voltage, such as zero volts.
- the breakdown voltage is the voltage at which the EPROM cell 42 begins to conduct with its control gate 44 below the threshold voltage, such as zero volts.
- an EPROM cell 42 has been programmed at a voltage of about 16V, where the circuit has a breakdown voltage of 15V.
- the floating gate voltage is in the range of 5V to 12V.
- the threshold voltage is in the range of 3V to 7V.
- the threshold voltage is detected using a sensor (not shown). Detecting the threshold voltage can be done by setting the gate/drain voltage and measuring the corresponding current or by setting the current and measuring the voltage.
- the on resistance (Ron) of the EPROM cell 42 changes by a factor of about 2 from being unprogrammed to being programmed.
- the EPROM cell 42 is selected by providing a row select voltage to one of the row lines 64a and 64b and a column select voltage to the gate of one of the column transistors 58a and 58b.
- a relatively high input voltage Vin such as 16V
- Vin is provided at 50.
- Only the selected EPROM cell 42 has substantially the full input voltage Vin across drain 46 to source 48. All other EPROM cells 42 have source 48 floating to the voltages on the other terminals.
- a relatively low input voltage pulse Vin such as 5V, is provided at 50 and the current through the selected EPROM cell 42 is monitored.
- each EPROM cell 42 has a different control transistor coupled to it, where each EPROM cell 42 is selected via one control line coupled to the corresponding control transistor.
- Figure 3 is a diagram illustrating one example of the layers in an EPROM chip 70.
- EPROM chip 70 includes EPROM cells, such as EPROM cell 20 of Figure 1.
- EPROM chip 70 includes EPROM array 40 of Figure 2 and EPROM cells 42 (shown in Figure 2).
- EPROM chip 70 is used in an inkjet printhead.
- EPROM chip 70 is an inkjet control EPROM chip.
- EPROM chip 70 includes a semiconductor substrate 72, an oxide layer 74, a polysilicon layer 76, a first dielectric layer 78, a metal 1 layer 80, a second dielectric layer 82, and a metal 2 layer 84.
- Oxide layer 74 is disposed on substrate 72 between substrate 72 and polysilicon layer 76.
- First dielectric layer 78 is disposed on polysilicon layer 76, and second dielectric layer 82 is dispose on metal 1 layer 80 that separates metal 1 layer 80 from metal 2 layer 84.
- Metal 1 layer 80 and metal 2 layer 84 provide row lines, column lines, and other connections in EPROM chip 70.
- oxide layer 74 is silicon dioxide (SiO2).
- second dielectric layer 82 includes silicon nitride.
- second dielectric layer 82 includes silicon carbide.
- second dielectric layer 82 includes silicon nitride and silicon carbide.
- Figure 4 is a diagram illustrating one example of an EPROM cell 90 that uses the layers of EPROM chip 70 of Figure 3.
- EPROM cell 20 of Figure 1 is similar to EPROM cell 90.
- each of the EPROM cells 42 (shown in Figure 2) is similar to EPROM cell 90.
- EPROM cell 90 is used in an inkjet printhead system. In other examples, EPROM cell 90 is created using the layers of a different process.
- EPROM cell 90 includes substrate 72 that has N+ source regions 92 and 94, an N+ drain region 96, and a p channel 98 including p channel regions 98a and 98b.
- Drain region 96 includes a top surface 100, a bottom 102, and sides 104 between top surface 100 and bottom 102.
- Channel 98 is situated between source region 92 and drain region 96 and between source region 94 and drain region 96.
- source regions 92 and 94 are connected and part of one continuous source region that surrounds channel 98.
- Channel 98 includes a rounded closed curve structure around drain region 96, where a curve is defined as an object similar to a line, but not required to be straight, which entails that a line is a special case of a curve, namely a curve with null curvature. Also, a closed curve is defined as a curve that joins up and has no endpoints, and a rounded closed curve is a closed curve that has at least one rounded or arched corner or no corners, such that it does not have sharp or angled corners.
- channel 98 including channel regions 98a and 98b, is an elliptically shaped channel around drain region 96.
- channel 98 is a circular shaped channel around drain region 96.
- channel 98, including channel regions 98a and 98b has multiple straight sides and at least one rounded corner to form a rounded closed curve channel around drain region 96.
- channel 98, including channel regions 98a and 98b has at least one rounded exterior corner to form a rounded closed curve channel around drain region 96.
- channel 98, including channel regions 98a and 98b has at least one rounded exterior corner and at least one rectangular interior corner to form a rounded closed curve channel around drain region 96.
- All of the above examples include a rounded closed curve structure to increase the uniformity of the length of the channel throughout the width of the channel, relative to a rectangular channel. Increasing the uniformity of the length of the channel, increases the uniformity of the generation of hot carriers and improves programming efficiency of the EPROM cell.
- One example channel includes a substantially uniform channel length throughout the width of the channel.
- EPROM cell 90 includes capacitive coupling between metal 1 layer 80 and metal 2 layer 84, where metal 1 layer 80 and metal 2 layer 84 form parallel opposing capacitor plates 106 and 108.
- One capacitor plate 106 is formed in metal 1 layer 80 and the other capacitor plate 108 is formed in metal 2 layer 84.
- the capacitor plate 108 formed in metal 2 layer 84 is the control gate 108 of EPROM cell 90.
- the input voltage Vin is applied to control gate 108 and capacitively coupled to the capacitor plate 106.
- control gate 108 is similar to control gate 32 (shown in Figure 1).
- control gate 108 is similar to one of the control gates 44 (shown in Figure 2).
- a parallel floating gate 110 is formed in polysilicon layer 76, where floating gate 110 includes polysilicon floating gate regions 76a and 76b situated over channel regions 98a and 98b, respectively.
- Floating gate 100 including floating gate regions 76a and 76b, forms a rounded closed curve floating gate, such that floating gate 110 and channel 98 include rounded closed curve structures.
- floating gate 110 including floating gate regions 76a and 76b, is the same shape as channel 98, including channel regions 98a and 98b.
- a break or hole in dielectric layer 78 allows capacitor plate 106 in metal 1 layer 80 to be electrically coupled to floating gate 110, including floating gate regions 76a and 76b.
- Floating gate 110 is separated from substrate 72 by dielectric layer 74.
- dielectric layer 74 is a silicon dioxide layer between channel 98 and floating gate 110.
- Floating gate 110 includes a rounded closed curve structure, where a curve is defined as an object similar to a line, but not required to be straight, which entails that a line is a special case of a curve, namely a curve with null curvature.
- a closed curve is defined as a curve that joins up and has no endpoints
- a rounded closed curve is a closed curve that has at least one rounded or arched corner or no corners, such that it does not have sharp or angled corners.
- floating gate 110 is an elliptically shaped floating gate.
- floating gate 110 is a circular shaped floating gate.
- floating gate 110 has multiple straight sides and at least one rounded corner to form a rounded closed curve floating gate. In one example, floating gate 110 has at least one rounded exterior corner to form a rounded closed curve floating gate. In one example, floating gate 110 has at least one rounded exterior corner and at least one rectangular interior corner to form a rounded closed curve floating gate.
- All of the above examples include a rounded closed curve structure to increase the uniformity of the length of the floating gate throughout the width of the floating gate, relative to a rectangular floating gate. Increasing the uniformity of the length of the floating gate, increases the uniformity of the generation of hot carriers and improves programming efficiency of the EPROM cell.
- One example floating gate includes a substantially uniform floating gate length throughout the width of the floating gate.
- EPROM cell 90 To program EPROM cell 90, a high input voltage pulse is applied to control gate 108 and drain region 96, across drain region 96 to source regions 92 and 94. This generates energetic "hot" carriers or electrons. A positive voltage bias between control gate 108 and drain region 96 pulls some of these hot electrons onto floating gate 110. As electrons are pulled onto floating gate 110, the threshold voltage of EPROM cell 90, i.e., the voltage required to cause channel 98 to conduct current, increases. If enough electrons are pulled onto floating gate 110, the threshold voltage increases to a level above a specified threshold voltage and EPROM cell 90 blocks current at a specified threshold voltage level, which changes the logic state of EPROM cell 90 from one logic value to the other logic value. Thus, EPROM cell 90 is programmed via hot carrier injection onto floating gate 110.
- the threshold voltage is detected using a sensor (not shown). Detecting the threshold voltage can be done by setting the gate/drain voltage and measuring the corresponding current or by setting the current and measuring the voltage.
- the on resistance (Ron) of EPROM cell 90 changes by a factor of about 2 from being unprogrammed to being programmed.
- the EPROM structure disclosed herein can replace fuses in many types of circuits without adding process layers and cost. This configuration provides cells that are larger than traditional EPROM cells, but smaller than fuses.
- EPROM cells configured this way can also be used for other purposes. Since the charge on the floating gate is cumulative, this configuration can be used to store cumulative quantities. For example, in an inkjet printhead, EPROM cells can be successively reprogrammed to track the number of pages printed out, or for other purposes. Also, since programming of EPROM cells modifies the threshold voltage of the cell, successive programming of these cells can be used to control analog circuits, such as to create a variable time delay. Other applications are also possible.
- the rounded closed curve structures of the channel and the floating gate improve programming efficiency over a rectangular channel and rectangular floating gate EPROM cell.
- the rounded closed curve structures of the channel and the floating gate provide a preprogramming EPROM ratio that is more centered around a specified value and reduced as compared to the
- preprogramming EPROM ratio provided via a rectangular channel and rectangular floating gate EPROM cell.
- programming efficiency is improved twenty percent over a rectangular channel and rectangular floating gate EPROM cell.
- Figure 5 is a top-view diagram illustrating one example of an EPROM cell 120 that includes a circular floating gate 122 and a circular channel 124.
- Channel 124 is situated under floating gate 122 and indicated by dotted lines. Also, some of the layers of EPROM cell 120, such as metal layers, are not shown for clarity. EPROM cell 120 is similar to EPROM cell 90 of Figure 4. In one example, a cross-section of EPROM cell 120 taken along the line A-A is similar to the cross-section of EPROM cell 90 of Figure 4.
- EPROM cell 120 includes floating gate 122, channel 124, a drain 126, and a source 128.
- Circular channel 124 is situated under circular floating gate 122.
- Channel 124 surrounds drain 126 and is situated between drain 126 and source 128.
- Source 128 surrounds channel 124.
- floating gate 122 is polysilicon
- channel 124 is a p channel region
- drain 126 is an N+ region
- source 128 is an N+ region.
- Circular floating gate 122 is an elliptically shaped floating gate, where its circular shape is a special case of an ellipse.
- Circular floating gate 122 includes a rounded closed curve structure having rounded corners or no comers, such that it does not have sharp or angled corners.
- Circular floating gate 122 has a floating gate length Lfg that is the distance from the exterior side 130 of circular floating gate 122 to the interior side 132 of circular floating gate 122.
- the width W of circular floating gate 122 is the distance around circular floating gate 122 measured at the midpoint of the floating gate length Lfg.
- floating gate 122 can be another elliptical shape, such as an oval, and/or another rounded closed curve shape, such as egg shaped.
- Circular channel 124 is an elliptically shaped channel, where its circular shape is a special case of an ellipse.
- Circular channel 124 includes a rounded closed curve structure having rounded corners or no corners, such that it does not have sharp or angled comers.
- Circular channel 124 has a channel length Lc that is the distance from the exterior side 134 of circular channel 124 to the interior side 36 of circular channel 124.
- the width W of circular channel 124 is the distance around circular channel 124 measured at the midpoint of the channel length Lc.
- channel 124 can be another elliptical shape, such as an oval, and/or another rounded closed curve shape, such as egg shaped.
- Figure 6 is a top-view diagram illustrating one example of an EPROM cell 140 that includes a floating gate 142 having multiple straight sides 142a-142d and rounded corners 142e-142h, and a channel 144 having multiple straight sides 144a-144d and rounded corners 144e-144h. Channel 144 is situated under floating gate 142 and indicated by dotted lines. Also, some of the layers of EPROM cell 140, such as metal layers, are not shown for clarity. EPROM cell 140 is similar to EPROM cell 90 of Figure 4. In one example, a cross- section of EPROM cell 140 taken along the line B-B is similar to the cross- section of EPROM cell 90 of Figure 4.
- EPROM cell 140 includes floating gate 142, channel 144, a drain 146, and a source 148.
- Channel 144 is situated under floating gate 142.
- Channel 144 surrounds drain 146 and is situated between drain 146 and source 148.
- Source 148 surrounds channel 144.
- floating gate 142 is polysilicon
- channel 144 is a p channel region
- drain 146 is an N+ region
- source 148 is an N+ region.
- Floating gate 142 has four straight sides 142a-142d and four rounded corners 142e-142h.
- Floating gate 142 includes a rounded closed curve structure having rounded corners 142e-142h, such that it does not have sharp or angled corners.
- Floating gate 142 has a floating gate length Lfg that is the distance from the exterior side 150 of floating gate 142 to the interior side 152 of floating gate 142.
- the width W of floating gate 142 is the distance around floating gate 142 measured at the midpoint of the floating gate length Lfg.
- floating gate 142 can have a different number of straight sides, such as two or three straight sides or more than four straight sides, and a different number of rounded corners, such as two or three rounded corners or more than four rounded corners.
- Channel 144 has four straight sides 144a-144d and four rounded corners 144e-144h.
- Channel 144 includes a rounded closed curve structure having rounded corners 144e-144h, such that it does not have sharp or angled corners.
- Channel 144 has a channel length Lc that is the distance from the exterior side 154 of channel 144 to the interior side 156 of channel 144.
- the width W of channel 144 is the distance around channel 144 measured at the midpoint of the channel length Lc.
- channel 144 can have a different number of straight sides, such as two or three straight sides or more than four straight sides, and a different number of rounded corners, such as two or three rounded corners or more than four rounded corners.
- Figure 7 is a top-view diagram illustrating one example of an EPROM cell 160 that includes a floating gate 162 having multiple straight sides 162a and 162b, a rounded top 162c, and a rounded bottom 162d, and a channel 164 having multiple straight sides 164a and 164b, a rounded top 164c, and a rounded bottom 164d.
- Channel 164 is situated under floating gate 162 and indicated by dotted lines.
- some of the layers of EPROM cell 160 such as metal layers, are not shown for clarity.
- EPROM cell 160 is similar to EPROM cell 90 of Figure 4. In one example, a cross-section of EPROM cell 160 taken along the line C-C is similar to the cross-section of EPROM cell 90 of Figure 4.
- EPROM cell 160 includes floating gate 162, channel 164, a drain 166, and a source 168.
- Channel 164 is situated under floating gate 162.
- Channel 164 surrounds drain 166 and is situated between drain 166 and source 168.
- Source 168 surrounds channel 164.
- floating gate 162 is polysilicon
- channel 164 is a p channel region
- drain 166 is an N+ region
- source 168 is an N+ region.
- Floating gate 162 has two straight sides 162a and 162b, a rounded top 162c, and a rounded bottom 162d.
- Floating gate 162 includes a rounded closed curve structure having a rounded top 162c and a rounded bottom 162d, such that it does not have sharp or angled corners.
- Floating gate 162 has a floating gate length Lfg that is the distance from the exterior side 170 of floating gate 162 to the interior side 172 of floating gate 162.
- the width W of floating gate 162 is the distance around floating gate 162 measured at the midpoint of the floating gate length Lfg.
- Channel 164 has two straight sides 164a and 164b, a rounded top 164c, and a rounded bottom 164d.
- Channel 164 includes a rounded closed curve structure having a rounded top 164c and a rounded bottom 164d, such that it does not have sharp or angled corners.
- Channel 164 has a channel length Lc that is the distance from the exterior side 174 of channel 164 to the interior side 176 of channel 164.
- the width W of channel 164 is the distance around channel 164 measured at the midpoint of the channel length Lc.
- the rounded closed curve floating gates and channels increase the uniformity of the channel length and the uniformity of the floating gate length and remove "corner effects' associated with a rectangular channel and rectangular floating gate EPROM cell. Making the channel length and floating gate length more uniform and removing "corner effects" leads to more uniform and efficient generation of hot electrons during programming. Also, the rounded channels and the rounded floating gates provide a
- preprogramming EPROM ratio that is more centered around a specified value and reduced as compared to the preprogramming EPROM ratio provided via a rectangular channel and rectangular floating gate EPROM cell.
- programming efficiency is improved twenty percent over a rectangular channel and rectangular floating gate EPROM cell.
- Figure 8 is a top-view diagram illustrating one example of an EPROM cell 180 that includes a rectangular floating gate 182 having multiple straight sides 182a-182d and sharp angled corners 182e-182h, and a rectangular channel 184 having multiple straight sides 184a-184d and sharp angled corners 184e- 184h.
- Channel 184 is situated under floating gate 182 and indicated by dotted lines. Also, some of the layers of EPROM cell 180, such as metal layers, are not shown for clarity.
- EPROM cell 180 includes floating gate 182, channel 184, a drain 186, and a source 188.
- Channel 184 is situated under floating gate 182.
- Channel 184 surrounds drain 186 and is situated between drain 186 and source 188.
- Source 188 surrounds channel 184.
- floating gate 182 is polysilicon
- channel 184 is a p channel region
- drain 186 is an N+ region
- source 188 is an N+ region.
- Floating gate 182 has four straight sides 182a-182d and four sharp angled corners 182e-182h. Floating gate 182 does not include a rounded closed curve structure and is not a rounded closed curve floating gate.
- Channel 184 has four straight sides 184a-184d and four sharp angled corners 184e-184h.
- Channel 184 does not include a rounded closed curve structure and is not a rounded closed curve channel.
- Figure 9 is a graph 200 illustrating EPROM resistance ratios of EPROM cells having circular floating gates and channels, such as EPROM cell 120 of Figure 5, and EPROM cells having rectangular floating gates and channels, such as EPROM cell 180 of Figure 8.
- plots and histograms for EPROM cells having circular floating gates and channels referred to as circular EPROM cells
- plots and histograms for EPROM cells having rectangular floating gates and channels referred to as rectangular EPROM cells
- the y-axis at 204 plots resistance ratios, where each ratio is a measured resistance value to a reference unprogrammed resistance value. Statistics for the graphed resistance ratios are shown in Table 1.
- Unprog_Rect are plotted at 206 in a type of box and whisker plot and at 208 in a histogram
- the resistance ratios of unprogrammed circular EPROM cells are plotted at 210 in a type of box and whisker plot and at 212 in a histogram.
- the resistance ratios of unprogrammed circular EPROM cells are generally less than the resistance ratios of unprogrammed rectangular EPROM cells, where the mean unprogrammed resistance ratio decreases from 1.08644 for the rectangular EPROM cells to 1.03602 for the circular EPROM cells.
- the mean resistance value of the unprogrammed circular EPROM cells is much closer to and more centered around the reference unprogrammed resistance value, as compared to the mean resistance value of the unprogrammed rectangular EPROM cells. Also, even though the standard deviation of resistance ratios increases from .013223 for the rectangular EPROM cells to .021055 for the circular EPROM cells, the resistance ratio distribution of the unprogrammed circular EPROM cells is further away from the bin 6 test failure limit at 214, referred to as an unprogrammed bit consistency failure, as compared to the resistance ratio distribution of the unprogrammed rectangular EPROM cells.
- the resistance ratios of programmed circular EPROM cells are generally higher than the resistance ratios of programmed rectangular EPROM cells, where the mean programmed resistance ratio increases from 1.84717 for the rectangular EPROM cells to 2.04736 for the circular EPROM cells.
- the mean resistance value of the programmed circular EPROM cells is more than twice the reference unprogrammed resistance value.
- the standard deviation of the resistance ratios decreases from .117780 for the rectangular EPROM cells to .045884 for the circular EPROM cells.
- the resistance ratio distribution of the programmed circular EPROM cells is further away from the bin 7 test failure limit at 224, referred to as a stubborn bit failure, than the resistance ratio distribution of the programmed rectangular EPROM cells.
- EPROM cells at 210 and 212 and programmed resistance values in circular EPROM cells at 220 and 222 is greater than the spread between unprogrammed resistance values in rectangular EPROM cells at 206 and 208 and programmed resistance values in rectangular EPROM cells at 216 and 218.
- the larger spread improves the programming efficiency of circular EPROM cells over the programming efficiency of rectangular EPROM cells. This improved programming efficiency improves programming reliability and provides opportunities for new EPROM applications. In one example, programming efficiency increases 20%.
- the robustness of the fabrication process is improved by building EPROM cells having rounded closed curve floating gates and channels, instead of EPROM cells having rectangular floating gates and channels.
- the rounded closed curve floating gates and channels increase the uniformity of the channel length and the uniformity of the floating gate length and remove "corner effects' associated with a rectangular channel and rectangular floating gate EPROM cell. Making the channel length and the floating gate length more uniform and removing "corner effects" leads to more uniform and efficient generation of hot electrons during programming, as shown by increased programmability.
- photolithography x-y astigmatism results in gate length variations in rectangular EPROM cells that contribute to reductions in programming efficiency and increased yield losses.
- the rounded closed curve floating gates and channels provide more uniform gate lengths by eliminating photolithography x-y
- Figures 10 and 11 are graphs illustrating resistance ratios in EPROM cells manufactured using a process having the layers of Figure 3 and providing the EPROM cell 90 of Figure 4.
- Figure 10 is a graph 300 illustrating unprogrammed resistance ratios for circular and rectangular EPROM cells. Resistance ratios are graphed as percentages along the x-axis at 302 versus the number of units along the y-axis at 304. Each of the resistance ratios is a measured unprogrammed resistance value divided by a reference unprogrammed resistance value.
- Unprogrammed resistance ratios of circular EPROM cells at 306 are centered around a percentage of about 104% and unprogrammed resistance ratios of rectangular EPROM cells at 308 are centered around a percentage of about 109%. This is a reduction in unprogrammed resistance of about 5% for circular EPROM cells over rectangular EPROM cells.
- the distribution of unprogrammed resistance ratios of circular EPROM cells at 306 is wider than the distribution of the unprogrammed resistance ratios of rectangular EPROM cells at 308, but most of the unprogrammed resistance ratios of circular EPROM cells at 306 are smaller than most of the unprogrammed resistance ratios of rectangular EPROM cells at 308.
- the centered unprogrammed resistance value of circular EPROM cells at 306 is much closer to and more centered around the reference unprogrammed resistance value, as compared to the centered unprogrammed resistance value of rectangular EPROM cells 308.
- Figure 11 is a graph 400 illustrating programmed resistance ratios for circular and rectangular EPROM cells. Resistance ratios are graphed as percentages along the x-axis at 402 versus the number of units along the y-axis at 404. Each of the resistance ratios is a measured programmed resistance value divided by a reference unprogrammed resistance value.
- Programmable resistance ratios of circular EPROM cells at 406 are centered around a percentage of about 205% and programmed resistance ratios of rectangular EPROM cells at 408 are centered around a percentage of about 185%. This is an increase of 20% for circular EPROM cells over rectangular EPROM cells, where the centered resistance value of the programmed circular EPROM cells at 406 is more than twice the reference unprogrammed resistance value.
- the distribution of programmed resistance ratios of circular EPROM cells at 406 is narrower than the distribution of programmed resistance ratios of rectangular EPROM cells at 408, and most of the programmed resistance ratios of circular EPROM cells at 406 are larger than most of the programmed resistance ratios of rectangular EPROM cells at 408.
- the centered programmed resistance value of circular EPROM cells at 406 is further away from the reference unprogrammed resistance value, as compared to the centered programmed resistance value of rectangular EPROM cells 408.
- EPROM cells at 306 and programmed resistance values in circular EPROM cells at 406 is greater than the spread between unprogrammed resistance values in rectangular EPROM cells at 308 and programmed resistance values in rectangular EPROM cells at 408.
- the larger spread improves the programming efficiency of circular EPROM cells over the programming efficiency of
- Figures 12 and 13 are graphs illustrating resistance ratios in EPROM cells manufactured using another suitable process.
- Figure 12 is a graph 500 illustrating unprogrammed resistance ratios for circular and rectangular EPROM cells. Resistance ratios are graphed as percentages along the x-axis at 502 versus the number of units along the y-axis at 504. Each of the resistance ratios is a measured unprogrammed resistance value divided by a reference unprogrammed resistance value.
- Unprogrammed resistance ratios of circular EPROM cells at 506 are centered around a percentage of about 107 or 108% and unprogrammed resistance ratios of rectangular EPROM cells at 508 are centered around a percentage of about 112%. This is a reduction in unprogrammed resistance of about 4 or 5% for circular EPROM cells over rectangular EPROM cells.
- the distribution of unprogrammed resistance ratios of circular EPROM cells at 506 is wider than the distribution of the unprogrammed resistance ratios of rectangular EPROM cells at 508, but most of the unprogrammed resistance ratios of circular EPROM cells at 506 are smaller than most of the unprogrammed resistance ratios of rectangular EPROM cells at 508.
- the centered unprogrammed resistance value of circular EPROM cells at 506 is closer to and more centered around the reference unprogrammed resistance value, as compared to the centered unprogrammed resistance value of rectangular EPROM cells 308.
- Figure 13 is a graph 600 illustrating programmed resistance ratios for circular and rectangular EPROM cells. Resistance ratios are graphed as percentages along the x-axis at 602 versus the number of units along the y-axis at 604. Each of the resistance ratios is a measured programmed resistance value divided by a reference unprogrammed resistance value.
- programmed resistance ratios of circular EPROM cells at 606 are centered around a percentage of about 170% and programmed resistance ratios of rectangular EPROM cells at 608 are centered around a percentage of about 158%. This is an increase of 12% for circular EPROM cells over rectangular EPROM cells, where the centered resistance value of the
- programmed circular EPROM cells at 606 is about 1.7 times the reference unprogrammed resistance value.
- the distribution of programmed resistance ratios of circular EPROM cells at 606 is similar to the distribution of programmed resistance ratios of rectangular EPROM cells at 608.
- the centered programmed resistance value of circular EPROM cells at 606 is further away from the reference unprogrammed resistance value, as compared to the centered programmed resistance value of rectangular EPROM cells 608.
- EPROM cells at 506 and programmed resistance values in circular EPROM cells at 606 is greater than the spread between unprogrammed resistance values in rectangular EPROM cells at 508 and programmed resistance values in rectangular EPROM cells at 608.
- the larger spread improves the programming efficiency of circular EPROM cells over the programming efficiency of
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Abstract
A memory cell including a drain, a channel, and a floating gate. The channel surrounds the drain and includes a first rounded closed curve structure around the drain. The floating gate is situated over the channel and includes a second rounded closed curve structure over the channel.
Description
MEMORY CELL HAVING CLOSED CURVE STRUCTURE
Background
Programmable read-only memory (PROM) chips are well known and widely used in a variety of computer devices. Typically, a PROM chip includes a grid of metal conductors forming rows and columns. Each row/column intersection includes a conductive fuse that provides one bit of memory. To program a fuse, a relatively high current is selectively routed to the fuse to cause the fuse to burn out. Intersections where fuses remain are one logic value and intersections where fuses are burned out are the other logic value.
In inkjet printheads, fuse technology has been included in N-channel metal-oxide semiconductor (NMOS) chips. In these NMOS chips, fuses are programmed in substantially the same way, where fuses are selectively burned out to program a bit. However, programming chips in this way has some drawbacks. If a chip is improperly programmed, there is no way to fix it and the chip must be discarded. Also, fuses are relatively large and can be unreliable. In addition, fuses can damage the orifice layer of the inkjet during programming and after a fuse burns out metal debris from the fuse can be drawn into the ink and cause blockage in the inkjet pen, resulting in poor quality printing.
In recent years, electronically programmable read-only memory
(EPROM) devices have been developed. These EPROM devices include a conductive grid of rows and columns, but they do not include fuses. Instead, a memory cell is located at each row/column intersection. Each memory cell includes a transistor structure and two gates that are separated from each other
by a thin dielectric layer. One of the gates is a floating gate and the other is a control gate or input gate. In an unprogrammed memory cell, the floating gate has no charge, which causes the threshold voltage to be low. In a programmed memory cell, the floating gate is charged with electrons and the threshold voltage is higher. To program a memory cell, a programming voltage (e.g., 10 to 16 volts) is applied to the control gate and drain. This programming voltage draws excited electrons to the floating gate, thereby increasing the threshold voltage. A memory cell having a lower threshold voltage is one logic value and a memory cell having a higher threshold voltage is the other logic value.
Brief Description of the Drawings
Figure 1 is a diagram illustrating one example of an EPRO cell that stores one bit of information.
Figure 2 is a diagram illustrating one example of an EPROM array.
Figure 3 is a diagram illustrating one example of the layers in an EPROM chip.
Figure 4 is a diagram illustrating one example of an EPROM cell that uses the layers of the EPROM chip of Figure 3.
Figure 5 is a top-view diagram illustrating one example of an EPROM cell that includes a circular floating gate and a circular channel.
Figure 6 is a top-view diagram illustrating one example of an EPROM cell that includes a floating gate having multiple straight sides and rounded corners, and a channel having multiple straight sides and rounded corners.
Figure 7 is a top-view diagram illustrating one example of an EPROM cell that includes a floating gate having multiple straight sides, a rounded top, and a rounded bottom, and a channel having multiple straight sides, a rounded top, and a rounded bottom.
Figure 8 is a top-view diagram illustrating one example of an EPROM cell that includes a rectangular floating gate and a rectangular channel.
Figure 9 is a graph illustrating EPROM resistance ratios of EPROM cells having circular floating gates and channels, and EPROM cells having
rectangular floating gates and channels.
Figure 10 is a graph illustrating unprogrammed resistance ratios for circular and rectangular EPROM cells.
Figure 11 is a graph illustrating programmed resistance ratios for circular and rectangular EPROM cells.
Figure 12 is a graph illustrating unprogrammed resistance ratios for circular and rectangular EPROM cells fabricated in another suitable process.
Figure 13 is a graph illustrating programmed resistance ratios for circular and rectangular EPROM cells fabricated in the other suitable process.
Detailed Description [001] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific examples in which the invention may be practiced. In this regard, directional terminology, such as "top," "bottom," "front," "back," "leading," "trailing," etc., is used with reference to the orientation of the Figure(s) being described. Because components of examples of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. It is to be understood that features of the various examples described herein may be combined with each other, unless specifically noted otherwise.
Figure 1 is a diagram illustrating one example of an EPROM cell 20 that stores one bit of information. EPROM cell 20 does not include a fuse and provides a number of advantages over an NMOS fused bit. EPROM cells, such
as EPROM cell 20, can be used to eliminate fuses in systems, such as ink jet printhead systems.
EPROM cell 20 includes a semiconductor substrate 22 having a source 24, a drain 26, and a channel 28, where channel 28 is situated between source 24 and drain 26. A floating gate 30 is situated over channel 28 and an input gate 32, also referred to as control gate 32, is situated over floating gate 30. Source 24 includes an N+ doped region and drain 26 includes an N+ doped region. Channel 28 is a p doped region situated between the N+ doped regions of source 24 and drain 26.
Control gate 32 is capacitively coupled to floating gate 30 via a dielectric material 34 that is situated between control gate 32 and floating gate 30. A voltage at control gate 32 is coupled to floating gate 30. Another layer of dielectric material 36 is disposed between floating gate 30 and substrate 22 over channel 28.
To program EPROM cell 20, a high voltage bias is applied to drain 26.
This high voltage bias on drain 26 generates energetic "hot" carriers or electrons. A positive voltage bias between control gate 32 and drain 26 pulls some of these hot electrons onto floating gate 30. As electrons are pulled onto floating gate 30, the threshold voltage of EPROM cell 20, i.e., the voltage required to cause channel 28 to conduct current, increases. If enough electrons are pulled onto floating gate 30, the threshold voltage increases to a level above a specified threshold voltage and EPROM cell 20 blocks current at the specified threshold voltage level, which changes the logic state of EPROM cell 20 from one logic value to the other logic value. Thus, EPROM cell 20 is programmed via hot carrier injection onto floating gate 30. In normal operation, a sensor (not shown) is used to detect the state of EPROM cell 20.
Figure 2 is a diagram illustrating one example of an EPROM array 40 including EPROM cells 42 arranged in rows and columns. In one example, each of the EPROM cells 42 is similar to EPROM cell 20 of Figure 1.
Each of the EPROM cells 42 includes a control gate 44, a drain 46, and a source 48. Control gates 44 are electrically coupled to input voltage Vin at 50. Drains 46 are electrically coupled together and to series resistor 52 via drain line
54, including drain lines 54a and 54b. The other side of series resistor 52 is electrically coupled to input voltage Vin at 50. Sources 48 are electrically coupled to the drains of row transistors 56, where the sources of row transistors 56 are electrically coupled to the drains of column transistors 58a and 58b via column lines 60a and 60b. The sources of column transistors 58a and 58b are electrically coupled to references at 62a and 62b, such as ground. Row transistors 56 and column transistors 58a and 58b provide selection of EPROM cells 42 for programming and reading.
Row lines 64a and 64b are electrically coupled to the gates of row transistors 56. Row line 64a provides row signal ROW1 at 64a to the gates of row transistors 56 in one row and row line 64b provides row signal ROW2 at 64b to the gates of row transistors 56 in another row. The sources of row transistors 56 in a given column are electrically coupled together and to the drain of one of the column transistors 58a and 58b that corresponds to the given column. The gates of each column transistor 58a and 58b are electrically coupled to a voltage source via column select lines (not shown).
Each of the EPROM cells 42 is programmed by applying a voltage pulse to the control gate 44 and drain 46 of the EPROM cell 42, across drain 46 to source 48 of the EPROM cell 42. This provides hot carriers or electrons to floating gate 66. The time required for programming is a function of at least the floating gate voltage, the quantity of hot electrons drawn to the floating gate, the threshold voltage needed, and the thickness of gate oxide between the substrate and the floating gate. For each of the EPROM cells 42, control gate 44 is coupled to drain 46 via resistor 52 to limit the breakdown current. In one example, resistor 52 has a resistance of 100 ohms.
In one example, the programming voltage across drain 46 to source 48 is close to the breakdown voltage of the EPROM cell 42, where the breakdown voltage is the voltage at which the EPROM cell 42 begins to conduct with its control gate 44 below the threshold voltage, such as zero volts. In one example, an EPROM cell 42 has been programmed at a voltage of about 16V, where the circuit has a breakdown voltage of 15V. In one example, the floating
gate voltage is in the range of 5V to 12V. In one example, the threshold voltage is in the range of 3V to 7V.
To read one of the EPROM cells 42, the threshold voltage is detected using a sensor (not shown). Detecting the threshold voltage can be done by setting the gate/drain voltage and measuring the corresponding current or by setting the current and measuring the voltage. The on resistance (Ron) of the EPROM cell 42 changes by a factor of about 2 from being unprogrammed to being programmed.
To program one of the EPROM cells 42, the EPROM cell 42 is selected by providing a row select voltage to one of the row lines 64a and 64b and a column select voltage to the gate of one of the column transistors 58a and 58b. Next, a relatively high input voltage Vin, such as 16V, is provided at 50. Only the selected EPROM cell 42 has substantially the full input voltage Vin across drain 46 to source 48. All other EPROM cells 42 have source 48 floating to the voltages on the other terminals. To sense the state of a selected EPROM cell 42, a relatively low input voltage pulse Vin, such as 5V, is provided at 50 and the current through the selected EPROM cell 42 is monitored. In other examples, each EPROM cell 42 has a different control transistor coupled to it, where each EPROM cell 42 is selected via one control line coupled to the corresponding control transistor.
Figure 3 is a diagram illustrating one example of the layers in an EPROM chip 70. In one example, EPROM chip 70 includes EPROM cells, such as EPROM cell 20 of Figure 1. In one example, EPROM chip 70 includes EPROM array 40 of Figure 2 and EPROM cells 42 (shown in Figure 2). In one example, EPROM chip 70 is used in an inkjet printhead. In one example, EPROM chip 70 is an inkjet control EPROM chip.
EPROM chip 70 includes a semiconductor substrate 72, an oxide layer 74, a polysilicon layer 76, a first dielectric layer 78, a metal 1 layer 80, a second dielectric layer 82, and a metal 2 layer 84. Oxide layer 74 is disposed on substrate 72 between substrate 72 and polysilicon layer 76. First dielectric layer 78 is disposed on polysilicon layer 76, and second dielectric layer 82 is dispose on metal 1 layer 80 that separates metal 1 layer 80 from metal 2 layer 84. Metal
1 layer 80 and metal 2 layer 84 provide row lines, column lines, and other connections in EPROM chip 70. In one example, oxide layer 74 is silicon dioxide (SiO2). In one example, second dielectric layer 82 includes silicon nitride. In one example, second dielectric layer 82 includes silicon carbide. In one example, second dielectric layer 82 includes silicon nitride and silicon carbide.
Figure 4 is a diagram illustrating one example of an EPROM cell 90 that uses the layers of EPROM chip 70 of Figure 3. In one example, EPROM cell 20 of Figure 1 is similar to EPROM cell 90. In one example, each of the EPROM cells 42 (shown in Figure 2) is similar to EPROM cell 90. In one example, EPROM cell 90 is used in an inkjet printhead system. In other examples, EPROM cell 90 is created using the layers of a different process.
EPROM cell 90 includes substrate 72 that has N+ source regions 92 and 94, an N+ drain region 96, and a p channel 98 including p channel regions 98a and 98b. Drain region 96 includes a top surface 100, a bottom 102, and sides 104 between top surface 100 and bottom 102. Channel 98, including channel regions 98a and 98b, surrounds drain region 96 around the sides 104 of drain region 96. Channel 98 is situated between source region 92 and drain region 96 and between source region 94 and drain region 96. In one example, source regions 92 and 94 are connected and part of one continuous source region that surrounds channel 98.
Channel 98 includes a rounded closed curve structure around drain region 96, where a curve is defined as an object similar to a line, but not required to be straight, which entails that a line is a special case of a curve, namely a curve with null curvature. Also, a closed curve is defined as a curve that joins up and has no endpoints, and a rounded closed curve is a closed curve that has at least one rounded or arched corner or no corners, such that it does not have sharp or angled corners. In one example, channel 98, including channel regions 98a and 98b, is an elliptically shaped channel around drain region 96. In one example, channel 98, including channel regions 98a and 98b, is a circular shaped channel around drain region 96. In one example, channel 98, including channel regions 98a and 98b, has multiple straight sides and at
least one rounded corner to form a rounded closed curve channel around drain region 96. In one example, channel 98, including channel regions 98a and 98b, has at least one rounded exterior corner to form a rounded closed curve channel around drain region 96. In one example, channel 98, including channel regions 98a and 98b, has at least one rounded exterior corner and at least one rectangular interior corner to form a rounded closed curve channel around drain region 96.
All of the above examples include a rounded closed curve structure to increase the uniformity of the length of the channel throughout the width of the channel, relative to a rectangular channel. Increasing the uniformity of the length of the channel, increases the uniformity of the generation of hot carriers and improves programming efficiency of the EPROM cell. One example channel includes a substantially uniform channel length throughout the width of the channel.
EPROM cell 90 includes capacitive coupling between metal 1 layer 80 and metal 2 layer 84, where metal 1 layer 80 and metal 2 layer 84 form parallel opposing capacitor plates 106 and 108. One capacitor plate 106 is formed in metal 1 layer 80 and the other capacitor plate 108 is formed in metal 2 layer 84. The capacitor plate 108 formed in metal 2 layer 84 is the control gate 108 of EPROM cell 90. The input voltage Vin is applied to control gate 108 and capacitively coupled to the capacitor plate 106. In one example, control gate 108 is similar to control gate 32 (shown in Figure 1). In one example, control gate 108 is similar to one of the control gates 44 (shown in Figure 2).
A parallel floating gate 110 is formed in polysilicon layer 76, where floating gate 110 includes polysilicon floating gate regions 76a and 76b situated over channel regions 98a and 98b, respectively. Floating gate 100, including floating gate regions 76a and 76b, forms a rounded closed curve floating gate, such that floating gate 110 and channel 98 include rounded closed curve structures. In one example, floating gate 110, including floating gate regions 76a and 76b, is the same shape as channel 98, including channel regions 98a and 98b.
A break or hole in dielectric layer 78 allows capacitor plate 106 in metal 1 layer 80 to be electrically coupled to floating gate 110, including floating gate regions 76a and 76b. Floating gate 110 is separated from substrate 72 by dielectric layer 74. In one example, dielectric layer 74 is a silicon dioxide layer between channel 98 and floating gate 110.
Floating gate 110, including floating gate regions 76a and 76b, includes a rounded closed curve structure, where a curve is defined as an object similar to a line, but not required to be straight, which entails that a line is a special case of a curve, namely a curve with null curvature. Also, a closed curve is defined as a curve that joins up and has no endpoints, and a rounded closed curve is a closed curve that has at least one rounded or arched corner or no corners, such that it does not have sharp or angled corners. In one example, floating gate 110 is an elliptically shaped floating gate. In one example, floating gate 110 is a circular shaped floating gate. In one example, floating gate 110 has multiple straight sides and at least one rounded corner to form a rounded closed curve floating gate. In one example, floating gate 110 has at least one rounded exterior corner to form a rounded closed curve floating gate. In one example, floating gate 110 has at least one rounded exterior corner and at least one rectangular interior corner to form a rounded closed curve floating gate.
All of the above examples include a rounded closed curve structure to increase the uniformity of the length of the floating gate throughout the width of the floating gate, relative to a rectangular floating gate. Increasing the uniformity of the length of the floating gate, increases the uniformity of the generation of hot carriers and improves programming efficiency of the EPROM cell. One example floating gate includes a substantially uniform floating gate length throughout the width of the floating gate.
To program EPROM cell 90, a high input voltage pulse is applied to control gate 108 and drain region 96, across drain region 96 to source regions 92 and 94. This generates energetic "hot" carriers or electrons. A positive voltage bias between control gate 108 and drain region 96 pulls some of these hot electrons onto floating gate 110. As electrons are pulled onto floating gate 110, the threshold voltage of EPROM cell 90, i.e., the voltage required to cause
channel 98 to conduct current, increases. If enough electrons are pulled onto floating gate 110, the threshold voltage increases to a level above a specified threshold voltage and EPROM cell 90 blocks current at a specified threshold voltage level, which changes the logic state of EPROM cell 90 from one logic value to the other logic value. Thus, EPROM cell 90 is programmed via hot carrier injection onto floating gate 110.
To read or sense the state of EPROM cell 90, the threshold voltage is detected using a sensor (not shown). Detecting the threshold voltage can be done by setting the gate/drain voltage and measuring the corresponding current or by setting the current and measuring the voltage. The on resistance (Ron) of EPROM cell 90 changes by a factor of about 2 from being unprogrammed to being programmed.
The EPROM structure disclosed herein can replace fuses in many types of circuits without adding process layers and cost. This configuration provides cells that are larger than traditional EPROM cells, but smaller than fuses.
EPROM cells configured this way can also be used for other purposes. Since the charge on the floating gate is cumulative, this configuration can be used to store cumulative quantities. For example, in an inkjet printhead, EPROM cells can be successively reprogrammed to track the number of pages printed out, or for other purposes. Also, since programming of EPROM cells modifies the threshold voltage of the cell, successive programming of these cells can be used to control analog circuits, such as to create a variable time delay. Other applications are also possible.
Manufacturers work on improving EPROM programming efficiency and production yields, where reductions in programming efficiency and yield can come from memory cells that are difficult to program, referred to as stubborn bits, and memory cells that have high or inconsistent unprogrammed resistance values, referred to as unprogrammed bit consistency.
The rounded closed curve structures of the channel and the floating gate improve programming efficiency over a rectangular channel and rectangular floating gate EPROM cell. The rounded closed curve structures of the channel and the floating gate provide a preprogramming EPROM ratio that is more
centered around a specified value and reduced as compared to the
preprogramming EPROM ratio provided via a rectangular channel and rectangular floating gate EPROM cell. In one example, programming efficiency is improved twenty percent over a rectangular channel and rectangular floating gate EPROM cell.
Figure 5 is a top-view diagram illustrating one example of an EPROM cell 120 that includes a circular floating gate 122 and a circular channel 124.
Channel 124 is situated under floating gate 122 and indicated by dotted lines. Also, some of the layers of EPROM cell 120, such as metal layers, are not shown for clarity. EPROM cell 120 is similar to EPROM cell 90 of Figure 4. In one example, a cross-section of EPROM cell 120 taken along the line A-A is similar to the cross-section of EPROM cell 90 of Figure 4.
EPROM cell 120 includes floating gate 122, channel 124, a drain 126, and a source 128. Circular channel 124 is situated under circular floating gate 122. Channel 124 surrounds drain 126 and is situated between drain 126 and source 128. Source 128 surrounds channel 124. In one example, floating gate 122 is polysilicon, channel 124 is a p channel region, drain 126 is an N+ region, and source 128 is an N+ region.
Circular floating gate 122 is an elliptically shaped floating gate, where its circular shape is a special case of an ellipse. Circular floating gate 122 includes a rounded closed curve structure having rounded corners or no comers, such that it does not have sharp or angled corners. Circular floating gate 122 has a floating gate length Lfg that is the distance from the exterior side 130 of circular floating gate 122 to the interior side 132 of circular floating gate 122. The width W of circular floating gate 122 is the distance around circular floating gate 122 measured at the midpoint of the floating gate length Lfg. In other examples, floating gate 122 can be another elliptical shape, such as an oval, and/or another rounded closed curve shape, such as egg shaped.
Circular channel 124 is an elliptically shaped channel, where its circular shape is a special case of an ellipse. Circular channel 124 includes a rounded closed curve structure having rounded corners or no corners, such that it does not have sharp or angled comers. Circular channel 124 has a channel length
Lc that is the distance from the exterior side 134 of circular channel 124 to the interior side 36 of circular channel 124. The width W of circular channel 124 is the distance around circular channel 124 measured at the midpoint of the channel length Lc. In other examples, channel 124 can be another elliptical shape, such as an oval, and/or another rounded closed curve shape, such as egg shaped.
Figure 6 is a top-view diagram illustrating one example of an EPROM cell 140 that includes a floating gate 142 having multiple straight sides 142a-142d and rounded corners 142e-142h, and a channel 144 having multiple straight sides 144a-144d and rounded corners 144e-144h. Channel 144 is situated under floating gate 142 and indicated by dotted lines. Also, some of the layers of EPROM cell 140, such as metal layers, are not shown for clarity. EPROM cell 140 is similar to EPROM cell 90 of Figure 4. In one example, a cross- section of EPROM cell 140 taken along the line B-B is similar to the cross- section of EPROM cell 90 of Figure 4.
EPROM cell 140 includes floating gate 142, channel 144, a drain 146, and a source 148. Channel 144 is situated under floating gate 142. Channel 144 surrounds drain 146 and is situated between drain 146 and source 148. Source 148 surrounds channel 144. In one example, floating gate 142 is polysilicon, channel 144 is a p channel region, drain 146 is an N+ region, and source 148 is an N+ region.
Floating gate 142 has four straight sides 142a-142d and four rounded corners 142e-142h. Floating gate 142 includes a rounded closed curve structure having rounded corners 142e-142h, such that it does not have sharp or angled corners. Floating gate 142 has a floating gate length Lfg that is the distance from the exterior side 150 of floating gate 142 to the interior side 152 of floating gate 142. The width W of floating gate 142 is the distance around floating gate 142 measured at the midpoint of the floating gate length Lfg. In other examples, floating gate 142 can have a different number of straight sides, such as two or three straight sides or more than four straight sides, and a different number of rounded corners, such as two or three rounded corners or more than four rounded corners.
Channel 144 has four straight sides 144a-144d and four rounded corners 144e-144h. Channel 144 includes a rounded closed curve structure having rounded corners 144e-144h, such that it does not have sharp or angled corners. Channel 144 has a channel length Lc that is the distance from the exterior side 154 of channel 144 to the interior side 156 of channel 144. The width W of channel 144 is the distance around channel 144 measured at the midpoint of the channel length Lc. In other examples, channel 144 can have a different number of straight sides, such as two or three straight sides or more than four straight sides, and a different number of rounded corners, such as two or three rounded corners or more than four rounded corners.
Figure 7 is a top-view diagram illustrating one example of an EPROM cell 160 that includes a floating gate 162 having multiple straight sides 162a and 162b, a rounded top 162c, and a rounded bottom 162d, and a channel 164 having multiple straight sides 164a and 164b, a rounded top 164c, and a rounded bottom 164d. Channel 164 is situated under floating gate 162 and indicated by dotted lines. Also, some of the layers of EPROM cell 160, such as metal layers, are not shown for clarity. EPROM cell 160 is similar to EPROM cell 90 of Figure 4. In one example, a cross-section of EPROM cell 160 taken along the line C-C is similar to the cross-section of EPROM cell 90 of Figure 4.
EPROM cell 160 includes floating gate 162, channel 164, a drain 166, and a source 168. Channel 164 is situated under floating gate 162. Channel 164 surrounds drain 166 and is situated between drain 166 and source 168. Source 168 surrounds channel 164. In one example, floating gate 162 is polysilicon, channel 164 is a p channel region, drain 166 is an N+ region, and source 168 is an N+ region.
Floating gate 162 has two straight sides 162a and 162b, a rounded top 162c, and a rounded bottom 162d. Floating gate 162 includes a rounded closed curve structure having a rounded top 162c and a rounded bottom 162d, such that it does not have sharp or angled corners. Floating gate 162 has a floating gate length Lfg that is the distance from the exterior side 170 of floating gate 162 to the interior side 172 of floating gate 162. The width W of floating gate
162 is the distance around floating gate 162 measured at the midpoint of the floating gate length Lfg.
Channel 164 has two straight sides 164a and 164b, a rounded top 164c, and a rounded bottom 164d. Channel 164 includes a rounded closed curve structure having a rounded top 164c and a rounded bottom 164d, such that it does not have sharp or angled corners. Channel 164 has a channel length Lc that is the distance from the exterior side 174 of channel 164 to the interior side 176 of channel 164. The width W of channel 164 is the distance around channel 164 measured at the midpoint of the channel length Lc.
The rounded closed curve floating gates and channels, shown in Figures
5-7, improve programming efficiency over a rectangular channel and rectangular floating gate EPROM cell. The rounded closed curve floating gates and channels increase the uniformity of the channel length and the uniformity of the floating gate length and remove "corner effects' associated with a rectangular channel and rectangular floating gate EPROM cell. Making the channel length and floating gate length more uniform and removing "corner effects" leads to more uniform and efficient generation of hot electrons during programming. Also, the rounded channels and the rounded floating gates provide a
preprogramming EPROM ratio that is more centered around a specified value and reduced as compared to the preprogramming EPROM ratio provided via a rectangular channel and rectangular floating gate EPROM cell. In one example, programming efficiency is improved twenty percent over a rectangular channel and rectangular floating gate EPROM cell.
Figure 8 is a top-view diagram illustrating one example of an EPROM cell 180 that includes a rectangular floating gate 182 having multiple straight sides 182a-182d and sharp angled corners 182e-182h, and a rectangular channel 184 having multiple straight sides 184a-184d and sharp angled corners 184e- 184h. Channel 184 is situated under floating gate 182 and indicated by dotted lines. Also, some of the layers of EPROM cell 180, such as metal layers, are not shown for clarity.
EPROM cell 180 includes floating gate 182, channel 184, a drain 186, and a source 188. Channel 184 is situated under floating gate 182. Channel
184 surrounds drain 186 and is situated between drain 186 and source 188. Source 188 surrounds channel 184. In one example, floating gate 182 is polysilicon, channel 184 is a p channel region, drain 186 is an N+ region, and source 188 is an N+ region.
Floating gate 182 has four straight sides 182a-182d and four sharp angled corners 182e-182h. Floating gate 182 does not include a rounded closed curve structure and is not a rounded closed curve floating gate.
Channel 184 has four straight sides 184a-184d and four sharp angled corners 184e-184h. Channel 184 does not include a rounded closed curve structure and is not a rounded closed curve channel.
Figure 9 is a graph 200 illustrating EPROM resistance ratios of EPROM cells having circular floating gates and channels, such as EPROM cell 120 of Figure 5, and EPROM cells having rectangular floating gates and channels, such as EPROM cell 180 of Figure 8. On the x-axis at 202, plots and histograms for EPROM cells having circular floating gates and channels, referred to as circular EPROM cells, are identified with a suffix of Cir, and plots and histograms for EPROM cells having rectangular floating gates and channels, referred to as rectangular EPROM cells, are identified with a suffix of Rect. The y-axis at 204 plots resistance ratios, where each ratio is a measured resistance value to a reference unprogrammed resistance value. Statistics for the graphed resistance ratios are shown in Table 1.
Resistance ratios of unprogrammed rectangular EPROM cells
(Unprog_Rect) are plotted at 206 in a type of box and whisker plot and at 208 in a histogram, and the resistance ratios of unprogrammed circular EPROM cells
(Unprog_Cir) are plotted at 210 in a type of box and whisker plot and at 212 in a histogram. The resistance ratios of unprogrammed circular EPROM cells are generally less than the resistance ratios of unprogrammed rectangular EPROM cells, where the mean unprogrammed resistance ratio decreases from 1.08644 for the rectangular EPROM cells to 1.03602 for the circular EPROM cells. Thus, the mean resistance value of the unprogrammed circular EPROM cells is much closer to and more centered around the reference unprogrammed resistance value, as compared to the mean resistance value of the unprogrammed rectangular EPROM cells. Also, even though the standard deviation of resistance ratios increases from .013223 for the rectangular EPROM cells to .021055 for the circular EPROM cells, the resistance ratio distribution of the unprogrammed circular EPROM cells is further away from the bin 6 test failure limit at 214, referred to as an unprogrammed bit consistency failure, as compared to the resistance ratio distribution of the unprogrammed rectangular EPROM cells.
The resistance ratios of programmed rectangular EPROM cells
(Prog_Rect) are plotted at 216 in a type of box and whisker plot and at 218 in a histogram, and the resistance ratios of programmed circular EPROM cells (Prog_Cir) are plotted at 220 in a type of box and whisker plot and at 222 in a histogram. The resistance ratios of programmed circular EPROM cells are generally higher than the resistance ratios of programmed rectangular EPROM cells, where the mean programmed resistance ratio increases from 1.84717 for the rectangular EPROM cells to 2.04736 for the circular EPROM cells. Thus, the mean resistance value of the programmed circular EPROM cells is more than twice the reference unprogrammed resistance value. Also, the standard deviation of the resistance ratios decreases from .117780 for the rectangular EPROM cells to .045884 for the circular EPROM cells. The resistance ratio distribution of the programmed circular EPROM cells is further away from the bin 7 test failure limit at 224, referred to as a stubborn bit failure, than the resistance ratio distribution of the programmed rectangular EPROM cells.
The spread between unprogrammed resistance values in circular
EPROM cells at 210 and 212 and programmed resistance values in circular
EPROM cells at 220 and 222 is greater than the spread between unprogrammed resistance values in rectangular EPROM cells at 206 and 208 and programmed resistance values in rectangular EPROM cells at 216 and 218. The larger spread improves the programming efficiency of circular EPROM cells over the programming efficiency of rectangular EPROM cells. This improved programming efficiency improves programming reliability and provides opportunities for new EPROM applications. In one example, programming efficiency increases 20%.
Also, the robustness of the fabrication process is improved by building EPROM cells having rounded closed curve floating gates and channels, instead of EPROM cells having rectangular floating gates and channels. The rounded closed curve floating gates and channels increase the uniformity of the channel length and the uniformity of the floating gate length and remove "corner effects' associated with a rectangular channel and rectangular floating gate EPROM cell. Making the channel length and the floating gate length more uniform and removing "corner effects" leads to more uniform and efficient generation of hot electrons during programming, as shown by increased programmability. Also, photolithography x-y astigmatism results in gate length variations in rectangular EPROM cells that contribute to reductions in programming efficiency and increased yield losses. The rounded closed curve floating gates and channels provide more uniform gate lengths by eliminating photolithography x-y
astigmatism.
Figures 10 and 11 are graphs illustrating resistance ratios in EPROM cells manufactured using a process having the layers of Figure 3 and providing the EPROM cell 90 of Figure 4.
Figure 10 is a graph 300 illustrating unprogrammed resistance ratios for circular and rectangular EPROM cells. Resistance ratios are graphed as percentages along the x-axis at 302 versus the number of units along the y-axis at 304. Each of the resistance ratios is a measured unprogrammed resistance value divided by a reference unprogrammed resistance value.
Unprogrammed resistance ratios of circular EPROM cells at 306 are centered around a percentage of about 104% and unprogrammed resistance
ratios of rectangular EPROM cells at 308 are centered around a percentage of about 109%. This is a reduction in unprogrammed resistance of about 5% for circular EPROM cells over rectangular EPROM cells. The distribution of unprogrammed resistance ratios of circular EPROM cells at 306 is wider than the distribution of the unprogrammed resistance ratios of rectangular EPROM cells at 308, but most of the unprogrammed resistance ratios of circular EPROM cells at 306 are smaller than most of the unprogrammed resistance ratios of rectangular EPROM cells at 308. The centered unprogrammed resistance value of circular EPROM cells at 306 is much closer to and more centered around the reference unprogrammed resistance value, as compared to the centered unprogrammed resistance value of rectangular EPROM cells 308.
Figure 11 is a graph 400 illustrating programmed resistance ratios for circular and rectangular EPROM cells. Resistance ratios are graphed as percentages along the x-axis at 402 versus the number of units along the y-axis at 404. Each of the resistance ratios is a measured programmed resistance value divided by a reference unprogrammed resistance value.
Programmed resistance ratios of circular EPROM cells at 406 are centered around a percentage of about 205% and programmed resistance ratios of rectangular EPROM cells at 408 are centered around a percentage of about 185%. This is an increase of 20% for circular EPROM cells over rectangular EPROM cells, where the centered resistance value of the programmed circular EPROM cells at 406 is more than twice the reference unprogrammed resistance value. The distribution of programmed resistance ratios of circular EPROM cells at 406 is narrower than the distribution of programmed resistance ratios of rectangular EPROM cells at 408, and most of the programmed resistance ratios of circular EPROM cells at 406 are larger than most of the programmed resistance ratios of rectangular EPROM cells at 408. Thus, the centered programmed resistance value of circular EPROM cells at 406 is further away from the reference unprogrammed resistance value, as compared to the centered programmed resistance value of rectangular EPROM cells 408.
The spread between unprogrammed resistance values in circular
EPROM cells at 306 and programmed resistance values in circular EPROM cells at 406 is greater than the spread between unprogrammed resistance values in rectangular EPROM cells at 308 and programmed resistance values in rectangular EPROM cells at 408. The larger spread improves the programming efficiency of circular EPROM cells over the programming efficiency of
rectangular EPROM cells. This improved programming efficiency improves programming reliability and provides opportunities for new EPROM applications. In one example, programming efficiency increases 20%.
Figures 12 and 13 are graphs illustrating resistance ratios in EPROM cells manufactured using another suitable process.
Figure 12 is a graph 500 illustrating unprogrammed resistance ratios for circular and rectangular EPROM cells. Resistance ratios are graphed as percentages along the x-axis at 502 versus the number of units along the y-axis at 504. Each of the resistance ratios is a measured unprogrammed resistance value divided by a reference unprogrammed resistance value.
Unprogrammed resistance ratios of circular EPROM cells at 506 are centered around a percentage of about 107 or 108% and unprogrammed resistance ratios of rectangular EPROM cells at 508 are centered around a percentage of about 112%. This is a reduction in unprogrammed resistance of about 4 or 5% for circular EPROM cells over rectangular EPROM cells. The distribution of unprogrammed resistance ratios of circular EPROM cells at 506 is wider than the distribution of the unprogrammed resistance ratios of rectangular EPROM cells at 508, but most of the unprogrammed resistance ratios of circular EPROM cells at 506 are smaller than most of the unprogrammed resistance ratios of rectangular EPROM cells at 508. The centered unprogrammed resistance value of circular EPROM cells at 506 is closer to and more centered around the reference unprogrammed resistance value, as compared to the centered unprogrammed resistance value of rectangular EPROM cells 308.
Figure 13 is a graph 600 illustrating programmed resistance ratios for circular and rectangular EPROM cells. Resistance ratios are graphed as percentages along the x-axis at 602 versus the number of units along the y-axis
at 604. Each of the resistance ratios is a measured programmed resistance value divided by a reference unprogrammed resistance value.
Programmed resistance ratios of circular EPROM cells at 606 are centered around a percentage of about 170% and programmed resistance ratios of rectangular EPROM cells at 608 are centered around a percentage of about 158%. This is an increase of 12% for circular EPROM cells over rectangular EPROM cells, where the centered resistance value of the
programmed circular EPROM cells at 606 is about 1.7 times the reference unprogrammed resistance value. The distribution of programmed resistance ratios of circular EPROM cells at 606 is similar to the distribution of programmed resistance ratios of rectangular EPROM cells at 608. Thus, the centered programmed resistance value of circular EPROM cells at 606 is further away from the reference unprogrammed resistance value, as compared to the centered programmed resistance value of rectangular EPROM cells 608.
The spread between unprogrammed resistance values in circular
EPROM cells at 506 and programmed resistance values in circular EPROM cells at 606 is greater than the spread between unprogrammed resistance values in rectangular EPROM cells at 508 and programmed resistance values in rectangular EPROM cells at 608. The larger spread improves the programming efficiency of circular EPROM cells over the programming efficiency of
rectangular EPROM cells. This improved programming efficiency improves programming reliability and provides opportunities for new EPROM applications.
Although specific examples have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
What is Claimed is:
Claims
1. A memory cell, comprising:
a drain;
a channel that surrounds the drain and includes a first rounded closed curve structure around the drain; and
a floating gate that is situated over the channel and includes a second rounded closed curve structure over the channel.
2. The memory cell of claim 1 , wherein the channel is elliptically shaped and the floating gate is elliptically shaped.
3. The memory cell of claim 2, wherein the channel is circular and the floating gate is circular.
4. The memory cell of claim 1 , wherein the channel has multiple straight sides and at least one exterior rounded corner.
5. The memory cell of claim 1 , comprising a silicon dioxide layer between the channel and the floating gate.
6. The memory cell of claim 1 , wherein the first rounded closed curve structure increases uniformity of the length of the channel throughout the width of the channel relative to a rectangular channel and the second rounded closed curve structure increases uniformity of the length of the floating gate throughout the width of the floating gate relative to a rectangular floating gate.
7. The memory cell of claim 1 , comprising a source that surrounds the channel.
8. An EPROM array, comprising:
EPROM cells disposed in rows and columns, wherein each EPROM cell includes:
a source;
a drain having a top and a bottom and sides between the top and the bottom;
a channel that surrounds the drain on the sides, wherein the channel includes a first closed curve structure and a substantially uniform channel length throughout the width of the channel; and
a floating gate over the channel, wherein the floating gate includes a second closed curve structure and a substantially uniform floating gate length throughtout the width of the floating gate.
9. The EPROM array of claim 8, wherein in each EPROM cell the channel is situated between the source and the drain.
10. The EPROM array of claim 9, wherein in each EPROM cell the source surrounds the channel. 1. The EPROM array of claim 8, wherein in each EPROM cell the channel is elliptically shaped and the floating gate is elliptically shaped.
12. The EPROM array of claim 8, wherein in each EPROM cell the first and second closed curve structures improve programming efficiency over a rectangular channel and rectangular floating gate EPROM cell.
13. A method of programming an EPROM cell, comprising:
providing a drain;
providing a channel having a first rounded closed curve structure that surrounds the drain; and
injecting hot carriers into a floating gate having a second rounded close curve structure situated over the channel, wherein the channel and the floating
gate improve programming efficiency over a rectangular channel and
rectangular floating gate EPROM cell.
14. The method of claim 13, wherein programming efficiency is improved twenty percent over the rectangular channel and rectangular floating gate EPROM cell.
15. The method of claim 13, wherein the channel and the floating gate provide a preprogramming EPROM ratio that is more centered around a specified value and reduced as compared to the preprogramming EPROM ratio provided via the rectangular channel and rectangular floating gate EPROM cell.
Priority Applications (5)
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CN201180069313.7A CN103503141A (en) | 2011-03-15 | 2011-03-15 | Memory cell having closed curve structure |
PCT/US2011/028537 WO2012125162A1 (en) | 2011-03-15 | 2011-03-15 | Memory cell having closed curve structure |
EP11860807.4A EP2686882A4 (en) | 2011-03-15 | 2011-03-15 | Memory cell having closed curve structure |
US14/000,620 US9524780B2 (en) | 2011-03-15 | 2011-03-15 | Memory cell having closed curve structure |
US15/352,449 US10504910B2 (en) | 2011-03-15 | 2016-11-15 | Memory cell having closed curve structure |
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PCT/US2011/028537 WO2012125162A1 (en) | 2011-03-15 | 2011-03-15 | Memory cell having closed curve structure |
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US14/000,620 A-371-Of-International US9524780B2 (en) | 2011-03-15 | 2011-03-15 | Memory cell having closed curve structure |
US15/352,449 Continuation US10504910B2 (en) | 2011-03-15 | 2016-11-15 | Memory cell having closed curve structure |
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EP2834843A4 (en) * | 2012-10-31 | 2016-03-09 | Hewlett Packard Development Co | Memory cell that prevents charge loss |
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EP2815431B1 (en) * | 2012-04-30 | 2020-01-15 | Hewlett-Packard Development Company, L.P. | Device including active floating gate region area that is smaller than channel area |
US9919517B2 (en) * | 2014-01-17 | 2018-03-20 | Hewlett-Packard Development Company, L.P. | Addressing an EPROM on a printhead |
US9953991B2 (en) * | 2014-03-14 | 2018-04-24 | Hewlett-Packard Development Company, L.P. | EPROM cell with modified floating gate |
US9564243B2 (en) * | 2014-04-23 | 2017-02-07 | Globalfoundries Singapore Pte. Ltd. | Equivalent fuse circuit for a one-time programmable read-only memory array |
US11758717B2 (en) * | 2021-05-06 | 2023-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor memory devices with one-sided staircase profiles and methods of manufacturing thereof |
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Also Published As
Publication number | Publication date |
---|---|
EP2686882A4 (en) | 2014-11-12 |
US20170062449A1 (en) | 2017-03-02 |
US20130329498A1 (en) | 2013-12-12 |
US10504910B2 (en) | 2019-12-10 |
US9524780B2 (en) | 2016-12-20 |
EP2686882A1 (en) | 2014-01-22 |
CN103503141A (en) | 2014-01-08 |
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