WO2012121650A1 - Semiconductor element - Google Patents

Semiconductor element Download PDF

Info

Publication number
WO2012121650A1
WO2012121650A1 PCT/SE2012/050234 SE2012050234W WO2012121650A1 WO 2012121650 A1 WO2012121650 A1 WO 2012121650A1 SE 2012050234 W SE2012050234 W SE 2012050234W WO 2012121650 A1 WO2012121650 A1 WO 2012121650A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
jfet
conductivity type
dual
substrate
Prior art date
Application number
PCT/SE2012/050234
Other languages
French (fr)
Inventor
Klas-Håkan Eklund
Lars VESTLING
Original Assignee
K.Eklund Innovation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by K.Eklund Innovation filed Critical K.Eklund Innovation
Priority to EP12754805.5A priority Critical patent/EP2684217A4/en
Priority to US14/003,530 priority patent/US8969925B2/en
Publication of WO2012121650A1 publication Critical patent/WO2012121650A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Definitions

  • the present invention relates to a semiconductor device, especially a semiconductor device for use in RF-LDMOS devices for integration into standard CMOS technologies so as to enable a cost-effective on-chip design of multi-band PAs for single-chip solutions, e.g. WLAN applications.
  • FIG. 1 which is FIG. 1 from US 5, 146, 298, is shown the above mentioned low voltage MOS device in series with 2 JFETs with common source and drain, and where now region 11 has been divided into regions 11A, 11B and 11C.
  • the region marked 11A is part of pocket 11, close to the source region 13.
  • 11B is part of the pocket 11 under region 15, and 11C is part of the pocket 11 close to the drain contact region 16.
  • the on-resistance and current will be determined mostly by the spreading resistances in region 11A and region llC.
  • the length of the path is around 2.5 ⁇ (depth of layer 15 is typically ⁇ ) as compared to along the surface 0.5 ⁇ , region 14, the n-top, which will increase the on- resistance .
  • region 11A is made as a very active vertical JFET with length 0.5 ⁇ (depth in the figure of region 15 is reduced to 0.5 ⁇ ) , and similar in length at the horizontal JFET at the surface.
  • a device fulfilling this is characterised in that a vertical JFET gate region is arranged essentially enclosed by the body region, a vertical JFET channel region being arranged between the vertical JFET gate region essentially enclosed by the body region and a dual JFET gate region, a reduced drain resistance region being arranged between said dual JFET gate region and the drain contact region, and a buried pocket being located under part of said body region, under said dual JFET gate region and under said vertical JFET channel and reduced drain resistance regions.
  • FIG.l shows, as mentioned above, a drawing from the prior art mentioned above, and in which region 11 has been divided into regions 11A, 11B and 11C, for explaining the difference in relation to the present invention.
  • FIG. 2 is shown a cross-sectional view of a MOS transistor according to the present invention, with an extended drain region which is a parallel combination of a lateral double- sided JFET or optionally single-sided JFET and a vertical double-sided JFET formed on a semiconductor die 21.
  • FIG. 3 shows a circuit diagram for the MOS transistor with an extended drain which is a parallel combination of a lateral double-sided JFET or optionally single-sided JFET and a ver ⁇ tical double-sided JFET shown in FIG. 2.
  • the present invention relates to a practical implementation of a semiconductor device, in which a substrate 22 of a first conductivity type is, for example, made of p-type material, doped with lxlO 16 atoms per cm 3 .
  • a typical depth of substrate 22 is 100 ⁇ .
  • a buried pocket 23 of a second conductivity type, for example n-type material, doped at 5xl0 13 atoms per cm 2 is arranged in the substrate 22.
  • the buried pocket 23 extends to a depth of, for example, 1 ⁇ below a surface 24 of the die 21.
  • the doping levels and dimensions given here and below are for a device with a breakdown voltage of ap- proximately 10 V.
  • a body region 25 of the first conductivity type for example p-type material, doped at lxlO 18 atoms per cm 3 .
  • the body region 25 typically extends to a depth of 0.5 ⁇ below the surface 24 of the die 21.
  • a source contact region 26 of the second conductivity type, for example n-type material, doped at between 10 and 10 atoms per cm 3 is located within the body region 25.
  • the source contact region 26 extends, for example, to a depth of 0.2 ⁇ below the surface 24 of the die 21.
  • a drain contact region 27 of the second conductivity type, for example n-type material, doped at between 10 and 10 atoms per cm 3 is arranged adjoined to the surface 24 but separated from the body region 25.
  • the drain contact region 27 extends, for example, to a depth of 0.2 ⁇ below the surface 24 of the die 21.
  • a source contact 28 is placed on the surface 24 in electrical contact with the body region 25 and a source contact region portion of the source contact region 26.
  • a drain contact 29 is placed on the surface 24 in electrical contact with the drain contact region 27.
  • An insulating layer 30 is placed on the surface 24 of the die 21.
  • a gate contact 31 is placed on the insulating layer 30 over a channel region portion of the body region 25. Partly in the body region 25 a vertical JFET gate region 32 of the first conductivity type is located. Between the body region 25 and region 27 is a dual JFET gate region 33 of the first conductivity type located.
  • the vertical JFET gate re ⁇ gion 32 and the dual JFET gate region 33 is, for example, p- type material both doped at lxlO 13 atoms per cm 2 .
  • the vertical JFET gate region 32 and the dual JFET gate region 33 extend downwards from the surface 24 to a depth of, for example, 0.5 ⁇ .
  • the dual JFET gate region 33 is connected to ground at the surface 24 in a plane not shown in FIG. 2.
  • a vertical JFET channel region 34 of the second conductivity type located between vertical JFET gate region 32 and the dual JFET gate region 33.
  • a reduced drain resis- tance region 35 of the second conductivity type located between the dual JFET gate region 33 and the drain contact region 27 .
  • the vertical JFET channel region 34 and the reduced drain resis ⁇ tance region 35 is, for example, n-type material both doped at lxlO 17 atoms per cm 3 .
  • the vertical JFET channel region 34 and reduced drain resistance region 35 extend downwards from the surface 24 to a depth of, for example, 0.5 ⁇ .
  • the later- al JFET channel region 36 is, for example, n-type material doped at 6xl0 12 atoms per cm 2 .
  • the lateral JFET channel region 36 extends downwards from the surface 24 to a depth of, for example, 0.2 ⁇ .
  • a distance 37 between an edge of the body region 25 and an edge of the drain contact region 27 is, for example 1 ⁇ .
  • a symmetry line 39 is used for placing a second half of the transistor in a mirror image to the first half shown in FIG . 2.
  • a lateral JFET gate region 38 of the first conductivity type located above the dual JFET gate region 33 and the lateral JFET chan- nel region 36 .
  • the lateral JFET gate region 38 is, for example, p-type material doped at 3xl0 12 atoms per cm 2 .
  • the lateral JFET gate region 38 extends downwards from the surface 24 to a depth of, for example, 0.05 ⁇ .
  • the lat- eral JFET gate region 38 is electrically connected to ground with a contact at the surface 24 or in a plane not shown in FIG. 2.
  • the lateral JFET gate region 38 and the dual JFET gate region 33 may also be grounded in the plane shown by extending the body region 25 to make contact with JFET gate regions 33 and 38, in given intervals regularly spaced from each other.
  • the lateral JFET gate region 38 is optional and if it is removed the lateral JFET channel region 36 is, for example, doped at 3xl0 12 atoms per cm 2 .
  • the device shown in FIG. 2 may also function as a bipolar transistor with the source contact region 26 functioning as an emitter, the body region 25 functioning as a base and the vertical JFET channel region 34, the lateral JFET channel region 36, the buried pocket 23, the reduced drain resistance region 35 and drain contact region 27 functioning as an extended collector.
  • FIG. 3 shows a circuit diagram for a MOS transistor with an extended drain which is a parallel combination of a lateral double-sided JFET or optionally single-sided JFET and a ver ⁇ tical double-sided JFET shown in FIG. 2.
  • the MOS transistor 40 is controlled by a gate contact 42. Current through the MOS transistor 42 travels from a source contact 41 through the MOS transistor 40, through the extended drain region to the drain contact 46.
  • the extended drain region includes a parallel combination of a lateral double-sided JFET 43 and a vertical double-sided JFET 44 in series with a resistor 45.
  • the gate of the lateral double-sided JFET 43 is connected to ground 47 and the gate of the vertical double-sided JFET 44 is connected to ground 48.
  • the source contact 41 and the gate contact 42 of the MOS transistor 40 corresponds to the source contact region 26 and the gate contact 31 in FIG. 2.
  • the channel of the lateral double-sided JFET 43 corresponds to the lateral JFET channel region 36 in FIG. 2.
  • the grounded gate 47 of the lateral double-sided JFET 43 corresponds to the dual JFET gate region 33 and the lateral JFET gate region 38.
  • the channel of the vertical double-sided JFET 44 corresponds to the vertical JFET channel region 34 in FIG. 2.
  • the grounded gate 48 of the vertical double-sided JFET 44 corresponds to the dual JFET gate region 33 and the vertical JFET gate region 32.
  • the resistor 45 corresponds to the buried pocket 23 and the re ⁇ cuted drain resistance region 35 in FIG. 2.
  • a power device implemented in a 65nm CMOS technology with gate oxide thickness of 5nm and channel length around 0.2 ⁇ will achieve an on- resistance of around 1 ohmmm and maximum drain current above 1 A/mm which is at least 2-3 times better than presently shown and should meet the performance specification for e.g. an integrated WLAN solution in the frequency range of 2-5 GHz.
  • an integrated WLAN solution in the frequency range of 2-5 GHz.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A semiconductor device comprising a substrate (22), a body region (25) adjoining the surface (24) of the substrate (22), a source contact region (26) within the body region (25), a drain contact region (27) adjoining the surface (24) of the substrate (22) and being separated from the body region (25), a dual JFET gate region (33) located between the body region (25) and the drain contact region (27),and a lateral JFET channel region (36) adjoining the surface (24) of the substrate (22) and which is located between the body region (25) and the drain contact region (27), wherein a vertical JFET gate region (32) is arranged essentially enclosed by the body region (25),a vertical JFET channel region (34) being arranged between the vertical JFET gate region (32) essentially enclosed by the body region (25) and said dual JFET gate region (33), a reduced drain resistance region (35) being arranged between said dual JFET gate region (33) and the drain contact region (27), and a buried pocket (23) being located under part of said body region (25), under said dual JFET gate region (33) and under said vertical JFET channel and reduced drain resistance regions (34, 35).

Description

Semiconductor element
The present invention relates to a semiconductor device, especially a semiconductor device for use in RF-LDMOS devices for integration into standard CMOS technologies so as to enable a cost-effective on-chip design of multi-band PAs for single-chip solutions, e.g. WLAN applications.
The strong trend toward integration in hand held communica- tion devices for cost and size advantages has started an intensive research effort on the implementation of high power and high efficiency power amplifiers in modern CMOS technolo¬ gies. The main workhorse up to date has been using the bipo¬ lar device in 0.13μπι BiCMOS technologies. Advanced standard CMOS technologies at the 65nm/45nm node, otherwise suitable for single chip solutions e.g. WLAN, lack high voltage (around 10V) devices with good linearity and efficiency re¬ quired for on-chip power amplifiers in the frequency range 2- 5 GHz.
In US patent No. 5,146,298 a high voltage LDMOS device is implemented as a low voltage MOS device in series with 2 JFETs with common source and drain. This type of device works well as long as the extended drift region is longer than a couple of μπι and with a breakthrough voltage in the region of 30-800V. [R.Y. Su, F.J. Yang, J.L. Tsay, C.C. Cheng, R.S. Liou and H.C. Tuan, "State-of-the-art Device in High Voltage Power IC with Lowest On-State Resistance", IEEE International Electron Devices Meeting (IEDM), pp. 492-495, 2010.]
In FIG. 1, which is FIG. 1 from US 5, 146, 298, is shown the above mentioned low voltage MOS device in series with 2 JFETs with common source and drain, and where now region 11 has been divided into regions 11A, 11B and 11C. The region marked 11A is part of pocket 11, close to the source region 13. 11B is part of the pocket 11 under region 15, and 11C is part of the pocket 11 close to the drain contact region 16. For a BV of around 10V where the distance 6 between gate and drain is around 0.5μπι the on-resistance and current will be determined mostly by the spreading resistances in region 11A and region llC. Further as the current goes from source to drain through layer 11, the length of the path is around 2.5μπι (depth of layer 15 is typically Ιμπι) as compared to along the surface 0.5μπι, region 14, the n-top, which will increase the on- resistance .
To overcome this problem a new device is proposed where re¬ gion 11B and region 11C are made very highly conductive and region 11A is made as a very active vertical JFET with length 0.5μπι (depth in the figure of region 15 is reduced to 0.5μπι) , and similar in length at the horizontal JFET at the surface.
A device fulfilling this is characterised in that a vertical JFET gate region is arranged essentially enclosed by the body region, a vertical JFET channel region being arranged between the vertical JFET gate region essentially enclosed by the body region and a dual JFET gate region, a reduced drain resistance region being arranged between said dual JFET gate region and the drain contact region, and a buried pocket being located under part of said body region, under said dual JFET gate region and under said vertical JFET channel and reduced drain resistance regions. The invention will now be described further with the help of non-limiting embodiments shown on the enclosed drawings.
FIG.l shows, as mentioned above, a drawing from the prior art mentioned above, and in which region 11 has been divided into regions 11A, 11B and 11C, for explaining the difference in relation to the present invention.
In FIG. 2 is shown a cross-sectional view of a MOS transistor according to the present invention, with an extended drain region which is a parallel combination of a lateral double- sided JFET or optionally single-sided JFET and a vertical double-sided JFET formed on a semiconductor die 21. FIG. 3 shows a circuit diagram for the MOS transistor with an extended drain which is a parallel combination of a lateral double-sided JFET or optionally single-sided JFET and a ver¬ tical double-sided JFET shown in FIG. 2. The present invention relates to a practical implementation of a semiconductor device, in which a substrate 22 of a first conductivity type is, for example, made of p-type material, doped with lxlO16 atoms per cm3. A typical depth of substrate 22 is 100 μπι. A buried pocket 23 of a second conductivity type, for example n-type material, doped at 5xl013 atoms per cm2 is arranged in the substrate 22. The buried pocket 23 extends to a depth of, for example, 1 μπι below a surface 24 of the die 21. The doping levels and dimensions given here and below are for a device with a breakdown voltage of ap- proximately 10 V.
Partly touching the pocket 23 is a body region 25 of the first conductivity type, for example p-type material, doped at lxlO18 atoms per cm3. The body region 25 typically extends to a depth of 0.5 μπι below the surface 24 of the die 21. A source contact region 26 of the second conductivity type, for example n-type material, doped at between 10 and 10 atoms per cm3 is located within the body region 25. The source contact region 26 extends, for example, to a depth of 0.2 μπι below the surface 24 of the die 21.
A drain contact region 27 of the second conductivity type, for example n-type material, doped at between 10 and 10 atoms per cm3 is arranged adjoined to the surface 24 but separated from the body region 25. The drain contact region 27 extends, for example, to a depth of 0.2 μπι below the surface 24 of the die 21.
A source contact 28 is placed on the surface 24 in electrical contact with the body region 25 and a source contact region portion of the source contact region 26. A drain contact 29 is placed on the surface 24 in electrical contact with the drain contact region 27. An insulating layer 30 is placed on the surface 24 of the die 21. A gate contact 31 is placed on the insulating layer 30 over a channel region portion of the body region 25. Partly in the body region 25 a vertical JFET gate region 32 of the first conductivity type is located. Between the body region 25 and region 27 is a dual JFET gate region 33 of the first conductivity type located. The vertical JFET gate re¬ gion 32 and the dual JFET gate region 33 is, for example, p- type material both doped at lxlO13 atoms per cm2. The vertical JFET gate region 32 and the dual JFET gate region 33 extend downwards from the surface 24 to a depth of, for example, 0.5 μπι. The dual JFET gate region 33 is connected to ground at the surface 24 in a plane not shown in FIG. 2.
Between vertical JFET gate region 32 and the dual JFET gate region 33 is a vertical JFET channel region 34 of the second conductivity type located. Between the dual JFET gate region 33 and the drain contact region 27 is a reduced drain resis- tance region 35 of the second conductivity type located. The vertical JFET channel region 34 and the reduced drain resis¬ tance region 35 is, for example, n-type material both doped at lxlO17 atoms per cm3. The vertical JFET channel region 34 and reduced drain resistance region 35 extend downwards from the surface 24 to a depth of, for example, 0.5 μπι.
Above the dual JFET gate region 33 is a lateral JFET channel region 36 of the second conductivity type located. The later- al JFET channel region 36 is, for example, n-type material doped at 6xl012 atoms per cm2. The lateral JFET channel region 36 extends downwards from the surface 24 to a depth of, for example, 0.2 μπι. A distance 37 between an edge of the body region 25 and an edge of the drain contact region 27 is, for example 1 μπι. A symmetry line 39 is used for placing a second half of the transistor in a mirror image to the first half shown in FIG . 2.
Above the dual JFET gate region 33 and the lateral JFET chan- nel region 36 is a lateral JFET gate region 38 of the first conductivity type located. The lateral JFET gate region 38 is, for example, p-type material doped at 3xl012 atoms per cm2. The lateral JFET gate region 38 extends downwards from the surface 24 to a depth of, for example, 0.05 μπι. The lat- eral JFET gate region 38 is electrically connected to ground with a contact at the surface 24 or in a plane not shown in FIG. 2. The lateral JFET gate region 38 and the dual JFET gate region 33 may also be grounded in the plane shown by extending the body region 25 to make contact with JFET gate regions 33 and 38, in given intervals regularly spaced from each other. The lateral JFET gate region 38 is optional and if it is removed the lateral JFET channel region 36 is, for example, doped at 3xl012 atoms per cm2. The device shown in FIG. 2 may also function as a bipolar transistor with the source contact region 26 functioning as an emitter, the body region 25 functioning as a base and the vertical JFET channel region 34, the lateral JFET channel region 36, the buried pocket 23, the reduced drain resistance region 35 and drain contact region 27 functioning as an extended collector.
FIG. 3 shows a circuit diagram for a MOS transistor with an extended drain which is a parallel combination of a lateral double-sided JFET or optionally single-sided JFET and a ver¬ tical double-sided JFET shown in FIG. 2. The MOS transistor 40 is controlled by a gate contact 42. Current through the MOS transistor 42 travels from a source contact 41 through the MOS transistor 40, through the extended drain region to the drain contact 46. The extended drain region includes a parallel combination of a lateral double-sided JFET 43 and a vertical double-sided JFET 44 in series with a resistor 45. The gate of the lateral double-sided JFET 43 is connected to ground 47 and the gate of the vertical double-sided JFET 44 is connected to ground 48.
The source contact 41 and the gate contact 42 of the MOS transistor 40 corresponds to the source contact region 26 and the gate contact 31 in FIG. 2. The channel of the lateral double-sided JFET 43 corresponds to the lateral JFET channel region 36 in FIG. 2. The grounded gate 47 of the lateral double-sided JFET 43 corresponds to the dual JFET gate region 33 and the lateral JFET gate region 38. The channel of the vertical double-sided JFET 44 corresponds to the vertical JFET channel region 34 in FIG. 2. The grounded gate 48 of the vertical double-sided JFET 44 corresponds to the dual JFET gate region 33 and the vertical JFET gate region 32. The resistor 45 corresponds to the buried pocket 23 and the re¬ duced drain resistance region 35 in FIG. 2.
A power device implemented in a 65nm CMOS technology with gate oxide thickness of 5nm and channel length around 0.2 μπι according to the preferred embodiment will achieve an on- resistance of around 1 ohmmm and maximum drain current above 1 A/mm which is at least 2-3 times better than presently shown and should meet the performance specification for e.g. an integrated WLAN solution in the frequency range of 2-5 GHz. [E.g. A. Mai, H. Rucker, R. Sorge, D. Schmidt and C. Wipf, "Cost-Effective Integration of RF-LDMOS Transistors in 0.13 μπι CMOS Technology", IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF '09), pp. 1-4, 2009.]

Claims

Claims
1. A semiconductor device comprising:
- a substrate (22) of a first conductivity type,
- a body region (25) of semiconductor material of the first conductivity type which adjoins the surface (24) of the substrate (22),
- a source contact region (26) of semiconductor material of the second conductivity type, the source contact re¬ gion (26) being within the body region (25) and adjoining the surface of the substrate (22),
- a drain contact region (27) of semiconductor material of the second conductivity type which adjoins the surface (24) of the substrate (22) and being separated from the body region (25) ,
- a dual JFET gate region (33) of semiconductor material of the first conductivity type located between the body region (25) and the drain contact region (27),
- a lateral JFET channel region (36) of semiconductor material of the second conductivity type which adjoins the surface (24) of the substrate (22) and which is located between the body region (25) and the drain contact re¬ gion (27), wherein at least a portion of the lateral JFET channel region (36) extends between the dual JFET gate region (33) and the surface (24) of the substrate (22) ,
c h a r a c t e r i s e d in that
- a vertical JFET gate region (32) of semiconductor material of the first conductivity type is arranged essen¬ tially enclosed by the body region (25) ,
- a vertical JFET channel region (34) of semiconductor material of the second conductivity type is arranged be- tween the vertical JFET gate region (32) essentially en¬ closed by the body region (25) and said dual JFET gate region ( 33 ) ,
- a reduced drain resistance region (35) of semiconductor material of the second conductivity type is arranged be¬ tween said dual JFET gate region (33) and the drain contact region (27), and
- a buried pocket (23) of semiconductor material of a second conductivity type which is located under part of said body region (25) , under said dual JFET gate region
(33) and under said vertical JFET channel and reduced drain resistance regions (34, 35) .
2. Semiconductor device according to claim 1, wherein said vertical JFET channel and reduced drain resistance regions
(34, 35) are arranged to adjoin the surface (24) of the sub¬ strate ( 22 ) .
3. Semiconductor device according to claim 1, wherein said vertical JFET channel and reduced drain resistance regions
(34, 35) are arranged isolated from the surface (24) of the substrate ( 22 ) .
4. Semiconductor device according to claim 1, wherein said vertical JFET channel and reduced drain resistance regions
(34, 32) extend downwards from the surface (24) of the sub¬ strate (22) to at least the same depth as the depth of said dual JFET gate region (33) . 5. Semiconductor device according to claim 4, wherein said vertical JFET channel and reduced drain resistance regions (34, 35) extend downwards from the surface (24) to a depth of at least 0.
5 μπι.
6. Semiconductor device according to claim 1, wherein said dual JFET gate region (33) adjoins the surface (24) of the substrate ( 22 ) .
7. Semiconductor device according to claim 1, wherein a lateral JFET gate region (38) of semiconductor material of the first conductivity type is located above said lateral JFET channel region (36) and said dual JFET gate region (33) .
8. Semiconductor device according to claim 1, wherein said semiconductor device is an insulated gate field effect tran¬ sistor with an extended drain region.
PCT/SE2012/050234 2011-03-08 2012-03-01 Semiconductor element WO2012121650A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP12754805.5A EP2684217A4 (en) 2011-03-08 2012-03-01 Semiconductor element
US14/003,530 US8969925B2 (en) 2011-03-08 2012-03-01 Semiconductor element

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE1150203A SE535621C2 (en) 2011-03-08 2011-03-08 Semiconductor component consisting of a lateral JFET combined with a vertical JFET
SE1150203-6 2011-03-08

Publications (1)

Publication Number Publication Date
WO2012121650A1 true WO2012121650A1 (en) 2012-09-13

Family

ID=46798444

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE2012/050234 WO2012121650A1 (en) 2011-03-08 2012-03-01 Semiconductor element

Country Status (4)

Country Link
US (1) US8969925B2 (en)
EP (1) EP2684217A4 (en)
SE (1) SE535621C2 (en)
WO (1) WO2012121650A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10008593B2 (en) * 2014-12-19 2018-06-26 Mediatek Inc. Radio frequency semiconductor device
CN104966736A (en) * 2015-06-01 2015-10-07 电子科技大学 Radio frequency LDMOS device and manufacturing method thereof
CN110739349A (en) * 2019-10-22 2020-01-31 深圳第三代半导体研究院 silicon carbide transverse JFET (junction field Effect transistor) device and preparation method thereof
US20230197846A1 (en) * 2021-12-17 2023-06-22 Infineon Technologies Austria Ag Power semiconductor device and methods of producing a power semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146298A (en) * 1991-08-16 1992-09-08 Eklund Klas H Device which functions as a lateral double-diffused insulated gate field effect transistor or as a bipolar transistor
US7064407B1 (en) * 2005-02-04 2006-06-20 Micrel, Inc. JFET controlled schottky barrier diode
US20080197445A1 (en) * 2002-08-14 2008-08-21 Advanced Analogic Technologies, Inc. Isolation and termination structures for semiconductor die
US20110127602A1 (en) * 2009-12-02 2011-06-02 Alpha And Omega Semiconductor Incorporated Dual Channel Trench LDMOS Transistors and BCD Process with Deep Trench Isolation

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6639277B2 (en) * 1996-11-05 2003-10-28 Power Integrations, Inc. High-voltage transistor with multi-layer conduction region
US6613622B1 (en) 2002-07-15 2003-09-02 Semiconductor Components Industries Llc Method of forming a semiconductor device and structure therefor
US8168466B2 (en) * 2007-06-01 2012-05-01 Semiconductor Components Industries, Llc Schottky diode and method therefor
US7915704B2 (en) * 2009-01-26 2011-03-29 Freescale Semiconductor, Inc. Schottky diode

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146298A (en) * 1991-08-16 1992-09-08 Eklund Klas H Device which functions as a lateral double-diffused insulated gate field effect transistor or as a bipolar transistor
US20080197445A1 (en) * 2002-08-14 2008-08-21 Advanced Analogic Technologies, Inc. Isolation and termination structures for semiconductor die
US7064407B1 (en) * 2005-02-04 2006-06-20 Micrel, Inc. JFET controlled schottky barrier diode
US20110127602A1 (en) * 2009-12-02 2011-06-02 Alpha And Omega Semiconductor Incorporated Dual Channel Trench LDMOS Transistors and BCD Process with Deep Trench Isolation

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2684217A4 *

Also Published As

Publication number Publication date
US8969925B2 (en) 2015-03-03
SE535621C2 (en) 2012-10-16
SE1150203A1 (en) 2012-09-09
US20140001517A1 (en) 2014-01-02
EP2684217A1 (en) 2014-01-15
EP2684217A4 (en) 2014-08-06

Similar Documents

Publication Publication Date Title
US10084039B2 (en) Semiconductor device having self-isolating bulk substrate and method therefor
US9673188B2 (en) Integrated electrostatic discharge (ESD) clamping for an LDMOS transistor device having a bipolar transistor
US9673323B2 (en) Embedded JFETs for high voltage applications
US20190228984A1 (en) Semiconductor device having biasing structure for self-isolating buried layer and method therefor
US8344472B2 (en) Semiconductor device and method
CN107026165B (en) Circuit including semiconductor device including first and second transistors and control circuit
EP3257085A1 (en) High voltage semiconductor devices and methods of making the devices
US9236372B2 (en) Combined output buffer and ESD diode device
US9190535B2 (en) Bootstrap MOS for high voltage applications
KR20120091231A (en) Power semiconductor devices having selectively doped jfet regions and related methods of forming such devices
US8912569B2 (en) Hybrid transistor
US8823097B2 (en) Protection device with a thin-film resistance connected to plural drain regions
US9716169B2 (en) Lateral double diffused metal oxide semiconductor field-effect transistor
US11004940B1 (en) Manufacture of power devices having increased cross over current
JP2018511163A (en) Power semiconductor devices
US8455953B2 (en) Semiconductor device and method of manufacturing semiconductor device
US8969925B2 (en) Semiconductor element
CN108258046B (en) Semiconductor device with a plurality of semiconductor chips
WO2003036699A2 (en) Lateral semiconductor-on-insulator structure and corresponding manufacturing methods
US8482060B2 (en) Semiconductor device
JP2004031519A (en) Semiconductor device
US20150115351A1 (en) Integrated Circuit and Method of Manufacturing an Integrated Circuit
KR20100061410A (en) Improved buried isolation layer
US20140312384A1 (en) Semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12754805

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 14003530

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2012754805

Country of ref document: EP