WO2012086102A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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WO2012086102A1
WO2012086102A1 PCT/JP2011/004170 JP2011004170W WO2012086102A1 WO 2012086102 A1 WO2012086102 A1 WO 2012086102A1 JP 2011004170 W JP2011004170 W JP 2011004170W WO 2012086102 A1 WO2012086102 A1 WO 2012086102A1
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film
metal film
step
gate
semiconductor device
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PCT/JP2011/004170
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French (fr)
Japanese (ja)
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征嗣 松山
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パナソニック株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Abstract

First, in a state wherein an upper region of a p-type gate stack structure on an interlayer insulating film (115) is masked, a polysilicon film (108) in an n-type gate pattern is removed by having an etch stop film (107) as an etch stop. Then, nitriding treatment is performed to the etch stop film (107) exposed from the interlayer insulating film (115), and a nitrogen-rich etch stop film (107A) is formed. Then, on the etch stop film (107A) in the n-type gate stack structure, an Nch work function metal laminate film (117A) is formed.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof, particularly to a semiconductor device and a manufacturing method thereof comprising a transistor having a high dielectric constant (high-k) film and the gate structure in which a metal gate electrode are stacked.

Speed ​​and lower power consumption of the operation of the transistor is based on the scaling rule, it has been achieved by miniaturization of transistors. In general, as a laminate material of the gate insulating film and the gate electrode of the transistor (gate stack material of the gate insulating film / gate electrode), a silicon oxide (SiO 2) or silicon oxynitride (SiON) / Polysilicon is used , the increase of the gate leakage current, the gate insulating film to be thinned is becoming difficult. Therefore, a high dielectric constant is a combination of an (High-k) gate dielectric and metal gate electrodes, High-k / metal gate technology has attracted attention.

For example, bulk CMOS (complementary MOS: Complementary Metal Oxide Semiconductor), a case of applying the metal gate electrode, in order to enable the threshold control by impurity implantation into the channel, n-type MOS transistor (nMOS) and p in the type of MOS transistors (pMOS), using a metal material having a different work function (work function) to each other. Such a gate structure is also referred to as a dual metal gate structure. Specifically, in the case of nMOS, a metal material having a work function value in the vicinity of the conduction band edge of silicon, in the case of pMOS, using a metal material having a work function value in the vicinity of the valence band edge. Further, it called lanthanum (La) system or an aluminum (Al) based cap material, by mixing the material to shift the work function value to each gate electrode or the gate insulating film, a method of separately forming the nMOS and pMOS proposed is (e.g., see Patent Document 1.).

Meanwhile, a manufacturing method of a transistor using a High-k / metal gate is said to MIPS (Metal Inserted Poly-Silicon), sequentially deposited high-k film / metal gate / poly silicon film was subjected to gate etch after forming the source drain diffusion layer and the silicide layer. Manufacturing method according to this conventional CMOS process, so-called gate-first process. Although this method does not require a relatively complicated process, there are the following problems.

That is, after forming the metal gate, the gate etch, the formation of the diffusion layer, activation annealing such high-temperature heat treatment, and a method for performing formation etc. of the silicide, the effective stack gate comprising a high-k film and the metal gate the work function: the value of (eWF effective work function) is known to vary the mid-gap side by the heat load. Therefore, it is difficult to obtain a work function in the vicinity of the desired band edge. Further, even when using a different cap material in the nMOS and pMOS, for performing gate etch once, it is difficult to achieve both the gate etch shape at the end of the particular gate insulating film of the MOS, each MOS deterioration of reliability and narrow channel characteristics is a major concern. Here, the effective work function (eWF), refers to the effective work function that acts on the silicon substrate side of the metal gate.

Therefore, first forming a dummy gate, diffusion layer as a mask, to form an activated annealing and silicide, after removal of the dummy gate, the process of forming a metal gate (hereinafter, referred to as gate-last process.) Of have been reported (e.g., see Patent Document 2.). Gate-last process to achieve dual metal integration, it is possible to obtain a very good device characteristics. Particularly, in the case of the gate-last process, after forming the metal material to control the value of the effective work function, it is possible to form a device at a low temperature process at a relatively. Therefore, it is possible to control the value of the effective work function of the stacked gate near the band edge. The dummy gate itself, because it is formed of the same material both nMOS and pMOS, difficulty in controlling the shape of the gate etch process is also compared to the gate-first process is low.

JP 2007-324594 JP U.S. Patent Application Publication No. 2010/0052070 Pat

However, the in conventional gate-last process has the following problems.

First, the polishing step in exposing the dummy gate from the interlayer insulating film, for example, chemical mechanical polishing (CMP: Chemical Mechanical Polishing) gate cue of by law is required, variation in the height of the gate due to CMP, i.e. resistance variations in is a concern.

Further, in the step of removing the dummy gate, not to enter damaged the high-k film, must be a metal film as an etch stop layer over the high-k film, such as titanium nitride (TiN) film is previously formed There are, after removal of the dummy gate, respectively suitable electrode material for nMOS or for pMOS is deposited on the TiN film. In this case, if the oxide on the surface of the TiN film is an etch stop layer remains, a problem that even by forming an electrode material described above is not obtained amount of shift required work function value It occurs.

Incidentally, in the gate-last process, High-k film is also a dummy insulating film, after removing the dummy gate, and removing the dummy insulating film, a method of forming a High-k film and the electrode film has been studied. However, the number of steps becomes complicated increasing, the side etching, and high-k degradation and yield characteristics by baking such as insufficient film occurs on the lower end of the sidewall spacer at the time of removing the dummy insulating film deterioration is also a concern.

Further, as the mask protective insulating film formed on the pMOS side of the dummy gate, the dummy gate in removing by wet etching, the chemical solution from the interface between the protective insulating film and the interlayer insulating film of a pMOS side there is a case to be entering. Vacancy occurs in the pMOS side of the dummy gate by the penetrated liquid medicine, caused or nMOS side of the metal material is mixed from the air holes, the removal of the dummy gate in removing pMOS side of the dummy gate in a subsequent step and lowered, there is a problem that pMOS characteristic deteriorates.

The present invention, the problem persists, the high dielectric constant (high-k) film and a transistor having a metal gate, the semiconductor having the desired properties in terms of film thickness and the like in the work function and high-k film in metal gate and an object thereof is to allow the device can be realized.

To achieve the above object, the present invention provides a method of manufacturing a semiconductor device, after exposing the etch stop layer thereunder was removed dummy gate, subjected to a nitriding treatment to the exposed etch stop layer, a high density nitride a configuration to form a layer.

Specifically, the method of manufacturing a semiconductor device according to the present invention, on a semiconductor substrate, a high dielectric constant film, sequentially forming a first metal film and the silicon film (a), a silicon film, a first the metal film and the high dielectric constant film is etched, (b) forming a first gate pattern and a second gate pattern, the first gate pattern as a mask, a first conductivity type in the semiconductor substrate (c) forming a first source drain region, the second gate pattern as a mask, and forming a second source drain region of the second conductivity type semiconductor substrate (d), step (c) and after the step (d), on a semiconductor substrate, and (e) forming an interlayer insulating film to cover the first gate pattern and a second gate pattern, the second in the top of the interlayer insulating film the upper side of the territory of the gate pattern In a state in which a mask and step (f) removing the silicon film in the first gate pattern of the first metal film as an etch stop layer, after the step (f), a first exposed from the interlayer insulating film and step (g) performing a nitriding treatment to the metal film, after the step (g), on the first metal film which is nitrided in the first gate pattern, forming a second metal film and step (h), a step (i) of forming a third metal film on the second metal film, the second metal film, adjust the value of the effective work function of the third metal film to.

According to the method of the present invention, after removing the silicon film in the first gate pattern, the nitriding process on the first metal film exposed from the interlayer insulating film. Therefore, since the oxide of the surface of the first metal film is an etch stop layer of the first gate pattern may be removed (replaced), it is possible to prevent the deterioration and variation in the deterioration and the gate capacitance of the threshold voltage it can. Moreover, it does not lower the operating characteristics and manufacturing yield in a transistor having a second gate pattern.

In the method of the present invention, the first conductivity type is n-type, it is preferable the second conductivity type is p-type.

In this case, the second metal film may be a laminated film consisting of aluminum and titanium and titanium nitride.

In the method of the present invention, the first metal film, it is possible to use a titanium nitride.

In the method of the present invention, nitriding treatment in step (g) may be a plasma nitridation or radical nitridation processing.

In the method of the present invention, the high dielectric constant film, hafnium, may be an insulating film containing at least hafnium or zirconium of the zirconium and silicon.

The method of manufacturing a semiconductor device of the present invention, between the step (e) and step (f), to flatten a top surface of the interlayer insulating film, the interlayer insulating film, a first gate pattern and a second gate pattern further comprising a step (j) exposing the in step (h), the second metal film is formed by removing the silicon film in the interlayer insulating film, and a bottom surface of the upper surface of the first metal film nitrided it may be formed on and over the wall bottom surface of the groove to be.

The method of manufacturing a semiconductor device of the present invention, between the step (e) and step (f), or steps (h) and between the step (i), the first gate pattern in the top of the interlayer insulating film while masking the upper region, a step of removing the silicon film in the second gate pattern (k), after the step (k), on the first metal film in the second gate pattern, the further comprising the step (l) forming a fourth metal film, in the step (i), the third metal film may be formed on the fourth metal film in the second gate pattern.

The method of manufacturing a semiconductor device of the present invention, before the steps (c) and (d) later and process than (e), a silicide on top of the first source drain region and the second source drain region it may further comprise a step (m) to form a layer.

The semiconductor device according to the present invention is formed on a semiconductor substrate, a first transistor of a first conductivity type, a semiconductor device and a second transistor of a second conductivity type targeted, the first transistor, high dielectric constant film are sequentially formed on a semiconductor substrate, a first metal film made of titanium nitride, the first gate pattern having a second metal film and the third metal film, the second transistor the high dielectric constant film that are sequentially formed on a semiconductor substrate, a fourth metal film made of titanium nitride, a second gate pattern having a silicon film, the second metal film, the gate length direction cross section is concave, the value of the composition ratio of nitrogen to titanium of the first metal film is 1.2 or more, and the value of the composition ratio of nitrogen to titanium of the fourth metal film is less than 1.2 is there.

According to the semiconductor device of the present invention, the value of the composition ratio of nitrogen to titanium of the first metal film of the first gate pattern is 1.2 or more, and, the fourth metal film in the second gate pattern value of the composition ratio of nitrogen to titanium is less than 1.2. Therefore, since the oxide on the surface of the first metal film is removed (replaced), it is possible to prevent deterioration and variation in the deterioration and the gate capacitance of the threshold voltage of the first transistor.

In the semiconductor device of the present invention, the first conductivity type is n-type, the second conductivity type is p-type, the second metal film may be a laminated film consisting of aluminum and titanium and titanium nitride .

In the semiconductor device of the present invention, the second gate pattern is formed on the fourth metal film, may have a fifth metal film gate length direction of the cross section consists of concave titanium nitride good.

In the semiconductor device of the present invention, the second metal film in the first gate pattern is directly formed without an intervening titanium oxide on the first metal film.

According to the semiconductor device and the manufacturing method thereof according to the present invention, for example, the oxidation of the metal gate material constituting the nMIS (n-type Metal Insulator Semiconductor) transistor is prevented, lowering of deterioration and the gate capacitance of the threshold voltage and it is possible to prevent the variation.

1 (a) is a sectional view in the process of production of a semiconductor device for evaluation according to the present invention. 1 (b) is a sectional view in the process of production of a semiconductor device according to a conventional example. Figure 2 is a graph showing the composition of a height direction of the gate stack structure of a semiconductor device according the conventional example shown in FIG. 1 (b). Figure 3 is a graph showing the improvement in properties due to conceptual structure of nMIS effective work function and the equivalent oxide thickness of the degradation and the present invention by the titanium oxide on the etch stop layer. Figure 4 is a sectional view showing a semiconductor device according to a first embodiment of the present invention. Figure 5 (a) ~ FIG. 5 (c) is a sectional view of a process sequence illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIG 6 (a) ~ FIG. 6 (c) is a sectional view of a process sequence illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Figure 7 (a) ~ FIG. 7 (c) is a sectional view of a process sequence illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Figure 8 (a) ~ FIG. 8 (c) is a sectional view of a process sequence illustrating a main part of a method of manufacturing a semiconductor device according to a second embodiment of the present invention. Figure 9 is a sectional view showing the method for manufacturing a semiconductor device according to a second embodiment of the present invention. Figure 10 (a) ~ FIG. 10 (c) is a sectional view of a process sequence illustrating a main part of a method of manufacturing a semiconductor device according to a modification of the second embodiment of the present invention.

Embodiments of the present invention will be described with reference to the drawings.

It should be noted that the technical scope of the present invention is not limited to the embodiments described below, the configuration requirements and range derivable particular effect obtained by the combination of the invention, various changes or improvements added It was also a form.

First compares the semiconductor device of conventional example of the semiconductor device (nMIS) according to the present invention and (nMIS) with reference to the drawings.

1 (a) is a cross-sectional view illustrating a process of producing a nMIS according to the present invention, FIG. 1 (b) shows a semiconductor device during manufacture of the cross-sectional configuration of the nMIS according to a conventional example.

As shown in FIG. 1 (a), the semiconductor device being manufactured according to the present invention, high-k film formed by interposing an interfacial oxide layer on the p-well 10 formed of p-type silicon (Si) and the etch stop layer 12A gate insulating film 11, on the gate insulating film 11, the composition of nitrogen consisting of greater than the stoichiometric ratio, titanium nitride formed in a so-called nitrogen-rich (TiN) is, the etch aluminum formed on the stopper film 12A (Al), a laminated film (Nch work function metal laminated film) 18 of titanium (Ti) and titanium nitride (TiN), on top of the Nch work function metal laminated film 18 embedding consists of forming aluminum (Al) or tungsten (W) and a metal material film 19.

Nch work function metal laminated film 18 and the buried metal material film 19 is formed also on the interlayer insulating film 17 to fill the gate stack in the subsequent steps, Nch work function metal laminated film 18 and the buried metal material film 19, by a CMP method or the like, a region excluding the gate stack is removed, the metal gate electrode is formed.

On both sides of the gate stack, the offset spacer film is interposed sidewalls 14 formed is formed in a region on both sides of the gate stack in the p-well 10, n-type source drain diffusion layer 13 is formed there. In the region of both sides of the sidewall 14 at the top of the n-type source drain diffusion layer 13, the silicide layer 15 is formed. Between the side walls 14 and the interlayer insulating film 17, the stress liner film 16 is formed.

In contrast, the semiconductor device according to the conventional example, as shown in FIG. 1 (b), not the nitrogen-rich, ie etch value of the composition ratio of nitrogen (N) to titanium (Ti) is less than 1.2 between the stop layer 12 and the Nch work function metal laminated film 18, oxide film 20 is formed of an oxide of titanium (TiO x) and the like.

The presence of the oxide film 20 is evident from the results analyzed using EDS (Energy Dispersive x-ray Spectroscopy) or EDX (Energy Dispersive X-ray spectroscopy) shown in FIG. The horizontal axis of the graph shown in FIG. 2 represents the height from the substrate surface.

Next, the equivalent oxide thickness in the effective work function (eWF) and the gate insulating film by the formation method of the gate stack structure in Figure 3: shows the results of measurement of the (EOT Equivalent Oxide Thickness).

3 is performed a comparison between eWF characteristics and EOT characteristics of three kinds of conditions.
(1) Left condition without forming a film and removal of the dummy gate, on High-k film (HfO 2 film), the film thickness is as a metal material embedded thereon a TiN film of 5nm tungsten ( W) shows a first gate stack structure in which film is laminated.
(2) central conditions applies a conventional method of manufacturing a gate-last, and removing the dummy polysilicon film thickness is etch stop layer on the High-k film is formed on the TiN film of 5nm after shows thickness 2nm of Al / Ti film thickness is 2nm of the TiN film, and the W film and the second gate stacked structure formed by stacking sequentially a.
(3) the right conditions, similarly to the first gate stacked structure, thickness and a TiN film of 5nm on the High-k film, without forming a film and removal of the dummy gate, thickness 2nm the Al / Ti film, a third gate stacked structure thickness by laminating TiN film of 2 nm, and a W film in succession. Here, represents a eWF value in the bar graph represents the EOT line graph.

The first gate stacked structure corresponds to a gate stack structure in pMIS, the value of the effective work function indicates the degree of 4.8 eV.

The third gate stacked structure corresponds to a gate stack structure in nMIS, the value of the effective work function, it can be seen that the shifting down to the 4.2eV about required by nMIS.

In contrast, the second gate stack structure corresponding to the gate stack structure in nMIS of the application of the conventional process flow, the value of the effective work function is about 4.6 eV, as shown in FIG. 2, titanium oxide on the surface of the TiN film is etch stop layer (TiO x) may remain, it oxidizes Ti / Al film, which is a material for work function adjustment of nMOS, by inhibiting shift of the effective work function it is a cause there are revealed.

In the case of the second gate stack structure TiO x film is left, equivalent oxide thickness (EOT) has become also clear that increasing the order of 0.1 nm.

Thus, in nMIS, after removing the dummy gate made of polysilicon, to form a metal electrode in a state of leaving a oxide such as TiO x, it revealed that degrade the operating characteristics of nMIS. This is that the present inventors have newly found.

The present invention is, after removal of the dummy gates of the nMIS, by substituting nitride oxide remaining on the surface of the etch stop layer in the nitriding treatment, while adopting the gate-last process, shown on the right side of FIG. 3 the third is to obtain a gate stack structure and characteristics equivalent to the.

(First Embodiment)
Hereinafter, based on the above findings, with the semiconductor device will be described with reference to FIG. 4 according to a first embodiment of the present invention.

As shown in FIG. 4, for example, above the semiconductor substrate 101 made of silicon (Si), nMIS region 100A and pMIS region 100B is formed which are separated from each other by an element isolation region 102.

The nMIS region 100A of the semiconductor substrate 101, p-well 103 is formed, also in the pMIS region 100B in the semiconductor substrate 101, n-well 104 is formed.

n-type gate stack structure is a first gate patterns forming the nMIS is interfacial silicon oxide film 105 are sequentially formed on the p-well 103, a high dielectric constant (high-k) film 106, the nitrogen-rich titanium nitride etch stop layer 107A as a first metal film made of (TiN), aluminum (Al) or tungsten (W) as a Nch work function metal laminated film 117A, and the third metal film as a second metal film become embedded and has a metal material film 119A. Here, the nitrogen-rich titanium nitride (TiN), the value of the composition ratio of N to Ti refers to TiN 1.2 or more. Further, the etch stop layer is not limited to titanium nitride, which is nitrided (TiN), titanium is respectively nitriding treatment (Ti), it can be used tantalum nitride (TaN) or titanium aluminum nitride (TiAlN) or the like.

Incidentally, Nch work function metal laminated film 117A is not only the upper surface of the etch stop layer 107A, by being formed on the wall surface (inner wall) of the offset spacer film 109, the gate length direction of the cross section is formed in a concave shape .

On both sides of the n-type gate stack structure, the offset spacer film 109 made of an insulator is formed on the outside of the offset spacer film 109, sidewalls 111 made of an insulating material are formed respectively.

In the lower region of the sidewall 111 from the both sides of the n-type gate stack structure in the upper portion of the p-well 103, the junction depth is relatively shallow n-type extension diffusion layer 110A is formed. Also, in the regions outside the n-type extension diffusion layer 110A at the top of the p-well 103 is connected to the n-type extension diffusion layer 110A, respectively, n-type source is deeper junction depth than the n-type extension diffusion layer 110A drain diffusion layer 112A is formed. Here, the top of each n-type source drain diffusion layer 112A, a silicide layer 113 are formed.

Further, on the silicide layer 113 and the sidewall 111, the stress liner film 114 made of an insulator is formed so as to cover the stress liner film 114, the upper surface is formed an interlayer insulating film 115 having a planarized there. Further, on the interlayer insulating film 115 is flattened, the stress liner film 114 exposed from the interlayer insulating film 115, side wall 111, the offset spacer film 109 and Nch work functions each upper end surface of the metal laminated film 117A, and so as to cover the upper surface of the buried metal material film 119A, the liner nitride film 121 is formed.

Next, p-type gate stack structure is a second gate pattern constituting the pMIS, describes only Aikototen the n-type gate stack structure constituting the nMIS.

Etch stop layer 107 formed on the high dielectric constant film 106 in the p-type gate stack structure usually of titanium nitride is not a nitrogen-rich (TiN), i.e. the value of the composition ratio of N for is less than 1.2 Ti It is constructed from a certain TiN. Further, on the etch stop layer 107, n-type polysilicon film 108 is formed of, in the upper portion of the polysilicon film 108, a silicide layer 120 is formed.

In the lower region of the sidewall 111 from the both sides of the p-type gate stack structure in the upper portion of the n-well 104, the junction depth is relatively shallow p-type extension diffusion layer 110B is formed. Also, in the regions outside the p-type extension diffusion layer 110B at the top of the n-well 104, are respectively connected to the p-type extension diffusion layer 110B, p-type source junction depth deeper than the p-type extension diffusion layer 110B drain diffusion layer 112B is formed. Here, the top of each p-type source drain diffusion layer 112B, a silicide layer 113 are formed. Thus, p-type gate stack structure constituting the pMIS takes a so-called MIPS structure.

It will be described below with reference to FIGS method for manufacturing the thus configured semiconductor device as.

First, as shown in FIG. 5 (a), the upper portion of the semiconductor substrate 101 made of Si, to form an element isolation region 102 made of silicon oxide (SiO 2) or the like, a semiconductor substrate 101 nMIS region 100A and pMIS region It is partitioned into a 100B. Here, the element isolation region 102 may be formed by LOCOS (local oxidation of silicon) method or STI (shallow trench isolation) method or the like.

Subsequently, the nMIS region 100A of the semiconductor substrate 101, and selectively implanting boron (B) or the like which is a p-type dopant to form a p-well 103. Thereafter, the pMIS region 100B in the semiconductor substrate 101, and selectively implanting arsenic (As) or phosphorus (P) or the like as an n-type dopant to form an n-well 104. The formation order of the p-well 103 and n-well 104 is not particularly limited.

Next, as shown in FIG. 5 (b), on the entire surface of the semiconductor substrate 101 to form an interfacial silicon oxide film 105. The interfacial silicon oxide film 105 may be used such as silicon oxide (SiO 2) or silicon oxynitride (SiON). More specifically, the optical film thickness 0.5 nm ~ 1 nm approximately chemical oxide film, or the film thickness can be used radical oxidation film of about 0.5 nm ~ 1.0 nm. Chemical oxide film, a mixed solution of common hydrochloric acid (HCl) and hydrogen peroxide (H 2 O 2), or sulfuric acid (H 2 SO 4) and the semiconductor by hydrogen peroxide (H 2 O 2) mixed chemical solution it may be formed by treating the substrate 101. On the other hand, the radical oxide film, hydrogen (H 2) and a temperature in a mixed gas atmosphere of dinitrogen monoxide (N 2 O) may be formed by performing heat treatment at about 600 ℃ ~ 850 ℃.

Then, for example, atomic layer deposition: by (ALD Atomic Layer Deposition) method, on the surface the silicon oxide film 105, to form a high dielectric constant film 106. The high dielectric constant film 106, a hafnium silicate (HfSiO), nitrogen-doped hafnium silicate (HfSiON), it is possible to use an insulating film of hafnium (Hf) system, such as hafnium oxide (HfO), or hafnium oxide, zirconium (HfZrO). Material in the case of using the ALD method, and an organic material containing tetrakis (ethylmethylamino) hafnium {Hf [N (C 2 H 5) CH 3] 4} , etc. hafnium (Hf), monosilane (SiH 4) or the like using an organic material containing silicon gas or tris containing (Si) (dimethylamino) silane {SiH [N (CH 3) 2] 3} , etc. silicon (Si), the temperature of 300 ° C. ~ 600 ° C. the extent of the film formation temperature is performed in a short time and deposited alternately, while purging the excess raw material, oxidation with oxygen (O 2) gas, ozone (O 3) gas or water vapor (H 2 O), etc. to. The starting of the Hf-based, instead of the organic material may be an inorganic material such as hafnium chloride (HfCl 4) or zirconium chloride (ZrCl 4).

Here, the film thickness of the high dielectric constant film 106, when a 0.5 nm ~ 1.5 nm about the EOT is a physical thickness combined with interfacial silicon oxide film 105 may be about 1 nm ~ 3 nm. The high dielectric constant film 106, as described above, may be a dielectric film of Hf system comprising zirconium oxide (ZrO), also as a high dielectric constant film other than Hf-based, zirconium oxide (ZrO) or as a single dielectric film.

Subsequently, a plasma nitriding process for the high dielectric constant film 106 as necessary. Plasma nitriding processing here, the nitrogen (N) in the high dielectric constant film 106, Hf, may be introduced about 5% to 10% with respect to elemental composition of O and Si. The plasma nitriding process, and prevents the crystallization of the high dielectric film 106, in order to improve the reliability of the high dielectric constant film 106. Note that the introduction of the nitrogen, the deterioration of interface characteristics of the transistor (interface characteristics between the gate insulating film and the semiconductor substrate), as well as for the pMIS, lowering of the effective work function value, and negative bias temperature instability (NBTI: since Negative Bias Temperature Instability) lowering of reliability such becomes a problem, the introduction amount of nitrogen to the high dielectric constant film 106 is preferably adjusted to an appropriate amount.

Subsequently, the high dielectric constant film 106, oxygen (O 2) in an atmosphere or nitrogen (N 2) may be subjected to heat treatment. Thus, it is possible to perform removal and defect repair impurities in the high dielectric constant film 106. Further, it is possible to improve the adhesion between the surface silicon oxide film 105 formed on the lower side of the high dielectric constant film 106.

Then, for example, physical vapor deposition (PVD: Physical Vapor Deposition) method, a chemical vapor deposition: by (CVD Chemical Vapor Deposition) method or ALD method, on the entire surface of the high dielectric constant film 106, the composition ratio to form the etch stop layer 107 made of titanium nitride (TiN), which corresponds to approximately stoichiometric ratio. The thickness of the etch stop layer 107 affects the value of the effective work function (eWF) of the gate electrode. Therefore, the thickness of the etch stop layer 107 is preferably about 1 nm ~ 15 nm.

Subsequently, by a CVD method or the like, on the entire surface of the etch stop layer 107, a thickness of about 80 nm ~ 150 nm, a polysilicon film 108 phosphorus (P) doped. The concentration of phosphorus may if 1 × 10 14 / cm 2 ~ 2 × 10 15 / cm 2 approximately. Incidentally, after forming the non-doped polysilicon film 108, the n-type dopant of arsenic (As) or the like may be ion-implanted. Then, by CVD or the like, on the entire surface of the polysilicon film 108, a hard mask film 130 having a thickness made of silicon oxide of about 10nm ~ 50nm (SiO 2).

Next, as shown in FIG. 5 (c), by a known lithography method and an etching method, the hard mask layer 130 was formed, the polysilicon film 108, the etch stop layer 107, high dielectric constant film 106 and the interface silicon oxide film against 105 to form the respective gate patterns for the nMIS and pMIS (gate etch). Thus, in the nMIS region 100A, n-type gate stack structure is formed, in the pMIS region 100B, p-type gate stack structure is formed. In this state, n-type gate stack structure and a p-type gate stack structure having the same configuration. Subsequently, the ALD method, the entire surface of the upper and side surfaces of the upper surface and the gate stack structure of the semiconductor substrate 101, the film thickness is deposited 5 nm ~ 10 nm of approximately silicon nitride (ALD-SiN) film. Then, by performing etching back against the formed silicon nitride film, by removing the portion excluding the upper sides of the gate stack structure in a silicon nitride film, on both sides of each gate stack structure, each offset forming a spacer layer 109.

Then, n as shown in FIG. 6 (a), by known methods, while masking the pMIS region 100B, the p-well 103 in the nMIS region 100A, the n-type gate stack structure and the offset spacer film 109 as a mask by injecting a mold dopant, junction depth to form a relatively shallow n-type extension diffusion layer 110A. Thereafter, while masking the nMIS region 100A, the n-well 104 in the pMIS region 100B, by implanting p-type dopant p-type gate stack structure and the offset spacer film 109 as a mask, a relatively shallow junction depth forming a p-type extension diffusion layer 110B. The formation order of the n-type extension diffusion layer 110A and the p-type extension diffusion layer 110B is not particularly limited.

Then, a sidewall 111 in each gate stack structure. That is, the entire surface of the semiconductor substrate 101 so as to cover each of the gate stack structure including an offset spacer film 109, using the CVD or ALD, a silicon oxide film. Thereafter, by etching back against the formed silicon oxide film, a sidewall 111, respectively on the side surfaces of the gate stack structure is formed.

Subsequently, while masking the pMIS region 100B, the p-well 103 in the nMIS region 100A, n-type gate stack structure, by implanting n-type dopant offset spacer film 109 and the sidewall 111 as a mask, n-type extension junction depth than the diffusion layer 110A to form a deep n-type source drain diffusion layer 112A. Thereafter, while masking the nMIS region 100A, the n-well 104 in the pMIS region 100B, the p-type gate stack structure, by implanting p-type dopant an offset spacer film 109 and the sidewall 111 as a mask, p-type extension diffusion junction depth to form a deep p-type source drain diffusion layer 112B than layer 110B. The formation order of the n-type source drain diffusion layer 112A and the p-type source drain diffusion layer 112B is not particularly limited.

Subsequently, by a PVD method or CVD method, the source drain diffusion layers 112A, over the entire surface of the semiconductor substrate 101 112B is formed of cobalt (Co), metal tungsten (W) or nickel (Ni), etc. depositing a film. Thereafter, by performing a predetermined heat treatment, the source-drain diffusion layer 112A, the top of 112B, to form a silicide layer 113 are each a metal silicide. Thereafter, the unreacted metal film is removed using an acidic solution or the like.

Next, as shown in FIG. 6 (b), by a CVD method or the like, to cover the nMIS and pMIS respectively, forming the stress liner film 114 made of silicon nitride (SiN). By providing the stress liner film 114, the oxide of the silicide layer 113 is prevented, it is possible to produce a distortion effect of the channel direction of the respective transistors. Thereafter, a CVD method, or the like on the semiconductor substrate 101, to cover the stress liner film 114, so as to fill between the gate stack structure, depositing an interlayer insulating film 115 made of silicon oxide.

Next, as shown in FIG. 6 (c), by CMP method, by performing a flattening process on the interlayer insulating film 115, by removing the hard mask layer 130 in the gate stack structure, the gate stack structure respectively to expose the polysilicon film 108 from. Subsequently, by a known lithography masks the pMIS region 100B, and a resist film 131 to expose the nMIS region 100A.

Next, as shown in FIG. 7 (a), by a wet etching method, the resist film 131 as a mask, and the etch stop film 107 as a stopper to remove the polysilicon film 108 from the n-type gate stack structure. The results of the polysilicon film 108 is removed, the n-type gate stack structure, and the wall surface of the offset spacer film 109 facing each other, a groove portion 132A of the etch stop layer 107 exposed to the bottom surface is formed. Thereafter, the resist film is removed 131.

Here, when removing the polysilicon film 108 is a dummy gate, no etching damage, and a high selectivity between the silicon oxide, tetramethyl ammonium hydroxide: cleaning using (TMAH TetraMmethyl Ammonium Hydroxide) solution removal by is desirable.

In the first embodiment, in the step shown in FIG. 6 (c), has been removed the hard mask layer 130 made of silicon oxide, leaving the hard mask layer 130, hard mask layer 130 left as a mask, it is also possible to adopt a method of removing the polysilicon film 108. However, if the gap is formed between the interlayer insulating film 115 and the hard mask layer 130, by the chemical solution entering through the gap, there is a possibility that the p-type gate stack structure in pMIS region 100B suffers damage . Therefore, in the present embodiment employs a method of forming a resist film 131 having a pattern including up element isolation region 102 for partitioning pMIS region 100B.

Meanwhile, after removing the resist film 131, as shown in FIG. 7 (a) and FIGS. 2 and 3, in the n-type gate stack structure, the surface of the etch stop layer 107, a titanium oxide (TiO x) 116 will be formed.

Therefore, as shown in FIG. 7 (b), in the first embodiment, by performing the nitriding process on the etch stop layer 107 which is exposed from the groove 132A, performs substitution of a nitride of titanium oxide further, as the composition of titanium nitride (TiN) is the value of the composition ratio of nitrogen (N) to titanium (Ti) of 1.2 or higher (N / Ti ≧ 1.2), high nitrogen in the titanium nitride subjected to nitriding treatment to a concentration of. Thus, in the n-type gate stack structure, the etch stop layer 107 is nitrogen-rich etch stop layer 107A.

Nitriding here is performed and high density nitriding treatment at a low temperature, and less damage conditions, for example, it is preferable to perform the plasma nitriding processing condition for performing the normal gate insulating film. As an example, a nitrogen (N 2) atmosphere at a pressure of several mTorr ~ several tens mTorr (1mTorr = 133.322mPa), several hundred W about processing conditions are preferred. As a guideline for hafnium oxide (HfO) film having a thickness of about 1 nm, it may be used conditions to introduce about 10% of nitrogen.

Incidentally, the nitriding of the etch stop film 107, as described above, although the plasma nitriding is preferred, may be used radical nitriding. For example, the radical nitriding process, a remote plasma nitridation downflow plasma or nitrogen atom beam by a radical principal or 500 ° C. ~ ammonia (NH 3) at a temperature of about 600 ° C. nitriding treatment using thermal nitride by gas it is also possible.

Next, as shown in FIG. 7 (c), on the etch stop layer 107A exposed from the groove 132A, shifts the value of the effective work function of the nMIS, forming the Nch work function metal laminated film 117A. Specifically, to cover the wall surfaces made of a bottom surface and offset spacer film 109 of the etch stop layer 107A of the groove 132A, over the entire surface, such as the stress liner film 114 has upper and exposure of the interlayer insulating film 115, the film thickness each about 1 nm ~ 5 nm of aluminum (Al) film, laminating the laminate film 117A made of titanium (Ti) film and a titanium nitride (TiN) film. Here, Nch work function metal laminated film 117A, it is necessary to deposit enough not embedded grooves 132A, thus, the film formation method, PVD method is preferable, if possible, the coverage of the groove 132A film formation by excellent Ionized PVD method is desirable.

Then, it embeds a metal material in the grooves 132A. For example, the ALD method, a sputtering method or the like, as the entire surface in the groove 132A on the Nch work function metal laminated film 117A is embedded, forming the metal material film 119 buried tungsten (W) or aluminum (Al) .

Incidentally, before embedding the metal material film 119 buried in the groove 132A, Nch work adhesion at the time of coating of the buried metal material film 119 onto the function metal laminated film 117A, the embedded Nch work function metal of the metal material film 119 diffusion barrier into the laminated film 117A, and to improve the interfacial resistance, by a PVD method or ALD method, may be formed underlay film 118 having a thickness consisting of 2 ~ 3 nm approximately TiN.

Next, by CMP, the metal material film 119 buried was formed by performing grinding against underlay film 118 and Nch work function metal laminated film 117A, to expose the polysilicon film 108 in the p-type gate stack structure. Thus, only the groove 132A of the n-type gate stack structure, and Nch work function metal laminated film 117A and the buried metal material film 119 remains, as shown in FIG. 4, the upper portion of the n-type gate stack structure, the buried metal material film 119A is formed. Subsequently, a resist film (not shown) covering the nMIS region 100A, the top of the polysilicon film 108 of the p-type gate stack structure in pMIS region 100B, selectively forming a silicide layer 120 such as cobalt. Thereafter, a CVD method, or the like on the interlayer insulating film 115 including the gate stack structure, forming a liner nitride film 121 to obtain the semiconductor device shown in FIG.

Thereafter, although not shown, forms the source-drain diffusion layer 112A through the interlayer insulating film 115 and stress liner film 114, a contact is connected to the 112B and contacts connected to the respective gate stack structure, respectively to. Subsequently, a wiring layer connected to the contact layer on the interlayer insulating film 115.

As described above, according to the first embodiment, the etch stop layer 107 made of TiN in the n-type gate stack structure constituting the nMIS, nitrogen-rich etch stop after removal of the polysilicon film 108 thereon to the film 107A, oxide on the etch stop layer 107A is replaced with nitride. Thus, the oxidation of the Nch work function metal laminated film 117A which shifts the value of the effective work function is prevented, it is possible to prevent deterioration and variation in the deterioration and the gate capacitance of the threshold voltage of the nMIS.

Moreover, in removing the polysilicon film 108 from the n-type gate stack structure, to mask each pMIS region 100B of p-type gate stack structure, to lower the operating characteristics and production yield of the pMIS having p-type gate stack structure that there is no.

(Second Embodiment)
Hereinafter, a semiconductor device will be described with reference to FIGS. 8 and 9 according to the second embodiment of the present invention. 8 and 9, by the same reference numerals are assigned to the same components as in FIG. 4, the description thereof is omitted.

In the first embodiment, it is applied to the gate-last process against nMIS, in the second embodiment, even for pMIS, in order to improve control of the effective work function of the pMIS, gate to apply the last process.

First, as described in the first embodiment, after the step of FIG. 7 (c), by CMP to remove the excess of the buried metal material film 119 deposited on the interlayer insulating film 115, in the pMIS region 110B exposing the polysilicon film 108 from the p-type gate stack.

Subsequently, as shown in FIG. 8 (a), by a known lithography masks the nMIS region 100A, and a resist film 133 to expose the pMIS region 100B. Subsequently, by wet etching, the resist film 133 as a mask, and the etch stop layer 107 of p-type gate stack structure as a stopper to remove the polysilicon film 108 from the p-type gate stack structure. At this time, as a result of the polysilicon film 108 is removed, the p-type gate stack structure, and the wall surface of the offset spacer film 109 facing each other, a groove portion 132B of the etch stop layer 107 exposed to the bottom surface is formed. Then, while leaving the etch stop layer 107, the resist film is removed 133. Note that when removing the polysilicon film 108, as in the case of nMIS, no etching damage, and a high selectivity between the silicon oxide, removal by washing with tetramethylammonium hydroxide (TMAH) solution It is desirable

Next, as shown in FIG. 8 (b), on the etch stop layer 107 which is exposed from the groove 132B, forming the Pch work function metal film 117B. Specifically, by ALD or PVD method so as to cover the wall surfaces made of a bottom surface and offset spacer film 109 of the etch stop film 107 of the groove 132B, on such stress liner film 114 has upper and exposure of the interlayer insulating film 115 entirely over, for example, the film thickness is deposited Pch work function metal film 117B made of titanium nitride of about 2nm ~ 10nm (TiN) to. Incidentally, Pch work function metal layer 117B, in addition to TiN, it is possible to use titanium aluminum (TiAlN) or tantalum nitride nitride (TaN) and the like.

Incidentally, with respect to the etch stop layer 107A in nMIS, but subjected to a nitriding treatment, for the etch stop layer 107 in the pMIS, it is not necessary to perform the nitriding treatment. This is because when subjected to nitriding treatment the p-type gate stack structure pMIS, because the value of the effective work function is decreased. Moreover, the high dielectric constant film 106, further by nitrogen is mixed into the semiconductor substrate 101, negative bias temperature is because (NBT Negative Bias Temperature) characteristic may be deteriorated.

Next, as shown in FIG. 8 (c), the ALD method, a sputtering method or the like, so that the groove 132B is embedded on the entire surface of the TiN film 117B, the metal embedded tungsten (W) or aluminum (Al) the material film 119 is deposited. Note, again, before forming the buried metal material film 119 may be formed underlay film 118 made of TiN.

Next, by CMP, polishing is performed with respect to the formed buried metal material film 119 and Pch work function metal layer 117B, exposing the metal material film 119A embedded in the n-type gate stack structure. Thus, only the groove 132B of the p-type gate stack structure, the Pch work function metal layer 117B and buried metal material film 119 remains, as shown in FIG. 9, the upper portion of the p-type gate stack structure, embedding a metal material film 119B is formed.

Subsequently, a CVD method, or the like on the interlayer insulating film 115 including the gate stack structure, forming a liner nitride film 121 to obtain the semiconductor device shown in FIG.

Thereafter, although not shown, a contact layer connected to the contact and the gate stack structure connected through the interlayer insulating film 115 and stress liner film 114 the source drain diffusion layers 112A, 112B and to. Subsequently, a wiring layer connected to the contact layer on the interlayer insulating film 115.

Thus, according to the second embodiment, it is possible to prevent deterioration and variation in the deterioration and the gate capacitance of the threshold voltage of the nMIS, thereon, it is possible to improve the controllability of the effective work function of pMIS it can.

In the second embodiment, to form a metal material film 119A buried by removing the polysilicon film 108 above the n-type gate stack structure nMIS, followed by polysilicon a p-type gate stack structure pMIS was formed a metal material film 119B buried by removing the membrane 108, on the contrary, it may be formed a metal material film 119B buried first from pMIS.

(A modification of the second embodiment)
Hereinafter, a semiconductor device will be described with reference to FIG. 10 according to a modification of the second embodiment of the present invention. 10, a description thereof will be omitted by retaining the same reference numerals to the same components as FIG.

In the second embodiment, the CMP process for the metal material film 119 buried in the formation of n-type gate stack structure after the FIG. 7 (c), the formation of p-type gate stack structure after shown in FIG. 8 (c) It is performed twice CMP process and CMP process for the metal material film 119 buried at.

This modification, embedded against metal material film 119 by performing a one CMP process, respectively configured to form the buried metal material film 119A and pMIS of the buried metal material film 119B of nMIS. Thus, it is possible to reduce variation in height and resistance of each gate electrode in the semiconductor substrate (wafer) 101 in the plane.

First, it is shown in the first embodiment, after the step of FIG. 7 (b), i.e., after the plasma nitridation process on the etch stop layer 107 in the n-type gate stack structure, by a PVD method, the bottom surface of the groove 132A and on the interlayer insulating film containing the wall, forming a Nch work function metal laminated film 117A.

Subsequently, as shown in FIG. 10 (a), on the Nch work function metal laminated film 117A, for example, by PVD, a conductive film 122A made of TiN or the like. At this time, the thickness of the conductive film 122A is set to 5nm approximately on and on the walls bottom, so as not to fill the groove 132A. Incidentally, to form a conductive film 122A on the Nch work function metal laminated film 117A is to protect the Nch work function metal laminated film 117A. Subsequently, a resist film is applied on the conductive film 122A, by lithography, the entire surface is exposed to the resist film 134.

Next, as shown in FIG. 10 (b), when developing the resist film 134, the resist film 134 remains in the groove 132A. Subsequently, by etching to remove the deposited conductive films 122A and Nch work function metal laminated film 117A on the interlayer insulating film 115 with an acidic solution or the like. Then, by lithography, to form a resist film 135 for masking the nMIS region 110A in the interlayer insulating film 115. Subsequently, by wet etching, the resist film 135 as a mask, and the etch stop film 107 as a stopper to remove the polysilicon film 108 in the p-type gate stack structure. Thus, the p-type gate stack structure, and the wall surface of the offset spacer film 109 facing each other, a groove portion 132B of the etch stop layer 107 exposed to the bottom surface is formed. Subsequently, the resist film 134 and 135 is removed by ashing, further performs cleaning using a mixed solution (SPM) of sulfuric acid and hydrogen peroxide solution to remove the resist residues.

Next, as shown in FIG. 10 (c), by an ALD method or a PVD method, the fill groove 132A of the n-type gate stack structure, the interlayer insulating comprising a bottom and walls of the groove 132B of p-type gate stack structure film 115 on top of, the formation of the Pch work function metal film 117B made of TiN. Subsequently, by an ALD method or a sputtering method, deposition on the entire surface of the Pch work function metal layer 117B, so that the groove 132B is embedded, the metal material film 119 buried tungsten (W) or aluminum (Al) to.

Then, by CMP, polishing is performed with respect to the formed buried metal material film 119 and Pch work function metal layer 117B, to expose the stress liner film 114. Thus, the n-type gate stack structure and a p-type gate stack structure is a metal gate structure together.

Thereafter, a CVD method, or the like on the interlayer insulating film 115 including the gate stack structure, forming a liner nitride film 121 to obtain a semiconductor device substantially equivalent to the second embodiment.

According to this modification, it is possible to dispense with one of the CMP process for embedding the metal material film 119. Therefore, on can significantly improve the in-plane variation in the height of the gate electrode, it is possible to thin the interlayer insulating film 115. When the interlayer insulating film 115 is thinned, generation of voids when embedding the gate stack structure, and it is possible to reduce the occurrence of during CMP occurs dishing, film stress liner film 114 decreases also decreases. Therefore, to improve the degree of freedom of the integration.

As described above, according to the first and second embodiments and modifications thereof of the present invention, it is possible to reliably control the effective work function value of nMIS, reduce the operating characteristics and manufacturing yield in pMIS it is possible to realize a semiconductor device is not be.

A semiconductor device and a manufacturing method thereof according to the present invention, since oxidation of the metal gate constituting the nMIS transistor is prevented, it is possible to eliminate the deterioration and variation in the deterioration and the gate capacitance of the threshold voltage, the high dielectric constant film to be useful for a semiconductor device or the like having a transistor and a metal gate electrode has a stacked gate structure.

10 p-well 11 gate insulating film 12A (nitrogen-rich) etch stop layer 12 etch stop layer 13 n-type source drain diffusion layer 14 sidewalls 15 silicide layer 16 stress liner film 17 interlayer insulating film 18 Al / Ti film 19 electrode formation film 100A nMIS region 100B pMIS region 101 semiconductor substrate 102 element isolation region 103 p-well 104 n-well 105 surface silicon oxide film 106 a high dielectric constant (high-k) film 107 etch stop layer (fourth metal film)
107A (nitrogen-rich) etch stop film (first metal film)
108 polysilicon film 109 offset spacer film 110A n-type extension diffusion layer 110B p-type extension diffusion layer 111 side wall 112A p-type source drain diffusion layer 112B n-type source drain diffusion layer 113 a silicide layer 114 stress liner film 115 interlayer insulating film 116 of titanium oxide 117A Nch work function metal laminated film 117B Pch work function metal layer (fifth metal film)
118 underlay film 119 buried metal material film (third metal film)
119A embedded metal material film 119B buried metal material film 120 silicide layer 121 liner nitride film 122A conductive film 130 hard mask layer 131 resist film 132A groove 132B groove 133 resist film 134 resist film 135 resist film

Claims (13)

  1. On a semiconductor substrate, a high dielectric constant film, sequentially forming a first metal film and the silicon film (a),
    The silicon layer, the first metal film and the high dielectric constant film is etched, (b) forming a first gate pattern and a second gate pattern,
    As a mask the first gate pattern, forming a first source drain region of the first conductivity type in the semiconductor substrate and (c),
    As a mask the second gate pattern, forming a second source drain region of the second conductivity type in the semiconductor substrate and (d),
    Later than the steps (c) and (d), on the semiconductor substrate, said first gate pattern and a second step of forming an interlayer insulating film to cover the gate pattern (e),
    While masking the upper region of the second gate pattern in top of the interlayer insulating film, the first step of removing the silicon film in the gate pattern the first metal film as an etch stop layer (f )When,
    Later than the step (f), and step (g) performing the nitriding process on the first metal film exposed from the interlayer insulating film,
    Later than said step (g), on the first the first metal film nitrided in the gate pattern, and (h) forming a second metal film,
    And a step (i) of forming a third metal film on the second metal film,
    The second metal film, a method of manufacturing a semiconductor device for adjusting the value of the effective work function of the third metal film.
  2. According to claim 1,
    It said first conductivity type is n-type, a method of manufacturing a semiconductor device wherein the second conductivity type is p-type.
  3. According to claim 2,
    The second metal film, a method of manufacturing a semiconductor device is a laminated film of aluminum and titanium and titanium nitride.
  4. In any one of claims 1 to 3,
    The first metal film, a method of manufacturing a semiconductor device made of titanium nitride.
  5. In any one of claims 1 to 4,
    The nitriding treatment, a method of manufacturing a semiconductor device is a plasma nitriding or radical nitridation process in the step (g).
  6. In any one of claims 1 to 5,
    The high dielectric constant film, hafnium, zirconium and a method of manufacturing a semiconductor device which is an insulating film containing at least hafnium or zirconium in the silicon.
  7. In any one of claims 1 to 6,
    Between the step (e) and said step (f), to flatten a top surface of the interlayer insulating film, from the interlayer insulating film, the step of exposing the first gate pattern and a second gate pattern ( j) further comprising a,
    In the step (h), the second metal film, the interlayer insulating film above is formed by removal of the silicon film, the bottom surface of the groove to the bottom surface of the upper surface of the first metal film nitrided and a method of manufacturing a semiconductor device to be formed on the wall surface.
  8. In any one of claims 1 to 7,
    Between said step (e) and said step (f), or between the step (h) and said step (i),
    While masking the upper region of the first gate pattern in top of the interlayer insulating film, a step (k) removing the silicon film in the second gate pattern,
    The step after the (k), on the first metal film in the second gate patterns, further comprising a step (l) forming a fourth metal film,
    In the step (i), the third metal film, a method of manufacturing a semiconductor device is also formed on the fourth metal film in the second gate pattern.
  9. In any one of claims 1 to 8,
    The step of forming the step (c) and prior to later and the step (e) to the step (d), the silicide layer on the first source drain region and the second source drain region (m method for manufacturing a) further comprising in that the semiconductor device.
  10. Formed in a semiconductor substrate, a semiconductor device including a first transistor of a first conductivity type and a second transistor of a second conductivity type,
    It said first transistor has a first gate pattern having a high dielectric constant film that are sequentially formed on a semiconductor substrate, a first metal film made of titanium nitride, the second metal film and the third metal film have,
    It said second transistor has a second gate pattern having the said high dielectric constant film are sequentially formed on a semiconductor substrate, a fourth metal film made of titanium nitride, silicon film,
    The second metal film, a gate length direction of the cross section is concave,
    The value of the composition ratio of nitrogen to titanium of the first metal film is 1.2 or more,
    And the value of the composition ratio of nitrogen to titanium of the fourth metal film semiconductor device is less than 1.2.
  11. According to claim 10,
    It said first conductivity type is n-type, the second conductivity type is p-type,
    The second metal film, a semiconductor device is a laminated film of aluminum and titanium and titanium nitride.
  12. According to claim 10 or 11,
    The second gate pattern, the formed on the fourth metal film, a semiconductor device having a gate length direction of the cross section has a fifth metal film composed of concave titanium nitride.
  13. In any one of claims 10-12,
    Wherein the first gate pattern and the second metal film, a semiconductor device is directly formed without an intervening titanium oxide on the first metal film.
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