WO2012084751A1

WO2012084751A1 - Vertical memory devices

Info

Publication number: WO2012084751A1
Application number: PCT/EP2011/073149
Authority: WO
Inventors: Pieter Blomme
Original assignee: Interuniversitair Microelektronica Centrum vzw IMEC
Current assignee: Interuniversitair Microelektronica Centrum vzw IMEC
Priority date: 2010-12-23
Filing date: 2011-12-16
Publication date: 2012-06-28
Anticipated expiration: 2013-06-23

Abstract

Described herein is a vertical memory device (200) which has a reduced contact area (204) when compared to memory cell area (207). The memory device (200) comprises a memory cell area (207) and a contact area (204) formed on a substrate, the memory cell area (207) having a plurality of memory cells (203) formed therein and a plurality of local wordlines (202) connected to the plurality of memory cells (203). The contact area (204) comprises at least one global wordline (201 ) and a stack (206) of transistors (205) connected to one of the global wordlines (201) and to the plurality of local wordlines (202) in the memory cell area (207).

Description

VERTICAL MEMORY DEVICES

Field of the Invention

The present invention relates to vertical memory devices, and is more particularly, although not exclusively, concerned with three dimensional stacked memory devices and a method for making such devices.

Background to the Invention

There is a continuous need for increasing bit density and reducing bit cost in memory devices, and new alternatives are being proposed for ultra-high density memory technologies, such as, three- dimensional (3D) stacked memories. One possible solution for multi- stacked memories is to use Bit Cost Scalable (BiCS) technology as described by Tanaka et al. in "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory", VLSI Technology Symposium 2007. In BiCS technology, a multi-stacked memory array is formed by so-called punch and plug. A whole stack of electrode plates is punched through and plugged by another electrode material.

In such multi-stacked memory arrays, a large number of wordlines may be stacked on top of one another in order to have a number of vertical strings of transistors in series that do not require more chip area than a single transistor. Whilst this yields a very compact memory array, outside the memory cell area, it is necessary to provide individual contacts for each local wordline, that is, each control gate. The space required for these contacts increases linearly with the number of wordline layers.

Ideally, for a conventional BiCS three-dimensional vertical memory device, the contact area should be kept as small as possible compared to the memory cell area. Therefore, one way of meeting this criterion is to make the local wordline, that is, the conductive plates or conductive layers of the stack of alternating dielectric and conductive layers in the memory cell area longer by putting more memory cells in the memory cell area. However, this has the disadvantage that reliability of the memory device decreases since the memory cells may interfere with one another.

Summary of the Invention

It is therefore an object of the present invention to provide a memory device that has increased reliability.

It is also an object of the present invention to provide a compact memory array with reduced space for contacts for the wordlines.

It is a further object of the present invention to provide a vertical non-volatile memory device.

It is another object of the present invention to provide a method for making a vertical non-volatile memory device.

In accordance with a first aspect of the present invention, there is provided a method for manufacturing a vertical memory device, the method comprising the steps of:- a) providing a semiconductor substrate; b) defining at least one memory cell area on the semiconductor substrate; c) forming a plurality of memory cells in the memory cell area; d) defining a plurality of local wordlines in at least each memory cell area; e) connecting the plurality of local wordlines to the plurality of memory cells; and f) defining at least one contact area on the semiconductor substrate; characterised in that the method further comprises the steps of:- g) forming at least one global wordline in each contact area; h) forming a stack of transistors in each contact area; and i) connecting each local wordline to one of the global wordlines via the stack of transistors.

By forming a stack of transistors in each contact area, it is possible to reduce the size of the contact area with respect to the memory cell area. In particular, the contacts are made in a vertical direction via the stack of vertically arranged transistors. This means that the size of the memory device itself can be scaled down whilst allowing the number of gate plates or wordlines within a three-dimensional stacked memory device to be increased without increasing the contact area required to provide the necessary contacts with the gate plates or wordlines.

Moreover, the method of the present invention provides a vertical memory device with increased reliability and performance when compared with conventional three-dimensional memory devices, such as, BiCS devices discussed above.

In one embodiment, step a) may further comprise forming a first stack of first conductive layers and dielectric layers on the semiconductor substrate, the first conductive layers alternating with the dielectric layers within the first stack.

In this case, step c) may comprise forming each memory cell by providing a vertical hole through the first stack of alternating first conductive layers and dielectric layers. Additionally, step c) may further comprise forming a dielectric layer on a sidewall of each vertical hole, and forming a channel region within each dielectric layer lined vertical hole.

In another embodiment, step h) may comprise forming at least one vertical trench through the first stack of alternating layers, replacing the first conductive layers with second conductive layers of a different material, and forming a gate stack in each vertical trench and on top of the stack of alternating layers. In this embodiment, the step of replacing the first conductive layers may comprise removing the first conductive layers to create cavities in the first stack of alternating layers, and refilling the cavities with the different material to form a second stack of alternating layers.

The first conductive layers of the stack of layers preferably comprise a conductive material, such as, for example, polysilicon, more preferably highly doped polysilicon or a metal. By the term "highly doped" is meant a material which has a doping concentration that is higher than 1 e18/cm³, more preferably higher than 1 e20/cm³.

The second conductive layers comprise a different material which is preferably a semiconducting material, more preferably a lowly- doped semiconducting material. The lowly doped semiconducting material has preferably a doping concentration lower than 1 e19/cm³, more preferably a doping concentration lower than 1 e18/cm³. The lowly doped semiconducting material may, for example, have a doping concentration in the range of 1 e16/cm³ to 1 e19/cm³. Examples of materials that can be used for the second conductive layers include, but are not limited to, silicon or silicon germanium.

As used herein, the values of 1 e16/cm³, 1 e18/cm³, 1 e19/cm³, 1 e20/cm³ etc. refer to concentrations of the order of 10¹⁶/cm³, 10¹⁸/cm³, 10¹⁹/cm³, 10²⁰/cm³ etc.

In one embodiment, the step of removing the first conductive layers may comprise etching the first conductive layers via each vertical trench.

It is preferred that the step of forming a gate stack comprises forming a gate dielectric layer along and in direct contact with sidewall surfaces of each vertical trench and on top of the stack of alternating layers, and forming a gate conductive layer in direct contact with the gate dielectric layer. As mentioned above, each second conductive layer preferably comprises a semiconducting material.

In accordance with another aspect of the present invention, there is provided a vertical memory device comprising: a semiconductor substrate; a memory cell area formed on the substrate, the memory cell area having a plurality of memory cells formed therein and a plurality of local wordlines connected to the plurality of memory cells; and a contact area formed on the substrate;

characterised in that the contact area comprises at least one global wordline and a stack of transistors connected to at least one of the global wordlines; and in that the stack of transistors is connected to the plurality of local wordlines in the memory cell area.

By forming a global wordline within the vertical memory device, compact connections are provided between the local wordlines, the stack of transistors and hence the global wordline.

In an embodiment, the stack of transistors may further comprise a stack of alternating channel layers and the dielectric layers, each channel layer corresponding to a channel region of one of the transistors in the stack of transistors.

Additionally, a gate stack may be located between the stack of alternating channel layers and dielectric layers, the gate stack being in contact with each channel region of the stack of transistors and comprising a gate dielectric layer in direct contact with each channel region of the transistors and a gate conductive layer in direct contact with the gate dielectric layer.

Furthermore, the memory cell area may also comprise alternating conductive layers and dielectric layers, the dielectric layers of the memory cell area being in common with the dielectric layers forming the stack of transistors in the contact area. In this case, the conductive layers in the memory cell area form gate electrode layers that may lie in the same plane as the channel layers of the contact area. It is preferred, although not essential, that the conductive layers in the memory cell area comprise a first conductive material which is different to a second conductive material forming the channel layers of the transistors in the contact area.

In another embodiment, the vertical memory device may comprise a three-dimensional vertical memory array.

This means that the present invention has the advantage that scaling of the semiconductor memory device is possible as the contact area is substantially the same regardless of the capacity of the memory device. The capacity of the memory device can be increased by providing more conductive layers so that a greater number of memory cells can be formed within the device.

Brief Description of the Drawings

For a better understanding of the present invention, reference will now be made, by way of example only, to the accompanying drawings in which:-

Figure 1 illustrates a side perspective view of a state-of-the art vertical memory device;

Figure 2 illustrates a top view of the state-of-the art vertical memory device shown in Figure 1 ;

Figure 3 illustrates a schematic top view of a vertical memory device in accordance with the present invention;

Figure 4 illustrates a flow diagram of a method for manufacturing a vertical memory device in accordance with the present invention; and

Figures 5 to 12 respectively illustrate schematically different manufacturing steps of the method for manufacturing a vertical memory device shown in Figure 4. Description of the Invention

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes.

It will be understood that the terms "vertical" and "horizontal" are used herein refer to particular orientations of the Figures and these terms are not limitations to the specific embodiments described herein.

The terms "first", "second" and the like in the description are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein may be capable of operation in sequences other than those described herein.

Moreover, the terms "top", "bottom", "over", "under" and the like in the description are used for descriptive purposes and not necessarily for describing relative positions. The terms so used are interchangeable under appropriate circumstances and the embodiments of the invention described herein can operate in other orientations than described or illustrated herein. For example, "underneath" and "above" an element indicates being located at opposite sides of this element.

Certain inventive embodiments of the present invention will be described with reference to a silicon (Si) substrate, but it should be understood that these inventive aspects apply equally well to other semiconductor substrates. In the described embodiments, the "substrate" may include a semiconductor substrate, such as, for example, a silicon, a gallium arsenide (GaAs), a gallium arsenide phosphide (GaAsP), an indium phosphide (InP), a germanium (Ge), or a silicon germanium (SiGe) substrate. The "substrate" may include for example, an insulating layer such as a S 1O2 or a S13N4 layer in addition to a semiconductor substrate portion. Thus, the term "substrate" also includes silicon-on-glass, silicon-on-sapphire substrates, and can be used to define generally the elements for layers that underlie a layer or portions of interest. In addition, the "substrate" may be any other base on which a layer is formed, for example, a glass or metal layer. Accordingly, a substrate may be a wafer, such as, a blanket wafer, or may be a layer applied to another base material, for example, an epitaxial layer grown onto a lower layer.

Figures 1 and 2 illustrate respectively side perspective and top views of a state-of-the art vertical memory device 100 comprising a memory cell area 1 10 and a contact area 120 as described, for example, in the article by Tanaka et al. mentioned above. The memory cell area 1 10 comprises an array of vertical cells 130 connected with bitlines 140. Here, memory cells are stacked on top of one another with three control electrode gate plates 150, 160, 170 and two select electrode gate plates 180, 190. Each control electrode gate plate or wordline 150, 160, 170 is connected in the contact area 120. This may be done, as shown, by using contact paths or lines 195. In order to be able to contact each control electrode gate plates 150, 160, 170, the size of each control electrode gate plate decreases in size from bottom to top as shown thereby enabling each control electrode gate plate to be connected to a contact path or line 195. It can readily be seen this requires a large chip area. For a half minimum pitch size F, at least a space equal to 4F²x#CG (where #CG is the number of control electrode gate plates 150, 160, 170, 180) is required. Suppose, for example, a 32nm technology node (thus F=32nm) and a stack of 32 control gate layers (thus #CG=32), at least 4^*32^*32²nm² (about 131072nm²) is needed to contact each wordline.

According to a specific embodiment of the present invention, the channel layers of the contact area comprise a semiconducting material, more preferably, a lowly-doped semiconducting material. The lowly doped semiconducting material has preferably a doping concentration lower than 1 e19/cm³, more preferably a doping concentration lower than 1 e18/cm³. The lowly doped semiconducting material may, for example, have a doping concentration in the range of 1 e16/cm³ to 1 e19/cm³. Such a semiconducting material may, for example, comprise silicon or silicon germanium.

Figure 3 shows a schematic top view of vertical memory device 200 according to an embodiment of the present invention as described in more detail below. The vertical memory device 200 comprises a memory cell area 207 and a transistor contact area 204. A number of memory cells (comprising the vertical channel regions 203) are provided in the memory cell area 207. A series of strings of memory cells 203 is connected with a stack of local wordlines 202. In Figure 3, on each layer of the stack of wordlines 202, three local wordlines are formed next to each other, each local wordline connecting 40 memory cell strings 203. It will be appreciated that only one local wordline 202 is referenced for clarity but it will be appreciated that each local wordline is substantially identical. These local wordlines 202 are connected to a global wordline 201 via a transistor 205 in the transistor contact area 204. As shown, a stack 206 of transistors 205 is provided in the contact area 204 and a gate stack 208 is formed in trenches in between the stack 206 of transistors 205. By forming a series or stack of transistors 205 in the transistor contact area 204, the stack of local wordlines 202 may easily be connected to a single stack of global wordlines 201 . Again, only one stack 206 of transistors 205 has reference numerals but it will be appreciated that there is one stack 206 of transistors and gates for each local wordline 202.

It will be appreciated that although three local wordlines 202 and their associated stacks 206 of transistors 205 and gate stacks 208 are shown in Figure 3, there may be any suitable number of local wordlines 202 and associated stacks 206 may be provided in the memory device 200.

Referring now to Figure 4, a flow diagram 400 illustrating the steps of manufacturing a vertical memory device 200 described above with reference to Figure 3 is shown. When describing the manufacturing steps, reference will also be made to Figures 5 to 12 where necessary. As described above with reference to Figure 3, the vertical memory device 200 comprises a memory cell area 207 and a contact area 204. The manufacturing steps described herein are directed to the formation of the contact area 204, whereas, for the formation of the memory cell area 207, techniques known by a person skilled in the art may be used, such as, for example, the punch-through technique as described by Tanaka et al. discussed above.

The first step 405 in the flow diagram is that of providing a semiconductor substrate 500 as shown in Figure 5. The semiconductor substrate 500 comprises a semiconducting material which may be monocrystalline or single crystalline. By the term "monocrystalline" or "single crystalline" material is meant a material having a crystal lattice which is continuous over the entire sample and unbroken up to the edges of the sample, with no grain boundaries. Alternatively, the semiconducting material may be polycrystalline. By the term "polycrystalline" material is meant a material consisting of a plurality of small crystals of material. For example, polycrystalline silicon is a material consisting of a plurality of small silicon crystals. Additionally, the semiconducting material may be amorphous. By the term "amorphous" is meant a non-crystalline allotropic form of the semiconducting material. For example, silicon may be amorphous (a-Si), monocrystalline or polycrystalline.

In an alternative embodiment, the substrate 500 may be a semiconducting-on-insulating substrate, such as, for example, a silicon- on-insulator (SOI) substrate. Several of the manufacturing steps may occur simultaneously during the formation of the memory cell area 207, both the memory cell area 207 and a contact area 204 being defined in the semiconductor substrate 500.

A stack 520 of layers 501 , 502a, 502b, 502c, 503, 504a,

504b, 504c, 504d, 504e is provided on the semiconductor substrate 500 in both the memory cell area and the contact area in step 410. In Figure 5, a schematic side view of the stack 520 of layers 501 , 502a, 502b, 502c, 503, 504a, 504b, 504c, 504d, 504e in the contact area is shown. The stack 520 of layers 501 , 502a, 502b, 502c, 503, 504a, 504b, 504c, 504d, 504e comprises alternating conductive layers 501 , 502a, 502b, 502c, 503 and dielectric layers 504a, 504b, 504c, 504d, 504e.

In the memory cell area, the same stack of layers is present and may be subdivided into at least a lower stack of layers, a middle stack of layers and an upper stack of layers. The lower stack of layers comprises a lower conductive layer 501 formed on a lower dielectric layer 504a on the semiconducting substrate 500. The middle stack of layers comprising at least one middle conductive layer 502a, 502b, 502c formed on a middle dielectric layer 504b, 504c, 504d, the lowest of the middle dielectric layer 504b being formed on the lower stack of layers. The upper stack of layers comprising an upper dielectric layer (not shown) formed on an upper conductive layer 503 formed on the middle stack of layers.

Each of the middle conductive layers 502a, 502b, 502c in the memory cell area 207 is also referred to as a local wordline of the vertical memory device 200 (Figure 3).

In the contact area 204, the stack of alternating conductive and dielectric layers will define a stack 206 of transistors 205 (Figure 3) after further processing. Each of the conductive layers 501 , 502a, 502b, 502c, 503, after being replaced by another conductive material, will act as a channel region of each transistor 205 of a stack of transistors 206 (Figure 3) as will be described in more detail below. In this way, each transistor will then be isolated from other adjacent transistors by the dielectric layers.

Having formed the stack 520 of layers 501 , 502a, 502b, 502c, 503 504a, 504b, 504c, 504d, 504e, a hard mask layer 505 can be formed on the top of the stack 520 before the memory cell area 207 and the contact area 204 are defined in steps 415, 420 respectively.

In order to manufacture a three-dimensional memory device, a vertical transistor with a deposited channel is necessary for the memory cell area 207. For this, a vertical stack of layers, that is, a stack of gate plates is formed. Each gate plate acts as a control gate except for the lowest gate plate, lower conductive layer 501 , which takes a role of lower select gate, and the highest gate plate, upper conductive layer 503, which takes a role of upper select gate. In between the lower and upper select gates, a number of control gate plates are provided by middle conductive layers 502a, 502b, 502c. The number of control gate plates, namely, the number of middle conductive layers 502a, 502b, 502c, determines the bit density of the memory device. By adding more middle conductive layers or control gate plates, the bit density may be increased without adding more complexity to the process flow of the memory device.

It will be appreciated that, in the simplest embodiment of the present invention, the stack of layers comprises at least three conductive layers, one of which comprises a lower conductive layer that forms a lower select gate, one of which comprises an upper conductive layer that forms an upper select gate, and one of which comprises a middle conductive layer that forms a control gate. However, it will be appreciated that more than one middle conductive layer may be formed. For an excellent performance of the memory device, the middle stack of layers preferably comprises between about 8 and 128 middle conductive layers, each layer being separated from one another by a middle dielectric layer.

The stack of layers 520 in the contact area 204 and the memory cell area 207 (step 410) may be formed simultaneously using standard deposition techniques well known for a person skilled in the art, such as, for example, chemical vapour phase deposition (CVD) and more particularly, low pressure CVD (LPCVD).

The conductive layers of the stack of layers comprise a conductive material, such as, for example, polysilicon, more preferably highly doped polysilicon or a metal. By the term "highly doped" is meant higher than 1 e18/cm³, more preferably higher than 1 e20/cm³.

In the next steps, step 425 and 430, vertical holes (not shown) and vertical trenches 508 (Figure 6) are provided through the stack of layers in the memory cell area 207 and in the contact area 204 respectively. Figure 6 shows a side sectioned view along A-A' of Figure 3 in the contact area 204 after the step of providing a vertical trench 508 in the stack 520 of layers 501 , 502a, 502b, 502c, 503 504a, 504b, 504c, 504d, 504e, 505. Figure 7 gives a schematic presentation of a side view along B-B' (Figure 3) in the contact area 204 after the step of providing a vertical trench 508 (step 430).

In the memory cell area 207, at least one hole (not shown), preferably a cylindrical opening, is provided in the stack 520 of layers 501 , 502a, 502b, 502c, 503 504a, 504b, 504c, 504d, 504e (step 425) thereby exposing part of the underlying semiconductor substrate 500, the hole comprising a sidewall surface and a bottom surface. In the hole, the channel from the vertical memory device will be formed. Each hole thus forms the opening in which the channel of the vertical memory device will be formed. Holes for the transistor channel are thus punched through the stack of layers. The formation of each hole may be carried out using standard process techniques known to a person skilled in the art, such as, for example, a lithography step comprising forming a hard mask layer 505 on the stack of layers 501 , 502a, 502b, 502c, 503 504a, 504b, 504c, 504d, 504e and a photoresist layer (not shown) on the hard mask layer 505, patterning the hard mask layer 505 by exposing and etching the photoresist layer, removing the photoresist layer, forming the vertical hole in the stack of layers by etching through the stack of layers using the hard mask layer 505, and removing the hard mask layer 505.

It will be appreciated that the hard mask layer 505 may be formed on top of the stack 520 of layers as shown in Figure 5 and removed when necessary.

In the contact area 204, at least one trench 508 is provided in the stack of layers (step 430) thereby exposing part of the underlying semiconductor substrate 500, each trench 508 comprising a sidewall surface 508a and a bottom surface 508b. In a later step, the gate stack will be provided in the trench 508 as will be described in more detail below. The formation of each trench 508 may be carried out using standard process techniques known to a person skilled in the art, such as, for example, a lithography step comprising forming a hard mask layer 505 on the stack of layers 520 and a photoresist layer (not shown) on the hard mask layer 505, patterning the hard mask layer 505 by exposing and etching the photoresist layer, removing the photoresist layer, forming the vertical trench in the stack 520 of layers 501 , 502a, 502b, 502c, 503 504a, 504b, 504c, 504d, 504e by etching through the stack of layers using the hard mask layer 505. The hard mask layer 505 remains present on the stack of layers 520.

It will be appreciated that the hard mask layer 505 may be formed on top of the stack 520 of layers as shown in Figure 5.

The formation of the trenches 508 in the contact area 204 and the holes (not shown) in the memory cell area 207 are preferably carried out in separate process steps. However, it will be appreciated that the trenches 508 and holes may also be formed in a single process step if required. ln each vertical trench 508 in the contact area 204, the gate electrode will be formed for driving each of the transistors 205 as will be described below in more detail.

After the formation of each trench 108 in the contact area 204, the conductive material of the conductive layers 501 , 502a, 502b, 502c, 503 in the stack 520 of layers is replaced by another material, preferably a semiconducting material, more preferably a lowly-doped semiconducting material, in step 435. Replacing the conductive material by another material comprises first removing the conductive material in each conductive layer 501 , 502a, 502b, 502c, 503 to create cavities 509 in between the dielectric layers 504a, 504b, 504c, 504d, 504e of the stack 520 of layers 501 , 502a, 502b, 502c, 503 504a, 504b, 504c, 504d, 504e, 505, as shown in Figures 7 and 8, and next filling the cavities 509 again with the another material 530 as shown in Figures 9 and 10.

Figures 7 and 8 illustrates the views on lines A-A' and B-B' respectively of Figure 3. One trench 508 in the contact area 204 is shown after the step of removing the conductive material from the conductive layers 501 , 502a, 502b, 502c, 503 of the stack 520 of layers (step 435) to create a number of cavities 509 in between the dielectric layers 504a, 504b, 504c, 504d, 504e of the stack of layers 520.

Removing the conductive material of the conductive layers 501 , 502a, 502b, 502c, 503 in the contact area 204 may be done by etching the conductive layers via the trench 508. A wet or dry etch step may be performed. Depending on the type of conductive material to be removed, an appropriate etching method may be chosen. During this etching step, the dielectric layers 504a, 504b, 504c, 504d, 504e of the stack 520 of layers should remain quasi intact, that is, the dielectric layers 504a, 504b, 504c, 504d, 504e are substantially not etched during the step of removing the conductive material.

After removing the conductive material, another material is provided 530 in the created cavities 509 (step 440). The other material is preferably a material which may serve as a good channel material for the stack of transistors 205 in the contact area 204. The other material is preferably a semiconducting material, more preferably a lowly doped semiconducting material, such as, for example, lowly doped poly-silicon. By the term "lowly doped" is meant having a doping concentration lower than 1 e19/cm³, and preferably in the range between 1 e16/cm³ and 1 e19/cm³. The other material may, for example, comprise silicon or silicon germanium.

Providing the other material in the created cavities 509 may be carried out via the trench 508. This may be done using any suitable deposition technique known to a person skilled in the art. Thereafter, the excess of other material in the trench 508 is removed, for example, by anisotropic etching using the hard mask layer 505 as the patterning mask to remove any excess other material in the trench 508.

Figure 9 illustrates a view along lines A-A' (Figure 3). The contact area 204 is shown after the step of replacing the conductive material in the stack 520 of layers with the other material 530. The cavities filled with the other material 530 will serve as the channel regions of the vertical transistors which are formed in the contact area 204.

The initial or first stack of layers 520 with alternating conductive 501 , 502a, 502b, 502c, 503 and dielectric layers 504a, 504b, 504c, 504d, 504e is thus partially replaced to a new or second stack 580 of layers with alternating layers of the other material 530 and dielectric layers 504a, 504b, 504c, 504d, 504e in the contact area 204.

During the step of replacing the conductive material of the stack of layers into another material, the memory device area 207 may be shielded such that the conductive material in the stack of layers in the memory device area 207 remains unchanged.

In Figure 10, a view along line B-B' (Figure 3) for the stack of transistors formed in the contact area 204 is shown. The current flows in a horizontal direction from a source 541 through drain 542 via the channel region 530 which corresponds to the cavity 509 filled with the other material after removing the initial conductive layers 501 , 502a, 502b, 502c, 503. Each source 541 and each drain 542 corresponds to respective ones of the portions of the original conductive layers 501 , 502a, 502b, 502c, 503 remaining after the conductive material has been removed in step 435 as described above.

After formation of the vertical holes (not shown) in the memory cell area 207 and after replacing the conductive material of the stack 520 of layers with the other material 530 in the contact area 204, the gate stack may be formed in the vertical trench and on top of the new stack 580 of layers (step 445). Forming the gate stack comprises providing a gate dielectric layer 570 along and in direct contact with the sidewall surface 508a of the vertical trench 508 and on top of the stack 580 of layers and a gate conductive layer in direct contact with the gate dielectric layer (step 450 described in more detail below).

The stack 570 of gate dielectric layers is formed at the sidewall surface and bottom surface of the hole (not shown) and of the trench 508 for the memory cell area 207 and contact area 204 respectively. The stack of gate dielectric layers formed in the memory cell area 207 and the stack of gate dielectric layers formed in the contact area 204 are preferably not the same.

For the contact area 204, the stack 570 of gate dielectric layers is thus conformally formed in the trench 508. This means that the stack 570 of dielectric layers is provided at the sidewall surface 508a of the trench 508 and on the bottom surface 508b of the trench 508, thereby leaving a cavity in the trench.

The stack 570 of gate dielectric layers for the trench 508 in the contact area 204 preferably comprises for example a silicon oxide layer or a high-k dielectric layer or any other dielectric layer which is suitable to serve as a gate dielectric layer known to a person skilled in the art. For example, for the stack 570 of gate dielectric layers in the contact area 204, there is no need for a trapping layer (which is necessary for the stack of gate dielectric layers formed in the memory cell area 207) and thus the stack 570 of gate dielectric layers in the contact area 204 is not the same as the stack of gate dielectric layers in the memory cell area 207.

In the memory cell area 207, the stack of gate dielectric layers will serve as the gate dielectric and the trapping layer in between the gates (from the stack of layers with control gates and select gates) and the channel region (which will be formed in the hole).

The stack of gate dielectric layers (not shown) for the hole in the memory cell area 207 preferably comprises a dielectric layer with a large density of charge traps, typically 1 e19 traps/cm³, sandwiched in between two dielectric layers with a substantially lower density of charge traps compared to the dielectric layer with a large density of charge traps.. The middle gate dielectric layer is therefore often referred to as the charge trapping layer. Preferably, the stack 570 of gate dielectric layers comprises a nitride containing dielectric layer sandwiched in between two oxygen containing dielectric layers. The stack 570 of gate dielectric layers may for example be a stack of a S13N4 layer sandwiched in between two S 1O2 layers. The stack of gate dielectric layers is also often referred to as an ONO stack, that is, oxygen-nitride-oxygen stack. The stack of gate dielectric layers may for example be a stack of as poly- Si layer sandwiched in between two S1O2 layers. The two outer dielectric layers may also comprise a high-k dielectric layer. The stack of dielectric layers will serve as the gate dielectric layer for the string of vertical transistors 205 formed in the contact area 204 of the vertical memory device 200 (Figure 3).

After the step of providing a gate dielectric layer or stack of gate dielectric layers 570 in the trench 508 of the contact area 204, a conductive layer 521 is deposited (step 450). This is done by filling the remaining part of the trench 508 with a conductive material. Such a conductive material may comprise a metal, such as, for example, TaN, TiN, W, etc.) or polysilicon. The conductive material is preferably a material which is suitable to serve as a gate electrode. This may be done by using techniques such as chemical vapour deposition (CVD), or more preferably low pressure chemical vapour deposition (LPCVD) or atomic layer deposition (ALD).

Figures 1 1 and 12 show respective side views along A-A' and B-B' in the contact area 204 after the step of providing a gate stack electrode which comprises providing a gate dielectric layer and a gate electrode (steps 445 and 450 as described above), the gate dielectric layer and gate electrode together forming the gate stack 208 of the stack 206 of transistors 205 (Figure 3).

The current flows in a horizontal direction perpendicular to the paper plane through the channel regions 530 which are the cavities 509 filled with the other material after removing the initial conductive layers 501 , 502a, 502b, 502c, 503. Furthermore, the vertical gate stack 570 is in contact with the channel region 530 of each of the transistors of the stack 580 of transistors.

In the contact area 204, a stack of transistors is thus formed with a stack of horizontal channel regions 530, a vertical gate stack (comprising a dielectric layer 570 and a gate electrode 521 ) through the stack of layers and horizontal source 541 and drain regions 542 either side of the channel region 530. These horizontal source 541 and drain regions 542 are the remaining parts of the conductive layers of the initial or first stack 520 of layers, as described above, which remain present after the step of creating the cavities 509.

Optionally, an annealing step may be performed in order to drive the dopants from the initial conductive material forming source 541 and drain 542 to the filled conductive material 530 in order to get junctions under the gate despite the undercut of the isotropic etching step (that is, the etching step which may be used to remove the conductive material from the initial or first stack 520 of layers.

As a stack of transistors is provided, the contact area 204 is reduced significantly compared to the contact area in conventional BiCS devices described above.

Stacked transistors are made in the wordlines themselves, that is, the initially formed conductive layers 501 , 502a, 502b, 502c, 503 of the stack 520, so that all transistors for connecting a set of local wordlines to their global wordlines are placed on top of each other, thereby consuming only the same area as for a single device.

Each local wordline may thus be electrically connected or disconnected from the global wordline by operating the gate electrode formed in the contact area 204.

In the memory cell area 207, a dielectric layer is provided along the sidewall of each hole (not shown), in step 455. The hole is then provided with a channel region, in step 460, in the remaining part of the hole so that the hole is substantially filled.

The foregoing description details certain embodiments of the invention. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the invention may be practiced in many ways. It should be noted that the use of particular terminology when describing certain features or aspects of the invention should not be taken to imply that the terminology is being re-defined herein to be restricted to including any specific characteristics of the features or aspects of the invention with which that terminology is associated.

While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the technology without departing from the invention.

Claims

A method for manufacturing a vertical memory device (200), the method comprising the steps of:- a) providing a semiconductor substrate (500);

b) defining at least one memory cell area (207) on the semiconductor substrate (500);

c) forming a plurality of memory cells (203) in the memory cell area (207);

d) defining a plurality of local wordlines (202) in at least each memory cell area (207);

e) connecting the plurality of local wordlines (202) to the plurality of memory cells (203); and

f) defining at least one contact area (204) on the semiconductor substrate (500);

characterised in that the method further comprises the steps of:- g) forming at least one global wordline (201 ) in each contact area (204);

h) forming a stack (206) of transistors (205) in each contact area (204); and

i) connecting each local wordline (202) to one of the global wordlines (201 ) via the stack (206) of transistors (205).

A method according to claim 1 , wherein step a) further comprises forming a first stack (520) of first conductive layers (501 , 502a, 502b, 502c, 503) and dielectric layers (504a, 504b, 504c, 504d, 504e) on the semiconductor substrate (500), the first conductive layers (501 , 502a, 502b, 502c, 503) alternating with the dielectric layers (504a, 504b, 504c, 504d, 504e) within the first stack (520). A method according to claim 2, wherein step c) comprises forming each memory cell (203) by providing a vertical hole through the first stack (520) of alternating first conductive layers (501 , 502a, 502b, 502c, 503) and dielectric layers (504a, 504b, 504c, 504d, 504e).

A method according to claim 3, wherein step c) further comprises forming a dielectric layer on a sidewall of each vertical hole, and forming a channel region within each dielectric layer lined vertical hole.

A method according to any one claims 2 to 4, wherein step h) comprises forming at least one vertical trench (508) through the first stack (520) of alternating layers (501 , 502a, 502b, 502c, 503, 504a, 504b, 504c, 504d, 504e), replacing the first conductive layers (501 , 502a, 502b, 502c, 503) with second conductive layers (530) of a different material, and forming a gate stack (521 , 570) in each vertical trench (508) and on top of the stack (580) of alternating layers.

A method according to claim 5, wherein the step of replacing the first conductive layers (501 , 502a, 502b, 502c, 503) comprises removing the first conductive layers (501 , 502a, 502b, 502c, 503) to create cavities (509) in the first stack (520) of alternating layers, and refilling the cavities (509) with the different material to form a second stack (580) of alternating layers.

A method according to claim 6, wherein the step of removing the first conductive layers (501 , 502a, 502b, 502c, 503) comprises etching the first conductive layers (501 , 502a, 502b, 502c, 503) via each vertical trench (508). A method according to any one of claims 5 to 7, wherein the step of forming a gate stack (521 , 570) comprises forming a gate dielectric layer (570) along and in direct contact with sidewall surfaces (508a) of each vertical trench (508) and on top of the stack (580) of alternating layers, and forming a gate conductive layer (521 ) in direct contact with the gate dielectric layer (570).

A method according to any one of claims 5 to 8, wherein each second conductive layer (530) comprises a semiconducting material.

A vertical memory device (200) comprising:

a semiconductor substrate (500);

a memory cell area (207) formed on the substrate (500), the memory cell area (207) having a plurality of memory cells (203) formed therein and a plurality of local wordlines (202) connected to the plurality of memory cells (203); and

a contact area (204) formed on the substrate (500);

characterised in that the contact area (204) comprises at least one global wordline (201 ) and a stack (206) of transistors (205) connected to at least one of the global wordlines (201 ); and in that the stack (206) of transistors (205) is connected to the plurality of local wordlines (202) in the memory cell area (207).

A vertical memory device according to claim 10, wherein the stack (206) of transistors (205) further comprises a stack (580) of alternating channel layers (530) and the dielectric layers (504a, 504b, 504c, 504d, 504e), each channel layer (530) corresponding to a channel region of one of the transistors (205) in the stack (206) of transistors (205).

A vertical memory device according to claim 1 1 , further comprising a gate stack (521 , 570) located between the stack (580) of alternating channel layers (530) and dielectric layers (504a, 504b, 504c, 504d, 504e), the gate stack (521 , 570) being in contact with each channel region of the stack (206) of transistors (205) and comprising a gate dielectric layer (570) in direct contact with each channel region of the transistors (205) and a gate conductive layer (521 ) in direct contact with the gate dielectric layer (570).

A vertical memory device according to claim 1 1 or 12, wherein the memory cell area (207) comprises alternating conductive layers (501 , 502a, 502b, 502c, 503) and dielectric layers (504a, 504b, 504c, 504d, 504e), the dielectric layers (504a, 504b, 504c, 504d, 504e) of the memory cell area (207) being in common with the dielectric layers forming the stack (206) of transistors (205) in the contact area (204).

A vertical memory device according to claim 13, wherein the conductive layers (501 , 502a, 502b, 502c, 503) in the memory cell area (207) form gate electrode layers that lie in the same plane as the channel layers (530) of the contact area (204).

A vertical memory device according to claim 13 or 14, wherein the conductive layers (501 , 502a, 502b, 502c, 503) in the memory cell area (207) comprise a first conductive material which is different to a second conductive material forming the channel layers (530) of the transistors (205) in the contact area

A vertical memory device according to any one of claims 10 to 15, comprising a three-dimensional vertical memory array.