WO2012055288A1 - 一种自对准金属硅化物的沟槽型半导体器件及制造方法 - Google Patents

一种自对准金属硅化物的沟槽型半导体器件及制造方法 Download PDF

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WO2012055288A1
WO2012055288A1 PCT/CN2011/078878 CN2011078878W WO2012055288A1 WO 2012055288 A1 WO2012055288 A1 WO 2012055288A1 CN 2011078878 W CN2011078878 W CN 2011078878W WO 2012055288 A1 WO2012055288 A1 WO 2012055288A1
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trench
semiconductor device
type semiconductor
self
mask
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PCT/CN2011/078878
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English (en)
French (fr)
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张崇兴
梁安杰
苏冠创
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香港商莫斯飞特半导体有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a trench type semiconductor device and a method of fabricating the same.
  • a self-aligned metal silicide is generally used to improve the sheet resistance of the silicon in the source region, the drain region and the gate region, and the contact resistance between the silicon and the metal to reach the device.
  • Lower on-resistance and gate resistance improve device efficiency.
  • a method for fabricating a gate oxide silicide gate of a metal oxide semiconductor field effect transistor is disclosed in US Pat. No. 2,030, 168, 695 A1, as shown in FIG. 18, in which a conductive polysilicon gate is only used in a trench of a semiconductor field effect transistor.
  • the surface is deposited with a layer of silicide (such as titanium silicide) and then a local thick oxide layer is deposited on the surface.
  • US Patent Publication discloses a semiconductor device and a method of fabricating the same. As shown in FIG. 19, the semiconductor device first divides the gate in the trench into two halves in a vertical direction, with an oxide as an isolation, and then A layer of silicide is deposited on the upper portion.
  • the semiconductor field effect transistor manufactured by the US Pat. No. 2,030,168, 695 A1 has a partially thick oxide layer on the surface of the silicide which causes the surface to be uneven, resulting in uneven thickness of the source metal, which affects the on-resistance consistency of the device.
  • the semiconductor field effect transistor manufactured by the US Patent Publication No. US20070023828A1 has high requirements for trench etching and complicated processes, which makes the polysilicon width difficult to control and affects device uniformity.
  • the present invention provides a self-aligned metal silicide trench type semiconductor device and a manufacturing method thereof, which avoids pollution and consistency caused by related processes by using fewer process steps and masks.
  • the control achieves the consistency of the electrical parameters such as the threshold voltage and the on-resistance.
  • a method of fabricating a self-aligned metal silicide trench type semiconductor device includes the following steps:
  • step 1) further comprises the following steps:
  • the first oxide layer is etched to form a source region mask, and then boron is partially implanted in the exposed epitaxial layer and advanced into the epitaxial layer to form a base region.
  • step 2) further comprises the following steps:
  • step 3 further comprises the following steps:
  • step 3) and step 4 the method further comprises the steps of depositing a lithographic coating and etching it to form a second base mask, implanting boron element.
  • step 3 wherein, between step 3) and step 4), the following steps are further included:
  • step 4) further includes:
  • step 5 further comprises the following steps:
  • step 5 further comprises the following steps:
  • a layer of aluminum-copper alloy is deposited and metal etching is performed through a metal mask to form a source metal pad layer, a gate metal pad layer and a metal wiring.
  • silicide is WSi2, TiSi2, MoSi2 or TaSi2.
  • the invention has obvious advantages and positive effects, and the manufacturing method using the invention adopts a mask plate.
  • the control of pollution and consistency caused by the process is avoided, the manufacturing process of the self-aligned metal silicide trench type semiconductor device is reduced, and the consistency of the threshold voltage and other electrical parameters of the semiconductor device is ensured;
  • the method is simple and easy, and the manufacturing process is easy to implement, so that the quality and reliability of the device are greatly improved.
  • Embodiment 1 is a flow chart of Embodiment 1 of a method for fabricating a self-aligned metal silicide trench-type semiconductor device according to the present invention
  • FIG. 2 is a schematic diagram of depositing a first oxide layer and forming a source region mask in a method of fabricating a self-aligned metal silicide trench-type semiconductor device according to the present invention, and implanting a boron element;
  • FIG. 3 is a schematic view showing a base region and a trench mask formed in a method of fabricating a self-aligned metal silicide trench-type semiconductor device according to the present invention
  • FIG. 4 is a schematic view showing etching of a trench and formation of a second oxide layer in a method of fabricating a self-aligned metal silicide trench-type semiconductor device according to the present invention
  • FIG. 5 is a schematic diagram of implanting a phosphorus element, forming a source region, and a gate (polysilicon) in a method of fabricating a self-aligned metal silicide trench-type semiconductor device according to the present invention
  • FIG. 6 is a schematic view showing a silicide formed on a source region and a polysilicon surface in Embodiment 1 of a method of fabricating a trench-type semiconductor device of a self-aligned metal silicide according to the present invention
  • FIG. 7 is a schematic view showing a deposition and chemical mechanical polishing interlayer medium in Embodiment 1 of a method of fabricating a self-aligned metal silicide trench type semiconductor device according to the present invention
  • FIG. 8 is a schematic view showing a contact hole formed by a contact hole mask in Embodiment 1 of a method of manufacturing a self-aligned metal silicide trench-type semiconductor device according to the present invention
  • FIG. 9 is a schematic view showing a portion of a method for fabricating a trench-type semiconductor device of a self-aligned metal silicide according to the present invention, in which an upper portion of a contact hole is enlarged and P+ is implanted;
  • FIG. 10 is a schematic view showing a metal pad layer and a metal wiring formed in Embodiment 1 of a method for fabricating a self-aligned metal silicide trench type semiconductor device according to the present invention
  • Embodiment 11 is a flow chart of Embodiment 2 of a method of fabricating a self-aligned metal silicide trench-type semiconductor device in accordance with the present invention
  • FIG. 12 is a schematic view showing a method of fabricating a self-aligned metal silicide trench-type semiconductor device according to the present invention in a second embodiment using a second base mask to implant boron;
  • FIG. 13 is a cross-sectional view taken along line B-B' of FIG. 12 after forming a silicide in a second base region and a polysilicon surface in Embodiment 2 of a method of fabricating a self-aligned metal silicide trench-type semiconductor device according to the present invention
  • FIG. 14 is a schematic diagram of a method for fabricating a self-aligned metal silicide trench-type semiconductor device according to the present invention, in which an aluminum-copper alloy is directly deposited on a silicide surface, a metal underlayer is formed, and a metal wiring is formed in FIG. AA' cross-sectional view;
  • Embodiment 15 is a flow chart of Embodiment 3 of a method of fabricating a self-aligned metal silicide trench type semiconductor device in accordance with the present invention.
  • FIG. 16 is a schematic view showing a contact hole formed by a contact hole mask in Embodiment 3 of a method of manufacturing a self-aligned metal silicide trench-type semiconductor device according to the present invention, and implanting boron element;
  • FIG. 17 is a schematic view showing a metal pad layer and a metal wiring formed by a metal mask in Embodiment 3 of a method for fabricating a trench-type semiconductor device of a self-aligned metal silicide according to the present invention
  • Figure 18 is a schematic view of a semiconductor field effect transistor disclosed in the prior art of the prior art (US20030168695A1);
  • Fig. 19 is a schematic view showing a semiconductor device disclosed in the prior art of the prior art (US20070023828A1).
  • Embodiment 1 is a flow chart of Embodiment 1 of a method for fabricating a self-aligned metal silicide trench type semiconductor device according to the present invention, and a method of fabricating a self-aligned metal silicide trench type semiconductor device of the present invention, with reference to FIG. Example 1 is elaborated in detail:
  • a boron element is implanted into the base region using a source region mask.
  • the step includes: forming a first oxide layer (oxide hard mask) by depositing or thermally growing on the epitaxial layer of the substrate, the first oxide layer having a thickness of about 8000 ⁇ ; etching the first oxide layer to form a source region mask And then implanting boron element in the exposed epitaxial layer portion, as shown in FIG. 2; using an annealing operation to push the boron element into the epitaxial layer to form a base region, as shown in FIG. 3;
  • the trench is etched using a trench mask and a second oxide layer is formed.
  • the step includes: forming a screen oxide layer on the surface of the exposed epitaxial layer, depositing a lithographic coating, and etching it to form a trench mask, as shown in FIG. 3; using the trench mask, in the exposed epitaxial layer Partially etching the trench; removing the lithographic coating, and performing sacrificial oxidation on the exposed epitaxial layer portion, the trench sidewall and the bottom surface, and then forming a second oxide layer (gate oxide layer), as shown in FIG. Show
  • step 103 polysilicon is deposited and a phosphorous element is implanted to form a source region.
  • firstly doped polysilicon is deposited in the trench, and the polysilicon is etched back; then, the phosphorus element is implanted, and an annealing operation is used to propagate the diffusion into the base region to form a source region, as shown in FIG. Show
  • a silicide is formed on the source region and the polysilicon surface.
  • the step includes: first, removing the second oxide layer on the surface of the source region; second, depositing the transition metal, performing an annealing operation to react the metal with the single crystal silicon to form a silicide; and third, selectively etching the excess unreacted The transition metal forms silicide on the surface of the polysilicon and the source region.
  • the silicide formed may be WSi2, TiSi2, MoSi2 or TaSi2.
  • a contact hole trench is formed through the contact hole mask.
  • an interlayer dielectric is deposited on the surface of the device and chemically polished to maintain a certain thickness of the interlayer dielectric, as shown in Figure 7.
  • a lithographic coating is deposited on the surface of the interlayer dielectric. And etching it to form a contact hole mask; finally, through the contact hole mask, the interlayer dielectric is etched into the base region by a dry method to form a contact hole trench, as shown in FIG. 8;
  • p+ boron element
  • the interlayer dielectric is first wet-etched through the contact hole mask, then the lithographic coating is removed, and finally P+ is implanted into the contact hole, and the high-temperature annealing operation is used to propagate the diffusion into the base region, such as Figure 9;
  • the contact hole trench is filled to form a trench plug.
  • the contact hole trench is filled with a titanium/titanium nitride layer and a tungsten layer to form a trench plug, and the surface layer is etched to remove the top layer of titanium/titanium nitride and tungsten;
  • a metal underlayer and wiring are formed using a metal mask.
  • a layer of aluminum-copper alloy is deposited on the device and annealed, and then metal etching is performed through a metal mask to form a source metal pad layer, a gate metal pad layer and a metal wiring, as shown in FIG.
  • Embodiment 11 is a flow chart of Embodiment 2 of a method for fabricating a self-aligned metal silicide trench-type semiconductor device according to the present invention, which will be described in detail below with reference to FIG.
  • steps 1101-1103 the manufacturing method is the same as that of the first embodiment, and the steps 101-103 are referred to, and details are not described herein again;
  • step 1104 in this step, first, deposit a layer of lithographic coating, and etch it to form a base mask, and then implant boron element, as shown in FIG. 12;
  • a rapid high temperature annealing operation is then employed to remove the lithographic coating and the second oxide layer on the surface of the source region; a transition metal is deposited, an annealing operation is performed to react the metal with the single crystal silicon to form a silicide; The unreacted transition metal forms silicide in the second base region, the source region and the polysilicon surface.
  • the silicide formed may be WSi2, TiSi2, MoSi2 or TaSi2;
  • an interlayer dielectric is deposited in the trench and etched back
  • an aluminum-copper alloy is deposited on the top layer to directly contact the silicide to form a source metal underlayer, a gate metal underlayer and a metal wiring, as shown in FIG.
  • Embodiment 15 is a flow chart of Embodiment 3 of a method of fabricating a self-aligned metal silicide trench-type semiconductor device according to the present invention, which will be described in detail below with reference to FIG.
  • steps 1501-1503 the manufacturing method is the same as that of the first embodiment, and the steps 101-103 are referred to, and details are not described herein again.
  • a lithographic coating is deposited and etched to form a first contact hole mask; a contact hole trench is formed through the first contact hole mask; boron element (P+) is implanted into the contact hole trench, and is advanced Diffusion into the base area, as shown in Figure 16;
  • the lithographic coating and the second oxide layer on the surface of the source region are removed; the transition metal is deposited, an annealing operation is performed to react the metal with the single crystal silicon to form a silicide; and the excess unreacted transition metal is selectively etched, A silicide is formed on the source region and the surface of the polysilicon, as shown in FIG. 6, the silicide is WSi2, TiSi2, MoSi2 or TaSi2;
  • step 1506 in a first step, an interlayer dielectric is deposited in the trench and etched back; in a second step, a lithographic coating is deposited and etched to form a second contact hole mask; and a third step is to utilize the second contact hole.
  • steps 1507 - 1508 the manufacturing method is the same as that of the embodiment 1, and the steps 107-108 are referred to, and details are not described herein again.
  • the structure of the metal underlayer formed by the metal mask and the metal wiring in the third embodiment is as shown in FIG.
  • the above embodiments are described in the fabrication process of a self-aligned metal silicide N-channel trench type semiconductor power device for the fabrication of a self-aligned metal silicide P-channel semiconductor power device,
  • the main difference is the type of dopant, which can be used to fabricate self-aligned metal silicide P-channel semiconductor devices by the method of the above embodiments, changing the type of dopant.

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Abstract

一种自对准金属硅化物的沟槽型半导体器件及制造方法，该方法包括：利用源区掩模形成基区；利用沟槽掩模蚀刻出沟槽，并沉积多晶硅；注入磷元素，形成源区；在所述多晶硅和源区表面形成硅化物；沉积铝铜合金，形成源极金属垫层，栅极金属垫层和金属连线。本发明的制造方法由于采用了较少的掩模板，减少了自对准金属硅化物的沟槽型半导体器件的制造工序和污染，保证了半导体器件的阈值电压等电参数的一致性。由于本发明的制造方法简单、容易，制造工艺容易实现，使器件的质量以及可靠性得到了较大的提高。

Description

一种自对准金属硅化物的沟槽型半导体器件及制造方法 技术领域
本发明涉及一种半导体器件，尤其涉及一种沟槽型半导体器件及制造方法。
 背景技术
在现有的沟槽型半导体器件制造过程中，通常采用形成自对准金属硅化物来改善在源区、漏区和栅区硅的薄膜电阻以及硅和金属之間的接触电阻，以达到器件更低的导通电阻和栅极电阻，提高器件的效率。
美国专利文献（US20030168695A1）公开了一种金属氧化物半导体场效应晶体管沟槽硅化物栅极的制造方法，如图18所示，该方法中，只在半导体场效应晶体管沟槽的导电多晶硅栅极的表面沉积有一层硅化物（例如硅化钛），然后在其表面沉积局部的厚氧化层。
美国专利文献（US20070023828A1）公开了一种半导体器件及其制造方法，如图19所示，该半导体器件首先把沟槽里的栅极在垂直方向分成两半，中间以氧化物作为隔离，然后在其上部份沉积一层硅化物。
采用公开号为US20030168695A1美国专利文献制造的半导体场效应晶体管，其硅化物表面的局部厚氧化层会使表面不平坦，导致源金属厚度的不均匀,影响了器件的导通电阻一致性，而采用公开号为US20070023828A1美国专利文献制造的半导体场效应晶体管，对沟槽蚀刻的要求高、工序比较复杂，使得多晶硅宽度难以控制，影响了器件的一致性。
 技术问题
为了解决现有技术存在的不足，本发明提供一种自对准金属硅化物的沟槽型半导体器件及制造方法，用较少的工艺步骤和掩模，避免了有关工序造成的污染和一致性的控制，达到阈值电压和导通电阻等电参数的一致性。
 技术解决方案
为了实现上述目的，根据本发明的自对准金属硅化物的沟槽型半导体器件的制造方法，包括以下步骤：
1) 利用源区掩模形成基区；
2) 利用沟槽掩模蚀刻出沟槽，并沉积多晶硅；
3) 注入磷元素，形成源区；
4) 在所述多晶硅和源区表面形成硅化物；
5) 沉积铝铜合金，形成源极金属垫层，栅极金属垫层和金属连线。
其中，所述步骤1）进一步包括以下步骤：
a) 在衬底的外延层上沉积厚度为8000Å左右的第一氧化层；
b) 蚀刻第一氧化层形成源区掩模，然后在暴露的外延层部分注入硼元素，並推进扩散到外延层中形成基区。
其中，所述步骤2）进一步包括以下步骤：
a) 生成屏敝氧化层，沉积光刻涂层，并对其进行蚀刻形成沟槽掩模；
b) 利用沟槽掩模，在暴露的外延层部分蚀刻出沟槽；
c) 移除光刻涂层，并对暴露的外延层部分、沟槽侧壁和底部表面进行牺牲氧化，然后再形成第二氧化层。
其中，所述步骤3）进一步包括以下步骤：
a) 在沟槽中沉积以掺杂的多晶硅，并对多晶硅进行回蚀；
b) 注入磷元素，并采用退火作业将其推进扩散到基区中形成源区。
其中，所述步骤3）和步骤4）之间还包括以下步骤：沉积光刻涂层，并对其进行蚀刻形成第二基区掩模，注入硼元素的步骤。
其中，所述步骤3）和步骤4）之间还包括以下步骤：
a) 沉积并蚀刻光刻涂层，形成第一接触孔掩模；
b) 通过第一接触孔掩模蚀刻出接触孔沟槽；向接触孔沟槽中注入硼元素，并将其推进扩散到基区。
其中，所述步骤4）还包括：
a) 去掉源区表面上的氧化物后；
b) 沉积过渡金属,进行退火作业使金属和单晶硅反应而形成硅化物；
c) 选择性蝕刻多餘的未反应的过渡金属。
其中，所述步骤5）进一步包括以下步骤：
a) 通过接触孔掩模形成接触孔沟槽；
b) 对接触孔沟槽进行填充形成沟槽插塞；
c) 沉积铝铜合金，并进行退火，然后通过金属掩模进行金属浸蚀，形成源极金属垫层，栅极金属垫层和金属连线。
其中，所述步骤5）进一步包括以下步骤：
a) 在沟槽中沉积层间介质并进行回蚀；
b) 沉积并蚀刻光刻涂层，形成第二接触孔掩模；
c) 利用第二接触孔掩模，蚀刻接触孔中的层间介质；
d) 对接触孔沟槽进行填充形成沟槽插塞；
e) 沉积一层铝铜合金，通过金属掩模进行金属浸蚀，使形成源极金属垫层，栅极金属垫层和金属连线。
其中，所述硅化物为WSi2、TiSi2、MoSi2或 TaSi2。
 有益效果
本发明具有明显的优点和积极效果，采用本发明的制造方法由于采用了掩模板, 避免了有关工序造成的污染和一致性的控制，减少了自对准金属硅化物的沟槽型半导体器件的制造工序，保证了半导体器件的阈值电压等电参数的一致性；由于本发明的制造方法简单、容易，制造工艺容易实现，使器件的质量以及可靠性得到了较大的提高。
 附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起，用于解释本发明，并不构成对本发明的限制。在附图中：
图1为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例1流程图；
图2位为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法中沉积第一氧化层并形成源区掩模，注入硼元素示意图；
图3为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法中形成的基区和沟槽掩模示意图；
图4为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法中蚀刻出沟槽及生成第二氧化层示意图；
图5为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法中注入磷元素、形成源区和栅极(多晶硅)示意图；
图6为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例1中源区和多晶硅表面生成的硅化物示意图；
图7为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例1中沉积和化学机械抛光层间介质示意图；
图8为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例1中利用接触孔掩模形成的接触孔示意图；
图9为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例1中扩大接触孔上部份和注入P+后的示意图；
图10为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例1中形成的金属垫层及金属连线示意图；
图11为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例2流程图；
图12为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例2中利用第二基区掩模，注入硼元素后的示意图；
图13为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例2中在第二基区和多晶硅表面生成硅化物后，沿图12中B-B′横切面示意图；
图14为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例2中在硅化物表面直接沉积铝铜合金，形成的金属垫层及金属连线后，沿图12中A-A′横切面示意图；
图15为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例3流程图；
图16为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例3中利用接触孔掩模形成的接触孔并注入硼元素示意图；
图17为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例3中通过金属掩模形成的金属垫层及金属连线示意图；
图18为现有技术中美国专利文献(US20030168695A1)公开的半导体场效应晶体管示意图；
图19为现有技术中美国专利文献（US20070023828A1）公开的半导体器件示意图。
 本发明的实施方式
以下结合附图对本发明的优选实施例进行说明，应当理解，此处所描述的优选实施例仅用于说明和解释本发明，并不用于限定本发明。
实施例1
图1为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例1流程图，下面将参考图1，对本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例1进行详细阐述：
首先，在步骤101，利用源区掩模注入硼元素形成基区。该步骤包括：在衬底的外延层上采用积淀或热生长方式生成第一氧化层（氧化物硬光罩），第一氧化层的厚度约为8000Å；蚀刻第一氧化层形成源区掩模，然后在暴露的外延层部分注入硼元素，如图2所示；采用退火作业将硼元素推进扩散到外延层中形成基区，如图3所示；
在步骤102，利用沟槽掩模蚀刻出沟槽，并生成第二氧化层。该步骤包括：在暴露的外延层表面生成屏敝氧化层，沉积光刻涂层，并对其进行蚀刻形成沟槽掩模，如图3所示；利用沟槽掩模，在暴露的外延层部分蚀刻出沟槽；移除光刻涂层，并对暴露的外延层部分、沟槽侧壁和底部表面进行牺牲氧化，然后再形成第二氧化层（栅极氧化层），如图4所示；
在步骤103，沉积多晶硅，并注入磷元素形成源区。在该步骤中，首先在沟槽中沉积以掺杂的多晶硅，并对多晶硅进行回蚀；然后，注入磷元素，并采用退火作业将其推进扩散到基区中形成源区，如图5所示；
在步骤104，在源区和多晶硅表面生成硅化物。该步骤包括：第一，移除源区表面的第二氧化层；第二，沉积过渡金属,进行退火作业使金属和单晶硅反应而形成硅化物；第三，选择性蝕刻多餘的未反应的过渡金属，在多晶硅和源区表面生成硅化物，如图6所示，形成的硅化物可以是WSi2、TiSi2、MoSi2或 TaSi2。
在步骤105，通过接触孔掩模形成接触孔沟槽。首先，在器件的表面沉积一层层间介质，并对其进行化学机械抛光处理，使层间介质保持一定厚度，如图7所示；其次，在层间介质表面沉积一层光刻涂层，并对其进行蚀刻，形成接触孔掩模；最后，通过接触孔掩模，利用干法由层间介质蚀刻到基区中形成接触孔沟槽，如图8所示；
在步骤106，向接触孔沟槽中注入p+（硼元素），并将其推进扩散到基区。在本步骤中，首先通过接触孔掩模利用湿法蚀刻层间介质，然后移除光刻涂层，最后向接触孔中注入P+，采用快速高温退火作业将其推进扩散到基区中，如图9所示；
在步骤107，对接触孔沟槽进行填充形成沟槽插塞。在该步骤中，先后使用钛/氮化钛层和钨层对接触孔沟槽进行填充以形成沟槽插塞，并对表层进行浸蚀，以去除顶层的钛/氮化钛和钨；
在步骤108，利用金属掩模形成金属垫层和连线。首先该器件的上面沉积一层铝铜合金，并进行退火，然后通过金属掩模进行金属浸蚀，形成源极金属垫层，栅极金属垫层和金属连线，如图10所示。
实施例2
图11为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例2流程图，下面将参考图11进行详细阐述：
在步骤1101-1103，与实施例1的制造方法相同，参考步骤101-103，这里不再赘述；
在步骤1104，在该步骤中，首先，沉积一层光刻涂层，并对其进行蚀刻形成基区掩模，然后注入硼元素，如图12所示；
在步骤1105，然后采用快速高温退火作业，移除光刻涂层以及源区表面的第二氧化层；沉积过渡金属,进行退火作业使金属和单晶硅反应而形成硅化物；选择性蝕刻多餘的未反应的过渡金属，在第二基区、源区和多晶硅表面生成硅化物，如图6和图13所示，形成的硅化物可以是WSi2、TiSi2、MoSi2或 TaSi2；
在步骤1106，在沟槽中沉积层间介质并进行回蚀；
在步骤1107，在顶层沉积铝铜合金，使其直接接触硅化物，形成源极金属垫层，栅极金属垫层和金属连线，如图14所示。
实施例3
图15为根据本发明的自对准金属硅化物的沟槽型半导体器件制造方法实施例3流程图，下面将参考图15进行详细阐述：
在步骤1501-1503，与实施例1的制造方法相同，参考步骤101-103，这里不再赘述；
在步骤1504，沉积并蚀刻光刻涂层，形成第一接触孔掩模；通过第一接触孔掩模形成接触孔沟槽；向接触孔沟槽中注入硼元素（P+），并将其推进扩散到基区，如图16所示；
在步骤1505，移除光刻涂层以及源区表面的第二氧化层；沉积过渡金属,进行退火作业使金属和单晶硅反应而形成硅化物；选择性蝕刻多餘的未反应的过渡金属，在源区和多晶硅表面生成硅化物，如图6所示，硅化物为WSi2、TiSi2、MoSi2或 TaSi2；
在步骤1506，第一步，在沟槽中沉积层间介质并进行回蚀；第二步，沉积并蚀刻光刻涂层，形成第二接触孔掩模；第三步，利用第二接触孔掩模，蚀刻接触孔中的层间介质；
在步骤1507 - 1508，与实施例1的制造方法相同，参考步骤107-108，这里不再赘述。
实施例3中通过金属掩模形成的金属垫层及金属连线后的結构如图17所示。
上述实施例是以自对准金属硅化物的N型通道沟槽型半导体功率器件的制造过程进行说明,对于自对准金属硅化物的P型通道半导体功率器件的制造, 主要不同是掺杂物的类型，采用上述实施例的方法，改变掺杂物的类型，同样可以用于制造自对准金属硅化物的P型通道半导体器件。
本领域普通技术人员可以理解，以上所述仅为本发明的优选实施例而已，并不用于限制本发明，本发明不排它地涉及用于制造半导体器件(例如，MOS器件或绝缘栅双极晶体管(IGBT)类型的器件或双极结型晶体管(BJT)类型的器件或双极二极管或肖特基二极管）的工艺及对应的器件。
尽管参照前述实施例对本发明进行了详细的说明，对于本领域的技术人员来说，其依然可以对前述实施例记载的技术方案进行修改，或者对其中部分技术特征进行等同替换。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (15)

  1. 一种自对准金属硅化物的沟槽型半导体器件的制造方法，该方法包括以下步骤：
    1) 利用源区掩模形成基区；
    2) 利用沟槽掩模蚀刻出沟槽，并沉积多晶硅；
    3) 注入磷元素，形成源区；
    4) 在所述多晶硅和源区表面形成硅化物；
    5) 沉积铝铜合金，形成源极金属垫层，栅极金属垫层和金属连线。
  2. 根据权利要求1所述的自对准金属硅化物的沟槽型半导体器件的制造方法，其特征在于，所述步骤1）进一步包括以下步骤：
    a) 在衬底的外延层上沉积厚度为8000Å左右的第一氧化层；
    b) 蚀刻第一氧化层形成源区掩模，然后在暴露的外延层部分注入硼元素，並推进扩散到外延层中形成基区。
  3. 根据权利要求1所述的自对准金属硅化物的沟槽型半导体器件的制造方法，其特征在于，所述步骤2）进一步包括以下步骤：
    a) 生成屏敝氧化层，沉积光刻涂层，并对其进行蚀刻形成沟槽掩模；
    b) 利用沟槽掩模，在暴露的外延层部分蚀刻出沟槽；
    c) 移除光刻涂层，并对暴露的外延层部分、沟槽侧壁和底部表面进行牺牲氧化，然后再形成第二氧化层。
  4. 根据权利要求1所述的自对准金属硅化物的沟槽型半导体器件的制造方法，其特征在于，所述步骤3）进一步包括以下步骤：
    a) 在沟槽中沉积以掺杂的多晶硅，并对多晶硅进行回蚀；
    b) 注入磷元素，并采用退火作业将其推进扩散到基区中形成源区。
  5. 根据权利要求1所述的自对准金属硅化物的沟槽型半导体器件的制造方法，其特征在于，所述步骤3）和步骤4）之间还包括以下步骤：沉积光刻涂层，并对其进行蚀刻形成第二基区掩模，注入硼元素的步骤。
  6. 根据权利要求1所述的自对准金属硅化物的沟槽型半导体器件的制造方法，其特征在于，所述步骤3）和步骤4）之间还包括以下步骤：
    a) 沉积并蚀刻光刻涂层，形成第一接触孔掩模；
    b) 通过第一接触孔掩模蚀刻出接触孔沟槽；向接触孔沟槽中注入硼元素，并将其推进扩散到基区。
  7. 根据权利要求1所述的自对准金属硅化物的沟槽型半导体器件的制造方法，其特征在于，所述步骤4）还包括：
    a) 去掉源区表面上的氧化物后；
    b) 沉积过渡金属,进行退火作业使金属和单晶硅反应而形成硅化物；
    c) 选择性蝕刻多餘的未反应的过渡金属。
  8. 根据权利要求1或7所述的自对准金属硅化物的沟槽型半导体器件的制造方法，其特征在于，所述硅化物为WSi2、TiSi2、MoSi2或 TaSi2。
  9. 根据权利要求1所述的自对准金属硅化物的沟槽型半导体器件的制造方法，其特征在于，所述步骤5）进一步包括以下步骤：
    a) 通过接触孔掩模形成接触孔沟槽；
    b) 对接触孔沟槽进行填充形成沟槽插塞；
    c) 沉积铝铜合金，并进行退火，然后通过金属掩模进行金属浸蚀，形成源极金属垫层，栅极金属垫层和金属连线。
  10. 根据权利要求9所述的自对准金属硅化物的沟槽型半导体器件的制造方法，其特征在于，所述步骤a）还包括：
    a) 沉积一层层间介质，并对其进行化学机械抛光处理；
    b) 在层间介质表面沉积一层光刻涂层，并对其进行蚀刻，形成接触孔掩模；
    c) 通过接触孔掩模，利用干法由层间介质蚀刻到基区中形成接触孔沟槽。
    d) 利用湿法，把层间介质中的接触孔扩大。
  11. 根据权利要求9所述的自对准金属硅化物的沟槽型半导体器件的制造方法，其特征在于，所述步骤b）还包括：
    a) 向接触孔沟槽中注入硼元素，并将其推进扩散到基区；
    b) 先后使用钛/氮化钛层和钨层对接触孔沟槽进行填充以形成沟槽插塞，并对表层进行浸蚀，以去除顶层的钛/氮化钛和钨。
  12. 根据权利要求1所述的自对准金属硅化物的沟槽型半导体器件的制造方法，其特征在于，所述步骤5）中是将所述铝铜合金直接与硅化物接触。
  13. 根据权利要求1所述的自对准金属硅化物的沟槽型半导体器件的制造方法，其特征在于，所述步骤5）进一步包括以下步骤：
    a) 在沟槽中沉积层间介质并进行回蚀；
    b) 沉积并蚀刻光刻涂层，形成第二接触孔掩模；
    c) 利用第二接触孔掩模，蚀刻接触孔中的层间介质；
    d) 对接触孔沟槽进行填充形成沟槽插塞；
    e) 沉积一层铝铜合金，通过金属掩模进行金属浸蚀，使形成源极金属垫层，栅极金属垫层和金属连线。
  14. 一种自对准金属硅化物的沟槽型半导体器件，其特征在于，采用权利要求1-13任一项所述的方法制造而成的N通道沟槽型半导体器件。
  15. 一种自对准金属硅化物的沟槽型半导体器件，其特征在于，采用权利要求1-13任一项所述的方法制造而成的P通道沟槽型半导体器件。
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