WO2012021053A1

WO2012021053A1 - Method of configuring built in self test of memory

Info

Publication number: WO2012021053A1
Application number: PCT/MY2011/000064
Authority: WO
Inventors: Azura Zakaria Nor; Weng Fook Lee
Original assignee: Mimos Bhd
Current assignee: Mimos Bhd
Priority date: 2010-08-09
Filing date: 2011-06-02
Publication date: 2012-02-16
Anticipated expiration: 2013-02-09

Abstract

A configurable built in self test is proposed for testing memory. Signals can be provided to configure desired bus data size, memory size and preset test algorithm. Multiple preset test algorithms can be selected and executed sequentially. The built in self test module comprises, a control register for determining the choice of test algorithm, data register for determining data bus width; and an address register for determining memory size. The control register, data register and address register can be programmed to configure the choice of test algorithm, bus width and memory size to be used for testing. A status register is additionally used to sequentially arrange test algorithm to be used. An interface for configuring the built in self test is also provided.

Description

METHOD OF CONFIGURING BUILT IN SELF TEST OF MEMORY

The present invention relates generally to memory of integrated circuits, more particularly to built in self test of integrated circuits.

BACKGROUND

Memory is used in the form of memory module within a chip or as a chip itself. In today's semiconductor practice, chips such as system on chip and application specific integrated circuit have memory modules built within. Tests are performed to identify manufacturing defects within these memory modules. Built In Self Test (BIST) are used to test memory device. In this method, additional hardware circuit is included in memory chips to automatically test the memory and produce fail flag status if the memory concerned is defective. A BIST controller circuit is built with a particular test algorithm that will cycle through necessary cycles to generate stimulus to the memory device and monitor the output of the memory device. If the memory device provides an output which is different from BIST controller expectation, than a fail flag status is provided to inform that the memory is defective.

BIST circuit is built around memory circuits. It pumps a pattern to the memory, read out patterns from the memory and compares the pattern. The memory is good if the pattern is identical. The memory is defective if the pattern is different. The patterns are based upon predetermined test algorithm such as March SS, March SR, March CL, March C-, checkerboard, and diagonal. Each algorithm has its own merit in capability and test time. The choice of test algorithm may be determined by the criteria of memory test.

Features of current BIST is relatively inflexible as the BIST controller is confined to a particular test algorithm. Furthermore, the BIST controller in memory BIST testing is always confined and limited to a particular address and data size, limiting the test subject. For example, when a BIST controller is designed for testing a 32 MB memory with 8 bits data bus using March C- algorithm, the BIST controller can only be designed into a chip to test memory that has only 32MB and 8 bits data width with March C- algorithm.

There are some developments to achieve programmable BIST, however these attempts are not offer flexibility for different memory size and different bus width. Some offer test algorithm choice programmability. Software has to be written in microcode to choose the relevant test.

It is an object of the invention to provide a flexible method of memory testing for configuring address size, data size and test algorithm for the memory module.

SUMMARY OF INVENTION

The present invention proposes a configurable memory BIST controller. Variable data bus width, variable memory size and predetermined test algorithms can be configured for memory testing. The test allows a combination of preset test algorithms to be performed

A test engineer can configure the data bus width and address of memory under test. A test program interface is proposed for the configuration of test to be performed. A method to configure the test is also explained.

A single BIST controller may have various test algorithms. It is implemented using shared commonality of its algorithms and control of which algorithm to be executed is determined by the contents of the programmed test configuration. Sub modules of address sequencer, BIST algorithm decode, pattern comparison and algorithm are built using shared commonality.

The proposed invention can be implemented for memory tests as part of the chip to perform testing on internal memory within the chip, or as a standalone memory testing unit. It is capable to be configured to test variable memory size and variable memory data bus width with choices of various predetermined test algorithms.

BRIEF DESCRIPTION OF DRAWINGS

The invention will now be described in greater detail, by way of an example, with reference to the accompanying drawings, in which:

Fig. 1 shows an overview of built in self test module according to the invention; Fig. 2 shows a diagram of register configuration for control register; Fig. 3 shows a diagram of functionality of internal do signals;

Fig. 4 shows a diagram of status register status for sequentially executing test algorithm;

Fig. 5 shows a diagram of register configuration of memory data bus width; and

Fig. 6 shows a diagram of register configuration of memory sizes.

DESCRIPTION OF EMBODIMENTS

Fig. 1 shows a block diagram of programmable built in self test (BIST) module which comprises a BIST register module and a BIST state controller module. The BIST register has a control register, a status register, a data size register and an address size register. The control register is used to define which algorithm to be used. The status register is used to signal the status of the algorithm for the memory testing. Address size register signals the size of the memory device while data size register signals memory data bus. These four registers allow a test engineer to control the size of memory being tested, data bus width of memory being tested and choice of algorithm. The test engineer can access these registers using a test interface to write data to the BIST register to control the configuration for testing. The contents of the BIST register can be modified by the test engineer. The BIST will start the test after the registers have been configured.

An embodiment of the invention has 8,388,608 kB different memory sizes, 256 bit different memory data bus width and 6 different March algorithms. Possible 6 different March algorithms are March SS, SR, CL, Raw23N, Raw13N and C-.

The control register, status register and data size register uses 16 bit [15:0]. The address size register uses 32 bit [31 :0]. Possible interface signals to be used are BIST data (BISTData), BIST address size register (BISTAddrSizeReg), BIST data size register (BISTDataSizeReg), BIST control register (BISTControlReg) and BIST enable (BISTEN).

The BIST state controller comprises address sequencer, BIST algorithm decode and pattern generator to communicate signals with memory. The control register is a 16 bit register with each bit representing a particular preset memory test algorithm, as shown in Fig. 2. Current design utilize bits [5:0] representing 6 algorithms of March SS, March SR, March CL, March Raw23N, March Raw13N and March C-. The other bits of [15:6] are unused and reserved for future expansion to cater to more different types of algorithms.

The control register is flexible and the user can enter multiple logic 1 across the bits [5:0] thereby allowing multiple choice of algorithms to be entered. If the control register contain '110100', then three predetermined algorithms will be executed sequentially.

Status register is also a 16 bit register with unused bits [15:6]. Bits [5:0] represent the status of algorithm predetermined in control register. The contents of control register and status register determines if BIST controller drives ouput signals of ceb, web, oeb, addr, and data to test the memory device. This is achieved through six internal signals of doMSS, doMSR, doMCL, doMR23N, doMR13N and doMCM which goes from register module to BIST controller module. The Boolean logic for these six internal signals is shown in Fig. 4. The programmable BIST can be programmed to execute more than one algorithm sequentially. For example, a control register bit value of '110001 ' would execute MarchSS algorithm, followed by March Raw13N algorithm and March C minus algorithm. This means that the doMSS, doMR13N and doMCM signals will be logic 1 to inform the BIST state controller module to execute each of those mentioned algorithms. When the March SS algorithm is completed, the BIST state controller module will assert the internal signal completeMSS which will set the March SS status bit in status register. In this case March SS is represented by status register. This is followed by signal completeMR13N which will set the March Raw 13N status bit in the status register and finally signal completMCM which will set the March C Minus status bit in status register. Fig. 5 shows the state diagram of the setting of the status register bits with reference to signals doMSS, doMSR, doMCL, doMR23N, doMR13N, doMCM and the signals completeMSS, completeMSR, completeMCL, completeMR23N, completeMR13N and complete MCM. Hence, the status register allows multiple preset test algorithms to be executed sequentially.

Data size register is a 16 bit register that allows different data sizes of memory module to be programmed. BIST can be accommodated from 1 to 256 bits [7:0], as shown in Fig. 6. The rest of the bits [15:8] is unused and reserved for future expansion.

The address size register is a 32 bit register that allows different address sizes of different memory modules to be programmed. BIST can be accommodated to test different memory ranges from 1 byte to 8192k, with capability for future expansion, as shown in Fig. 7.

By combining the different configurations for address size register, data size register and control register, a plurality of test configurations can be achieved during testing, giving the test engineer great flexibility in configuring the tests. After a test algorithm is completed, a signal for memory test pass or fails status is provided.

Accordingly, the invention disclosed a method of configuring built in self test of memory. It is the combination of the above features and its technical advantages give rise to the uniqueness of such invention. Although the descriptions above contain much specificity, these should not be construed as limiting the scope of the embodiment but as merely providing illustrations of some of the presently prefe ed embodiments.

Claims

1. A method of configuring built in self test of memory, comprising:

providing signal of desired bus data size to be tested;

providing signal of desired memory size to be tested; and

providing signal of desired choice of preset test algorithm to be used.

2. A method according to claim 1 , wherein multiple preset test algorithms can be selected and executed sequentially.

3. A method according to claim 1 , wherein the preset test algorithm are March SS, March SR, March CL, March Raw23N, March Raw13N, and March C-.

4. A method according to claim 1 , wherein the bus data size ranges from 1 to 256 bits and memory size ranges from 1 to 8192k address.

5. A method according to claim 1 , further comprising providing a signal for memory test pass or fail status.

6. A built in self test module, comprising:

a control register for determining the choice of test algorithm;

a data register for determining data bus width; and

an address register for determining memory size;

characterized in that, the control register, data register and address register can be programmed to configure the choice of test algorithm, bus width and memory size to be used for testing.

7. A test module according to claim 6, further comprising an interface for providing the following signals: