WO2012006025A2 - A method and apparatus for dynamic memory termination - Google Patents

A method and apparatus for dynamic memory termination Download PDF

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Publication number
WO2012006025A2
WO2012006025A2 PCT/US2011/042029 US2011042029W WO2012006025A2 WO 2012006025 A2 WO2012006025 A2 WO 2012006025A2 US 2011042029 W US2011042029 W US 2011042029W WO 2012006025 A2 WO2012006025 A2 WO 2012006025A2
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WO
WIPO (PCT)
Prior art keywords
termination
memory
impedance value
value setting
operable
Prior art date
Application number
PCT/US2011/042029
Other languages
French (fr)
Other versions
WO2012006025A3 (en
Inventor
James A. Mccall
Kuljit S. Bains
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to EP11804090.6A priority Critical patent/EP2586028B1/en
Priority to EP18150048.9A priority patent/EP3324411B1/en
Priority to KR1020127034084A priority patent/KR20130030277A/en
Priority to CN201180032081.8A priority patent/CN102971794B/en
Priority to JP2013518535A priority patent/JP5670565B2/en
Priority to KR1020157009592A priority patent/KR101645552B1/en
Publication of WO2012006025A2 publication Critical patent/WO2012006025A2/en
Publication of WO2012006025A3 publication Critical patent/WO2012006025A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Definitions

  • Embodiments of the invention relate generally to the field of memories. More particularly, embodiments of the invention relate to a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level.
  • I/O memory input-output
  • a memory controller facilitates the access of a memory module in the computer system.
  • the memory module may include one or more memories that are referred to as ranks.
  • the memory controller communicates with the ranks of the memory module via input-output (I/O) interfaces and transmission lines.
  • I/O interfaces exist at both the memory controller end and at the memory module end.
  • the memory controller transmits via its I/O interfaces a host of signals to the ranks including address signals, control signals, clock signals, etc., to access data from the ranks or to send data to the ranks.
  • termination impedance is set on the I/O interfaces of the memory controller and/or the ranks.
  • the term correct communication herein refers to sending and/or receiving expected data between the memory module and the memory controller, where the expected data meets performance specifications e.g., timing, voltage margin, signal integrity, etc.
  • the value of the termination impedance determines the quality of the signal being
  • a termination impedance of the I/O interface at the ranks is set to a value for reducing noise on the signal being communicated between the rank and the memory controller.
  • DDR3 Double Data Rate 3
  • the memory controller is only operable to set the termination impedance on the DDR3 I O interface of the ranks being accessed to a single finite termination value.
  • the termination impedance for DDR3 I O interface of ranks not being accessed is set to a high impedance value (infinite impedance caused by tri-stating the termination devices) as a default termination impedance value.
  • DDR3 I/O interfaces are required by specification to have a center-tap termination scheme having a pull-up termination resistor connected to a power supply node and a pull-down termination resistor connected to a ground supply node.
  • a center-tap termination scheme provides an electrical path from the power supply node to the ground node via the pulldown termination resistor and the pull-down termination resistor. The electrical path is a source of power consumption when the center-tap termination scheme is enabled.
  • the termination impedance of the rank remains at default value of high impedance.
  • Such high termination impedance i.e., infinite impedance
  • DDR4 I/O interface As demand for higher speeds of memory I/O interfaces is increasing e.g., DDR3 I/O interface speed of 1600-3200 Mega Transfers per second (MT/s) vs. 800-1600 MT/s for Double Data Rate 4 (DDR4) I/O interface, a default value of high termination impedance reduces memory system performance.
  • Fig. 1 is a memory system comprising a memory controller and memory modules for dynamically providing finite termination impedance settings to ranks within the memory modules, according to one embodiment of the invention.
  • Fig. 2A is a memory controller for dynamically providing finite termination impedance settings to the ranks, according to one embodiment of the invention.
  • Fig. 2B is a memory rank for dynamically providing finite termination impedance settings to the on-die termination units of the memory rank, according to one embodiment of the invention.
  • Fig. 3 is a flowchart for dynamically providing finite termination impedance settings to the memory ranks, according to one embodiment of the invention.
  • Fig. 4 is computer system to implement the method for providing dynamic memory termination impedance settings to the memory ranks, according to one embodiment of the invention. DETAILED DESCRIPTION
  • Embodiments of the invention relate to a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level.
  • I/O memory input-output
  • a memory controller reads a first finite impedance value setting from a register and assigns that value setting to a termination unit of one of the memory ranks which are not being accessed.
  • a first programmable finite impedance value setting is assigned to the termination unit of the ranks that are not being accessed.
  • a second termination impedance value setting is assigned to the ranks being accessed when a termination signal level asserts. In the embodiments discussed herein, both the first and the second termination impedance values are programmable.
  • a termination unit of the rank from which data is being accessed is configured to have the second termination impedance value.
  • the termination unit of the rank being accessed is operable to transition its termination impedance value setting from the first finite programmable termination impedance value setting to the second termination impedance value setting when the termination signal level asserts.
  • the termination signal is an on-die termination signal.
  • the embodiments herein result in 20-30% improvement in timing and voltage margins for memory accesses of ranks compared to the traditional architecture that is configured to transition from a high impedance termination value setting to a finite impedance termination value setting during memory access of a rank. Consequently, the embodiments herein result in higher yield (i.e., fewer failing parts) of memory systems because the timing margin improves over memory systems that do not allow dynamic switching of termination impedance value settings for its termination units.
  • dynamic switching refers to switching between finite impedance value settings for the termination units of the ranks without causing the termination units to transition into a high impedance state or any other intermediary impedance state. Such switching occurs directly from one termination impedance value setting to another termination impedance value setting in response to a memory access when the termination signal level changes from one logical level to another logical level.
  • the I/O interface is a Double Date Rate 4 (DDR4) interface having a termination unit that comprises pull-up resistors and no pull-down resistors.
  • the I/O interface comprises a termination unit having pull-down resistors and no pull-up resistors.
  • the one or more ranks include a Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), DDR4 SDRAM, and any other type of random access memory device.
  • SDRAM Synchronous Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • RDRAM RAMBUS Dynamic Random Access Memory
  • DDR4 SDRAM DDR4 SDRAM
  • the ranks reside in a memory module.
  • DIMM Dual In-Line Memory Module
  • DDR4 I/O interface a Dual In-Line Memory Module having one or more SDRAMs, which are also called ranks, wherein the DIMM is communicatively coupled to the memory module via a DDR4 I/O interface.
  • DIMM Dual In-Line Memory Module
  • the above embodiments are not limiting embodiments.
  • Other embodiments having different memory modules (other than the DIMM), memories without memory modules, and other I/O interfaces e.g., newer I/O interfaces than a DDR4 I/O interface
  • I/O interfaces e.g., newer I/O interfaces than a DDR4 I/O interface
  • signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme, e. g., differential pair, single-ended, etc.
  • Fig. 1 is a memory system 100 comprising a memory controller 101 operable to dynamically set programmable finite termination impedance values for memory modules 102I_N, according to one embodiment of the invention.
  • the memory controller 101 is integrated within a microprocessor (CPU).
  • the memory controller 101 is a separate integrated circuit (IC) on the motherboard and is coupled to the CPU (not shown) and the memory modules 102I_N via motherboard routings (not shown) and connectors (not shown).
  • the memory module 102i includes one or more memories, register devices, buffer devices, etc.
  • the one or more memories are also referred herein as ranks.
  • the ranks 103I_N are SDRAMs.
  • the ranks 103I_N share the same address, command and control buses.
  • the ranks 103I-N are not in a memory module.
  • the memory controller 101 communicates with the memory module 102i via signals including data signals 105, clock signals 106, address signals 107, on-die termination (ODT) signal 109, and any other signals to cause communication between the memory controller 101 and the memory modules 102i_ N .
  • ODT on-die termination
  • each I/O pin/pad (not shown) of the ranks 103I_N has a termination unit 104I_N.
  • the termination units 104I_N are implemented within the die of the ranks 103I_N i.e., ODT units. In other embodiments, the termination units 104i_N are implemented off-die.
  • the I/O pins/pads of each rank are not shown.
  • the termination units 104I_N discussed for the embodiments herein are ODT units to cancel signal reflections on the transmission lines during memory access.
  • One skilled in the art can replace the ODT units with off-die termination units without changing the essence of the embodiments.
  • the ranks being accessed set their ODT units to have the second termination impedance value.
  • the ODT signal 109 is a control signal.
  • there is one ODT pin per rank which is operable to receive the ODT signal 109 from the memory controller 101.
  • the second termination impedance value is programmed in a mode register and is accessed in response to the ODT signal 109 being asserted.
  • the mode register resides in the memory controller 101.
  • the mode register is a memory mode register (e.g., a DRAM mode register) and resides in each memory rank.
  • the ODT unit 104i comprises a pull-up resistor R T1 and a pulldown capacitor coupled to the I/O pin.
  • the value of the resistor R T1 is configured/set according to the specifications of the DDR4 I/O interface. As mentioned above, contrary to the termination units of DDR3 I/O interface and earlier DDR I/O interfaces, the ODT units 104I_N of the embodiments of the invention do not have an electrical path within the termination units from power supply to ground.
  • the ODT units 104I_N consume less power than termination units of DDR3 I/O interface and earlier DDR I/O interfaces because the memory controller 101 pulls-up the signal levels on the transmission lines coupled to the ODT units 104i_ when the ODT signal 109 is de-asserted.
  • any number of pull-up resistors may comprise the pull-up resistor wherein pull-up resistors are operable to turn on or off via logic (not shown) to achieve a first and/or second termination impedance values.
  • the first impedance value is 180 Ohms while the second impedance value is 60 Ohms.
  • the memory controller 101 comprises a logic unit 108 for dynamically configuring the termination impedance of the ODT units 104I_N.
  • the logic unit 108 is operable to set the impedance of the ODT units 104i_ to a first finite termination impedance value setting when the memory controller 101 is not accessing memory from the ranks. In such an embodiment, the level of the ODT signal 109 is de-asserted.
  • the logic unit dynamically switches the impedance value setting of any of the ODT units 104I_N from the first termination impedance value setting to a second termination impedance value setting in response to an assertion of the ODT signal 109.
  • assertion refers herein to a transition from a logical low level to a logical high level.
  • de-assertion refers herein to a transition from a logical high level to a logical low level.
  • a de-asserted signal is a logical low level signal while an asserted signal is a logical high level signal.
  • Fig. 2A is a memory controller 200 (same as 101 of Fig. 1) for dynamically providing finite termination impedance settings to the ranks of the memory modules, according to one embodiment of the invention.
  • the memory controller 101 comprises a register 201 having the first and the second termination impedance values, value 1 and value 2 respectively.
  • the first and the second termination impedance values are programmable values.
  • the first and the second termination impedance values are predetermined values set at the time the memory system boots up.
  • the register 201 is programmable via an operating system.
  • the first and the second termination impedance values are finite values.
  • the register 201 is a DRAM Mode Register residing in the ranks 103I_N and is operable to store the programmable first and second termination impedance values.
  • the DRAM Mode Register of each rank of the plurality of ranks 103I_N is accessible via an operating system and/or the memory controller 101.
  • the memory controller 101 and/or the Basic Input-Output System (BIOS) is operable to program the DRAM Mode Registers of every rank based on the system memory.
  • BIOS Basic Input-Output System
  • Fig. 2B is a high level logical block diagram 210 of a memory rank 103i comprising a DRAM Mode Register 211 which is operable to store the programmable first and second termination impedance values for the ODT unit 104i, according to one embodiment of the invention.
  • a single memory rank 103i is being illustrated with a single ODT unit 104i for a single I/O pin/pad.
  • the memory rank 103i has multiple ODT units for each pin/pad, and the same description is applicable to all memory ranks 103I-N, according to the embodiments of the invention.
  • the memory rank 103i resides in a memory module. In other embodiments, the memory rank 103i does not reside in a memory module.
  • the memory rank 103i receives the ODT signal 109 from the memory controller 101 via a receiver 212.
  • a termination logic unit 212 coupled to the receiver 212 assigns the first or the second termination impedance value to the ODT unit 104i.
  • the termination logic unit 212 comprises the first and the second logic units 202 and 203 discussed with reference to Fig. 2A.
  • the termination unit 212 receives a signal from the first and the second logic units 202 and 203 discussed below with reference to Fig. 2A to provide the first and the second termination impedance values from the DRAM Mode Register 211 to the ODT
  • the first termination impedance value (value 1) which is also the default termination impedance value for the ODT unit 104i, is assigned to the ODT unit 104i from the DRAM Mode Register 211.
  • the second termination impedance value (value 2) is assigned to the ODT unit 104i from the DRAM Mode Register 211.
  • the termination impedance values (value 1 and value 2) in the DRAM Mode Register 211 are programmable via hardware or software.
  • the memory controller 101 further comprises a first logic unit 202 and a second logic unit 203.
  • the first logic unit 202 is operable to assign the first termination impedance value setting from the register 201 to any of the ODT units 104I_N that correspond to the ranks 103i_ N that are not being accessed by the memory controller 101. In such an embodiment, the level of the ODT signal 109 is de-asserted.
  • the first logic unit 202 is operable to assign the first termination impedance value setting stored in the DRAM Mode register of the rank to the ODT unit of the rank.
  • the first logic unit 202 is operable to assign the first termination impedance value setting by turning on or off the pull-up resistors of the ODT units 104I_N to configure them to have the first termination impedance value setting.
  • the level of the ODT signal 109 is de-asserted when setting the first termination impedance value for the ODT units 104i_ N of the ranks not being accessed by the memory controller 101.
  • the second logic unit 203 is operable to dynamically switch the first termination impedance value setting to the second termination impedance value settings for the ODT units 104I_N of the ranks being assessed in response to the level of the ODT signal 109 being asserted.
  • the second logic unit 203 is operable to turn on or off the resistors from the plurality of resistors of the termination units 104i_ that correspond to the I/O pins/pads of the ranks being accessed by the memory controller 101.
  • the first and the second logic units assign the first and the second termination value settings to the ODT units 104I_N via an I/O transmitter 204 of the memory controller 101.
  • the first and the second logic units are operable assign the first and the second termination value settings to the ODT units 104I_N of each rank from the values stored in the DRAM Mode Register of each rank 103I_N.
  • Fig. 3 is a flowchart 300 for dynamically providing finite termination impedance settings to the ranks, according to one embodiment of the invention. The flowchart is discussed with respect to the embodiments of Fig 1 and Figs. 2A-B.
  • a first impedance value is set in the register 201 of the memory controller 101 or in the one or more ranks 103 I_N.
  • the first impedance value (value 1) is a finite impedance value for any of the ODT units 104I_N of the I/O pins/pads that corresponds to the ranks that are not being accessed by the memory controller 101.
  • a second impedance value (value 2) is also set in the register 201 of the memory controller 101 or in the one or more ranks 103 ⁇ _ ⁇ AS discussed above, in one embodiment, the register 201 resides in the individual ranks 103I_N (See, DRAM Mode Register 211 of Fig. 2B).
  • the second impedance value is also a finite impedance value for any of the ODT units 104I_N of the I/O pins/pads that correspond to the ranks being accessed by the memory controller 101.
  • the memory controller 101 is operable to set the first and the second impedance values via an operating system.
  • the first termination impedance value setting is assigned via the first logic unit 202 and/or via the logic unit 212 of Fig. 2B to any of the ODT units 104i_ of the I/O pins that correspond to the ranks not being accessed by the memory controller 101.
  • the first termination impedance value is a default impedance value for the ODT units 104i_ N of the I/O pins/pads that correspond to the ranks not being accessed by the memory controller 101.
  • the first termination impedance value is assigned to the ODT units 104i_ N that are not being accessed. In such an embodiment, the level of the ODT signal 109 de-asserts.
  • the second logic unit 203 and/or the logic unit 212 of Fig. 2B dynamically switches the first termination impedance value setting to the second termination impedance value setting in response to the assertion of the ODT signal 109.
  • the second impedance value setting is assigned to any of the ODT units 104I_N of the I O pins/pads that correspond to the ranks being accessed by the memory controller 101. In such an embodiment, the level of the ODT signal 109 asserts.
  • the above embodiments allow different ranks of a memory system from among the ranks 103I_N of the one or more memory modules 102I_N to have different
  • the finite impedance termination values dynamically switch from the first finite termination impedance value setting to the second finite termination impedance value setting and vice-a-versa in response to the ranks being accessed and the level of the ODT signal 109.
  • the above embodiments result in improved timing and voltage margins for the entire memory system compared to memory systems that only allow switching between a high impedance (infinite impedance) value setting and a finite impedance value setting.
  • One reason for the improved timing and voltage margins is the reduction of signal reflections on the transmission lines between the memory controller and the ranks caused by the different finite termination impedance value settings for ODT units when the memories are being accessed and when they are not being accessed.
  • the embodiments of the invention thus allow a memory system with DDR4 I/O interface to have a finite programmable termination impedance as its default impedance value.
  • Embodiments of the invention are also implemented via programmable computer- executable instructions stored on a machine-readable storage medium.
  • a machine-readable storage medium may include, but is not limited to, flash memory, optical disks, CD- ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, or other type of machine-readable storage media suitable for storing electronic or computer- executable instructions.
  • embodiments of the invention may be downloaded as a computer program which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).
  • a remote computer e.g., a server
  • a requesting computer e.g., a client
  • a communication link e.g., a modem or network connection
  • Fig. 4 illustrates a system 400 to implement the methods disclosed herein, according to one embodiment of the invention.
  • the system 400 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, an Internet appliance or any other type of computing device.
  • the system 400 used to implement the methods disclosed herein may be a system on a chip (SOC) system.
  • the processor 410 has a processing core 412 to execute instructions of the system 400.
  • the processing core 412 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like.
  • the processor 410 has a cache memory 416 to cache instructions and/or data of the system 400.
  • the cache stores the instructions to execute the method of Fig. 3.
  • the cache memory 416 includes level one, level two and level three, cache memory, or any other configuration of the cache memory within the processor 410.
  • the memory controller 101 which is also referred to as the memory control hub
  • MCH memory 414
  • the volatile memory 432 includes, but is not limited to,
  • the non-volatile memory 434 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.
  • PCM phase change memory
  • ROM read-only memory
  • EEPROM electrically erasable programmable read-only memory
  • the memory 430 stores information and instructions to be executed by the processor 410. In one embodiment, memory 430 may also store temporary variables or other intermediate information while the processor 410 is executing instructions.
  • chipset 420 connects with processor 410 via Point-to-Point (PtP or P-P) interfaces 417 and 422. In one embodiment, chipset 420 enables processor 410 to connect to other modules in the system 400.
  • interfaces 417 and 422 operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like.
  • chipset 420 connects to a display device 440 via an interface 426.
  • the display 440 includes, but is not limited to, liquid crystal display (LCD), cathode ray tube (CRT) display, or any other form of visual display device.
  • processor 410 and chipset 420 are merged into a SOC.
  • chipset 420 connects to one or more buses 450 and 455 that interconnect various modules 474, 460, 462, 464, and 466.
  • buses 450 and 455 may be interconnected together via a bus bridge 472 if there is a mismatch in bus speed or communication protocol.
  • chipset 420 couples with, but is not limited to, a non-volatile memory 460, a mass storage device(s) 462, a
  • keyboard/mouse 464 and a network interface 466 via interface 424.
  • the mass storage device 462 includes, but is not limited to, a solid state drive, a hard disk drive, an universal serial bus flash memory drive, or any other form of computer data storage medium.
  • network interface 466 is implemented by any type of well known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface.
  • the wireless interface operates in accordance with, but is not limited to, the IEEE 802.1 1 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
  • modules shown in Fig. 4 are depicted as separate blocks within the system 400, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits.
  • the cache memory 416 is depicted as a separate block within the processor 410, the cache memory 416 can be incorporated into the processor core 412 respectively.
  • the system 400 may include more than one processor/processing core in another embodiment of the invention.
  • operable used herein means that the device, module, system, logic unit, protocol etc, is able to operate or is adapted to operate for its desired functionality when the device, module, system, or logic unit is in off-powered state.
  • the dynamic switching of the termination impedance values from the first impedance value to the second impedance value may occur when the ODT signal 109 de- asserts instead of asserting.
  • ODT signal 109 is de-asserted in response to a memory access from a rank.
  • the memory coupled to the memory controller 101 is a standalone DRAM.

Abstract

Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.

Description

A METHOD AND APPARATUS FOR DYNAMIC MEMORY TERMINATION
FIELD OF THE INVENTION
Embodiments of the invention relate generally to the field of memories. More particularly, embodiments of the invention relate to a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. BACKGROUND
In a typical memory system of a computer system, a memory controller facilitates the access of a memory module in the computer system. The memory module may include one or more memories that are referred to as ranks. The memory controller communicates with the ranks of the memory module via input-output (I/O) interfaces and transmission lines. The I/O interfaces exist at both the memory controller end and at the memory module end. The memory controller transmits via its I/O interfaces a host of signals to the ranks including address signals, control signals, clock signals, etc., to access data from the ranks or to send data to the ranks.
For correct communication between the ranks and the memory controller, termination impedance is set on the I/O interfaces of the memory controller and/or the ranks. The term correct communication herein refers to sending and/or receiving expected data between the memory module and the memory controller, where the expected data meets performance specifications e.g., timing, voltage margin, signal integrity, etc. The value of the termination impedance determines the quality of the signal being
communicated between the memory controller and the ranks.
Typically, during memory access (e.g., memory read) initiated by the memory controller, a termination impedance of the I/O interface at the ranks is set to a value for reducing noise on the signal being communicated between the rank and the memory controller. For a Double Data Rate 3 (DDR3) I/O interface, the memory controller is only operable to set the termination impedance on the DDR3 I O interface of the ranks being accessed to a single finite termination value. The termination impedance for DDR3 I O interface of ranks not being accessed is set to a high impedance value (infinite impedance caused by tri-stating the termination devices) as a default termination impedance value.
One reason for having the default termination impedance value for the DDR3 I/O interface as a high impedance value is to save power consumption. DDR3 I/O interfaces are required by specification to have a center-tap termination scheme having a pull-up termination resistor connected to a power supply node and a pull-down termination resistor connected to a ground supply node. Such a center-tap termination scheme provides an electrical path from the power supply node to the ground node via the pulldown termination resistor and the pull-down termination resistor. The electrical path is a source of power consumption when the center-tap termination scheme is enabled.
To reduce power consumption on the DDR3 I/O interface when there is no memory access on a rank, the termination impedance of the rank remains at default value of high impedance. Such high termination impedance (i.e., infinite impedance) reduces timing and voltage margins on the read signals being communicated between the memory controller and other active ranks. As demand for higher speeds of memory I/O interfaces is increasing e.g., DDR3 I/O interface speed of 1600-3200 Mega Transfers per second (MT/s) vs. 800-1600 MT/s for Double Data Rate 4 (DDR4) I/O interface, a default value of high termination impedance reduces memory system performance.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only.
Fig. 1 is a memory system comprising a memory controller and memory modules for dynamically providing finite termination impedance settings to ranks within the memory modules, according to one embodiment of the invention.
Fig. 2A is a memory controller for dynamically providing finite termination impedance settings to the ranks, according to one embodiment of the invention.
Fig. 2B is a memory rank for dynamically providing finite termination impedance settings to the on-die termination units of the memory rank, according to one embodiment of the invention.
Fig. 3 is a flowchart for dynamically providing finite termination impedance settings to the memory ranks, according to one embodiment of the invention. Fig. 4 is computer system to implement the method for providing dynamic memory termination impedance settings to the memory ranks, according to one embodiment of the invention. DETAILED DESCRIPTION
Embodiments of the invention relate to a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level.
In one embodiment, a memory controller reads a first finite impedance value setting from a register and assigns that value setting to a termination unit of one of the memory ranks which are not being accessed. In contrast to having a high impedance termination value for ranks as a default value when there is no memory access, as is the case for Double Data Rate 3 (DDR3) I/O interfaces, in the embodiment herein a first programmable finite impedance value setting is assigned to the termination unit of the ranks that are not being accessed. In one embodiment, a second termination impedance value setting is assigned to the ranks being accessed when a termination signal level asserts. In the embodiments discussed herein, both the first and the second termination impedance values are programmable.
In one embodiment, when the memory controller initiates memory access from one of the ranks, a termination unit of the rank from which data is being accessed is configured to have the second termination impedance value. In such an embodiment, the termination unit of the rank being accessed is operable to transition its termination impedance value setting from the first finite programmable termination impedance value setting to the second termination impedance value setting when the termination signal level asserts. As discussed below, the termination signal is an on-die termination signal.
The embodiments herein result in 20-30% improvement in timing and voltage margins for memory accesses of ranks compared to the traditional architecture that is configured to transition from a high impedance termination value setting to a finite impedance termination value setting during memory access of a rank. Consequently, the embodiments herein result in higher yield (i.e., fewer failing parts) of memory systems because the timing margin improves over memory systems that do not allow dynamic switching of termination impedance value settings for its termination units.
The term dynamic switching herein refers to switching between finite impedance value settings for the termination units of the ranks without causing the termination units to transition into a high impedance state or any other intermediary impedance state. Such switching occurs directly from one termination impedance value setting to another termination impedance value setting in response to a memory access when the termination signal level changes from one logical level to another logical level.
The term high impedance herein refers to infinite impedance caused by turning off the termination unit (i.e., setting the termination unit to tri-state) resulting in full reflection of signals on the transmission line at the termination unit end. In one embodiment, the I/O interface is a Double Date Rate 4 (DDR4) interface having a termination unit that comprises pull-up resistors and no pull-down resistors. In one embodiment, the I/O interface comprises a termination unit having pull-down resistors and no pull-up resistors.
In one embodiment of the invention, the one or more ranks include a Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), DDR4 SDRAM, and any other type of random access memory device. In one embodiment, the ranks reside in a memory module.
So as not to obscure the embodiments of the invention, the embodiments herein are discussed with reference to a Dual In-Line Memory Module (DIMM) having one or more SDRAMs, which are also called ranks, wherein the DIMM is communicatively coupled to the memory module via a DDR4 I/O interface. However, the above embodiments are not limiting embodiments. Other embodiments having different memory modules (other than the DIMM), memories without memory modules, and other I/O interfaces (e.g., newer I/O interfaces than a DDR4 I/O interface) can be used without changing the essence of the invention.
In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present invention. It will be apparent, however, to one skilled in the art, that embodiments of the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present invention.
Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme, e. g., differential pair, single-ended, etc.
Fig. 1 is a memory system 100 comprising a memory controller 101 operable to dynamically set programmable finite termination impedance values for memory modules 102I_N, according to one embodiment of the invention. In one embodiment, the memory controller 101 is integrated within a microprocessor (CPU). In other embodiments, the memory controller 101 is a separate integrated circuit (IC) on the motherboard and is coupled to the CPU (not shown) and the memory modules 102I_N via motherboard routings (not shown) and connectors (not shown).
In one embodiment of the invention, the memory module 102i includes one or more memories, register devices, buffer devices, etc. The one or more memories are also referred herein as ranks. In one embodiment the ranks 103I_N are SDRAMs. In one embodiment, the ranks 103I_N share the same address, command and control buses. In one embodiment, the ranks 103I-N are not in a memory module. In one embodiment, the memory controller 101 communicates with the memory module 102i via signals including data signals 105, clock signals 106, address signals 107, on-die termination (ODT) signal 109, and any other signals to cause communication between the memory controller 101 and the memory modules 102i_N.
In one embodiment, each I/O pin/pad (not shown) of the ranks 103I_N has a termination unit 104I_N. In one embodiment, the termination units 104I_N are implemented within the die of the ranks 103I_N i.e., ODT units. In other embodiments, the termination units 104i_N are implemented off-die.
So as not to obscure the embodiments of the invention, the I/O pins/pads of each rank are not shown. Also, the termination units 104I_N discussed for the embodiments herein are ODT units to cancel signal reflections on the transmission lines during memory access. One skilled in the art can replace the ODT units with off-die termination units without changing the essence of the embodiments.
In one embodiment, when the memory controller 101 asserts the ODT signal 109, the ranks being accessed set their ODT units to have the second termination impedance value. In one embodiment, the ODT signal 109 is a control signal. In one embodiment, there is one ODT pin per rank which is operable to receive the ODT signal 109 from the memory controller 101. In one embodiment, the second termination impedance value is programmed in a mode register and is accessed in response to the ODT signal 109 being asserted. In one embodiment, the mode register resides in the memory controller 101. In another embodiment, the mode register is a memory mode register (e.g., a DRAM mode register) and resides in each memory rank.
In one embodiment, the ODT unit 104i comprises a pull-up resistor RT1 and a pulldown capacitor coupled to the I/O pin. In one embodiment, the value of the resistor RT1 is configured/set according to the specifications of the DDR4 I/O interface. As mentioned above, contrary to the termination units of DDR3 I/O interface and earlier DDR I/O interfaces, the ODT units 104I_N of the embodiments of the invention do not have an electrical path within the termination units from power supply to ground. Consequently, the ODT units 104I_N consume less power than termination units of DDR3 I/O interface and earlier DDR I/O interfaces because the memory controller 101 pulls-up the signal levels on the transmission lines coupled to the ODT units 104i_ when the ODT signal 109 is de-asserted.
While the ODT units 1041-N are shown with one pull-up resistor, any number of pull-up resistors may comprise the pull-up resistor wherein pull-up resistors are operable to turn on or off via logic (not shown) to achieve a first and/or second termination impedance values. In one embodiment, the first impedance value is 180 Ohms while the second impedance value is 60 Ohms.
In one embodiment, the memory controller 101 comprises a logic unit 108 for dynamically configuring the termination impedance of the ODT units 104I_N. In one embodiment, the logic unit 108 is operable to set the impedance of the ODT units 104i_ to a first finite termination impedance value setting when the memory controller 101 is not accessing memory from the ranks. In such an embodiment, the level of the ODT signal 109 is de-asserted. In one embodiment, the logic unit dynamically switches the impedance value setting of any of the ODT units 104I_N from the first termination impedance value setting to a second termination impedance value setting in response to an assertion of the ODT signal 109.
The term assertion refers herein to a transition from a logical low level to a logical high level. Similarly, the term de-assertion refers herein to a transition from a logical high level to a logical low level. Hence, a de-asserted signal is a logical low level signal while an asserted signal is a logical high level signal.
Fig. 2A is a memory controller 200 (same as 101 of Fig. 1) for dynamically providing finite termination impedance settings to the ranks of the memory modules, according to one embodiment of the invention. In one embodiment, the memory controller 101 comprises a register 201 having the first and the second termination impedance values, value 1 and value 2 respectively. In one embodiment, the first and the second termination impedance values are programmable values. In one embodiment, the first and the second termination impedance values are predetermined values set at the time the memory system boots up. In one embodiment, the register 201 is programmable via an operating system. In one embodiment the first and the second termination impedance values are finite values.
In one embodiment as discussed with reference to Fig. 2B, the register 201 is a DRAM Mode Register residing in the ranks 103I_N and is operable to store the programmable first and second termination impedance values. In one embodiment, the DRAM Mode Register of each rank of the plurality of ranks 103I_N is accessible via an operating system and/or the memory controller 101. In one embodiment the memory controller 101 and/or the Basic Input-Output System (BIOS) is operable to program the DRAM Mode Registers of every rank based on the system memory.
Fig. 2B is a high level logical block diagram 210 of a memory rank 103i comprising a DRAM Mode Register 211 which is operable to store the programmable first and second termination impedance values for the ODT unit 104i, according to one embodiment of the invention. So as not to obscure the embodiments of the invention, a single memory rank 103i is being illustrated with a single ODT unit 104i for a single I/O pin/pad. However, the memory rank 103i has multiple ODT units for each pin/pad, and the same description is applicable to all memory ranks 103I-N, according to the embodiments of the invention. In one embodiment, the memory rank 103i resides in a memory module. In other embodiments, the memory rank 103i does not reside in a memory module. In one embodiment, the memory rank 103i receives the ODT signal 109 from the memory controller 101 via a receiver 212.
In one embodiment, depending on the logical level of the ODT signal 109, a termination logic unit 212 coupled to the receiver 212 (shown as a single block for simplicity purposes) assigns the first or the second termination impedance value to the ODT unit 104i. In one embodiment, the termination logic unit 212 comprises the first and the second logic units 202 and 203 discussed with reference to Fig. 2A. In one embodiment, the termination unit 212 receives a signal from the first and the second logic units 202 and 203 discussed below with reference to Fig. 2A to provide the first and the second termination impedance values from the DRAM Mode Register 211 to the ODT
In one embodiment, when the ODT signal 109 is de-asserted, the first termination impedance value (value 1), which is also the default termination impedance value for the ODT unit 104i, is assigned to the ODT unit 104i from the DRAM Mode Register 211. In one embodiment, when the ODT signal 109 is asserted, the second termination impedance value (value 2) is assigned to the ODT unit 104i from the DRAM Mode Register 211. In one embodiment, the termination impedance values (value 1 and value 2) in the DRAM Mode Register 211 are programmable via hardware or software.
Referring back to Fig. 2A, in one embodiment, the memory controller 101 further comprises a first logic unit 202 and a second logic unit 203. In one embodiment, the first logic unit 202 is operable to assign the first termination impedance value setting from the register 201 to any of the ODT units 104I_N that correspond to the ranks 103i_Nthat are not being accessed by the memory controller 101. In such an embodiment, the level of the ODT signal 109 is de-asserted. In one embodiment, the first logic unit 202 is operable to assign the first termination impedance value setting stored in the DRAM Mode register of the rank to the ODT unit of the rank. In one embodiment, the first logic unit 202 is operable to assign the first termination impedance value setting by turning on or off the pull-up resistors of the ODT units 104I_N to configure them to have the first termination impedance value setting.
As mentioned above, the level of the ODT signal 109 is de-asserted when setting the first termination impedance value for the ODT units 104i_N of the ranks not being accessed by the memory controller 101. In one embodiment, the second logic unit 203 is operable to dynamically switch the first termination impedance value setting to the second termination impedance value settings for the ODT units 104I_N of the ranks being assessed in response to the level of the ODT signal 109 being asserted.
In such an embodiment, the second logic unit 203 is operable to turn on or off the resistors from the plurality of resistors of the termination units 104i_ that correspond to the I/O pins/pads of the ranks being accessed by the memory controller 101. In one embodiment, the first and the second logic units assign the first and the second termination value settings to the ODT units 104I_N via an I/O transmitter 204 of the memory controller 101. In one embodiment, the first and the second logic units are operable assign the first and the second termination value settings to the ODT units 104I_N of each rank from the values stored in the DRAM Mode Register of each rank 103I_N.
Fig. 3 is a flowchart 300 for dynamically providing finite termination impedance settings to the ranks, according to one embodiment of the invention. The flowchart is discussed with respect to the embodiments of Fig 1 and Figs. 2A-B.
At block 301 a first impedance value is set in the register 201 of the memory controller 101 or in the one or more ranks 103 I_N. AS mentioned above, the first impedance value (value 1) is a finite impedance value for any of the ODT units 104I_N of the I/O pins/pads that corresponds to the ranks that are not being accessed by the memory controller 101. At block 301, a second impedance value (value 2) is also set in the register 201 of the memory controller 101 or in the one or more ranks 103Ι_Ν· AS discussed above, in one embodiment, the register 201 resides in the individual ranks 103I_N (See, DRAM Mode Register 211 of Fig. 2B). The second impedance value is also a finite impedance value for any of the ODT units 104I_N of the I/O pins/pads that correspond to the ranks being accessed by the memory controller 101. In one embodiment, the memory controller 101 is operable to set the first and the second impedance values via an operating system.
At block 302, the first termination impedance value setting is assigned via the first logic unit 202 and/or via the logic unit 212 of Fig. 2B to any of the ODT units 104i_ of the I/O pins that correspond to the ranks not being accessed by the memory controller 101. In one embodiment, the first termination impedance value is a default impedance value for the ODT units 104i_N of the I/O pins/pads that correspond to the ranks not being accessed by the memory controller 101. In one embodiment, the first termination impedance value is assigned to the ODT units 104i_N that are not being accessed. In such an embodiment, the level of the ODT signal 109 de-asserts.
At block 303, the second logic unit 203 and/or the logic unit 212 of Fig. 2B dynamically switches the first termination impedance value setting to the second termination impedance value setting in response to the assertion of the ODT signal 109. At block 303, the second impedance value setting is assigned to any of the ODT units 104I_N of the I O pins/pads that correspond to the ranks being accessed by the memory controller 101. In such an embodiment, the level of the ODT signal 109 asserts. The above embodiments allow different ranks of a memory system from among the ranks 103I_N of the one or more memory modules 102I_N to have different
programmable finite termination impedance value settings depending on which rank is being accessed and the logical level of the ODT signal 109. The finite impedance termination values dynamically switch from the first finite termination impedance value setting to the second finite termination impedance value setting and vice-a-versa in response to the ranks being accessed and the level of the ODT signal 109.
The above embodiments result in improved timing and voltage margins for the entire memory system compared to memory systems that only allow switching between a high impedance (infinite impedance) value setting and a finite impedance value setting. One reason for the improved timing and voltage margins is the reduction of signal reflections on the transmission lines between the memory controller and the ranks caused by the different finite termination impedance value settings for ODT units when the memories are being accessed and when they are not being accessed. The embodiments of the invention thus allow a memory system with DDR4 I/O interface to have a finite programmable termination impedance as its default impedance value.
Embodiments of the invention are also implemented via programmable computer- executable instructions stored on a machine-readable storage medium. For example, the method of Fig. 3 is programmable and executable by a computer. The machine-readable storage medium may include, but is not limited to, flash memory, optical disks, CD- ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, or other type of machine-readable storage media suitable for storing electronic or computer- executable instructions. For example, embodiments of the invention may be downloaded as a computer program which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).
Fig. 4 illustrates a system 400 to implement the methods disclosed herein, according to one embodiment of the invention. In one embodiment, the system 400 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, an Internet appliance or any other type of computing device. In another embodiment, the system 400 used to implement the methods disclosed herein may be a system on a chip (SOC) system. In one embodiment, the processor 410 has a processing core 412 to execute instructions of the system 400. In one embodiment, the processing core 412 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In one embodiment, the processor 410 has a cache memory 416 to cache instructions and/or data of the system 400. In one embodiment, the cache stores the instructions to execute the method of Fig. 3. In another embodiment of the invention, the cache memory 416 includes level one, level two and level three, cache memory, or any other configuration of the cache memory within the processor 410.
The memory controller 101, which is also referred to as the memory control hub
(MCH) 414, is operable to perform functions that enable the processor 410 to access and communicate with a memory 430 that includes a volatile memory 432 and/or a nonvolatile memory 434. The volatile memory 432 includes, but is not limited to,
Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. The non-volatile memory 434 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.
The memory 430 stores information and instructions to be executed by the processor 410. In one embodiment, memory 430 may also store temporary variables or other intermediate information while the processor 410 is executing instructions. In one embodiment, chipset 420 connects with processor 410 via Point-to-Point (PtP or P-P) interfaces 417 and 422. In one embodiment, chipset 420 enables processor 410 to connect to other modules in the system 400. In one embodiment of the invention, interfaces 417 and 422 operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like.
In one embodiment, chipset 420 connects to a display device 440 via an interface 426. In one embodiment, the display 440 includes, but is not limited to, liquid crystal display (LCD), cathode ray tube (CRT) display, or any other form of visual display device. In one embodiment of the invention, processor 410 and chipset 420 are merged into a SOC. In addition, chipset 420 connects to one or more buses 450 and 455 that interconnect various modules 474, 460, 462, 464, and 466. In one embodiment, buses 450 and 455 may be interconnected together via a bus bridge 472 if there is a mismatch in bus speed or communication protocol. In one embodiment, chipset 420 couples with, but is not limited to, a non-volatile memory 460, a mass storage device(s) 462, a
keyboard/mouse 464, and a network interface 466 via interface 424.
In one embodiment, the mass storage device 462 includes, but is not limited to, a solid state drive, a hard disk drive, an universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 466 is implemented by any type of well known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.1 1 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
While the modules shown in Fig. 4 are depicted as separate blocks within the system 400, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although the cache memory 416 is depicted as a separate block within the processor 410, the cache memory 416 can be incorporated into the processor core 412 respectively. In one embodiment, the system 400 may include more than one processor/processing core in another embodiment of the invention.
The term operable used herein means that the device, module, system, logic unit, protocol etc, is able to operate or is adapted to operate for its desired functionality when the device, module, system, or logic unit is in off-powered state.
Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the element. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.
While the invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, the dynamic switching of the termination impedance values from the first impedance value to the second impedance value may occur when the ODT signal 109 de- asserts instead of asserting. In such an embodiment, ODT signal 109 is de-asserted in response to a memory access from a rank. In one embodiment, the memory coupled to the memory controller 101 is a standalone DRAM.
The embodiments of the invention are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

Claims

We claim: 1. A method comprising:
setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory;
assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and
switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.
2. The method of claim I, wherein setting the first termination impedance value comprises setting a register in the memory with the first termination impedance value via an operating system.
3. The method of claim I, wherein the first termination impedance value is a default impedance value.
4. The method of claim 1 , wherein the termination signal level is an on-die
termination (ODT) signal of the memory.
5. The method of claim 4, wherein switching from the first termination impedance value setting to a second termination impedance value setting occurs the ODT signal is asserted.
6. The method of claim 4, wherein assigning the first termination impedance value setting to the termination unit occurs when the ODT signal is de-asserted.
7. The method of claim 1 further comprising setting the first and the second
termination value settings to finite impedance values respectively in a register of the memory.
8. The method of claim 1, wherein the termination unit comprises a plurality of pull- up resistors operable to turn on or off, and wherein assigning the first termination impedance value setting to the termination unit comprises turning on or off the resistors from the plurality of resistors.
9. The method of claim 1, wherein the VO interface of the memory is a Double Data Rate 4 (DDR4) interface of the memory.
10. The method of claim 1, wherein the memory resides in a memory module which is a Dual In-Line Memory Module (DIMM) with one or more Dynamic Random Access Memories (DRAMs).
11. The method of claim 1 , wherein the memory is a Dynamic Random Access
Memory (DRAM).
12. An apparatus comprising:
an interface operable to access a memory having a register with a first termination impedance value setting for a termination unit of an input-output (I/O) interface of the memory;
a first logic unit operable to assign the first termination impedance value setting to the termination unit when the memory is not being accessed; and
a second logic unit operable to switch from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.
13. The apparatus of claim 12, wherein the VO interface of the memory is a Double Data Rate 4 (DDR4) interface of the memory.
14. The apparatus of claim 12, wherein the memory is a Dynamic Random Access Memory (DRAM).
15. The apparatus of claim 12, wherein the memory resides in a memory module which is a Dual In-Line Memory Module (DIMM) with one or more Dynamic Random Access Memories (DRAMs).
16. The apparatus of claim 12, wherein the termination unit comprises a plurality of pull-up resistors operable to turn on or off in response to the termination signal level.
17. The apparatus of claim 12, wherein the first and the second logic units are operable to turn on or off the resistors from the plurality of resistors to set an impedance of the termination unit to the first and the second termination impedance value settings respectively.
18. The apparatus of claim 12, wherein the register is operable to be set with the first and second termination impedance values via an operating system.
19. The apparatus of claim 12, wherein the termination signal level is an on-die
termination (ODT) signal of the memory.
20. The apparatus of claim 19, wherein the second logic unit is operable to switch from the first termination impedance value setting to the second termination impedance value setting when the ODT signal is asserted.
21. The apparatus of claim 18, wherein the first logic unit is operable to assign the first termination impedance value setting to the termination unit when the ODT signal is de-asserted.
22. A system comprising:
a memory having a register operable to store a first termination impedance value setting for a termination unit of an I/O interface of the memory; and
a memory controller coupled to the memory and operable to adjust the termination impedance setting of the I/O interface of the memory, the memory controller comprising:
a first logic unit operable to assign the first termination impedance value setting to the termination unit when the memory is not being accessed; and
a second logic unit operable to switch from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.
23. The system of claim 21, wherein the I/O interface of the memory is a Double Data Rate 4 (DDR4) interface of the memory.
24. The system of claim 21, wherein the memory is a Dynamic Random Access
Memory (DRAM).
25. The system of claim 21, wherein the memory resides in a memory module which is a Dual In-Line Memory Module (DIMM) with one or more Dynamic Random Access Memories (DRAMs).
26. The system of claim 21, wherein the termination unit comprises a plurality of pull- up resistors operable to turn on or off in response to the termination signal level.
27. The system of claim 21, wherein the first and the second logic units are operable to turn on or off the resistors from the plurality of resistors to set an impedance of the termination unit to the first and the second termination impedance value settings respectively.
28. The system of claim 21, wherein the register is operable to be set with the first and second termination impedance values by an operating system or the memory controller.
29. The system of claim 21, wherein the termination signal level is an on-die
termination (ODT) signal of the memory.
30. The system of claim 28, wherein the second logic unit is operable to switch from the first termination impedance value setting to the second termination impedance value setting when the ODT signal is asserted, and wherein the first logic unit is operable to assign the first termination impedance value setting to the termination unit when the ODT signal is de-asserted.
PCT/US2011/042029 2010-06-28 2011-06-27 A method and apparatus for dynamic memory termination WO2012006025A2 (en)

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