WO2011138023A2 - Method and system for accurate synchronization of frequency, phase and symbol timing - Google Patents

Abstract

Disclosed is a method and system for synchronization of communication devices. The synchronization system or method includes a preamble formed by three stages or intervals, including a code generator for generating a set of complementary sequences having ideal autocorrelation properties; the codes are modulated and transmitted in a first stage of said preamble for the communication system to be synchronized; after this first stage a second stage of sinusoidal tones are transmitted; the method or system for synchronization also includes a code generator for generating a set of orthogonal families of sequences; the codes are modulated and transmitted as a channel distortion identification third stage in the preamble. The method or system for synchronization also includes a receiver that correlates the signal received by a stored replica of the first stage of the preamble obtaining a time stamp from the output of the correlation stage, also includes some Digital Phase Locked Loop to detect the tones of the second stage of the preamble, a demodulator for demodulating the third channel identification stage of the preamble, a correlator for correlating the sequences used in said third preamble obtaining the information of the distortion of the channel, a logic machine that uses the information to control the system clocks to extract the correct frequency, phase, and symbol time of the received signal.

Description

METHOD AND SYSTEM FOR ACCURATE SYNCHRONIZATON OF FREQUENCY, PHASE AND SYMBOL TIMING

Cross Reference to Related Application

This application claims the benefit of Provisional U.S. Patent Application No. 61/331 ,558, filed May 5, 2010, and incorporates by reference herein in its entirety.

Field of Technology

This application discloses subject matter that is related to the subject matter disclosed and claimed in the following applications: (1) Spanish Application No. P200401299, filed May 28, 2004; (2) International Patent Application No. PCT/ES2004/000553 filed on April 29, 2005; and (3) U.S. Patent Application No. 1 1/587,680, filed May 21 , 2007. The content of all such applications are incorporated by reference in this application as if they were fully set forth herein.

In current communication systems, when a high signal to noise ratio (SNR) is present in a channel and the theor etical efficiency is high, current devices are unable to obtain a great efficiency mainly because of channel identification errors and carrier, phase, and timing recovery errors due mainly to the interference or crosstalk caused by simultaneous users in the same area (in cell phone applications) or bundle (in Power Line Communications or Digital Subscriber Line applications). Equipment in a central office, called DSLAM, gather a number of communication links with Customers on the other side at home (Fig. 1). The continuous growing demand of broadband data links has become a big issue for telecom operators as noise generated by their customers (called crosstalk) degrades the performance of the overall system thereby reducing the quality of the service, increasing the number of claims, and lowering the benefits (i.e., the more users sharing a cable, the more degradation of every user link). In fact, crosstalk is the main source of degradation both in Digital Subscriber Line (xDSL) and Power Line Communications (PLC) systems reducing range and rate of such systems especially in the Far End (FEXT) where signals from other users in the same bundle couple with each other (Fig. 1 below). Due to the adverse effect of crosstalk in such communication systems, a lot of patent applications relating to crosstalk cancellation in the last few y ears have been filed, trying to cope with the source of the problem. A simple search in the USPTO database for "crosstalk" inside the title, produces more than 700 entries. Nevertheless, to cancel crosstalk you must know the exact noise that is interfering with every user independently. This is a difficult task to be solved that requires not only the identification of the noise generated by every user to the rest, but also the processing of all of these noises and then subtracting them from the signal received by every user.

Another way of understanding the problem of crosstalk is studying which effects induce crosstalk on communication systems performance and trying to reduce such degradation. This way, instead of cancelling crosstalk, the system, devices, and methods disclosed in this patent application cancel or reduce its effects on synchronization and channel identification blocks inside the system minimizing the degradation of its performance.

In communication systems such as xDSL and PLC, SNR of the channel can sometimes be very high; nevertheless, when trying to get the maximum theoretical throughput, complex Quadrature Amplitude Modulation (QAM) constellation must be used. These systems are nowadays mostly based on Discrete Multi-Tone (DMT) Modulation also called Orthogonal Frequency Division Multiplexing (OFDM) and, as will be shown below, they suffer from high degradation when crosstalk is introduced into their carrier, timing, phase, and channel recovery blocks.

The degradation of carrier and timing recovery in these systems has been very much studied. An example of such studies c an be seen i n T . Nicholas and John M. Cioffi, "The Effect of Timing Jitter on the Performance of a Discrete Multitone System," IEEE Trans. On Comm., Vol. 44, No. 7, July 1996. Also, phase estimation is a source of degradation in OFDM systems, as explained in Jinwen Shentu et al., "Effects of Phase Noise on Performance of OFDM Systems Using an ICI," I EEE Trans On Broadcasting, Vol. 49, No. 2, June 2003. Morever, channel identification errors in the performance of OFDM systems have also been studied as in, for example, Mohamad Aoude, Ph.D., "Performance Analysis of QPS OFDM with Fading, Frequency Offset, and Channel Estimation Error," Journal of Theoretical and Applied Information Technology, where not only synchronization issues are taken into account but also its implication in the channel estimation performance of OFDM.

Current techniques for OFDM synchronization make use of pilot frequencies that give the receiver information for frequency and phase recovery. Digital Phase Locked Loops (DPLL) techniques are extensively used to do this job, but the accuracy of these techniques are limited to the SNR (or carrier to noise ratio) on t h e pilot frequency, and the compromise between speed response and accuracy makes optimal synchronization a difficult task.

In current xDSL systems, efficiency is limited to 15 bits per second per Hertz due to technological aspects related to noise and implementation issues. Main noise sources are thermal, background, crosstalk, and digital signal processing (DSP) noise. Thermal noise and background noise can be modeled as an uncorrelated white Gaussian noise with a given spectral noise density. The crosstalk noise and DSP noise cannot be modeled as uncorrelated as it is due to similar signals being coupled to the line from other lines using the same bundle and the same frequencies. This noise generates high phase noise and interference to carrier frequency, phase, and symbol time estimation blocks and also to channel estimation blocks, three of the most important factors of degradation in current systems for relatively short distances and high data rates.

Golay complementary sequences have good properties for synchronization and have been widely used for generating accurate time stamps in data communication systems by sending these sequences using different modulation and demodulation techniques, such as disclosed in U.S. 6,567,482. In fact, PCT/ES2004/000553 by Diaz is used in this application as a first stage method to recover an accurate time stamp and then using the channel identification method described in U.S. Patent Application Publication No. 2008/01 12501 by using some of the symmetry properties of Golay complementary sequences to improve phase, carrier frequency, and symbol time recovery as well as channel recovery blocks in any data communication system. Nevertheless, the present system can be implemented also by using other kinds of sequences for time stamping as long as they have good autocorrelation properties.

Due to all these problems, a new way to obtain phase, carrier frequency, and symbol timing is proposed that can also improve the identification of the channel in real time for both wireline and wireless communication systems in high interference environments. Particularly in the case of wireless, when applying the techniques disclosed in this patent application, the performance of a mobile communication system can be improved very much (more than doubling the range and the rate) as cell phones and base stations can track in real time the carrier, phase, and timing as well as channel changes in order to correct their effects on data link, thus increasing the number of bits per Hertz that can be sent and the distance of coverage reducing also the power needed to communicate.

Brief Description of the Drawings

Fig. 1 is a block diagram of a DSL communication system where the present invention can be applied. It shows the connection from a Central Office (CO) grouping device (DSLAM) to many Customer Premises Equipment (CPE) at home, and below, as an example, a detail of the interference (FEXT Crosstalk) from other lines to the line number M(CPE_M).

Fig. 2. is a generic block diagram as an example of a wireless modem, inside a cell phone, performing the techniques described in this patent application.

Fig. 3 is an example of a preferred frame preamble schema of a communication system based on the techniques applied in this application.

Fig. 4 is a detailed result of the input synchronization signal and the result of the autocorrelation using the procedure disclosed in PCT/ES2004/000553.

Fig. 5 shows a pair of Golay complementary sequences: a) A sequence, 32 bits; b) B sequence, 32 bits; c) autocorrelation of A sequence; d) autocorrelation of B sequence; and e) sum of A and B autocorrelations.

Fig. 6 is a channel identification schematic with all the fundamental processing blocks. (Al , B) and (Al ort, Blort) are complementary pairs of sequences, and orthogonal to each other, this schematic being a preferred embodiment of U.S. Patent Application Publication No. 2008/01 12501.

Fig. 7 is a phase trimming algorithm flow diagram.

Fig. 8 is a detailed representation of how repetition pilot tones are added periodically to compensate slow variation of carrier frequencies. This way the efficiency is increased in slow changing channels.

Fig. 9 shows a symbol timing and phase balancing process using the result of the method defined in U.S. Patent Application Publication No. 2008/01 12501. A non-ideal delta, with unbalanced lateral lobes (arrows indicate the adjustments needed to balance the lobes) and optimized delta, obtained by equilibrating the lateral lobes are also shown as well as a conceptual drawing of the symbol sampling point, before (with arrows) and after balancing adjustment.

Fig. 10 is a flow chart of an exemplary transmission using the synchronization system and method described herein.

Detailed Description

One aspect of the invention relates to a method and apparatus for accurate synchronization of a communication system. Applying this method, a high immunity to noise carrier, symbol timing, and phase trimming can be done with very accurate results that allow any communication system to be more efficient in terms of energy and/or data rate and range.

Further, this method and apparatus, in multiple simultaneous communication systems sharing a transmission media and affected by crosstalk (e.g., in xDSL systems when multiple users share a bundle of wires, a PLC system sharing wires or power phases, etc), reduce the effect of crosstalk allowing a better performance without using crosstalk cancelling techniques and reducing the complexity of the system compared to current crosstalk reducing based communication systems.

An important aspect of this invention is that it is based on a specially generated preamble previous to sending any information data (see Fig. 3). This preamble can be repeated on every data transmission frame (see Fig. 8) or periodically and has three time intervals (31 , 32 and 33) allowing the receiver to obtain accurate information in order to recover data correctly transmitted during the frame. This preamble gives any device the correct information to correct all the transmission parameters discussed above: frequency, phase, and timing deviations, as well as transmission channel changes. Data can be sent in any way and by any means after this preamble, but the preamble remains the same structure.

Fig. 1 is an example of an application where the present system is applied. Other applications can be implemented but, in this case, a DSL modem based system is shown as it is a widespread application. Data from one personal computer (PC) at home is inserted to the modem at the Customer Premises Equipment (CPE) 10, the modem (see Fig. 2 for details) performs the preamble generation described herein at preamble encoder 26, modulates the information data afterward, and transmits the modulated signal in 27 to the Radio Frequency (RF) stage 28 and to a transmission medium. After travelling through the wire 1 1 , the Central Office (CO) equipment 12 demodulates the received signal and extracts from the preamble the information needed for correction. This process is done on both sides of the link as it is assumed to be bi-directional.

Fig. 2 reflects a detailed diagram of main blocks in a device (a wireless transceiver for any side of the link), for example, a cell phone, where the whole process is performed. A signal coming from the antenna 20 is demodulated in the block 21. Block 22 decodes the preamble and extracts the timing information for synchronization. Signal to Noise Ratio (SNR) 30 and channel information 24 are extracted and sent to a programmable system 29 that executes the algorithms described, finding and correcting any deviations in frequency and timing by controlling the oscillator (DDS) block 23. Simultaneously, block 24 extracts the information of the channel and this information is sent to the programmable device 29 where algorithms defined in this patent application are executed correcting any channel distortion in the receiver by controlling directly blocks 24 and 25. After activating equalization in 25, QAM modulation 27 is selected as a function of the SNR estimated in 30 and sent to the transmitter in order to change the QAM modulation in 27. After all these processes are done, information data arriving next to (i.e., immediately after) the preamble can be extracted correctly by the demodulator block 21 , depending on the modulation used 27 in the transmitter, and sent to the voice or data decoder at the application module 201. Fig. 3 is an example of a preferred preamble to be transmitted in order to extract the correct information to be used by this method. The proposed preamble is divided in three timing stages: frame and frequency synchronization time stamp (synchronization sequence) 31, frequency/phase synchronization (carrier pilot tones) 32, and equalization/symbol trimming (equalization sequences) 33.

First of all, applying the method described in PCT/ES2004/000553, a time synchronization period 31 is generated in order to detect the beginning of the preamble. The method described in PCT/ES2004/000553 is very accurate so it gives a good time stamp to be used in the rest of the stages. A possible implementation of the synchronism sequence consists of a prerecorded Golay sequence, which has previously been filtered in order to improve spectral efficiency and modulated using Quadrature Phase Shift Keying (QPSK). Nevertheless, any other kind of sequences, providing a good autocorrelation function, can be used for the same task. The frequency of the carrier is selected low enough so that it suffers the smallest attenuation and distortion as possible for a given application, even at large distances. On the other hand, the lower the carrier frequency, the higher the memory needed for storing the prerecorded synchronization sequence and for the synchronization processing modules in reception. So frequency has to be chosen as a compromise between hardware complexity and system reliability at large distances.

Fig. 4 shows the transmitted synchronization sequence 40 generated at the output of block 26 during synchronization interval 31 of the preamble. In reception, the synchronization sequence is filtered using a matched filter and then autocorrelated. The received synchronization signal is autocorrelated by using the process defined in PCT/ES2004/000553 at the receiver in 22. The result is passed through a synchronism detector block. This block locks to the highest synchronism peak 41 and generates a signal corresponding to the previous zero-crossing 42 of the highest peak, called the sync point. This signal is used as a time stamp indicating that a new frame has just started. This hardware indication resets the state of the machines and all the DDS in the receiver in order to adjust them in phase with the DDS in the transmitter.

As indicated in the previous paragraph, the synchronization sequence 40 and its result peak 41 serves as a reference point for both transmitter and receiver devices to synchronize all their oscillators (also called DDS) in equivalent phase. Therefore, every time a new frame starts, the transmitter and receiver will start working from a known, repeatable situation. In a communication system modem based on this method, DDS are used for generating the carrier frequencies and also for generating the symbol intervals (symbol timing), and a periodic defined reset must be applied to all the DDS in the system in order to work properly when a synchronization signal is received.

However, due to the fact that the transmitter and receiver are two different devices, each one with their own clocking mechanism, there is a frequency deviation between both devices. To compensate the frequency deviation, the receiver should use a different Frequency Carrier Word (FCW) than in the transmitter for its DDS, and this FCW should be calculated according to the clock difference between the two devices. Therefore, the clock difference between transmitter and receiver must be obtained. In order to achieve this, the transmitter uses a counter that starts from zero at the beginning of the transmission frame, and increments each system clock cycle. When a new frame starts, the value of this counter is saved in a readable register. The counter is reset and starts to increment again as each frame arrives. This counter value is called the nominal Period of Repetition Interval (PRInom or nominal frame period value), and it is a fixed value, which never changes in the transmitter used as the master. The same mechanism is used in the receiver in order to count the amount of clock cycles elapsed between two consecutive synchronism sequences. The synchronism signal generated by the peak of the autocorrelated sync sequence is used as a reference for this process. This is the measured PRI (PRImeas) value, and it can vary from one PRI to another, depending on the evolution of the receiver clock with respect to the transmitter one. This value can be used as such, or an average of previous values can be used for calculating the frequency compensation in receiver.

The formula used for calculating the adjusted FCW (FCWnew) in the receiver is as follows:

N

The FCWnew value is calculated and then updated into the corresponding registers. The hardware takes into account this new value just after the synchronization occurs in order not to distort the arriving information and to prevent changes occurring during the transmission of data or equalization sequences, which could temporarily disrupt the functionality of the system.

The precision of this adjustment depends on the precision of the FCW and DDS phase accumulator, the length of the PRI, and the number of PRInom values taken into account for calculating the average value. Although this method drastically reduces the frequency deviation in the receiver, it still lacks precision in order to achieve a perfect frequency and phase synchronization. The main reason for this is that the PRImeas is an indication of what has happened in the previous PRI, and this measure is used to adjust the frequency for current PRI, whose evolution cannot be predicted. This is an open-loop controller; therefore, no feedback is received from the changes that have been made before, which limits the precision of the adjustments. Also, as said above, the modem must use DDS not only for generating the carrier frequencies, but also for generating the symbol interval (symbol timing) and the periodic frequency compensation technique applied to both carrier DDS and symbol interval DDS, in order to work properly.

Although at this stage of the synchronization process, frequency, and symbol timing has been correctly estimated, there are still some differences in the phase estimation between transmitter and receiver that must be corrected.

In a communication system, a third stage is used for channel estimation and equalization (defined in U.S. Patent Application Publication No. 2008/01 12051 ) that is used in the system of this patent application for phase trimming. In order to understand the concept of phase trimming, we need to briefly describe the equalization process first.

Marcel J. E. Golay introduced the concept of complementary sequences in 1961. These complementary sequences are sets of L-length sequences with the useful property that their periodic autocorrelation coefficients sum corresponds to a r6necker delta. Fig. 5 shows an example of this property where a pair of Complementary Sequences 50 and 51 , of length L=32, have their corresponding autocorrelations 52 and 53. The addition of both autocorrelations results in an ideal Kronecker delta 54 without lateral lobes.

It is well known that data sent through any medium gets distorted and attenuated. The useful properties of the Golay complementary sequences help to estimate the transfer function of the channel, and use this transfer function to equalize the received data. Applying the method disclosed in U.S. Patent Application Publication No. 2008/01 12501 , using two pairs of orthogonal complementary Golay sequences, the channel transfer function can be identified and the information obtained is used to correct the distorted received data. Fig. 6 shows the block diagram of a channel identification system applying these properties. The set of orthogonal sequences (in this case two pairs Al , B l and A l ort, B l ort) are generated on the transmitter side 60 and 61 respectively. They are shaped in order to improve spectral efficiency and reduce Inter-Symbol Interference (ISI) 62, then modulated in quadrature 63 and sent to the channel 64. Each quadrature carrier conveys a set of complementary sequences, delayed in time by A symbols by means of blocks 65. The two sets of complementary sequences transmitted in quadrature are orthogonal between them (Al , Bl) and (Al_ort, B l_ort)- The receiver (Fig. 8 down) demodulates the signals received 66, passes them through a set of filters 67 that remove unwanted spectral components, and then calculates the autocorrelation function 68 of the filtered signals recovering the original delays and adding the results 69.

Although the main use of the complementary sequences in this embodiment is to equalize data, they optionally are also used to optimally adjust the phase of the carriers, a process called phase-trimming. This is a software-based process that uses as a feedback the autocorrelation peak 54, which will be called "delta" on what follows. The main concept behind the phase trimming procedure is that if the correct phase is set in the carrier DDS in reception, the equalization delta at the output of the correlator will have a maximum value.

In order to properly adjust the phase, two different phases are set and the values of the delta corresponding to these two phases are obtained. With these two delta values, the correct phase can be calculated for the carrier DDS in reception. This process is done only once, while the operating conditions of the modem remain the same.

In order to define a fast and simple algorithm that allows to set the correct phase for the carrier DDS in reception, the behavior of the delta peaks at the output of the correlator (51 and 5Q) related to the phase error is analyzed. The two values of the delta (51 and 5Q) decrease proportionally to the cosine of the phase error (p). 61 and 5Q are very sensitive to the noise when the phase error is almost zero, therefore, we cannot use a successive approximation algorithm, because of the lack of precision.

The maximum values of the delta (51 and 6Q), at the output of the correlator, can be expressed as:

δ = 0_max cos(Ap)

Therefore, the delta values that correspond to different angles and different phase errors (pi and p2) are represented as:

δΐ = 6_max cos(Apl )

δ2 = 6_max cos(Ap2)

Solving these equations, by eliminating S_max and representing Δρ ΐ as a function of Δρ2, we obtain the formula for the phase error (Δρΐ ) and therefore the value to correct phase (P).

δΐ = 6_max cos(Apl )

δ2 = d_max cos(Apl -7t/2) = dmax sin(Ap 1 - π/2)

Δρΐ = atan (81/62) ρ = ρ1 - Δρ1

Fig. 7 shows a flow diagram of the phase trimming where the steps for this algorithm are as follows:

First, block 70 sets an initial phase value (p i ), and block 71 reads the delta that belongs to this phase (δΐ ). In order for the algorithm to work properly, block 72 checks that the chosen phase is a valid one assuring that the delta value is not too small Ιδΐ l>0.05 δπ_ΐΒχ)· If this is not true, block 73 sets another initial phase pi = pi + π/4 and the value of the corresponding delta (Ιδΐ l>0.05 6_max) is checked again. Next, block 74 sets a new phase value p2 = pi - π/2, and block 75 reads the associated delta value from the hardware. A block 76 checks again that the chosen phase is valid by checking the value of the delta as described in more detail for block 72.

Thereafter, block 77 computes the phase error, wherein the phase error = atan (52/51), and the correct phase is calculated as p = pi - error.

Sometimes the phase obtained as a result of the phase trimming algorithm is 180° opposite to the correct phase. To solve this issue, the delta sign is checked, and if negative, the phase is replaced by its opposite phase.

Although the phase trimming technique does a good job for identifying the proper phase for the carrier DDS, it still needs some fine adjustments to lock to the perfect phase. To achieve this, short-interval pilot tones 31 are transmitted and a basic Costas Loop is used in reception to recover the phase. As the main job of phase recovery has been done by the phase trimming algorithm of Fig. 7, the pilot tones can be very short in duration, as the Costas Loop will lock very fast to the proper phase. The phase trimming process is done only once, during the initialization stage of the modem, and the Costas adjustment is done periodically, at the beginning of each frame. The phase trimming adjusts the carriers' phases only, while the Costas Loop adjusts the phase of the carrier DDS and the phase of the DDS that generates the symbol timing, as well.

In this method, a number of pilot tones 32 are added in the preamble, depending on the bandwidth applied, and only one pilot for the DDS that' generates the symbol timing. Although parallel tones can be applied, for more accuracy, tones are sent in a serial mode, one at a time. Although this introduces some overhead in the PRI, it has two advantages. First, it leads to very precise phase detection, without an aggressive filtering. The low-pass filter used for the Costas Loop is a compromise between proper filtering, fast response time, and low hardware footprint. By having just one tone at its inputs, the filter specifications can be less stringent. Second, it allows the use of just one Costas Loop module for all the eight carriers plus the symbol timing tone. The Costas Loop module is a module with a heavy on chip hardware footprint (6-7 multipliers, plus the filter memory); using just one module, allows a big hardware reduction.

The two techniques described above employed for carrier phase adjustment complement each other and lead to an optimal phase synchronization. However, due to the lack of precision of the Period Frequency Compensation technique, this phase synchronization gets degraded as the PRI evolves. One solution for this would be to identify an optimum PRI length (frame length) that allows a good recovery of symbols, while not introducing too much overhead. However, studies done in simulation and real- life environments have indicated that the PRI could be as large as desired (providing that the system hardware supports it), if a good synchronization is achieved and kept during the PRI. Therefore, the PRI could be extended to the desired length, and the Pilot Tones could be inserted at certain intervals, allowing the modem to keep tightly synchronized. This way, the overhead of the communication can be drastically reduced because the synchronization and equalization sequences are sent only once in preamble interval 80 during large PRI. Fig. 8 (up) shows the repetitive Pilot Tones 81 inserted into the data frame interval 82 out of the preamble interval 80 and a detail of the space added inside the data frame interval (Fig. 8, down).

Another problem to solve is the trimming of the symbol phase or symbol phase balancing. An ideal Kronecker delta is obtained when the autocorrelated Golay sequences used for channel identification are added together. However, due to the filters used in transmission and reception, modulation/demodulation process and the channel attenuation and distortion, the delta obtained in real environments presents lateral lobes as shown in Fig. 9. The delta 94 is not symmetrical, the lateral lobes present a certain unbalance 90. It has been proved that a strong unbalance can have a notable impact on the equalizer performance, leading it to poorer results. Therefore, it is desirable to have a delta with lateral lobes as symmetrical as possible 91 in order to achieve good results.

The delta lobes can be reduced or increased in value by shifting the phase of the symbol sampling DDS 92 that generates the symbol sampling point. The action done on one of the lobes has a complementary effect on the other lobe: when one increases, the other one decreases, and the opposite.

It is easy to develop an algorithm based on the information the delta lobes provide. Such an algorithm has to take into consideration the initial level of the delta lobes, and start applying changes to the symbol timing phase, until a good equilibrium is achieved and receiver DDS phase 92 approach to ideal 93. A successive approximation algorithm is very adequate for this implementation. The symbol timing phase can be adjusted in discrete steps 92, which are implemented as symbol timing delays, in hardware. Therefore, such an algorithm is extremely fast. Besides, it has to be done, only once during the initialization stage of the communication system. Fig. 9 describes in graphical detail the Symbol Phase Balancing algorithm. This technique is complementary to the other adjustments applied to the symbol timing DDS and it helps to achieve a good equalization when in this stage of the preamble.

When a user starts the process of making a digital data transmission from a transmission terminal, such as a user transceiver terminal, to a receiver terminal, such as a base transceiver terminal or a second user transceiver terminal, the user transceiver terminal generates (preferably internally) the three stages that form the whole synchronization preamble 80 to be transmitted, i.e., the synchronization sequence 31 , the pilot tones 32, and the equalization sequences 33. The user transceiver terminal then transmits the entire synchronization preamble 80 periodically in the manner described previously herein until both the user transceiver terminal and the base transceiver terminal are synchronized. After the user transceiver terminal and the base transceiver terminal are synchronized, digital data, such as data, pictures, music, voice or any other type of digital data capable of being transmitted by the user transceiver terminal, is added to the transmission following the synchronization preamble, as described previously herein, and the user transceiver terminal exchanges information with the base transceiver terminal. Thereafter, the base transceiver terminal sends to a network of additional transceivers that the first user transceiver terminal wants to send digital data to the second user transceiver terminal, and the same synchronization protocol is repeated with each transceiver in the link between the first user transceiver terminal and the second user transceiver terminal until each transceiver terminal in the link is synchronized and then starts communication by adding data to the preamble. The process is performed simultaneously in both directions of communication, i.e., up and down the link, in order to achieve full duplex communication between the first and second user transceiver terminals.

In Fig. 10, an exemplary implementation of the system and method of conducting a transmission using the synchronization system described herein is shown in the context of a telephone call made by a mobile telephone on a wireless telephone network. At block 101 a user begins a telephone call and/or text transmission on his/her mobile telephone by, for example, initiating a call or text send function on the mobile telephone. At blocks 102a, 102b, and 102c, the mobile telephone internally generates the three synchronization stages, i.e., the time synchronization period 31 , the pilot tones 32, and the equalization sequence 33, that form the whole preamble 80 to be transmitted. The synchronization sequence 31 is generated at block 102a, the pilot tones are generated at block 102b, and the equalization sequence(s) is/are generated at block 102c. Next at block 103, the synchronization preamble 80 is transmitted from the mobile telephone to a base station, and at block 104 the mobile telephone and the base station are synchronized with each other in the manner described previously herein. The mobile telephone continues to transmit the synchronization preamble 80 periodically to the base station, until both the mobile telephone and the base station are synchronized with each other. After the mobile telephone and the base station are synchronized, data and/or voice are added following the synchronization preamble, as described previously herein, and the mobile telephone interchanges information with the base station. Then, the base station sends to the broader network that the first mobile telephone wants to send information or voice to a second mobile telephone, and this process is repeated along as many receiver/transmitter links as necessary until the second mobile phone receives the telephone call at block 106. The second mobile phone, when reached, receives the synchronization preamble at block 107, and at block 108 synchronizes in the same manner as described previously (i.e., with the same synchronization protocol) with its base station. The second mobile telephone further, at block 1 10, equalizes the received digital data using the equalization sequence 33 received during the equalization interval. After both the second mobile telephone and its base station are fully synchronized, the second mobile telephone also starts communication at block 1 1 1 by adding data after its own synchronization preamble. This process is performed simultaneously in both directions between the two mobile telephones in communication, i.e., up and down the network, in order to perform a full duplex communication. When either mobile telephone stops transmissions, the telephone call is ended at block 1 12. It is apparent to a person of skill in the art that the present synchronization system and method are not limited to mobile telephone calls, and that the synchronization system and method may be used for many other suitable digital data communications modes in a similar manner.

An exemplary embodiment of the present invention concerns a method for accurate synchronization of frequency carrier, phase carrier, and symbol timing comprising the steps of:

(a) generating a complementary sequence set at the transmitter;

(b) modulating such sequences in quadrature modulation;

(c) transmitting the generated signal as a preamble for communication system synchronization;

(d) generating a set of sinusoidal tones with different frequencies and different time separation and transmitting them after the synchronization sequence;

(e) generating a set of orthogonal complementary sequences for the equalization preamble;

(f) modulating the complementary sequences set in quadrature, separated in time and transmitting them after the synchronization tones;

(g) receiving the transmitted preamble distorted by a transmission medium;

(h) correlating the synchronization signal by a stored replica of the transmitted one and obtaining a synchronization time stamp in the receiver;

(i) resetting the receiver digital oscillator (DDS) to recover the frequency and phase differences;

G) demodulating the equalization preamble and use the lateral lobes unbalance to be used as a signal control for symbol timing and sampling.

This exemplary method can be further adapted in one or more of the following

(1) wherein a trigger begins step of generating a synchronization preamble before sending data;

(2) wherein the preamble is composed by at least two time intervals: synchronization and channel identification;

(3) wherein the preamble is composed by three time intervals: synchronization, Pilot tones, and channel identification;

(4) wherein the synchronization interval of the preamble is generated by transmitting a set of complementary

sequences;

(5) wherein the synchronization interval of the preamble is generated by transmitting a set of sequences with good autocorrelation properties;

(6) wherein the sinusoidal tones are generated after the synchronization interval; (7) wherein the channel identification interval is generated by transmitting a family of sets of complementary sequences in parallel;

(8) wherein the channel identification interval is generated by transmitting a family of sets of complementary sequences in a sequential way;

(9) wherein the channel identification interval is generated by transmitting a family of sets of complementary sequences in a sequential way, adding blank spaces (silences) among them;

(10) wherein the sequences used are modulated using a quadrature modulation;

(1 1) wherein the quadrature modulation is a M-QAM modulation technique;

(12) wherein the quadrature modulation is a QPSK modulation technique;

(13) wherein a set of N complementary sequences are generated;

(14) wherein a replica of the synchronization signal is stored in the receiver;

(15) wherein the received signal is correlated with the stored synchronization signal in the receiver to detect a time stamp;

(16) wherein the time stamp signal starts a reset in the oscillators of the receiver;

(17) wherein the calculation of the differences in frequency between transmitter and receiver is calculated counting the number of system clock intervals between at least two received time stamps and using this information to correct the receiver oscillators; (18) wherein the channel identification interval received signal is used to obtain information of the channel transfer function to equalize data in module and phase;

(19) wherein the channel identification interval received signal is equalized with data extracted in previous channel identification intervals;

(20) wherein the levels of the peaks of the equalized channel identification interval signal are used to control the phase of the demodulator blocks at receiver; and/or

(21) wherein the unbalance in lateral lobes of the equalized channel identification interval signal is used to control the symbol timing and sampling at the receiver.

A device incorporating one or more aspects of the claimed invention comprises a program memory; a data storage memory; a processor that is operatively coupled to the program memory and the data storage memory; wherein the program memory contains:

a first set of instructions that, when executed, generates a complementary sequence set;

a second set of instructions that, when executed, modulates such sequences in quadrature modulation;

a third set of instructions that, when executed, transmits the generated signal as a preamble for communication system

synchronization;

a fourth set of instructions that, when executed, generate a set of sinusoidal tones with different frequencies and different time separation and transmit them after the synchronization sequence;

a fifth set of instructions that, when executed, generate a set of orthogonal complementary sequences for the equalization preamble; and

a sixth set of instructions that, when execute, modulate the complementary sequences set in quadrature, separated in time, and transmits them after the synchronization tones.

The device also includes the following sets of instructions in the program memory;

a seventh set of instructions that, when executed, receives a transmitted preamble distorted by a transmission medium;

an eighth set of instructions that, when executed, correlate the synchronization signal by a stored replica of a transmitted one and otain

a synchronization time stamp in the receiver;

a ninth set of instructions that, when executed, reset the receiver digital oscillator (DDS) to recover the frequency and phase differences;

and

a tenth set of instructions that, when executed, demodulate the

equalization preamble and use the lateral lobes unbalance to be used as a

signal control for symbol timing and sampling.

The above-noted sets of instructions can be modified to accomplish one or more of the criteria specified in indented paragraphs 1 -21 on the preceding two pages.

Although the foregoing text sets forth a detailed description of numerous different embodiments, it should be understood that the scope of the patent is defined by the words of the claims set forth at the end of this patent application. The detailed description is to be construed as exemplary only and does not describe every possible embodiment because describing every possible embodiment would be impractical, if not impossible. Numerous alternative embodiments could be implemented, using either current technology or technology development after the filing date of this disclosure, which would still fall within the scope of the claims.

Claims

I/we claim:

1. A method for accurate synchronization of frequency carrier, phase carrier, and symbol timing, the method comprising:

generating a complementary sequence set at a transmitter;

modulating the sequence set in a quadrature modulation, thereby generating a synchronization sequence, and transmitting the synchronization sequence;

generating a set of synchronization tones comprising a set of sinusoidal tones with different frequencies and different time separation and transmitting the synchronization tones after the synchronization sequence;

generating a set of orthogonal complementary sequences;

modulating the orthogonal complementary sequences set in quadrature, separated in time, thereby forming an equalization sequence, and transmitting the equalization sequence after the synchronization sequence;

wherein the synchronization sequence, synchronization tones, and equalization sequence form a preamble to a data signal for communication system synchronization;

receiving at a receiver the preamble distorted by a transmission medium;

correlating the distorted synchronization sequence with a stored replica of the transmitted synchronization sequence and obtaining therefrom a synchronization time stamp in the receiver;

resetting a digital oscillator of the receiver to recover frequency and phase differences between the transmitter and the receiver; and

demodulating with a demodulator block the equalization sequence of the preamble and using unbalanced lateral lobes contained therein as a signal control for symbol timing and sampling.

2. The method of claim 1 , wherein a trigger begins a step of generating the synchronization sequence before sending the data signal.

3. The method of claim 1 , wherein the preamble is composed of at least two time intervals comprising a synchronization interval and a channel identification interval.

4. The method of claim 3, wherein the preamble comprises three time intervals: the synchronization interval, a pilot tone interval, and the channel identification interval.

5. The method of claim 4, wherein the synchronization interval of the preamble is generated by transmitting a set of complementary sequences.

6. The method of claim 4, wherein the synchronization interval of the preamble is generated by transmitting a set of sequences with good autocorrelation properties.

7. The method of claim 4, wherein the sinusoidal tones are generated after the synchronization interval.

8. The method of claim 4, wherein the channel identification interval is generated by transmitting a family of sets of complementary sequences in parallel.

9. The method of claim 4, wherein the channel identification interval is generated by transmitting a family of sets of complementary sequences sequentially.

10. The method of claim 4, wherein the channel identification interval is generated by transmitting a family of sets of complementary sequences sequentially and adding blank spaces among them, wherein the blank spaces comprise silences.

1 1. The method of claim 1 , wherein the equalization sequence is modulated using a quadrature modulation.

12. The method of claim 1 1 , wherein the quadrature modulation is an M-QAM modulation technique.

13. The method of claim 1 1 , wherein the quadrature modulation is a QPSK modulation technique.

14. The method of claim 2, wherein a set of N complementary sequences are generated.

15. The method of claim 1 , wherein the replica of the synchronization signal is stored in the receiver.

16. The method of claim 1 , wherein the received preamble is correlated with the stored synchronization signal in the receiver to detect the time stamp.

17. The method of claim 1 , wherein the time stamp starts a reset in the digital oscillator.

18. The method of claim 1 , wherein the differences in frequency between the transmitter and the receiver is calculated by counting the number of system clock intervals between at least two received time stamps and using this information to correct the digital oscillator.

19. The method of claim 4, wherein the channel identification interval received is used to obtain information of the channel transfer function to equalize data in module and phase.

20. The method of claim 4, wherein the channel identification interval received is equalized with data extracted in previous channel identification intervals.

21. The method of claim 20, wherein the levels of peaks of the equalized channel identification interval signal are used to control the phase of the demodulator block at the receiver.

22. The method of claim 20, wherein unbalance in lateral lobes of the equalized channel identification interval signal is used to control symbol timing and sampling at the receiver.

23. A device for synchronizing a frequency carrier, the device comprising:

a computer processor;

a transmitter operatively coupled to the computer processor;

a data storage memory operatively coupled to the computer processor; and a program memory operatively coupled to the computer processor, wherein the program memory comprises instructions that, when executed by the computer processor, implement the following steps:

generating a complementary sequence set;

modulating the sequence set in a quadrature modulation;

transmitting the modulated sequence set as a preamble to a data set, the modulated sequence set comprising a synchronization sequence for communication system

synchronization;

generating a set of sinusoidal tones with different frequencies and different time separation and transmitting the set of sinusoidal tones after the synchronization sequence; generating a set of orthogonal complementary sequences for an equalization preamble; and

modulating the equalization preamble, separated in time, and transmitting the modulated orthogonal complementary sequence set after the sinusoidal tones.

24. The device of claim 23, further comprising a receiver comprising a digital oscillator, the receiver operatively coupled to the computer processor, wherein the program memory further comprises instructions that, when executed by the computer processor, implement the following steps:

receiving at the receiver a transmitted preamble distorted by a transmission medium, wherein the transmitted preamble comprises a synchronization sequence;

correlating the received synchronization sequence to a stored replica of the transmitted synchronization sequence and obtaining therefrom a synchronization time stamp in the receiver;

resetting the digital oscillator of the receiver to recover frequency and phase differences between the transmitter and the receiver; and

demodulating the equalization preamble and using unbalance of lateral lobes contained therein as a signal control for symbol timing and sampling.