WO2011126525A1 - Active mute scheme for an amplifier - Google Patents
Active mute scheme for an amplifier Download PDFInfo
- Publication number
- WO2011126525A1 WO2011126525A1 PCT/US2010/061431 US2010061431W WO2011126525A1 WO 2011126525 A1 WO2011126525 A1 WO 2011126525A1 US 2010061431 W US2010061431 W US 2010061431W WO 2011126525 A1 WO2011126525 A1 WO 2011126525A1
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- WO
- WIPO (PCT)
- Prior art keywords
- amplifier
- switch
- coupled
- control signal
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
Definitions
- the invention relates generally to an amplifier and, more particularly, to an active mute scheme for an amplifier.
- Muting circuitry is commonly employed with audio and other amplifiers.
- a example embodiment of the invention accordingly, provides an apparatus.
- the apparatus comprises a first pin; a second pin; a third pin; an amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the output terminal of the amplifier is coupled to the third pin; a first switch network that is coupled between the first pin and the first input terminal of the amplifier and that is coupled between the second pin and the second input terminal of the amplifier; a second switch network that is coupled to the first input terminal of the amplifier, the second input terminal of the amplifier, and the output terminal of the amplifier; and a controller that is coupled to provide a first control signal to the first switch network and that is coupled to provide a second control signal to the second switch network, wherein the first control signal activates each switch in the first switch network during an amplify mode and a transition mode, and wherein the second control signal activates each switch in the second switch network during a mute mode and the transition mode, and wherein feedback through the amplifier during the mute mode actively mutes the amplifier.
- the amplifier further comprises a class AB audio amplifier.
- first switch network further comprises: a first switch that is coupled between the first pin and the first input terminal of the amplifier, wherein the first switch is controlled by the first control signal; and a second switch that is coupled between the second pin and the second input terminal of the amplifier, wherein the second switch is controlled by the first control signal.
- the first and second switches further comprise MOSFET switches.
- rise and fall times for the first control signal are about 30 ⁇ 8.
- the second switch network further comprises: a first switch that is coupled between the output terminal of the amplifier and the first input terminal of the amplifier, wherein the first switch is controlled by the second control signal; and a second switch that is coupled between the second input terminal of the amplifier and ground, wherein the second switch is controlled by the second control signal.
- the second switch network further comprises a resistor that is coupled between the first switch and the first input terminal of the amplifier.
- the resistor further comprises a first resistor
- the second switch network further comprises: a third switch that is coupled to the first input terminal of the amplifier, wherein the third switch is controlled by the second control signal; and a second resistor that is coupled between the third switch and ground.
- the first and second resistor each have a resistance of about 10kQ.
- the first, second, and third switches further comprise MOSFET switches.
- rise and fall times for the second control signal are about 30 ⁇ 8.
- the length of the transition mode is at least about 100 ⁇ 8.
- an apparatus comprising a first pin; a second pin; a third pin; an amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the output terminal of the amplifier is coupled to the third pin; a first switch network having: a first switch that is coupled between the first pin and the first input terminal of the amplifier; and a second switch that is coupled between the second pin and the second input terminal of the amplifier; a second switch network having: a third switch that is coupled to the output terminal of the amplifier; a fourth switch that is coupled between the second input terminal of the amplifier and ground; a first resistor that is coupled between the first switch and the first input terminal of the amplifier; a fifth switch that is coupled to the first input terminal of the amplifier; and a second resistor that is coupled between the third switch and ground; and a controller that is coupled to provide a first control signal to the first and second switches and that is coupled to provide a second control signal to the third, fourth, and fifth switches,
- a method comprises activating a plurality of switches in a first switch network with a first control signal during an active mode so as to amplify a signal from a signal source with an amplifier; activating a plurality of switches in a second switch network with a second control signal during a transition mode to retain closed loop operation of the amplifier; and deactivating the plurality of switches in the first switch network with the first control signal during a mute mode so that feedback through the amplifier actively mutes the amplifier, wherein the mute mode follows the transition mode.
- FIG. 1 is a block diagram of an example of a circuit in accordance with an example embodiment of the invention.
- FIG. 2 is a timing diagram for the control signals of the circuit of FIG. 1.
- the reference numeral 100 generally designates a circuit in accordance with an example embodiment of the invention.
- Circuit 100 generally comprises an integrated circuit (IC) 102 and resistors R3, R4, R5, and R6. Resistors R3, R4, R5, and R6 are coupled to pins 108, 110, and 112 of IC 102 in order to amplify input signal AIN so as generate output signal OUT.
- IC 102 generally comprises switch networks, amplifier 104 (which is typically a class AB audio amplifier), and controller 106.
- IC 102 generally operates the amplifier 104 in three modes: active mode, transition mode, and mute mode. Each of these modes can be seen in FIG. 2.
- active mode which is shown between times tO and tl of FIG. 2
- control signal CNTL2 is asserted by controller 106 so that switches SI and S2 (of one of the switch networks) are activated.
- switches SI and S2 are activated, the amplifier 104 normally amplifies the input signal AIN.
- control signals CNTL1 and CNTL2 are both asserted by controller 106 to activate switches SI through S5 (of all of the switch networks).
- the transition mode (which is generally at least about 100 ⁇ 8 in length) is provided to maintain closed loop operation of amplifier 104; without the transition mode, the amplifier 104 would generate audible artifacts (for audio applications) associated with open loop operation.
- control signal CNTL1 is asserted to activate switches S3, S4, and S5 (of one of the switch networks). Switches S3, S4, and S5 enable the positive input terminal of amplifier 104 to be grounded while feedback from the output terminal of amplifier 104 can be provided through resistors Rl and R2 (which are each generally about 10kQ) to the negative input terminal of amplifier 104. This feedback actively mutes the amplifier 104 by driving the output signal OUT to null or ground with an attenuation of about 70-80dB or higher.
- each switch SI through S5 is generally a MOSFET switch. This means that charge injection from these switches SI through S5 should be considered for the relative sizes of switches SI through S5 and rise/fall times of control signals CNTL1 and CNTL2. Typically, the rise and fall times for control signals CNTL1 and CNTL2 (as shown between times tl to t2 and times t3 to t4 in FIG. 2) are about 30 ⁇ 8. Additionally, dummy switches can be employed for switch injection cancellation.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
Conventional muting circuitry for amplifiers (which usually uses clamps) generally has about 20- 30dB of attenuation. A described circuit (100) generally comprises an integrated circuit (IC) (102) and resistors (R3, R4, R5, R6) coupled to pins (108, 110, 112) of the IC (102) in order to amplify an input signal (AIN) so as generate an output signal (OUT). IC (102) generally comprises switch networks, amplifier (104) (which is typically a class AB audio amplifier), and a controller (106). The controller provides control signals to the switch network to provide mute functionality by actively muting the amplifier. In particular, feedback is provided through at least one of the switch networks to drive the output of the amplifier to null or ground so as to provide 70-80dB (or more) of attenuation.
Description
ACTIVE MUTE SCHEME FOR AN AMPLIFIER
[0001] The invention relates generally to an amplifier and, more particularly, to an active mute scheme for an amplifier.
BACKGROUND
[0002] Muting circuitry is commonly employed with audio and other amplifiers.
Typically, clamps are employed (either on the input or output terminals of the amplifier) to provide this function. These conventional muting circuits, however, usually only provide about 20-30dB of attenuation. So there is a need for muting circuitry with greater attenuation. Some examples of conventional circuits are described in U.S. Patent Nos. 5,166,983; 7,102,400; and 7,102,414.
SUMMARY
[0003] A example embodiment of the invention, accordingly, provides an apparatus is provided. The apparatus comprises a first pin; a second pin; a third pin; an amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the output terminal of the amplifier is coupled to the third pin; a first switch network that is coupled between the first pin and the first input terminal of the amplifier and that is coupled between the second pin and the second input terminal of the amplifier; a second switch network that is coupled to the first input terminal of the amplifier, the second input terminal of the amplifier, and the output terminal of the amplifier; and a controller that is coupled to provide a first control signal to the first switch network and that is coupled to provide a second control signal to the second switch network, wherein the first control signal activates each switch in the first switch network during an amplify mode and a transition mode, and wherein the second control signal activates each switch in the second switch network during a mute mode and the transition mode, and wherein feedback through the amplifier during the mute mode actively mutes the amplifier.
[0004] In accordance with an example embodiment of the invention, the amplifier further comprises a class AB audio amplifier.
[0005] In accordance with an example embodiment of the invention, first switch network further comprises: a first switch that is coupled between the first pin and the first input terminal of the amplifier, wherein the first switch is controlled by the first control signal; and a second
switch that is coupled between the second pin and the second input terminal of the amplifier, wherein the second switch is controlled by the first control signal.
[0006] In accordance with an example embodiment of the invention, the first and second switches further comprise MOSFET switches.
[0007] In accordance with an example embodiment of the invention, rise and fall times for the first control signal are about 30μ8.
[0008] In accordance with an example embodiment of the invention, the second switch network further comprises: a first switch that is coupled between the output terminal of the amplifier and the first input terminal of the amplifier, wherein the first switch is controlled by the second control signal; and a second switch that is coupled between the second input terminal of the amplifier and ground, wherein the second switch is controlled by the second control signal.
[0009] In accordance with an example embodiment of the invention, the second switch network further comprises a resistor that is coupled between the first switch and the first input terminal of the amplifier.
[0010] In accordance with an example embodiment of the invention, the resistor further comprises a first resistor, and wherein the second switch network further comprises: a third switch that is coupled to the first input terminal of the amplifier, wherein the third switch is controlled by the second control signal; and a second resistor that is coupled between the third switch and ground.
[0011] In accordance with an example embodiment of the invention, the first and second resistor each have a resistance of about 10kQ.
[0012] In accordance with an example embodiment of the invention, the first, second, and third switches further comprise MOSFET switches.
[0013] In accordance with an example embodiment of the invention, rise and fall times for the second control signal are about 30μ8.
[0014] In accordance with an example embodiment of the invention, the length of the transition mode is at least about 100μ8.
[0015] In accordance with an example embodiment of the invention, an apparatus is provided. The apparatus comprises a first pin; a second pin; a third pin; an amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the output terminal of the amplifier is coupled to the third pin; a first switch network having: a first switch that is
coupled between the first pin and the first input terminal of the amplifier; and a second switch that is coupled between the second pin and the second input terminal of the amplifier; a second switch network having: a third switch that is coupled to the output terminal of the amplifier; a fourth switch that is coupled between the second input terminal of the amplifier and ground; a first resistor that is coupled between the first switch and the first input terminal of the amplifier; a fifth switch that is coupled to the first input terminal of the amplifier; and a second resistor that is coupled between the third switch and ground; and a controller that is coupled to provide a first control signal to the first and second switches and that is coupled to provide a second control signal to the third, fourth, and fifth switches, wherein the first control signal activates each of the first and second switches switch in the first switch network during an amplify mode and a transition mode, and wherein the second control signal activates each of the third, fourth, and fifth switches in the second switch network during a mute mode and the transition mode, and wherein feedback through the amplifier during the mute mode actively mutes the amplifier.
[0016] In accordance with an example embodiment of the invention, a method is provided. The method comprises activating a plurality of switches in a first switch network with a first control signal during an active mode so as to amplify a signal from a signal source with an amplifier; activating a plurality of switches in a second switch network with a second control signal during a transition mode to retain closed loop operation of the amplifier; and deactivating the plurality of switches in the first switch network with the first control signal during a mute mode so that feedback through the amplifier actively mutes the amplifier, wherein the mute mode follows the transition mode.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Example embodiments are described with reference to the accompanying drawings, wherein:
[0018] FIG. 1 is a block diagram of an example of a circuit in accordance with an example embodiment of the invention; and
[0019] FIG. 2 is a timing diagram for the control signals of the circuit of FIG. 1.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0020] In FIG. 1, the reference numeral 100 generally designates a circuit in accordance with an example embodiment of the invention. Circuit 100 generally comprises an integrated circuit (IC) 102 and resistors R3, R4, R5, and R6. Resistors R3, R4, R5, and R6 are coupled to
pins 108, 110, and 112 of IC 102 in order to amplify input signal AIN so as generate output signal OUT. IC 102 generally comprises switch networks, amplifier 104 (which is typically a class AB audio amplifier), and controller 106.
[0021] Operationally, IC 102 generally operates the amplifier 104 in three modes: active mode, transition mode, and mute mode. Each of these modes can be seen in FIG. 2. During the active mode (which is shown between times tO and tl of FIG. 2), control signal CNTL2 is asserted by controller 106 so that switches SI and S2 (of one of the switch networks) are activated. When switches SI and S2 are activated, the amplifier 104 normally amplifies the input signal AIN. During the transition mode (which is shown between times tl and t4 of FIG. 2), control signals CNTL1 and CNTL2 are both asserted by controller 106 to activate switches SI through S5 (of all of the switch networks). The transition mode (which is generally at least about 100μ8 in length) is provided to maintain closed loop operation of amplifier 104; without the transition mode, the amplifier 104 would generate audible artifacts (for audio applications) associated with open loop operation. Finally, in mute mode, control signal CNTL1 is asserted to activate switches S3, S4, and S5 (of one of the switch networks). Switches S3, S4, and S5 enable the positive input terminal of amplifier 104 to be grounded while feedback from the output terminal of amplifier 104 can be provided through resistors Rl and R2 (which are each generally about 10kQ) to the negative input terminal of amplifier 104. This feedback actively mutes the amplifier 104 by driving the output signal OUT to null or ground with an attenuation of about 70-80dB or higher.
[0022] Looking specifically to switches SI through S5, each switch SI through S5 is generally a MOSFET switch. This means that charge injection from these switches SI through S5 should be considered for the relative sizes of switches SI through S5 and rise/fall times of control signals CNTL1 and CNTL2. Typically, the rise and fall times for control signals CNTL1 and CNTL2 (as shown between times tl to t2 and times t3 to t4 in FIG. 2) are about 30μ8. Additionally, dummy switches can be employed for switch injection cancellation.
[0023] Embodiments having different combinations of one or more of the features or steps described in the context of example embodiments having all or just some of such features or steps are intended to be covered hereby. Those skilled in the art will appreciate that many other embodiments and variations are also possible within the scope of the claimed invention.
Claims
1. An apparatus comprising;
a first pin;
a second pin;
a third pin;
an amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the output terminal of the amplifier is coupled to the third pin;
a first switch network that is coupled between the first pin and the first input terminal of the amplifier and that is coupled between the second pin and the second input terminal of the amplifier;
a second switch network that is coupled to the first input terminal of the amplifier, the second input terminal of the amplifier, and the output terminal of the amplifier; and
a controller that is coupled to provide a first control signal to the first switch network and that is coupled to provide a second control signal to the second switch network, wherein the first control signal activates each switch in the first switch network during an amplify mode and a transition mode, and wherein the second control signal activates each switch in the second switch network during a mute mode and the transition mode, and wherein feedback through the amplifier during the mute mode actively mutes the amplifier.
2. The apparatus of Claim 1, wherein the amplifier further comprises a class AB audio amplifier.
3. The apparatus of Claim 1, wherein first switch network further comprises:
a first switch that is coupled between the first pin and the first input terminal of the amplifier, wherein the first switch is controlled by the first control signal; and
a second switch that is coupled between the second pin and the second input terminal of the amplifier, wherein the second switch is controlled by the first control signal.
4. The apparatus of Claim 3, wherein the first and second switches further comprise MOSFET switches.
5. The apparatus of Claim 4, wherein rise and fall times for the first control signal are about 30μ8.
6. The apparatus of Claim 1, wherein the second switch network further comprises: a first switch that is coupled between the output terminal of the amplifier and the first input terminal of the amplifier, wherein the first switch is controlled by the second control signal; and
a second switch that is coupled between the second input terminal of the amplifier and ground, wherein the second switch is controlled by the second control signal.
7. The apparatus of Claim 6, wherein the second switch network further comprises a resistor that is coupled between the first switch and the first input terminal of the amplifier.
8. The apparatus of Claim 7, wherein the resistor further comprises a first resistor, and wherein the second switch network further comprises:
a third switch that is coupled to the first input terminal of the amplifier, wherein the third switch is controlled by the second control signal; and
a second resistor that is coupled between the third switch and ground.
9. The apparatus of Claim 8, wherein the first and second resistor each have a resistance of about 10kQ.
10. The apparatus of Claim 8, wherein the first, second, and third switches further comprise MOSFET switches.
11. The apparatus of Claim 4, wherein rise and fall times for the second control signal are about 30μ8.
12. The apparatus of Claim 1, wherein the length of the transition mode is at least about 100μ8.
13. The apparatus of Claim 1, wherein:
the first switch network has a first switch that is coupled between the first pin and the first input terminal of the amplifier, and a second switch that is coupled between the second pin and the second input terminal of the amplifier;
the second switch network has a third switch that is coupled to the output terminal of the amplifier, a fourth switch that is coupled between the second input terminal of the amplifier and ground, a first resistor that is coupled between the first switch and the first input terminal of the amplifier, a fifth switch that is coupled to the first input terminal of the amplifier, and a second resistor that is coupled between the third switch and ground; and
the controller is coupled to provide the first control signal to the first and second switches and is coupled to provide the second control signal to the third, fourth, and fifth switches;
wherein the first control signal activates each of the first and second switches switch in the first switch network during the amplify mode and the transition mode; and
wherein the second control signal activates each of the third, fourth, and fifth switches in the second switch network during the mute mode and the transition mode.
14. The apparatus of Claim 13, wherein the amplifier further comprises a class AB audio amplifier.
15. A method comprising:
activating a plurality of switches in a first switch network with a first control signal during an active mode so as to amplify a signal from a signal source with an amplifier;
activating a plurality of switches in a second switch network with a second control signal during a transition mode to retain closed loop operation of the amplifier; and
deactivating the plurality of switches in the first switch network with the first control signal during a mute mode so that feedback through the amplifier actively mutes the amplifier, wherein the mute mode follows the transition mode.
16. The method of Claim 15, wherein the rise and fall times of the first and second control signal are about 30μ8, and wherein the length of the transition mode is about 100μ8.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013502558A JP5822912B2 (en) | 2010-03-30 | 2010-12-21 | Active mute system for amplifier |
| CN201080065294.6A CN102792587B (en) | 2010-03-30 | 2010-12-21 | Active noise elimination scheme for amplifier |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/750,431 US8138828B2 (en) | 2010-03-30 | 2010-03-30 | Active mute scheme for an amplifier |
| US12/750,431 | 2010-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2011126525A1 true WO2011126525A1 (en) | 2011-10-13 |
Family
ID=44708926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2010/061431 Ceased WO2011126525A1 (en) | 2010-03-30 | 2010-12-21 | Active mute scheme for an amplifier |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8138828B2 (en) |
| JP (1) | JP5822912B2 (en) |
| CN (1) | CN102792587B (en) |
| WO (1) | WO2011126525A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9172381B2 (en) * | 2013-03-15 | 2015-10-27 | Hittite Microwave Corporation | Fast turn on system for a synthesized source signal |
| US11736075B2 (en) * | 2021-04-01 | 2023-08-22 | Macom Technology Solutions Holdings, Inc. | High accuracy output voltage domain operation switching in an operational amplifier |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0095774A2 (en) * | 1982-05-31 | 1983-12-07 | Nec Corporation | A switching circuit operable as an amplifier and a muting circuit |
| EP0482290A2 (en) * | 1990-10-25 | 1992-04-29 | Pioneer Electronic Corporation | Circuit for muting noises for an audio amplifier |
| US20070009110A1 (en) * | 2005-07-08 | 2007-01-11 | Matsushita Electric Industrial Co., Ltd. | Muting circuit and semiconductor integrated circuit |
| US20080137882A1 (en) * | 2006-12-11 | 2008-06-12 | Mediatek Inc. | Apparatus and muting circuit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5166983A (en) | 1991-07-22 | 1992-11-24 | Motorola, Inc. | Mute circuit for audio amplifiers |
| JP3112522B2 (en) * | 1991-09-11 | 2000-11-27 | ローム株式会社 | Audio signal amplifier circuit |
| JP2005051609A (en) * | 2003-07-30 | 2005-02-24 | Mitsumi Electric Co Ltd | Signal output circuit |
| US7102400B1 (en) | 2004-08-30 | 2006-09-05 | Sitel Semiconductor B.V. | Phase locked loop charge pump and method of operation |
| TWI259735B (en) | 2004-10-13 | 2006-08-01 | Princeton Technology Corp | Muting circuit of audio amplifier |
| CN201204568Y (en) * | 2008-06-10 | 2009-03-04 | 上海韦矽微电子有限公司 | Audio power amplification circuit |
-
2010
- 2010-03-30 US US12/750,431 patent/US8138828B2/en active Active
- 2010-12-21 CN CN201080065294.6A patent/CN102792587B/en active Active
- 2010-12-21 JP JP2013502558A patent/JP5822912B2/en active Active
- 2010-12-21 WO PCT/US2010/061431 patent/WO2011126525A1/en not_active Ceased
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0095774A2 (en) * | 1982-05-31 | 1983-12-07 | Nec Corporation | A switching circuit operable as an amplifier and a muting circuit |
| EP0482290A2 (en) * | 1990-10-25 | 1992-04-29 | Pioneer Electronic Corporation | Circuit for muting noises for an audio amplifier |
| US20070009110A1 (en) * | 2005-07-08 | 2007-01-11 | Matsushita Electric Industrial Co., Ltd. | Muting circuit and semiconductor integrated circuit |
| US20080137882A1 (en) * | 2006-12-11 | 2008-06-12 | Mediatek Inc. | Apparatus and muting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102792587B (en) | 2016-08-31 |
| US8138828B2 (en) | 2012-03-20 |
| JP2013524623A (en) | 2013-06-17 |
| CN102792587A (en) | 2012-11-21 |
| US20110241771A1 (en) | 2011-10-06 |
| JP5822912B2 (en) | 2015-11-25 |
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