WO2011123635A2 - Synchronous transfer of streaming data in a distributed antenna system - Google Patents

Synchronous transfer of streaming data in a distributed antenna system Download PDF

Info

Publication number
WO2011123635A2
WO2011123635A2 PCT/US2011/030712 US2011030712W WO2011123635A2 WO 2011123635 A2 WO2011123635 A2 WO 2011123635A2 US 2011030712 W US2011030712 W US 2011030712W WO 2011123635 A2 WO2011123635 A2 WO 2011123635A2
Authority
WO
WIPO (PCT)
Prior art keywords
data
clock signal
high speed
unit
signal
Prior art date
Application number
PCT/US2011/030712
Other languages
French (fr)
Other versions
WO2011123635A3 (en
Inventor
Donald Mcallister
Chris Ranson
Fred William Phillips
Original Assignee
Andrew Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=44709685&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2011123635(A2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Andrew Llc filed Critical Andrew Llc
Priority to EP18200679.1A priority Critical patent/EP3448116B1/en
Priority to KR1020127026847A priority patent/KR101847631B1/en
Priority to EP11713439.5A priority patent/EP2554015B2/en
Priority to CN201180016515.5A priority patent/CN102823321B/en
Priority to BR112012024716-6A priority patent/BR112012024716B1/en
Publication of WO2011123635A2 publication Critical patent/WO2011123635A2/en
Publication of WO2011123635A3 publication Critical patent/WO2011123635A3/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0079Receiver details
    • H04L7/0087Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • H04J3/0638Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658Clock or time synchronisation among packet nodes
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/02Arrangements for detecting or preventing errors in the information received by diversity reception
    • H04L1/06Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
    • H04L1/0618Space-time coding
    • H04L1/0625Transmitter arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/02Arrangements for detecting or preventing errors in the information received by diversity reception
    • H04L1/06Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
    • H04L1/0618Space-time coding
    • H04L1/0631Receiver arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W88/00Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/08Access point devices
    • H04W88/085Access point devices with remote components

Definitions

  • each cell includes a base station that employs RF transceiver equipment, antennas, and wireline communication equipment.
  • the subscriber units in the area of a cell site thus use RF transceivers to communicate with the RF transceivers of the base station.
  • the base station relays voice and data traffic to/from the mobile units and to/from a mobile telephone switching office or access service gateway.
  • This office or gateway is, in turn, generally connected to a central network, such as a public switched telephone network.
  • High data rate serial protocols such as 10GBase-T Ethernet, which are required to handle the high data rates necessary to transport wideband digitized RF, are particularly susceptible to alien crosstalk because of the more complex modulation schemes and wide bandwidths employed by such formats. Increased crosstalk and noise will lead to more jitter on the data and, hence, more jitter on the recovered clock as well. This jitter must be removed to avoid contaminating the analog to digital and digital to analog conversion processes in order to exploit the cost and installation advantages of unshielded twisted pair.
  • the remote unit further includes a clock recovery circuit that includes a phase-locked loop, the phase-locked loop including a loop filter having a bandwidth that does not substantially block the jitter or long-term drift in a modulated signal, the clock recovery circuit configured to receive the modulated signal from the high speed data interface circuitry that includes a serial encoded binary data stream and further configured to generate a recovered clock signal therefrom, as well as a filtering circuit configured to filter the recovered clock signal to remove jitter and generate a stable recovered clock signal.
  • the remote unit still further includes a scaling circuit configured to scale the frequency of the stable recovered clock signal to generate at least one output signal at a respective predetermined target frequency.
  • Still further embodiments of the invention include a distributed antenna system that includes a master unit and at least one remote unit.
  • the master unit clocks an encoded data stream onto high speed data interface circuitry via a modulated signal based upon an output of a reference oscillator.
  • the remote unit includes high speed data interface circuitry for receiving the modulated signal from the master unit and a clock recovery circuit.
  • the clock recovery circuit includes a phase-locked loop, the phase-locked loop in turn including a loop filter configured with a bandwidth that does not substantially block the jitter or long-term drift in the modulated signal.
  • the clock recovery circuit is configured to generate a recovered clock signal from the modulated signal that includes the encoded data stream.
  • Additional embodiments of the invention include a method of generating a jitter reduced clock signal from an encoded data stream.
  • the method comprises generating a recovered clock signal based on the encoded data stream, the recovered clock signal being phase locked to an oscillator used to clock the encoded data stream onto a modulated signal.
  • the method further comprises clocking data from the encoded data stream into a processing unit based on the recovered clock signal and detecting a periodic signal component, other than the bit rate, of the encoded data stream with the processing unit.
  • FIG. 1 Further alternative embodiments include a master unit for a distributed antenna system.
  • the master unit includes high speed data interface circuitry for exchange of data with at least one remote unit and first RF transceiver circuitry for communicating with at least one base transceiver system.
  • the master unit further comprises a processing unit that multiplexes data from the at least one secondary interface, the first RF transceiver, and the second RF transceiver and routes the multiplexed data to a PHY for transmission via the high speed data interface circuitry, and that de-multiplexes data from the high speed data interface circuitry and routes the de-multiplexed data to at least one of the at least one secondary interface, the first RF transceiver, or the second RF transceiver.
  • the master unit comprises a reference oscillator that is used to multiplex and/or demultiplex the data to and/or from the high speed data interface.
  • FIG. 3 is a block diagram of a master unit of the distributed antenna system of FIG. 2;
  • FIG. 4 is a block diagram of a remote unit of the distributed antenna system of FIG. 2;
  • FIG. 7 is a block diagram of an alternative embodiment of modules used to recover a clock signal in the remote unit or extension unit of the distributed antenna system of FIG. 2.
  • Embodiments of the present invention provide a remote unit that can be used to recover a clock signal embedded in a modulated signal.
  • embodiments of the invention are capable of extracting the clock signal from the modulated signal, reducing the jitter on that extracted signal, then scaling the frequency of that signal.
  • this allows a master unit to communicate with remote units over an unshielded twisted pair cable such that the cost for deployment is lessened.
  • Embodiments of the invention further account for distributed antenna systems that use a mixed combination of fiber optic and twisted pair cables and also can be used to recover a clock signal embedded as a component of the modulated signal.
  • cells 22 may be divided into sectors 38 or are further subdivided into smaller cells with the base station 24 being replaced with lower cost, reduced capability micro or pico cells 36.
  • DAS distributed antenna systems
  • These approaches permit the reuse of a limited number of expensive RF channels without incurring the costs of one or more complete base stations 24.
  • these techniques may also be used to extend coverage to areas within the cell site where RF propagation may be limited by obstruction, such as in buildings and tunnels, or to areas where the amount of traffic (revenue) does not justify the investment required for a complete base station 24.
  • Distributed antenna systems allow the RF coverage to be adapted to the specific environment in a homogeneous way to assist in reducing the amount of introduced interference.
  • the amount of extra traffic is kept low as only existing cells are distributed and no hand-off between cells is required.
  • the system 20 may also include a distributed antenna system 40 that, in turn, includes a master unit 42 collocated with at least one base station 24.
  • the master unit 42 may be connected to the base station 24, which is then connected to the Mobile Telephone Switching Office 32 via a wireline 28 connection.
  • a group of distributed antenna units 44 are interconnected via high speed digital transport links 46.
  • the transport of RF signals in a digital format may assist in preventing any appreciable degradation due to the transport link.
  • Spectral filtering may also be used to allow or prevent the distribution of specific radio signals.
  • the individual group delay of spectral components may be individually adjusted without hardware modifications. Thus, quality degrading delay differences between overlapping simulcast cells may be avoided.
  • the digital transport mechanism employed in embodiments of the invention allows for flexible use of the available bandwidth over the high speed data interfaces.
  • the dominant use of these links is generally for RF spectrum.
  • a time division multiplexed format of the links permits transport of multiple signals, which may even be at the same RF frequency.
  • data from data communication links such as Ethernet may also be inserted in the digital transport links for system monitoring, configuration, control, as well as other user applications, such as public safety communications and WiFi hot spots.
  • the master unit or remote units dynamically scale the amount of RF bandwidth transmitted over the high speed serial data interfaces or eliminate low priority data.
  • the distributed antenna system 50 includes one or more master units 42 and a system controller 52 configured to control each master unit 42 collocated with a base station 24a-d.
  • each master unit 42 is capable of handling up to six RF bands with up to four service providers per band for Frequency Division Duplexed (FDD) air interfaces and one operator per band for Time Division Duplexed (TDD) air interfaces, although one of ordinary skill in the art will appreciate that other master units 42 may be capable of handling more or fewer RF bands, service providers or operators.
  • the master unit 42 is connected to a base station 24a-d via coupling interfaces 54.
  • the master unit 42 is also connected to a series of distributed antenna units 44, hereinafter referred to as remote units, or remote antenna units via high speed data interfaces. In the illustrated embodiment of Figure 2, four such interfaces are shown, although one of ordinary skill in the art will appreciate that other master units may have more than four interfaces.
  • the master unit 42 is connected directly to each remote unit 44 via a respective high speed communication medium 60 employing low cost communication cable having at least three conductors, such as unshielded twisted pair.
  • Each remote unit 44 may be configured to handle up to six RF bands, for example.
  • the master unit 42 For each RF band 56a, 56b, the master unit 42 combines the downlink signal from the base stations 24a-d on a per band basis and digitizes the combined signal into a binary encoded data stream.
  • the binary encoded data streams from each of the RF bands 56a, 56b may then be time division multiplexed and converted to a single serial stream.
  • the serial data is transmitted to the remote units 44a-c via respective communication medium 60, such as twisted pair cables 60a-c.
  • the distributed antenna system 50 may include more or fewer components, including more or fewer master units 42, remote units 44, and/or extension units 64 than illustrated in Figure 2.
  • each master unit 42, remote unit 44, and/or extension unit 64 may include more or fewer components.
  • the master unit 42 may include more or fewer input interfaces, each of which may be wireless or wireline RF interfaces.
  • the master unit 42 may receive various cellular base transceiver system signals (GSM, LTE, CDMA, UMTS, etc.), such as via the signals from the base stations 24a - 24d, and may implement connections 57 for other RF services (e.g., from public safety entities), WiFi data, Ethernet data, or data from a maintenance terminal.
  • the master unit 42 may be connected to a plurality of remote units 44 connected serially through one or two dedicated communication interfaces or one dedicated interface.
  • the distributed antenna system 50 may include remote units 44 that utilize more than six RF bands and/or that include additional interfaces.
  • the Digitally Modulated Optical Cables (DMOC) 66 including the optical transceiver may also be replaced by a different transceiver for high data rate media such as coax cable, twisted pair copper wires, free space RF or optics, or shared networks such as Ethernet, SONET, SDH, ATM, PDH, among others.
  • the master unit 42 may include one or more optical links that are connected to an expansion and/or extension unit 64 via the DMOC 66.
  • the extension unit 64 provides additional communication mediums for distribution of voice and data traffic, command and control, and user data for to up to sixteen remote units 44, thereby increasing the number of remote units 44 a single master unit 42 can handle.
  • the extension unit 64 may communicate with master units 42 using the same wavelength in both directions.
  • the remote units 44d-e also receive RF voice and/or data signals, designated as the uplink signal, from the customer or subscriber units/devices 30 via the local antennas 62.
  • each RF uplink band is digitized separately.
  • the uplink signals for each band are combined into a single serial digital protocol and transmitted via the respective communication medium 60a-e to the respective master unit 42 or to the master unit 42 through the extension unit 64.
  • the master unit 42 separates the signals from each band, converts them to analog signals, converts or translates each to the appropriate radio frequency, and sends them to the appropriate base station 24.
  • the master unit 42 receives RF signals from a variety of base transceiver stations (BTS) and other services, then downconverts and digitizes those signals using appropriate RF transceiver circuitry 84 that may include frequency down converter circuits 43 and AID converters 45.
  • the master unit 42 includes a stable reference oscillator 70 that feeds
  • phase/frequency locked loops/frequency divider circuitry 72 to generate one or more LO references, sampling clocks, and PHY references.
  • a processing unit 74 such as an FPGA, or other suitable processor produces a serial stream and routes that data to a high-rate Ethernet physical layer device (PHY) 76, using the PHY reference, which is synchronized to the reference oscillator 70.
  • PHY physical layer device
  • Each PHY 76a-d encodes the data into an encoded data stream to eliminate long strings of ones and zeros, then clocks the data on the respective communication mediums (e.g., unshielded twisted pair cable) as a modulated signal using the PHY reference that is based upon reference oscillator 70.
  • the PHY reference which is phase locked to the reference oscillator 70, any long-term drift in the frequency of the oscillator 70 is transferred to the bit rate of the encoded data stream transmitted over the interfaces as a modulated signal.
  • data received from a remote unit 44 or extension unit 64 is decoded, error corrected by the respective PHY 76a-d, then routed to the processing unit 74.
  • the processing unit 74 de-multiplexes the data and routes the digital signals through appropriate RF transceiver circuitry 82, which may include a D/A converter 47 and a frequency upconverter 49.
  • the D/A converter 47 is for conversion of the digitized baseband data to analog signals.
  • the analog signals are then up-converted to appropriate frequencies using appropriate frequency upconverters 49.
  • Data for WiFi and other non-RF services are routed to slower high speed data interface circuitry 86, which in turn includes Ethernet PHYs 78, UARTs 80, or other similar devices for distribution.
  • the down- conversion or up-conversion of signals is done with the LO reference tied to the oscillator 70.
  • the conversion of a down-converted signal to digital data, and the conversion of digital data to an analog signal is performed with the sampling clock tied to the oscillator 70. In this manner, all signals in to the master unit 42 and all signals from the master unit 42 are tied to the oscillator 70 consistent with embodiments of the invention.
  • PHYs 76a-d are illustrated as being used to send data to the remote units 44 and/or extension unit 64, the data is sent in a synchronous manner without typical inter-packet gaps to maximize throughput.
  • utilizing PHYs 76 allows high data rates of at least 10 Gbps over inexpensive unshielded twisted pair cable when the length of the run from the master unit 42 to the remote unit is sufficiently short. This may significantly reduce the cost of a distributed antenna system 40 for some application, and in particular those in buildings.
  • FIG. 4 contains a detailed block diagram of a remote unit 44.
  • Each remote unit 44 includes a high speed data interface, such as a PHY 90, that receives an encoded serial digital signal with a bit rate modulated by the drift in the reference oscillator 70, hereinafter referred to as a modulated signal, from the master unit 42 or an extension unit 64 and extracts the encoded data stream therefrom.
  • the PHY 90 in turn, produces a recovered clock signal as at 92 that is phase locked to the encoded data stream, and thus to the oscillator 70 of the master unit 42.
  • the recovered clock signal 92 is filtered by a jitter reduction circuit 94, which may include a narrowband phase-locked loop or a crystal filter.
  • the jitter reduction circuit 94 produces a stable recovered clock signal 95 that is further phase locked and/or frequency divided by a phase/divider circuit 96.
  • the phase/divider circuit 96 produces an LO reference, a sampling clock, and a processing unit clock signal (illustrated as "CPU CLOCK").
  • the data output of the PHY 90 e.g., the encoded data stream
  • a processing unit 98 which may be an FPGA or other suitable processor, that demultiplexes the data stream.
  • the processing unit 98 routes that demultiplexed data to appropriate RF transceiver circuitry 1 06, that may include a digital to analog (D/A) converters 99 and upconverter circuits 101 .
  • D/A digital to analog
  • the D/A converters 99 are for conversion into analog signals, while the upconverter circuits 1 01 frequency upconvert the analog signals into appropriate RF frequencies and transmit the upconverted signal to subscriber units 30 via one or more suitable antennas, such as local antenna 62.
  • the present invention is not limited to specific RF transceiver circuitry used to communicate with particular subscriber units 30.
  • the remote unit 44 may include additional RF transceiver circuitry for communicating non-cellular RF voice and/or data with a subscriber unit 30, Non- baseband data is routed to high speed data interface circuitry 109, which in turn includes lower speed Ethernet PHYs 100 or UARTs 102.
  • RF signals received from subscriber units 30 via antenna 62 are received by RF transceiver circuitry 108, which includes a downconverter circuits 103 and A/D converters 105.
  • the downconverter circuits 103 downconvert the received RF signal, which are each digitized by A/D converters 105 and routed to the processing unit 98.
  • the processing unit 98 time-division multiplexes the data into a serial stream along with lower rate Ethernet data and/or other serial data from the Ethernet PHYs 100 and/or UART 102. This data is routed to the PHY 44 where it is coded and sent to the master unit 42 or extension unit 64.
  • the PHY 90 in the remote unit 44 phase and/or frequency locks at least one voltage-controlled oscillator (VCO) (not shown in FIG. 4) of a phase-locked loop (PLL) to the incoming data from the master unit 42 or extension unit 64.
  • VCO voltage-controlled oscillator
  • PLL phase-locked loop
  • the output of a voltage-controlled oscillator (VCO) is used to recover the data and decode it.
  • the bandwidth of the frequency locked loop is configured to be wide enough to track the long-term drift in the rate of the data due to variation in the frequency of the oscillator 70 of the master unit 42 as well as any wide band jitter introduced by or in the high speed serial link communication couplings between the remote unit 44 and the master unit 42. This, in effect, transfers any drift in the frequency of the oscillator 70 of the master unit 42 to the remote unit 44.
  • each remote unit 44 reduces the jitter in a recovered clock signal 92 with a jitter reduction circuit 94 that is configured to lock a second voltage- controlled oscillator (not shown in FIG. 4) to the oscillator 70 of the master unit 42.
  • the jitter reduction circuit 94 may have much lower phase noise than the oscillator of the PHY 90.
  • the jitter reduction circuit 94 may use a narrowband PLL for locking phase and frequency as noted. The bandwidth of this narrowband PLL is configured to track the long-term drift of the oscillator 70 of the master unit 42 and reject short-term jitter contributed by the PHY 90 oscillator and impairments in the communication couplings between the remote unit 44 and the master unit 42 (e.g.
  • the narrowband PLL may be replaced with a narrowband crystal filter in applications where interference in the serial communication couplings between the remote unit 44 and the master unit 42 are less severe.
  • the output 95 of the jitter reduction circuit 94 may be used to derive the LO reference, sampling clocks, and CPU CLK signals, each of which are frequency and/or phase locked by the phase/divider circuit 96. This ensures that all references and/or clock signals in the remote unit 44 and the master unit 42 that are used for frequency translation are phase and/or frequency locked to the oscillator 70 in the master unit 42.
  • the distributed antenna system 40 does not shift the signals being broadcast, distributed, and/or repeated.
  • FIG. 5 A detailed block diagram of an extension unit 64 is illustrated in FIG. 5.
  • the extension unit 64 routes data from a master unit 42 to each remote unit 44 connected thereto. It also combines the data from the remote units 44 connected thereto into a single serial stream and routes that data via a PHY 1 10 to the master unit 42.
  • the extension unit 64 also transfers the drift of the oscillator 70 in the master unit 42 to the remote units 44 to ensure that the references and/or clock signals for the remote units 44 are phase and/or frequency locked to that oscillator 70.
  • the extension unit 64 includes a PHY 1 10 that receives the modulated signal from the master unit 42 and extracts the encoded data stream therefrom.
  • the PHY 1 in turn, produces a recovered clock signal as at 1 12 that is phase locked to the encoded data stream, and thus to the oscillator 70 of the master unit 42.
  • the PHY 1 10 passes the encoded data stream to a processing unit 1 14, which may be an FPGA.
  • the recovered clock signal 1 12 is also filtered by a jitter reduction circuit 1 16, which may include a narrowband PLL or a crystal filter, and outputs a recovered clock signal that is utilized as a PHY reference signal as at 1 1 8.
  • the processing unit 1 14 sends data for the remote units 44 to the remote units 44 via a separate set of PHYs 120. Each PHY 120 sends the data with reference to the PHY reference.
  • the extension unit 64 may be coupled to the master unit 42 through unshielded twisted pair cable for applications where the number of remote units 44 necessary for the distributed antenna system 40 exceeds the capability of the master unit 42, or fiber where the distance between the extension unit 64 and the master unit 42 exceeds the length limitations of the PHY 1 10. Similar to the PHY 90 of the remote units 44, the PHY 1 10 phase and/or frequency locks the recovered clock signal 1 12 to the incoming data. The recovered clock signal 1 12 is used to recover and decode the data.
  • the bandwidth of the jitter reduction circuit 1 16 is again configured to be wide enough to track the long-term drift in the rate of data due to a variation in the oscillator 70 of the master unit 42 as well as any wide band jitter introduced by or in the communication couplings between the extension unit 64 and the master unit 42. This, in effect, transfers any drift in the oscillator 70 of the master unit 42 to the extension unit 64.
  • the extension unit 64 reduces the jitter in the recovered clock signal 1 12 using a narrowband PLL or crystal filter similar to that described above.
  • One of the clock outputs of the jitter reduction circuit 1 16 may be the PHY reference 1 18 for the PHYs 120 that send and receive data from the remote units 44.
  • this PHY reference 1 18 is tracking the long-term drift of the oscillator 70, the drift is imparted to the rate of the data sent to the remote units 44.
  • this may preclude the accumulation of jitter that may occur if the recovered clock signal 1 12 were used as the PHY reference 1 18 without first performing jitter reduction.
  • FIG. 6 illustrates a detailed block diagram of at least a portion of a clock recovery circuit 200 that may be included in the PHY 90 or 1 10, at least a portion of a noise filtering circuit 202 that may be included in the jitter reduction circuit 94 or 1 1 6, and at least a portion of a clock scaling circuit 204 that may be included in the phase/divider circuit 96, as well as the interconnections
  • FIG. 6 further illustrates that the clock recovery circuit 200, the noise filtering circuit 202, and the clock scaling circuit 204 may be interconnected to recover a clock signal imposed on a data stream extracted from a modulated digital signal from a master unit 42.
  • the invention is not limited to how the circuits 200, 202, 204 are arranged in one or more of the elements 90, 1 10, 94, 1 16, or 96 as illustrated in FIG. 4 and FIG. 5.
  • the clock recovery circuit 200 receives a stream of binary encoded data extracted from a modulated signal and generates a recovered clock signal as at 206 (e.g., that may correspond to the recovered clock signal 92 or 1 12) based thereon.
  • the recovered clock signal 206 is then processed by the noise filtering circuit 104 to reduce jitter and to produce a stable recovered clock signal as at 208 (e.g. , that may correspond to the PHY reference for the extension unit 64 illustrated in FIG. 5).
  • the stable recovered clock signal 208 advantageously has a phase and/or frequency corresponding to the phase and/or frequency of the oscillator 70 of the master unit that was used to clock the data received by the clock recover circuit 200.
  • the clock scaling circuit 204 may be used to generate one or more scaled clock signals (e.g., such as the LO reference, the sampling clock signal, the PHY reference, and/or the CPU CLK) as at 210 for use in operating a remote unit 44.
  • the clock recovery circuit 200, noise filtering circuit 202, and clock scaling circuit 204 may be implemented with a phase locked loop that each includes a phase-frequency detector charge pump 212, a loop filter 214, and a voltage controller oscillator (VCO) 216.
  • the VCO 216 may be implemented as an LC tank circuit that includes at least one voltage controlled capacitor.
  • the phase-frequency detector charge pump 212a may compare a rising edge of a pulse within the received binary encoded data stream from the master unit 42 with a rising edge of a pulse received as a feedback signal from the VCO 216a (illustrated as FVC01 FB). The phase-frequency detector charge pump 212a then produces a frequency error signal (illustrated as VERROR) that is representative of both the sign and scale to the phase and/or frequency difference detected by the phase-frequency detector charge pump 212a between the encoded binary data input signal from the master unit 42 and the feedback signal FVC01 FB.
  • VERROR frequency error signal
  • the loop filter 214a then receives and integrates the frequency error signal VERROR to generate a smoothed VCO control signal (illustrated as VCONTROL) that is passed to the VCO 216a.
  • VCO 216a of the clock recovery circuit 200 in turn, generates the recovered clock signal 206.
  • the recovered clock signal 206 has a frequency that is proportional to the VCO control signal VCONTROL such that the recovered clock signal 206 is locked in phase and/or frequency to the oscillator 70 used by the master unit 42 to clock the binary encoded data stream into the modulated signal therefrom.
  • the recovered clock signal 206 may exhibit jitter and/or other noise, as noted above.
  • the noise filtering circuit 202 is configured to process the recovered clock signal 206 through a second PLL to reduce jitter and provide the functionality of a jitter reduction circuit.
  • the PLL for the noise filtering circuit 202 is substantially similar to the PLL for the clock recovery circuit 200.
  • the output of the noise filtering circuit 202 is the stable recovered clock signal 208 that is locked in phase and/or frequency to that of the recovered clock signal 206 and that, in turn, matches the phase and/or frequency of the oscillator 70 of the master unit 42, but that does not include jitter and/or noise accumulated between the clock recovery circuit 200 and the master unit 42.
  • the bandwidth of the PLL for the clock recovery circuit 200 is configured to be sufficiently wide to track short-term jitter (e.g., high frequency jitter), on data, as well as long-term drift of the oscillator 70. This assures that no data is filtered from the signal.
  • the clock recovery circuit 200 is not configured to filter the long-term drift or the short-term jitter.
  • the bandwidth of the noise filtehng circuit 202 is configured to be narrower than the bandwidth of the clock recovery circuit 200 such that short-term jitter is filtered out without filtering out long- term drift in the reference signal from the oscillator 70.
  • short-term jitter is not propagated to the VCO 216b while long-term drift is.
  • the noise filtering circuit 202 may be replaced by a narrow band crystal filter to eliminate jitter in the recovered clock signal 206.
  • the clock recovery circuit 200 and the noise filtering circuit 202 are not configured with dividers. As such, the circuits 200 and 202 are configured to produce respective output signals 206 and 208 that are phase and/or frequency matched to the phase and/or frequency of the signal received by the clock recovery circuit 200.
  • a frequency divider may be used at the input of the noise filtering circuit 202, at the feedback signal FVC02FB from the VCO 216b to the phase-frequency detector charge pump 212b, or at the output of the noise filtering circuit 202.
  • Such dividers may be used to generate particular clock signals at particular frequencies.
  • the clock scaling circuit 204 may not be included (e.g., such as illustrated for the extension unit 64 in FIG. 6).
  • the stable recovered clock signal 208 may be further processed by the clock scaling circuit 204 to generate one or more clock signals (e.g. , such as those signals illustrated as output by the phase/divider circuit 96 in the remote unit 44 in FIG. 5).
  • the PLL for the clock scaling circuit 204 is substantially similar to the PLL for the noise filtering circuit 202 and the clock recovery circuit 200.
  • the clock scaling circuit 204 may include, or otherwise be coupled to, signal dividers such that an output signal has a different output frequency from, but locked to, the stable recovered clock signal 208.
  • a first signal frequency divider 218 receives the stable recovered clock signal 208 and generates an input signal for the phase-frequency detector charge pump 212c (illustrated as
  • a second signal frequency divider 220 may receive a scaled clock signal 210 from the VCO 21 6c to feed back to the phase-frequency detector charge pump 212c to increase the frequency of that signal above that of the input signal
  • a third signal frequency divider 222 (illustrated as “%L”) may also receive a scaled clock signal from the VCO 216c to reduce the frequency of that scaled clock signal. Consistent with one embodiment of the invention, the clock scaling circuit
  • 204 is configured to lock onto a stable recovered clock signal 208 of about 156.25
  • the third signal frequency divider 222 is used to generate an output signal 224 of about 100
  • scaled clock signal 210 may be about five times the stable recovered clock signal 208, while the scaled clock signal 210 may be about eight times the output signal 224.
  • the second signal frequency divider 220 may be matched to the increase in the frequency applied by the VCO 216c to the input signal FVC02M such that the VCO feedback signal (illustrated as VFV03FB) is frequency locked to the input signal FVC02M. Equations 1 through 3 illustrate this relationship.
  • inserting the first signal frequency divider 21 8 prior to the feedback loop allows the generation of the scaled clock signal 21 0 with a frequency that is proportional to the scaled recovered clock signal 208 as determined by the ratios of the first signal frequency divider 218 and the second signal frequency divider 220.
  • the second signal frequency divider 220 may be a fractional N divider to permit flexibility in selecting the clock frequency.
  • FIG. 7 illustrates at least a portion of a circuit 250 that may be used to recover a clock signal from a bit stream of data consistent with alternative embodiments of the invention.
  • the FPGA or other processor in a remote unit can provide a signal aligned with a periodic signal present in the serial data that could be used in place of the recovered clock as a reference for the oscillator.
  • the circuit 250 includes the clock recovery circuit 200 that generates the recovered clock signal 206 from an encoded data stream.
  • the data and the recovered clock signal 206 are applied to a D flip-flop circuit 252 with the data applied to the D input thereof and the recovered clock signal 206 applied to the clock input thereof.
  • the Q output of the D flip-flop circuit 252, in turn, is provided to a processor 254, such as an FPGA, that is configured to produce a signal as at 256 based on a detected periodic signal that is used to adjust the frequency of the oscillator at 258.
  • the signal 256 generated by the processor is based on processed data clocked in from data lines using the recovered clock signal 206.
  • This reference signal 260 may then be supplied to a clock scaling circuit 204 to generate clock signals. This approach can use any periodic component of the encoded data stream.

Abstract

Embodiments of the invention provide a method, distributed antenna system (50), and components that generate a jitter reduced clock signal from a serial encoded binary data stream transmitted over a communication medium (60, 60a-e, 66). The method comprises receiving a modulated signal that includes the encoded binary data stream and extracting the encoded binary data stream. The method further comprises generating a recovered clock signal (92, 1 12, 206) that is phase locked to the encoded binary data stream, generating an error signal (VERROR) based on a difference between a phase of the encoded binary data stream and the recovered clock signal (92, 112, 206), and integrating the error signal (VERROR) to generate a signal (VCONTROL) to control a voltage controlled oscillator (70, 216, 216a-c, 258). The method further comprises generating a stable recovered clock signal (95, 208) and producing at least one output clock (224) by scaling the stable recovered clock signal (95, 208) frequency.

Description

SYNCHRONOUS TRANSFER OF STREAMING DATA IN A
DISTRIBUTED ANTENNA SYSTEM
CROSS-REFERENCE TO RELATED APPLICATION
[0001 ] This Application claims the benefit of U.S. Patent Application Serial No. 61/319,623 to McAllister et al. entitled "SYNCHRONOUS TRANSFER OF
STREAMING DATA VIA ETHERNET PHYS AND MECHANISMS OF CLOCK RECOVERY AND SYNCHRONIZATION" and filed on March 31 , 2010, which application is incorporated by reference in its entirety herein.
FIELD OF THE INVENTION
[0002] The present invention is directed to wireless communication systems, and specifically is directed to the synchronous transfer of streaming data in a distributed antenna system.
BACKGROUND OF THE INVENTION
[0003] Conventional communication systems, such as cellular phone systems and broadband wireless metropolitan networks, are often divided into a number of cells. These cells are typically distributed in a pattern to preclude co-channel interference and thus provide coverage of subscriber units operating within the service area of the system. In some systems, each cell includes a base station that employs RF transceiver equipment, antennas, and wireline communication equipment. The subscriber units in the area of a cell site thus use RF transceivers to communicate with the RF transceivers of the base station. In turn, the base station relays voice and data traffic to/from the mobile units and to/from a mobile telephone switching office or access service gateway. This office or gateway is, in turn, generally connected to a central network, such as a public switched telephone network.
[0004] To improve system capacity, some cells are further divided into sectors or smaller cells, with the base station replaced by lower cost but reduced capability micro or pico cells. In addition, distributed antenna systems are often employed to optimize the RF distribution in larger cells to increase coverage at a lower cost than multiple pico or micro cells. These approaches permit the reuse of a limited number of RF channels without the costs of installing new base stations. Also, such techniques can be used to extend coverage to areas where RF propagation is limited by obstructions, such as buildings and tunnels, and to areas where the amount of traffic and revenue do not justify the investment for another base station. The distributed antenna systems (DAS) themselves often include a master unit connected to various base transceiver stations of various cellular providers employing different air interfaces. The master unit, in turn, is connected to a series of physically separate remote antenna units. The remote units are connected to the master unit using a high speed serial link (HSSL), and the master unit downconverts and digitizes signals from the base station and time division multiplexes the digital data that is transmitted over serial links to the remote units. The remote units convert the signals back to analog, upconvert, and transmit to subscribers. Similarly, the remote units downconvert and digitize uplink signals from the subscribers and transmit the signals back to the master unit, which converts them to the proper format to transmit to the base stations. [0005] Air interface standards for the distributed antenna system levy requirements on the frequency shift that can be imposed on the signals of the system. Some standards, such as GSM impose such strict standards that they can only be met by frequency locking all signals used for frequency translation within the distributed antenna system to a single common standard. This ensures that all frequency errors introduced by the up and down conversion processes cancel.
Consequently, local oscillator signals used for up and down conversion and the clocks used for digital to analog and analog to digital conversion processes must be frequency locked to a common reference. Use of disciplined oscillators, where the oscillators are disciplined by other communication systems, such as GPS or WWV, in all components of the distributed antenna system could be employed to effect the frequency locking. However, this would significantly increase the cost of the distributed antenna system and in many applications where a distributed antenna system would be employed, such as in buildings or tunnels, reception of such signals is problematic at best and nonexistent at worst. The master unit reference could be cabled to remote units with additional cables or additional wires within the serial link cables being used to transfer data. But adding extra cables multiplies the cost of deployment and in some cases may not be physically possible. Moreover, adding additional wires to cables is not always possible as is the case in applications using existing CAT 5/6/6A cable in buildings or other structures, where all cable pairs are required for high speed data transfer and/or are already otherwise used.
[0006] To minimize the cost of installation and to take advantage of existing cabling infrastructure, it is also desirable, whenever possible, to use low cost communication cables employing a plurality of conductors, such as unshielded twisted pair cable instead of more expensive shielded twisted pair or fiber optic cables. Use of twisted pair also permits the use of relatively inexpensive copper PHYs such as 10GBase-T Ethernet, instead of the more expensive optical transceivers such as SFP and XFP modules. Use of unshielded twisted pair cables, however, results in additional susceptibility to interfering signals. High data rate serial protocols, such as 10GBase-T Ethernet, which are required to handle the high data rates necessary to transport wideband digitized RF, are particularly susceptible to alien crosstalk because of the more complex modulation schemes and wide bandwidths employed by such formats. Increased crosstalk and noise will lead to more jitter on the data and, hence, more jitter on the recovered clock as well. This jitter must be removed to avoid contaminating the analog to digital and digital to analog conversion processes in order to exploit the cost and installation advantages of unshielded twisted pair.
[0007] With respect to other communication links, signals on fiber optic cables are generally not as susceptible to crosstalk from other cables, and crosstalk is not nearly as severe in shielded cables. But such fiber optic cables and shielded cables, as well as the equipment used therewith, is often cost prohibitive and also cannot be used in those applications attempting to reuse cable already in buildings. For example, it may be necessary to take advantages of existing infrastructure, to accommodate mixed systems that use both fiber-optics (such as between floors) and twisted pairs (such as in horizontal runs on a floor).
[0008] Therefore, there is a need in the art for a system that can effectively reuse existing communication system infrastructures, such as for distributed antenna systems, without introducing additional costs associated therewith. There is further a need to address jitter, cross-talk, and noise issues in a DAS with twisted pair infrastructure to ensure the system master clock can be transferred to all remote elements to preclude a shift in RF from being introduced during up and down conversions. Still further, there is a need to have a DAS that can handle not only cellular communications but also other communications, such as public safety and radio and WiFi in a single cost-effective system.
SUMMARY OF THE INVENTION
[0009] Embodiments of the invention provide a method, distributed antenna system, and components thereof that generate a jitter reduced clock signal from a serial encoded binary data stream transmitted over a communication medium. The method comprises receiving a modulated signal that includes the encoded binary data stream via high speed data interface circuitry and extracting the encoded binary data stream from the modulated signal. The method further comprises generating a recovered clock signal that is phase locked to the encoded binary data stream with a phase-locked loop. The method still further comprises generating an error signal based on a difference between a phase of the encoded binary data stream and the recovered clock signal and integrating the error signal with a loop filter configured with a bandwidth that allows the jitter and drift in the encoded binary data stream to generate a signal to control a voltage controlled oscillator. The method further comprises generating a stable recovered clock signal by filtering the recovered clock signal to remove jitter without substantially affecting the frequency of the stable recovered clock signal to allow the stable recovered clock signal to track drift of the encoded binary data stream, and producing at least one output clock by scaling the stable recovered clock signal frequency. [0010] In alternative embodiments, a remote unit for a distributed antenna system is provided. The remote unit includes high speed data interface circuitry for communicating with a master unit, RF transceiver circuitry for communicating with a subscriber unit, and a processing unit that multiplexes and routes data to the high speed data interface and that de-multiplexes and routes data from the high speed data interface circuitry to the RF transceiver circuitry. The remote unit further includes a clock recovery circuit that includes a phase-locked loop, the phase-locked loop including a loop filter having a bandwidth that does not substantially block the jitter or long-term drift in a modulated signal, the clock recovery circuit configured to receive the modulated signal from the high speed data interface circuitry that includes a serial encoded binary data stream and further configured to generate a recovered clock signal therefrom, as well as a filtering circuit configured to filter the recovered clock signal to remove jitter and generate a stable recovered clock signal. The remote unit still further includes a scaling circuit configured to scale the frequency of the stable recovered clock signal to generate at least one output signal at a respective predetermined target frequency.
[0011] Still further embodiments of the invention include a distributed antenna system that includes a master unit and at least one remote unit. The master unit clocks an encoded data stream onto high speed data interface circuitry via a modulated signal based upon an output of a reference oscillator. The remote unit includes high speed data interface circuitry for receiving the modulated signal from the master unit and a clock recovery circuit. The clock recovery circuit, in turn, includes a phase-locked loop, the phase-locked loop in turn including a loop filter configured with a bandwidth that does not substantially block the jitter or long-term drift in the modulated signal. As such, the clock recovery circuit is configured to generate a recovered clock signal from the modulated signal that includes the encoded data stream. Still further, the remote unit includes a filtering circuit configured to filter the recovered clock signal to remove jitter and further configured to generate a stable recovered clock signal and a scaling circuit configured to scale the frequency of the stabled recovered clock signal to generate an output signal at a predetermined target frequency.
[0012] Additional embodiments of the invention include a method of generating a jitter reduced clock signal from an encoded data stream. The method comprises generating a recovered clock signal based on the encoded data stream, the recovered clock signal being phase locked to an oscillator used to clock the encoded data stream onto a modulated signal. The method further comprises clocking data from the encoded data stream into a processing unit based on the recovered clock signal and detecting a periodic signal component, other than the bit rate, of the encoded data stream with the processing unit. Still further, the method comprises generating a reference clock signal based on the detected periodic signal component, filtering the reference clock signal with a circuit having a bandwidth that substantially blocks jitter while substantially allowing long term drift of the reference clock signal, and scaling a frequency of the reference clock signal to generate at least one output signal at a predetermined target frequency.
[0013] Further alternative embodiments include a master unit for a distributed antenna system. The master unit includes high speed data interface circuitry for exchange of data with at least one remote unit and first RF transceiver circuitry for communicating with at least one base transceiver system. The master unit further comprises a processing unit that multiplexes data from the at least one secondary interface, the first RF transceiver, and the second RF transceiver and routes the multiplexed data to a PHY for transmission via the high speed data interface circuitry, and that de-multiplexes data from the high speed data interface circuitry and routes the de-multiplexed data to at least one of the at least one secondary interface, the first RF transceiver, or the second RF transceiver. Still further, the master unit comprises a reference oscillator that is used to multiplex and/or demultiplex the data to and/or from the high speed data interface.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with a general description of the invention given above, and the detailed description given below, serve to explain the invention.
[0015] FIG. 1 is a block diagram of a cellular phone system and broadband wireless metropolitan network consistent with embodiments of the invention.
[0016] FIG. 2 is a block diagram of a distributed antenna system included in the system and network of FIG. 1 ;
[0017] FIG. 3 is a block diagram of a master unit of the distributed antenna system of FIG. 2;
[0018] FIG. 4 is a block diagram of a remote unit of the distributed antenna system of FIG. 2;
[0019] FIG. 5 is a block diagram of an extension unit of the distributed antenna system of FIG. 2; [0020] FIG. 6 is a block diagram of one embodiment of modules used to recover a clock signal in the remote unit or extension unit of the distributed antenna system of FIG. 2; and
[0021] FIG. 7 is a block diagram of an alternative embodiment of modules used to recover a clock signal in the remote unit or extension unit of the distributed antenna system of FIG. 2.
[0022] It should be understood that the appended drawings are not necessarily to scale, presenting a somewhat simplified representation of various features illustrative of the basic principles of embodiments of the invention. The specific design features of the sequence of operations as disclosed herein, including, for example, specific dimensions, orientations, locations, and shapes of various illustrated components, will be determined in part by the particular intended application and use environment. Certain features of the illustrated embodiments may have been enlarged or distorted relative to others to facilitate visualization and clear understanding. In particular, thin features may be thickened, for example, for clarity or illustration.
DETAILED DESCRIPTION OF THE INVENTION
[0023] Embodiments of the present invention provide a remote unit that can be used to recover a clock signal embedded in a modulated signal. To do this, embodiments of the invention are capable of extracting the clock signal from the modulated signal, reducing the jitter on that extracted signal, then scaling the frequency of that signal. Advantageously, this allows a master unit to communicate with remote units over an unshielded twisted pair cable such that the cost for deployment is lessened. Embodiments of the invention further account for distributed antenna systems that use a mixed combination of fiber optic and twisted pair cables and also can be used to recover a clock signal embedded as a component of the modulated signal.
[0024] Cellular phone systems and broadband wireless metropolitan networks 20, as shown in FIGS. 1 and 2, are generally divided into a number of cells 22 distributed in a pattern to preclude co-channel interferences and provide coverage of mobile and fixed subscriber units operating within the service area of the system. Each cell 22 includes a base station 24 that employs radio frequency (RF) transceiver equipment, antennas 26, and wireline 28 communication equipment. Mobile/fixed subscriber units 30 within the geographic area of the cell site use RF transceiver equipment to communicate with RF transceivers within the base station 24. The base station 24 relays voice and data traffic to/from the subscriber mobile units or devices (e.g. a phone) 30 and to/from a Mobile Telephone Switching Office 32 or Access Service Gateway which in turn are connected to a central network such as the public switched telephone network (PSTN) 34 or packet switched networks such as the Internet, for example.
[0025] To improve the capacity of a base station 24 to handle more mobile users 30, cells 22 may be divided into sectors 38 or are further subdivided into smaller cells with the base station 24 being replaced with lower cost, reduced capability micro or pico cells 36. In some configurations, distributed antenna systems (DAS) may be employed to optimize the RF distribution in larger cells in order to increase capacity at an even lower cost than with pico and/or micro cells 36. These approaches permit the reuse of a limited number of expensive RF channels without incurring the costs of one or more complete base stations 24. Further, these techniques may also be used to extend coverage to areas within the cell site where RF propagation may be limited by obstruction, such as in buildings and tunnels, or to areas where the amount of traffic (revenue) does not justify the investment required for a complete base station 24. Distributed antenna systems allow the RF coverage to be adapted to the specific environment in a homogeneous way to assist in reducing the amount of introduced interference. In addition, the amount of extra traffic is kept low as only existing cells are distributed and no hand-off between cells is required.
[0026] In order to reduce the costs associated with the development of their communication systems, multiple service providers often locate their base stations 24 at the same geographical point. The providers can then share such items as antennas, antenna towers, primary power drops, land costs, and regulatory costs. These service providers may employ multiple RF bands, multiple channels within the same RF band and multiple air interface standards (e.g. GSM, LTE, CDMA, UMTS, TDMA, and WiMax).
[0027] The system 20 may also include a distributed antenna system 40 that, in turn, includes a master unit 42 collocated with at least one base station 24. The master unit 42 may be connected to the base station 24, which is then connected to the Mobile Telephone Switching Office 32 via a wireline 28 connection. A group of distributed antenna units 44 are interconnected via high speed digital transport links 46. The transport of RF signals in a digital format may assist in preventing any appreciable degradation due to the transport link. Spectral filtering may also be used to allow or prevent the distribution of specific radio signals. Additionally, the individual group delay of spectral components may be individually adjusted without hardware modifications. Thus, quality degrading delay differences between overlapping simulcast cells may be avoided.
[0028] The digital transport mechanism employed in embodiments of the invention allows for flexible use of the available bandwidth over the high speed data interfaces. The dominant use of these links is generally for RF spectrum. A time division multiplexed format of the links permits transport of multiple signals, which may even be at the same RF frequency. Further, data from data communication links such as Ethernet may also be inserted in the digital transport links for system monitoring, configuration, control, as well as other user applications, such as public safety communications and WiFi hot spots. When the communication medium employed on the high speed data links does not support the full rate transfer, the master unit or remote units dynamically scale the amount of RF bandwidth transmitted over the high speed serial data interfaces or eliminate low priority data. In particular, a processing unit of a master unit 42 or remote unit 44 may determine that the communication medium is unable to transfer data at a particular rate, speed, such as 10 Gbps. As such, the processing unit of the master unit 42 or remote unit 44 may dynamically shed RF bandwidth of the signal transmitted between the master unit 42 and remote unit 44, or the processing unit of the master unit 42 or remote unit 44 may not transmit lower priority data, such as Ethernet data or WiFi data , transmitted between the master unit 42 and remote unit 44.
[0029] In one embodiment, the distributed antenna system 50, as illustrated in FIG. 2, includes one or more master units 42 and a system controller 52 configured to control each master unit 42 collocated with a base station 24a-d. In one embodiment, each master unit 42 is capable of handling up to six RF bands with up to four service providers per band for Frequency Division Duplexed (FDD) air interfaces and one operator per band for Time Division Duplexed (TDD) air interfaces, although one of ordinary skill in the art will appreciate that other master units 42 may be capable of handling more or fewer RF bands, service providers or operators. The master unit 42 is connected to a base station 24a-d via coupling interfaces 54. The master unit 42 is also connected to a series of distributed antenna units 44, hereinafter referred to as remote units, or remote antenna units via high speed data interfaces. In the illustrated embodiment of Figure 2, four such interfaces are shown, although one of ordinary skill in the art will appreciate that other master units may have more than four interfaces. In specific embodiments, the master unit 42 is connected directly to each remote unit 44 via a respective high speed communication medium 60 employing low cost communication cable having at least three conductors, such as unshielded twisted pair. Each remote unit 44 may be configured to handle up to six RF bands, for example.
[0030] For each RF band 56a, 56b, the master unit 42 combines the downlink signal from the base stations 24a-d on a per band basis and digitizes the combined signal into a binary encoded data stream. One of ordinary skill in the art will recognize there may be more or fewer base stations 24 communicating with the master unit 42. The binary encoded data streams from each of the RF bands 56a, 56b may then be time division multiplexed and converted to a single serial stream. The serial data is transmitted to the remote units 44a-c via respective communication medium 60, such as twisted pair cables 60a-c. The remote units 44a-c receive that modulated signal, extract the data stream from the modulated signal, then extract a clock signal from that data stream, de-multiplex them and retransmit each band at an RF frequency, via a local antenna 62, to subscriber units 30. In alternative embodiments, the master unit 42 may digitize the downlink signal from the base stations 24a-d on a per band basis, then multiplex the digitized signal into the binary encoded data stream.
[0031 ] The distributed antenna system 50 may include more or fewer components, including more or fewer master units 42, remote units 44, and/or extension units 64 than illustrated in Figure 2. In turn, each master unit 42, remote unit 44, and/or extension unit 64 may include more or fewer components.
Specifically, the master unit 42 may include more or fewer input interfaces, each of which may be wireless or wireline RF interfaces. For example, the master unit 42 may receive various cellular base transceiver system signals (GSM, LTE, CDMA, UMTS, etc.), such as via the signals from the base stations 24a - 24d, and may implement connections 57 for other RF services (e.g., from public safety entities), WiFi data, Ethernet data, or data from a maintenance terminal. Moreover, the master unit 42 may be connected to a plurality of remote units 44 connected serially through one or two dedicated communication interfaces or one dedicated interface. In turn, the distributed antenna system 50 may include remote units 44 that utilize more than six RF bands and/or that include additional interfaces. Moreover, the Digitally Modulated Optical Cables (DMOC) 66 including the optical transceiver may also be replaced by a different transceiver for high data rate media such as coax cable, twisted pair copper wires, free space RF or optics, or shared networks such as Ethernet, SONET, SDH, ATM, PDH, among others. [0032] In some embodiments, the master unit 42 may include one or more optical links that are connected to an expansion and/or extension unit 64 via the DMOC 66. The extension unit 64 provides additional communication mediums for distribution of voice and data traffic, command and control, and user data for to up to sixteen remote units 44, thereby increasing the number of remote units 44 a single master unit 42 can handle. The extension unit 64 may communicate with master units 42 using the same wavelength in both directions. The remote units 44d-e also receive RF voice and/or data signals, designated as the uplink signal, from the customer or subscriber units/devices 30 via the local antennas 62.
[0033] With respect to the remote units 44, each RF uplink band is digitized separately. The uplink signals for each band are combined into a single serial digital protocol and transmitted via the respective communication medium 60a-e to the respective master unit 42 or to the master unit 42 through the extension unit 64. The master unit 42 separates the signals from each band, converts them to analog signals, converts or translates each to the appropriate radio frequency, and sends them to the appropriate base station 24.
[0034] In addition to the digitized signal from each RF band, the uplink communication mediums 60a-c and 66 also contain Operation and Maintenance (O&M) data, Ethernet data, User Ethernet (10 Mb/s, 100 Mb/s, 1 Gb/s, or higher data rate signals), and WiFi data. The former signal is used to configure and control the system and monitor system status. The User Ethernet signals may be used by the service providers as they see fit. The system controller 52 provides overall supervision and control of the master unit 42 and the remote units 44 as well as alarm forwarding. [0035] Focusing now on the master unit 42, FIG. 3 contains a detailed block diagram of an example of the master unit 42. The master unit 42 receives RF signals from a variety of base transceiver stations (BTS) and other services, then downconverts and digitizes those signals using appropriate RF transceiver circuitry 84 that may include frequency down converter circuits 43 and AID converters 45. The master unit 42 includes a stable reference oscillator 70 that feeds
phase/frequency locked loops/frequency divider circuitry 72 to generate one or more LO references, sampling clocks, and PHY references. A processing unit 74, such as an FPGA, or other suitable processor produces a serial stream and routes that data to a high-rate Ethernet physical layer device (PHY) 76, using the PHY reference, which is synchronized to the reference oscillator 70. Each PHY 76a-d encodes the data into an encoded data stream to eliminate long strings of ones and zeros, then clocks the data on the respective communication mediums (e.g., unshielded twisted pair cable) as a modulated signal using the PHY reference that is based upon reference oscillator 70. By using the PHY reference, which is phase locked to the reference oscillator 70, any long-term drift in the frequency of the oscillator 70 is transferred to the bit rate of the encoded data stream transmitted over the interfaces as a modulated signal.
[0036] In the reverse, data received from a remote unit 44 or extension unit 64 is decoded, error corrected by the respective PHY 76a-d, then routed to the processing unit 74. The processing unit 74 de-multiplexes the data and routes the digital signals through appropriate RF transceiver circuitry 82, which may include a D/A converter 47 and a frequency upconverter 49. The D/A converter 47 is for conversion of the digitized baseband data to analog signals. The analog signals are then up-converted to appropriate frequencies using appropriate frequency upconverters 49. Data for WiFi and other non-RF services are routed to slower high speed data interface circuitry 86, which in turn includes Ethernet PHYs 78, UARTs 80, or other similar devices for distribution. In the master unit 42, the down- conversion or up-conversion of signals is done with the LO reference tied to the oscillator 70. In turn, the conversion of a down-converted signal to digital data, and the conversion of digital data to an analog signal, is performed with the sampling clock tied to the oscillator 70. In this manner, all signals in to the master unit 42 and all signals from the master unit 42 are tied to the oscillator 70 consistent with embodiments of the invention.
[0037] Although PHYs 76a-d are illustrated as being used to send data to the remote units 44 and/or extension unit 64, the data is sent in a synchronous manner without typical inter-packet gaps to maximize throughput. Specifically, utilizing PHYs 76 allows high data rates of at least 10 Gbps over inexpensive unshielded twisted pair cable when the length of the run from the master unit 42 to the remote unit is sufficiently short. This may significantly reduce the cost of a distributed antenna system 40 for some application, and in particular those in buildings.
[0038] Moreover, although a PHY 76 is shown and disclosed as being connected to a remote unit 44 or extension unit 64 through a communication medium 60 to transmit data to and/or from the remote unit 44 or extension unit 64, additional RF transceiver circuitry may be included in the master unit 42 at the high speed data interface circuitry, or the RF circuitry 82, 84, to communicate non-cellular radio frequency voice or data with a subscriber unit 30 through a master unit antenna (not shown). [0039] Focusing now on a remote unit 44, FIG. 4 contains a detailed block diagram of a remote unit 44. Each remote unit 44 includes a high speed data interface, such as a PHY 90, that receives an encoded serial digital signal with a bit rate modulated by the drift in the reference oscillator 70, hereinafter referred to as a modulated signal, from the master unit 42 or an extension unit 64 and extracts the encoded data stream therefrom. The PHY 90, in turn, produces a recovered clock signal as at 92 that is phase locked to the encoded data stream, and thus to the oscillator 70 of the master unit 42. In accordance with one aspect of the invention, the recovered clock signal 92 is filtered by a jitter reduction circuit 94, which may include a narrowband phase-locked loop or a crystal filter. The jitter reduction circuit 94 produces a stable recovered clock signal 95 that is further phase locked and/or frequency divided by a phase/divider circuit 96. The phase/divider circuit 96, in turn, produces an LO reference, a sampling clock, and a processing unit clock signal (illustrated as "CPU CLOCK"). The data output of the PHY 90 (e.g., the encoded data stream) is routed to a processing unit 98, which may be an FPGA or other suitable processor, that demultiplexes the data stream. In turn, the processing unit 98 routes that demultiplexed data to appropriate RF transceiver circuitry 1 06, that may include a digital to analog (D/A) converters 99 and upconverter circuits 101 . The D/A converters 99 are for conversion into analog signals, while the upconverter circuits 1 01 frequency upconvert the analog signals into appropriate RF frequencies and transmit the upconverted signal to subscriber units 30 via one or more suitable antennas, such as local antenna 62. The present invention is not limited to specific RF transceiver circuitry used to communicate with particular subscriber units 30. For example, the remote unit 44 may include additional RF transceiver circuitry for communicating non-cellular RF voice and/or data with a subscriber unit 30, Non- baseband data is routed to high speed data interface circuitry 109, which in turn includes lower speed Ethernet PHYs 100 or UARTs 102.
[0040] RF signals received from subscriber units 30 via antenna 62 are received by RF transceiver circuitry 108, which includes a downconverter circuits 103 and A/D converters 105. The downconverter circuits 103 downconvert the received RF signal, which are each digitized by A/D converters 105 and routed to the processing unit 98. The processing unit 98 time-division multiplexes the data into a serial stream along with lower rate Ethernet data and/or other serial data from the Ethernet PHYs 100 and/or UART 102. This data is routed to the PHY 44 where it is coded and sent to the master unit 42 or extension unit 64.
[0041 ] The PHY 90 in the remote unit 44 phase and/or frequency locks at least one voltage-controlled oscillator (VCO) (not shown in FIG. 4) of a phase-locked loop (PLL) to the incoming data from the master unit 42 or extension unit 64. In turn, the output of a voltage-controlled oscillator (VCO) is used to recover the data and decode it. The bandwidth of the frequency locked loop is configured to be wide enough to track the long-term drift in the rate of the data due to variation in the frequency of the oscillator 70 of the master unit 42 as well as any wide band jitter introduced by or in the high speed serial link communication couplings between the remote unit 44 and the master unit 42. This, in effect, transfers any drift in the frequency of the oscillator 70 of the master unit 42 to the remote unit 44.
As illustrated in FIG. 4, each remote unit 44 reduces the jitter in a recovered clock signal 92 with a jitter reduction circuit 94 that is configured to lock a second voltage- controlled oscillator (not shown in FIG. 4) to the oscillator 70 of the master unit 42. The jitter reduction circuit 94, however, may have much lower phase noise than the oscillator of the PHY 90. In particular, the jitter reduction circuit 94 may use a narrowband PLL for locking phase and frequency as noted. The bandwidth of this narrowband PLL is configured to track the long-term drift of the oscillator 70 of the master unit 42 and reject short-term jitter contributed by the PHY 90 oscillator and impairments in the communication couplings between the remote unit 44 and the master unit 42 (e.g. , including through an extension unit 64, if necessary). The narrowband PLL, however, may be replaced with a narrowband crystal filter in applications where interference in the serial communication couplings between the remote unit 44 and the master unit 42 are less severe. The output 95 of the jitter reduction circuit 94, in turn, may be used to derive the LO reference, sampling clocks, and CPU CLK signals, each of which are frequency and/or phase locked by the phase/divider circuit 96. This ensures that all references and/or clock signals in the remote unit 44 and the master unit 42 that are used for frequency translation are phase and/or frequency locked to the oscillator 70 in the master unit 42. Thus, the distributed antenna system 40 does not shift the signals being broadcast, distributed, and/or repeated.
[0042] A detailed block diagram of an extension unit 64 is illustrated in FIG. 5. The extension unit 64 routes data from a master unit 42 to each remote unit 44 connected thereto. It also combines the data from the remote units 44 connected thereto into a single serial stream and routes that data via a PHY 1 10 to the master unit 42. The extension unit 64 also transfers the drift of the oscillator 70 in the master unit 42 to the remote units 44 to ensure that the references and/or clock signals for the remote units 44 are phase and/or frequency locked to that oscillator 70. As such, the extension unit 64 includes a PHY 1 10 that receives the modulated signal from the master unit 42 and extracts the encoded data stream therefrom. The PHY 1 10, in turn, produces a recovered clock signal as at 1 12 that is phase locked to the encoded data stream, and thus to the oscillator 70 of the master unit 42. The PHY 1 10 passes the encoded data stream to a processing unit 1 14, which may be an FPGA. The recovered clock signal 1 12 is also filtered by a jitter reduction circuit 1 16, which may include a narrowband PLL or a crystal filter, and outputs a recovered clock signal that is utilized as a PHY reference signal as at 1 1 8. The processing unit 1 14 sends data for the remote units 44 to the remote units 44 via a separate set of PHYs 120. Each PHY 120 sends the data with reference to the PHY reference.
[0043] The extension unit 64 may be coupled to the master unit 42 through unshielded twisted pair cable for applications where the number of remote units 44 necessary for the distributed antenna system 40 exceeds the capability of the master unit 42, or fiber where the distance between the extension unit 64 and the master unit 42 exceeds the length limitations of the PHY 1 10. Similar to the PHY 90 of the remote units 44, the PHY 1 10 phase and/or frequency locks the recovered clock signal 1 12 to the incoming data. The recovered clock signal 1 12 is used to recover and decode the data. Also, similar to the jitter reduction circuit 94 of the remote units 44, the bandwidth of the jitter reduction circuit 1 16 is again configured to be wide enough to track the long-term drift in the rate of data due to a variation in the oscillator 70 of the master unit 42 as well as any wide band jitter introduced by or in the communication couplings between the extension unit 64 and the master unit 42. This, in effect, transfers any drift in the oscillator 70 of the master unit 42 to the extension unit 64. The extension unit 64 reduces the jitter in the recovered clock signal 1 12 using a narrowband PLL or crystal filter similar to that described above. One of the clock outputs of the jitter reduction circuit 1 16 may be the PHY reference 1 18 for the PHYs 120 that send and receive data from the remote units 44. Since this PHY reference 1 18 is tracking the long-term drift of the oscillator 70, the drift is imparted to the rate of the data sent to the remote units 44. Advantageously, this may preclude the accumulation of jitter that may occur if the recovered clock signal 1 12 were used as the PHY reference 1 18 without first performing jitter reduction.
[0044] FIG. 6 illustrates a detailed block diagram of at least a portion of a clock recovery circuit 200 that may be included in the PHY 90 or 1 10, at least a portion of a noise filtering circuit 202 that may be included in the jitter reduction circuit 94 or 1 1 6, and at least a portion of a clock scaling circuit 204 that may be included in the phase/divider circuit 96, as well as the interconnections
therebetween. FIG. 6 further illustrates that the clock recovery circuit 200, the noise filtering circuit 202, and the clock scaling circuit 204 may be interconnected to recover a clock signal imposed on a data stream extracted from a modulated digital signal from a master unit 42. However, the invention is not limited to how the circuits 200, 202, 204 are arranged in one or more of the elements 90, 1 10, 94, 1 16, or 96 as illustrated in FIG. 4 and FIG. 5. Specifically, the clock recovery circuit 200 receives a stream of binary encoded data extracted from a modulated signal and generates a recovered clock signal as at 206 (e.g., that may correspond to the recovered clock signal 92 or 1 12) based thereon. The recovered clock signal 206 is then processed by the noise filtering circuit 104 to reduce jitter and to produce a stable recovered clock signal as at 208 (e.g. , that may correspond to the PHY reference for the extension unit 64 illustrated in FIG. 5). The stable recovered clock signal 208 advantageously has a phase and/or frequency corresponding to the phase and/or frequency of the oscillator 70 of the master unit that was used to clock the data received by the clock recover circuit 200. The clock scaling circuit 204, in turn, may be used to generate one or more scaled clock signals (e.g., such as the LO reference, the sampling clock signal, the PHY reference, and/or the CPU CLK) as at 210 for use in operating a remote unit 44. In specific embodiments, the clock recovery circuit 200, noise filtering circuit 202, and clock scaling circuit 204 may be implemented with a phase locked loop that each includes a phase-frequency detector charge pump 212, a loop filter 214, and a voltage controller oscillator (VCO) 216. Alternatively, the VCO 216 may be implemented as an LC tank circuit that includes at least one voltage controlled capacitor.
[0045] Referring to the clock recovery circuit 200, the phase-frequency detector charge pump 212a may compare a rising edge of a pulse within the received binary encoded data stream from the master unit 42 with a rising edge of a pulse received as a feedback signal from the VCO 216a (illustrated as FVC01 FB). The phase-frequency detector charge pump 212a then produces a frequency error signal (illustrated as VERROR) that is representative of both the sign and scale to the phase and/or frequency difference detected by the phase-frequency detector charge pump 212a between the encoded binary data input signal from the master unit 42 and the feedback signal FVC01 FB. The loop filter 214a then receives and integrates the frequency error signal VERROR to generate a smoothed VCO control signal (illustrated as VCONTROL) that is passed to the VCO 216a. VCO 216a of the clock recovery circuit 200, in turn, generates the recovered clock signal 206. The recovered clock signal 206 has a frequency that is proportional to the VCO control signal VCONTROL such that the recovered clock signal 206 is locked in phase and/or frequency to the oscillator 70 used by the master unit 42 to clock the binary encoded data stream into the modulated signal therefrom.
[0046] In some embodiments, however, the recovered clock signal 206 may exhibit jitter and/or other noise, as noted above. As such, the noise filtering circuit 202 is configured to process the recovered clock signal 206 through a second PLL to reduce jitter and provide the functionality of a jitter reduction circuit. In one embodiment, the PLL for the noise filtering circuit 202 is substantially similar to the PLL for the clock recovery circuit 200. The output of the noise filtering circuit 202, however, is the stable recovered clock signal 208 that is locked in phase and/or frequency to that of the recovered clock signal 206 and that, in turn, matches the phase and/or frequency of the oscillator 70 of the master unit 42, but that does not include jitter and/or noise accumulated between the clock recovery circuit 200 and the master unit 42.
[0047] For example, the bandwidth of the PLL for the clock recovery circuit 200 is configured to be sufficiently wide to track short-term jitter (e.g., high frequency jitter), on data, as well as long-term drift of the oscillator 70. This assures that no data is filtered from the signal. Thus, the clock recovery circuit 200 is not configured to filter the long-term drift or the short-term jitter. The bandwidth of the noise filtehng circuit 202, however, is configured to be narrower than the bandwidth of the clock recovery circuit 200 such that short-term jitter is filtered out without filtering out long- term drift in the reference signal from the oscillator 70. Thus, short-term jitter is not propagated to the VCO 216b while long-term drift is. [0048] In alternative embodiments, the noise filtering circuit 202 may be replaced by a narrow band crystal filter to eliminate jitter in the recovered clock signal 206.
[0049] As illustrated in FIG. 6, the clock recovery circuit 200 and the noise filtering circuit 202 are not configured with dividers. As such, the circuits 200 and 202 are configured to produce respective output signals 206 and 208 that are phase and/or frequency matched to the phase and/or frequency of the signal received by the clock recovery circuit 200. However, in some embodiments, a frequency divider may be used at the input of the noise filtering circuit 202, at the feedback signal FVC02FB from the VCO 216b to the phase-frequency detector charge pump 212b, or at the output of the noise filtering circuit 202. Such dividers may be used to generate particular clock signals at particular frequencies. However, if no clock signals at particular frequencies are required, the clock scaling circuit 204 may not be included (e.g., such as illustrated for the extension unit 64 in FIG. 6).
When clock signals at particular frequencies are required, the stable recovered clock signal 208 may be further processed by the clock scaling circuit 204 to generate one or more clock signals (e.g. , such as those signals illustrated as output by the phase/divider circuit 96 in the remote unit 44 in FIG. 5). In specific embodiments, the PLL for the clock scaling circuit 204 is substantially similar to the PLL for the noise filtering circuit 202 and the clock recovery circuit 200. But the clock scaling circuit 204 may include, or otherwise be coupled to, signal dividers such that an output signal has a different output frequency from, but locked to, the stable recovered clock signal 208. [0050] As illustrated in FIG. 6, a first signal frequency divider 218 (illustrated as "%M") receives the stable recovered clock signal 208 and generates an input signal for the phase-frequency detector charge pump 212c (illustrated as
"FVC02M") that is a fraction of the stable recovered clock signal 208. Additionally, a second signal frequency divider 220 (illustrated as "%N") may receive a scaled clock signal 210 from the VCO 21 6c to feed back to the phase-frequency detector charge pump 212c to increase the frequency of that signal above that of the input signal
FVC02M. A third signal frequency divider 222 (illustrated as "%L") may also receive a scaled clock signal from the VCO 216c to reduce the frequency of that scaled clock signal. Consistent with one embodiment of the invention, the clock scaling circuit
204 is configured to lock onto a stable recovered clock signal 208 of about 156.25
MHz and produce a scaled clock signal 210 of about 800 MHz. The third signal frequency divider 222, in turn, is used to generate an output signal 224 of about 100
MHz signal from the scaled clock signal 210 of about 800 MHz. Thus, scaled clock signal 210 may be about five times the stable recovered clock signal 208, while the scaled clock signal 210 may be about eight times the output signal 224.
In some embodiments, the second signal frequency divider 220 may be matched to the increase in the frequency applied by the VCO 216c to the input signal FVC02M such that the VCO feedback signal (illustrated as VFV03FB) is frequency locked to the input signal FVC02M. Equations 1 through 3 illustrate this relationship.
FVC02/M = FVCQ2
M
EQ. 1
FVC03 = FVC02/M * N = FVC02 * N/M
EQ. 2 FVC03FB = FVC03 = FVC02
N M
EQ. 3
[0051] Thus, and with reference to Equation 2, inserting the first signal frequency divider 21 8 prior to the feedback loop allows the generation of the scaled clock signal 21 0 with a frequency that is proportional to the scaled recovered clock signal 208 as determined by the ratios of the first signal frequency divider 218 and the second signal frequency divider 220. The second signal frequency divider 220 may be a fractional N divider to permit flexibility in selecting the clock frequency.
[0052] Specifically, FIG. 7 illustrates at least a portion of a circuit 250 that may be used to recover a clock signal from a bit stream of data consistent with alternative embodiments of the invention.
[0053] As an alternative implementation of the jitter reduction process of the invention, the FPGA or other processor in a remote unit can provide a signal aligned with a periodic signal present in the serial data that could be used in place of the recovered clock as a reference for the oscillator.
[0054] In one example, the circuit 250 includes the clock recovery circuit 200 that generates the recovered clock signal 206 from an encoded data stream. The data and the recovered clock signal 206 are applied to a D flip-flop circuit 252 with the data applied to the D input thereof and the recovered clock signal 206 applied to the clock input thereof. The Q output of the D flip-flop circuit 252, in turn, is provided to a processor 254, such as an FPGA, that is configured to produce a signal as at 256 based on a detected periodic signal that is used to adjust the frequency of the oscillator at 258. The signal 256 generated by the processor is based on processed data clocked in from data lines using the recovered clock signal 206. It is developed by averaging the rate of the detected periodic signal sync component as determined by the processor. In such an embodiment, the noise filtering circuit 202 is not required. This reference signal 260 may then be supplied to a clock scaling circuit 204 to generate clock signals. This approach can use any periodic component of the encoded data stream.
[0055] While the present invention has been illustrated by a description of one or more embodiments thereof and while these embodiments have been described in considerable detail, they are not intended to restrict or in any way limit the scope of the appended claims to such detail. Additional advantages and modifications will readily appear to those skilled in the art. Thus, the invention in its broader aspects is therefore not limited to the specific details, representative apparatus and method, and illustrative examples shown and described. Accordingly, departures may be made from such details without departing from the scope of the general inventive concept.

Claims

[0056] WHAT !S CLAIMED IS:
1 . A method of generating a jitter reduced clock signal from a serial encoded binary data stream transmitted over a communication medium, the method comprising:
receiving a modulated signal that includes the encoded binary data stream via high speed data interface circuitry;
extracting the encoded binary data stream from the modulated signal;
generating a recovered clock signal that is phase locked to the encoded binary data stream with a phase-locked loop;
generating an error signal based on a difference between a phase of the encoded binary data stream and the recovered clock signal;
integrating the error signal with a loop filter configured with a bandwidth that allows the jitter and drift in the encoded binary data stream to generate a signal to control a voltage controlled oscillator;
generating a stable recovered clock signal by filtering the recovered clock signal to remove jitter without substantially affecting the frequency of the stable recovered clock signal to allow the stable recovered clock signal to track drift of the encoded binary data stream; and
producing at least one output clock by scaling the stable recovered clock signal frequency.
2. The method of claim 1 , wherein the high speed data interface circuitry includes at least a one gigabit per second (Gbps) Ethernet interface.
3. The method of claim 2, wherein the Ethernet interface is synchronous or asynchronous.
4. The method of claim 1 , wherein the communication medium is a
communication cable having at least one twisted pair cable.
5. A remote unit for a distributed antenna system, comprising:
high speed data interface circuitry for communicating with a master unit;
RF transceiver circuitry for communicating with a subscriber unit;
a processing unit that multiplexes and routes data to the high speed data interface and that de-multiplexes and routes data from the high speed data interface circuitry to the RF transceiver circuitry;
a clock recovery circuit that includes a phase-locked loop, the phase-locked loop including a loop filter having a bandwidth that does not substantially block the jitter or long-term drift in a modulated signal, the clock recovery circuit configured to receive the modulated signal from the high speed data interface circuitry that includes a serial encoded binary data stream and further configured to generate a recovered clock signal therefrom;
a filtering circuit configured to filter the recovered clock signal to remove jitter without removing long-term drift in the modulated signal to generate a stable recovered clock signal; and a scaling circuit configured to scale the frequency of the stable recovered clock signal to generate at least one output signal at a respective predetermined target frequency.
6. The remote unit of claim 5, wherein the high speed data interface circuitry is coupled to a communication medium having at least one twisted pair cable.
7. The remote unit of claim 5, wherein the data that is multiplexed and routed to the high speed data interface circuitry includes at least one of digitized RF cellular voice data, digitized RF non-cellular voice data, digitized RF cellular data, digitized RF non-cellular data, control data, maintenance data, Ethernet data, or WiFi data.
8. The remote unit of claim 5, wherein the processing unit is configured to adjust the rate or the content of data being transmitted on the high speed data link to match the capability of that link by excluding low priority data from the multiplexed stream.
9. The remote unit of claim 5, wherein the RF transceiver circuitry is configured to communicate cellular data with the subscriber unit.
10. The remote unit of claim 9, wherein the RF transceiver circuitry is further configured to communicate non-cellular data with the subscriber unit.
1 1 . The remote unit of claim 5, further comprising:
an auxiliary interface for at least one of communicating control data, maintenance data, Ethernet data, or WiFi data.
12. A distributed antenna system, comprising:
a master unit that clocks an encoded data stream onto high speed data interface circuitry via a modulated signal based upon an output of a reference oscillator; and
at least one remote unit that receives the modulated signal from the master unit, each remote unit including:
high speed data interface circuitry for receiving the modulated signal from the master unit,
a clock recovery circuit that includes a phase-locked loop, the phase- locked loop in turn including a loop filter configured with a bandwidth that does not substantially block the jitter or long-term drift in the modulated signal, the clock recovery circuit configured to generate a recovered clock signal from the modulated signal that includes the encoded data stream;
a filtering circuit configured to filter the recovered clock signal to remove jitter without removing long-term drift in the modulated signal and further configured to generate a stable recovered clock signal; and
a scaling circuit configured to scale the frequency of the stabled recovered clock signal to generate an output signal at a predetermined target frequency.
13. The system of claim 12, wherein the high speed data interface circuitry is coupled to a communication medium having at least one twisted pair cable.
14. The system of claim 12, further comprising:
an extension unit that relays the modulated signal from the master unit to the remote unit.
15. The system of claim 12, wherein the master unit further includes:
master unit RF transceiver circuitry for communication with a base transceiver station,
wherein the base transceiver station provides the master unit with cellular data and wherein the encoded data stream includes the cellular data.
16. The system of claim 12, the master unit RF transceiver circuitry is configured to communicate with a subscriber unit, wherein the master unit further includes: master unit high speed data interface circuitry for communication with the at least one remote unit;
an auxiliary interface for communicating at least one of control data, maintenance data, Ethernet data, or WiFi data;
a processor that multiplexes data from the master unit transceiver circuitry and the auxiliary interface for transmission to the at least one remote unit via the master unit high speed data interface circuitry, and that de-multiplexes data received from the master unit high speed data interface circuitry for transmission to the base transceiver station via the master unit RF transceiver circuitry.
17. The system of claim 12, wherein the high speed data interface circuitry is an at least a one gigabit per second (Gbps) Ethernet interface.
18. The system of claim 17, wherein the Ethernet interface is synchronous or asynchronous.
19. The system of claim 12, the remote unit further including:
RF transceiver circuitry for communicating with a subscriber unit; and a processing unit that de-multiplexes data from the high speed data interface circuitry for transmission by the RF transceiver circuitry, and that multiplexes data from the RF transceiver circuitry for transmission by the high speed data interface circuitry,
wherein the processing unit is configured adjust the rate of data being transmitted on the high speed data interface to match the capability of that interface by excluding low priority data from the multiplexed stream.
20. The system of claim 19, wherein the data that is multiplexed to the high speed data interface circuitry includes at least one of digitized RF cellular voice data, digitized RF non-cellular voice data, digitized RF cellular data, digitized RF non- cellular data, control data, maintenance data, or WiFi data.
21 . The system of claim 12, the remote unit further including:
RF transceiver circuitry for communicating cellular and non-cellular data with a subscriber unit; an auxiliary interface for communicating at least one of control data, maintenance data, Ethernet data, or WiFi data; and
a processing unit that de-multiplexes data from the high speed data interface circuitry for transmission by the RF transceiver circuitry or the auxiliary interface, and that multiplexes data from the RF transceiver circuitry and the auxiliary interface for transmission by the high speed data interface circuitry.
22. A method of generating a jitter reduced clock signal from an encoded data stream, the method comprising:
generating a recovered clock signal based on the encoded data stream, the recovered clock signal being phase locked to an oscillator used to clock the encoded data stream onto a modulated signal;
clocking data from the encoded data stream into a processing unit based on the recovered clock signal;
detecting a periodic signal component, other than the bit rate, of the encoded data stream with the processing unit;
generating a reference clock signal based on the detected periodic signal component;
filtering the reference clock signal with a circuit having a bandwidth that substantially blocks jitter while substantially allowing long term drift of the reference clock signal; and
scaling a frequency of the reference clock signal to generate at least one output signal at a predetermined target frequency.
23. A master unit for a distributed antenna system, comprising:
high speed data interface circuitry for exchange of data with at least one remote unit;
first RF transceiver circuitry for communicating with at least one base transceiver system;
a processing unit that multiplexes data from the at least one secondary interface, the first RF transceiver, and the second RF transceiver and routes the multiplexed data to a PHY for transmission via the high speed data interface circuitry, and that de-multiplexes data from the high speed data interface circuitry and routes the de-multiplexed data to at least one of the at least one secondary interface, the first RF transceiver, or the second RF transceiver; and
a reference oscillator that is used to multiplex and/or de-multiplex the data to and/or from the high speed data interface.
24. The master unit of claim 23, wherein the high speed data interface circuitry is coupled to a communication medium having at least one twisted pair cable.
25. The master unit of claim 23, wherein the data that is multiplexed to the high speed data interface circuitry includes at least one of digitized RF cellular voice data, digitized RF non-cellular voice data, digitized RF cellular data, digitized RF non- cellular data, control data, maintenance data, Ethernet data, or WiFi data.
26. The master unit of claim 23, wherein the processing unit can adjust the rate of data being transmitted on the high speed data interface circuitry to match the capability thereof by excluding low priority data from the multiplexed data or by reducing the amount of RF bandwidth being transmitted.
27. The master unit of claim 23, further comprising:
auxiliary interface circuitry for communicating non-radio frequency data.
28. The master unit of claim 23, further comprising:
second RF transceiver circuitry for communicating non-cellular radio frequency data with a subscriber unit.
PCT/US2011/030712 2010-03-31 2011-03-31 Synchronous transfer of streaming data in a distributed antenna system WO2011123635A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP18200679.1A EP3448116B1 (en) 2010-03-31 2011-03-31 Synchronous transfer of streaming data in a distributed antenna system
KR1020127026847A KR101847631B1 (en) 2010-03-31 2011-03-31 Synchronous transfer of streaming data in a distributed antenna system
EP11713439.5A EP2554015B2 (en) 2010-03-31 2011-03-31 Synchronous transfer of streaming data in a distributed antenna system
CN201180016515.5A CN102823321B (en) 2010-03-31 2011-03-31 The synchronous driving of the flow data in distributing antenna system
BR112012024716-6A BR112012024716B1 (en) 2010-03-31 2011-03-31 DISTRIBUTED ANTENNA SYSTEM AND METHOD OF GENERATION OF A CLOCK SIGNAL FROM A STREAM OF CODED DATA TRANSMITTED THROUGH A COMMUNICATION MEDIA

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US31962310P 2010-03-31 2010-03-31
US61/319,623 2010-03-31
US13/076,002 2011-03-30
US13/076,002 US8681917B2 (en) 2010-03-31 2011-03-30 Synchronous transfer of streaming data in a distributed antenna system

Publications (2)

Publication Number Publication Date
WO2011123635A2 true WO2011123635A2 (en) 2011-10-06
WO2011123635A3 WO2011123635A3 (en) 2012-01-26

Family

ID=44709685

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/030712 WO2011123635A2 (en) 2010-03-31 2011-03-31 Synchronous transfer of streaming data in a distributed antenna system

Country Status (5)

Country Link
US (6) US8681917B2 (en)
EP (2) EP2554015B2 (en)
KR (1) KR101847631B1 (en)
CN (2) CN102823321B (en)
WO (1) WO2011123635A2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014127519A1 (en) * 2013-02-22 2014-08-28 Telefonaktiebolaget L M Ericsson(Publ) Time synchronous pluggable transceiver
US9509487B2 (en) 2010-03-31 2016-11-29 Commscope Technologies Llc Synchronous transfer of streaming data in a distributed antenna system
CN108476415A (en) * 2016-02-03 2018-08-31 康普技术有限责任公司 Scheme is reconfigured priority-based for remote unit
WO2019125848A1 (en) * 2017-12-18 2019-06-27 Commscope Technologies Llc Synchronization and fault management in a distributed antenna system

Families Citing this family (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1403065B1 (en) 2010-12-01 2013-10-04 Andrew Wireless Systems Gmbh DISTRIBUTED ANTENNA SYSTEM FOR MIMO SIGNALS.
US8380143B2 (en) 2002-05-01 2013-02-19 Dali Systems Co. Ltd Power amplifier time-delay invariant predistortion methods and apparatus
US8811917B2 (en) 2002-05-01 2014-08-19 Dali Systems Co. Ltd. Digital hybrid mode power amplifier system
KR20140091616A (en) 2006-12-26 2014-07-21 달리 시스템즈 씨오. 엘티디. Method and system for baseband predistortion linearization in multi-channel wideband communication systems
WO2009053910A2 (en) 2007-10-22 2009-04-30 Mobileaccess Networks Ltd. Communication system using low bandwidth wires
EP2394378A1 (en) 2009-02-03 2011-12-14 Corning Cable Systems LLC Optical fiber-based distributed antenna systems, components, and related methods for monitoring and configuring thereof
US8280259B2 (en) 2009-11-13 2012-10-02 Corning Cable Systems Llc Radio-over-fiber (RoF) system for protocol-independent wired and/or wireless communication
IT1398025B1 (en) 2010-02-12 2013-02-07 Andrew Llc DISTRIBUTED ANTENNA SYSTEM FOR MIMO COMMUNICATIONS.
US8275265B2 (en) 2010-02-15 2012-09-25 Corning Cable Systems Llc Dynamic cell bonding (DCB) for radio-over-fiber (RoF)-based networks and communication systems and related methods
US9525488B2 (en) 2010-05-02 2016-12-20 Corning Optical Communications LLC Digital data services and/or power distribution in optical fiber-based distributed communications systems providing digital data and radio frequency (RF) communications services, and related components and methods
US8472579B2 (en) 2010-07-28 2013-06-25 Adc Telecommunications, Inc. Distributed digital reference clock
WO2012024247A1 (en) * 2010-08-16 2012-02-23 Corning Cable Systems Llc Remote antenna clusters and related systems, components, and methods supporting digital data signal propagation between remote antenna units
KR20180026793A (en) 2010-08-17 2018-03-13 달리 시스템즈 씨오. 엘티디. Neutral host architecture for a distributed antenna system
KR101829517B1 (en) 2010-09-14 2018-02-14 달리 시스템즈 씨오. 엘티디. Remotely Reconfigurable Distributed Antenna System and Methods
WO2012044969A1 (en) 2010-10-01 2012-04-05 Andrew Llc Distributed antenna system for mimo signals
US9252874B2 (en) 2010-10-13 2016-02-02 Ccs Technology, Inc Power management for remote antenna units in distributed antenna systems
US8532242B2 (en) 2010-10-27 2013-09-10 Adc Telecommunications, Inc. Distributed antenna system with combination of both all digital transport and hybrid digital/analog transport
CN203504582U (en) 2011-02-21 2014-03-26 康宁光缆系统有限责任公司 Distributed antenna system and power supply apparatus for distributing electric power thereof
EP2702780A4 (en) 2011-04-29 2014-11-12 Corning Cable Sys Llc Systems, methods, and devices for increasing radio frequency (rf) power in distributed antenna systems
IN2014CN04237A (en) 2011-11-07 2015-07-17 Dali Systems Co Ltd
EP2829152A2 (en) 2012-03-23 2015-01-28 Corning Optical Communications Wireless Ltd. Radio-frequency integrated circuit (rfic) chip(s) for providing distributed antenna system functionalities, and related components, systems, and methods
WO2013148986A1 (en) 2012-03-30 2013-10-03 Corning Cable Systems Llc Reducing location-dependent interference in distributed antenna systems operating in multiple-input, multiple-output (mimo) configuration, and related components, systems, and methods
US9439242B2 (en) 2012-08-13 2016-09-06 Dali Systems Co., Ltd. Time synchronized routing in a distributed antenna system
US9112549B2 (en) 2012-10-05 2015-08-18 Dali Systems Co. Ltd. DAS integrated digital off-air repeater
US9455784B2 (en) 2012-10-31 2016-09-27 Corning Optical Communications Wireless Ltd Deployable wireless infrastructures and methods of deploying wireless infrastructures
CN105308876B (en) 2012-11-29 2018-06-22 康宁光电通信有限责任公司 Remote unit antennas in distributing antenna system combines
US9179336B2 (en) 2013-02-19 2015-11-03 Mimosa Networks, Inc. WiFi management interface for microwave radio and reset to factory defaults
US9930592B2 (en) 2013-02-19 2018-03-27 Mimosa Networks, Inc. Systems and methods for directing mobile device connectivity
CN105144666B (en) * 2013-02-22 2019-06-11 Adc电信股份有限公司 From the primary standard of the base station network interface of distributing antenna system
US8909605B1 (en) 2013-02-28 2014-12-09 Emc Corporation Method and system for accelerating data movement using change information concerning difference between current and previous data movements
WO2014137370A1 (en) 2013-03-06 2014-09-12 Mimosa Networks, Inc. Waterproof apparatus for cables and cable interfaces
US9362629B2 (en) 2013-03-06 2016-06-07 Mimosa Networks, Inc. Enclosure for radio, parabolic dish antenna, and side lobe shields
US10742275B2 (en) 2013-03-07 2020-08-11 Mimosa Networks, Inc. Quad-sector antenna using circular polarization
WO2014137346A1 (en) 2013-03-07 2014-09-12 Hewlett-Packard Development Company, L.P. Synchronizing signal transmissions by antenna apparatuses
US9191081B2 (en) 2013-03-08 2015-11-17 Mimosa Networks, Inc. System and method for dual-band backhaul radio
WO2014146274A1 (en) * 2013-03-21 2014-09-25 Telefonaktiebolaget L M Ericsson (Publ) Method and apparatus for implementing clock holdover
US9295103B2 (en) 2013-05-30 2016-03-22 Mimosa Networks, Inc. Wireless access points providing hybrid 802.11 and scheduled priority access communications
US10938110B2 (en) 2013-06-28 2021-03-02 Mimosa Networks, Inc. Ellipticity reduction in circularly polarized array antennas
WO2015002584A1 (en) * 2013-07-03 2015-01-08 Telefonaktiebolaget Lm Ericsson (Publ) Radio unit and method performed by a radio unit operable in a base station system of a wireless communication network for reducing interference at the radio unit
US9787457B2 (en) 2013-10-07 2017-10-10 Commscope Technologies Llc Systems and methods for integrating asynchronous signals in distributed antenna system with direct digital interface to base station
US20170250927A1 (en) * 2013-12-23 2017-08-31 Dali Systems Co. Ltd. Virtual radio access network using software-defined network of remotes and digital multiplexing switches
US9001689B1 (en) 2014-01-24 2015-04-07 Mimosa Networks, Inc. Channel optimization in half duplex communications systems
US9444470B2 (en) * 2014-01-31 2016-09-13 Microsemi Semiconductor Ulc Double phase-locked loop with frequency stabilization
WO2015126828A1 (en) 2014-02-18 2015-08-27 Commscope Technologiees Llc Selectively combining uplink signals in distributed antenna systems
US9780892B2 (en) 2014-03-05 2017-10-03 Mimosa Networks, Inc. System and method for aligning a radio using an automated audio guide
US9998246B2 (en) 2014-03-13 2018-06-12 Mimosa Networks, Inc. Simultaneous transmission on shared channel
US9775123B2 (en) 2014-03-28 2017-09-26 Corning Optical Communications Wireless Ltd. Individualized gain control of uplink paths in remote units in a distributed antenna system (DAS) based on individual remote unit contribution to combined uplink power
WO2015156927A1 (en) 2014-04-09 2015-10-15 Commscope Technologies Llc Multistage combining sub-system for distributed antenna system
EP3407675B1 (en) 2014-04-15 2022-03-09 CommScope Technologies LLC Wideband remote unit for distributed antenna system
EP3531597B1 (en) * 2014-05-02 2021-06-16 CommScope Technologies LLC Link-fault tolerance in a distributed antenna system
US9525472B2 (en) 2014-07-30 2016-12-20 Corning Incorporated Reducing location-dependent destructive interference in distributed antenna systems (DASS) operating in multiple-input, multiple-output (MIMO) configuration, and related components, systems, and methods
GB2529184A (en) * 2014-08-12 2016-02-17 Kathrein Werke Kg Method and system for relaying telecommunications signals
US9730228B2 (en) 2014-08-29 2017-08-08 Corning Optical Communications Wireless Ltd Individualized gain control of remote uplink band paths in a remote unit in a distributed antenna system (DAS), based on combined uplink power level in the remote unit
US10958332B2 (en) 2014-09-08 2021-03-23 Mimosa Networks, Inc. Wi-Fi hotspot repeater
USD752566S1 (en) 2014-09-12 2016-03-29 Mimosa Networks, Inc. Wireless repeater
US10659163B2 (en) 2014-09-25 2020-05-19 Corning Optical Communications LLC Supporting analog remote antenna units (RAUs) in digital distributed antenna systems (DASs) using analog RAU digital adaptors
US9420542B2 (en) 2014-09-25 2016-08-16 Corning Optical Communications Wireless Ltd System-wide uplink band gain control in a distributed antenna system (DAS), based on per band gain control of remote uplink paths in remote units
US9184960B1 (en) 2014-09-25 2015-11-10 Corning Optical Communications Wireless Ltd Frequency shifting a communications signal(s) in a multi-frequency distributed antenna system (DAS) to avoid or reduce frequency interference
US9397871B2 (en) * 2014-09-30 2016-07-19 Infineon Technologies Ag Communication devices
WO2016071902A1 (en) 2014-11-03 2016-05-12 Corning Optical Communications Wireless Ltd. Multi-band monopole planar antennas configured to facilitate improved radio frequency (rf) isolation in multiple-input multiple-output (mimo) antenna arrangement
WO2016075696A1 (en) 2014-11-13 2016-05-19 Corning Optical Communications Wireless Ltd. Analog distributed antenna systems (dass) supporting distribution of digital communications signals interfaced from a digital signal source and analog radio frequency (rf) communications signals
US9729267B2 (en) 2014-12-11 2017-08-08 Corning Optical Communications Wireless Ltd Multiplexing two separate optical links with the same wavelength using asymmetric combining and splitting
EP3235336A1 (en) 2014-12-18 2017-10-25 Corning Optical Communications Wireless Ltd. Digital interface modules (dims) for flexibly distributing digital and/or analog communications signals in wide-area analog distributed antenna systems (dass)
WO2016098111A1 (en) 2014-12-18 2016-06-23 Corning Optical Communications Wireless Ltd. Digital- analog interface modules (da!ms) for flexibly.distributing digital and/or analog communications signals in wide-area analog distributed antenna systems (dass)
US9584209B2 (en) * 2014-12-31 2017-02-28 Nxp B. V. Multiple antenna distributed radio system
US10499269B2 (en) 2015-11-12 2019-12-03 Commscope Technologies Llc Systems and methods for assigning controlled nodes to channel interfaces of a controller
WO2017123558A1 (en) 2016-01-11 2017-07-20 Mimosa Networks, Inc. Printed circuit board mounted antenna and waveguide interface
WO2017214229A1 (en) * 2016-06-10 2017-12-14 At&T Intellectual Property I, L.P. Method and apparatus for use with a radio distributed antenna system having a clock reference
BR112018075523A2 (en) * 2016-06-10 2019-03-19 At & T Ip I Lp host node device and methods for use with it
CN109314568A (en) * 2016-06-10 2019-02-05 At&T知识产权部有限合伙公司 The client node device of distributing antenna system
EP3491697B8 (en) 2016-07-29 2023-10-18 Mimosa Networks, Inc. Multi-band access point antenna array
JP2020509688A (en) 2017-02-21 2020-03-26 メイベン ワイヤレス スウェーデン アクティエボラーグ Distributed antenna system for multi-operator networks
US10819568B2 (en) * 2017-06-26 2020-10-27 Commscope Technologies Llc System and method for configuring the ethernet network and RF connections for links between nodes of a distributed antenna system
US10511074B2 (en) 2018-01-05 2019-12-17 Mimosa Networks, Inc. Higher signal isolation solutions for printed circuit board mounted antenna and waveguide interface
CN111837429B (en) * 2018-01-12 2023-09-12 皇家飞利浦有限公司 System and method for clock recovery in wireless communications
US11069986B2 (en) 2018-03-02 2021-07-20 Airspan Ip Holdco Llc Omni-directional orthogonally-polarized antenna system for MIMO applications
US10582569B2 (en) * 2018-06-04 2020-03-03 Withusplanet Inc. WiFi network system for highly dense network environment
KR101912872B1 (en) * 2018-06-04 2018-10-30 주식회사 위더스플래닛 WiFi NETWORK SYSTEM FOR HIGHLY CONCENTRATED NEWTORK ENVIRONMENT
US11289821B2 (en) 2018-09-11 2022-03-29 Air Span Ip Holdco Llc Sector antenna systems and methods for providing high gain and high side-lobe rejection
US11314623B2 (en) * 2019-01-23 2022-04-26 Red Hat, Inc. Software tracing in a multitenant environment
CN112319498B (en) * 2020-10-12 2023-04-11 武汉蓝星科技股份有限公司 Method and system for reducing power consumption of electronic equipment based on GPS

Family Cites Families (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4397017A (en) 1981-03-02 1983-08-02 Nippon Electric Co., Ltd. Stuff synchronization device with reduced sampling jitter
CA1262173A (en) 1986-05-29 1989-10-03 James Angus Mceachern Synchronization of asynchronous data signals
US4764941A (en) 1987-05-22 1988-08-16 American Telephone And Telegraph Company, At&T Bell Laboratories Digital frame synchronizer
US4791652A (en) 1987-06-04 1988-12-13 Northern Telecom Limited Synchronization of asynchronous data signals
US4862485A (en) 1987-10-14 1989-08-29 National Semiconductor Corporation Quotient phase-shift processor for digital phase-locked-loops
GB2229874B (en) 1989-02-04 1992-09-16 Plessey Co Plc Improvements relating to communication systems
US4928275A (en) 1989-05-26 1990-05-22 Northern Telecom Limited Synchronization of asynchronous data signals
CA1326719C (en) 1989-05-30 1994-02-01 Thomas E. Moore Ds3 to 28 vt1.5 sonet interface circuit
US5359605A (en) 1989-06-22 1994-10-25 U.S. Philips Corporation Circuit arrangement for adjusting the bit rates of two signals
DE3922897A1 (en) 1989-07-12 1991-01-17 Philips Patentverwaltung PLUG DECISION CIRCUIT FOR A BITRATE ADJUSTMENT ARRANGEMENT
DE3942883A1 (en) 1989-12-23 1991-06-27 Philips Patentverwaltung BITRATE ADJUSTMENT CIRCUIT
DE3942885A1 (en) 1989-12-23 1991-06-27 Philips Patentverwaltung BITRATE ADJUSTMENT CIRCUIT
DE4013317A1 (en) 1990-04-26 1990-08-23 Ant Nachrichtentech STAMPING METHOD FOR REDUCING THE WAITING PERIOD AND ARRANGEMENT FOR IMPLEMENTING THE METHOD
US5111485A (en) 1990-05-18 1992-05-05 Northern Telecom Limited Method of and circuit for synchronizing data
US5276688A (en) 1990-06-09 1994-01-04 U.S. Philips Corporation Circuit arrangement for bit rate adjustment
US5052025A (en) 1990-08-24 1991-09-24 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer
DE4027968A1 (en) 1990-09-04 1992-03-05 Philips Patentverwaltung CIRCUIT ARRANGEMENT FOR BITRATE ADJUSTMENT OF TWO DIGITAL SIGNALS
DE4027967A1 (en) 1990-09-04 1992-03-05 Philips Patentverwaltung PLUG DECISION CIRCUIT FOR A BITRATE ADJUSTMENT ARRANGEMENT
DE4035438A1 (en) 1990-11-08 1992-05-14 Philips Patentverwaltung CIRCUIT ARRANGEMENT FOR REMOVING STOPBITS
DE4101270A1 (en) 1991-01-17 1992-07-23 Siemens Ag METHOD FOR TRANSMITTING DIGITAL SIGNALS
DE4108429A1 (en) 1991-03-15 1992-09-17 Philips Patentverwaltung TRANSMISSION SYSTEM FOR THE DIGITAL SYNCHRONOUS HIERARCHY
DE4110933A1 (en) 1991-04-04 1992-10-08 Philips Patentverwaltung TRANSMISSION SYSTEM FOR THE SYNCHRONOUS DIGITAL HIERACHIE
US5319680A (en) 1991-09-03 1994-06-07 The Whitaker Corporation Phase locked loop synchronization system for use in data communications
US5268935A (en) 1991-12-20 1993-12-07 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer
US5604768A (en) 1992-01-09 1997-02-18 Cellnet Data Systems, Inc. Frequency synchronized bidirectional radio system
JPH05199199A (en) 1992-01-20 1993-08-06 Fujitsu Ltd Stuff synchronization control system
JPH0677823A (en) 1992-08-24 1994-03-18 Oki Electric Ind Co Ltd Frequency synthesizer
JP3066690B2 (en) 1993-09-20 2000-07-17 富士通株式会社 Phase-locked oscillation circuit
FR2711435B1 (en) 1993-10-20 1995-12-29 Cit Alcatel Device to justify a digital train at regular intervals.
DE4339586B4 (en) 1993-11-20 2006-04-13 Philips Intellectual Property & Standards Gmbh transmission system
US5539785A (en) 1994-07-27 1996-07-23 Adtran Jitter/wander reduction circuit for pulse-stuffed, synchronized digital communications
JP2616731B2 (en) 1994-12-27 1997-06-04 日本電気株式会社 Transmission signal processing circuit
US5761619A (en) 1995-03-23 1998-06-02 Telefoanktiebolaget Lm Ericsson Distributed telecommunications system
US5619506A (en) 1995-04-27 1997-04-08 Adtran, Inc. Method and apparatus for reducing waiting time jitter in pulse stuffing synchronized digital communications
US5680422A (en) 1995-04-27 1997-10-21 Adtran Method and apparatus for reducing waiting time jitter in pulse stuffing synchronized digital communications
US6307868B1 (en) 1995-08-25 2001-10-23 Terayon Communication Systems, Inc. Apparatus and method for SCDMA digital data transmission using orthogonal codes and a head end modem with no tracking loops
US5563891A (en) 1995-09-05 1996-10-08 Industrial Technology Research Institute Waiting time jitter reduction by synchronizer stuffing threshold modulation
US6157810A (en) 1996-04-19 2000-12-05 Lgc Wireless, Inc Distribution of radio-frequency signals through low bandwidth infrastructures
US5983070A (en) 1996-04-19 1999-11-09 Lgc Wireless, Inc. Method and system providing increased antenna functionality in a RF distribution system
US5889781A (en) 1996-06-11 1999-03-30 Vlsi Technology Asynchronous timing generator
US6266385B1 (en) 1997-12-23 2001-07-24 Wireless Facilities, Inc. Elastic store for wireless communication systems
GB9723189D0 (en) 1997-11-03 1998-01-07 Wireless Systems Int Ltd Apparatus for and method of synchronising oscillators within a data communication system
GB2331643A (en) 1997-11-22 1999-05-26 Motorola Inc Local oscillator arrangement
US6111712A (en) * 1998-03-06 2000-08-29 Cirrus Logic, Inc. Method to improve the jitter of high frequency phase locked loops used in read channels
US6229863B1 (en) 1998-11-02 2001-05-08 Adc Telecommunications, Inc. Reducing waiting time jitter
US6542754B1 (en) 1999-05-12 2003-04-01 Cisco Systems, Inc. Synchronizing clock signals in wireless networks
US6501942B1 (en) 1999-10-29 2002-12-31 Qualcomm, Incorporated In-building radio-frequency coverage
CA2442597C (en) 2000-03-27 2011-11-01 Transcept Opencell, Inc. Multi-protocol distributed wireless system architecture
AU7360301A (en) 2000-06-16 2002-01-02 Qualcomm Inc Improved diversity coverage
US6704545B1 (en) 2000-07-19 2004-03-09 Adc Telecommunications, Inc. Point-to-multipoint digital radio frequency transport
US6316974B1 (en) * 2000-08-26 2001-11-13 Rgb Systems, Inc. Method and apparatus for vertically locking input and output signals
JP2003152694A (en) 2001-11-14 2003-05-23 Mitsubishi Electric Corp Data/clock reproducing device
KR100487234B1 (en) * 2002-07-02 2005-05-03 삼성전자주식회사 Base station system for mobile telecommunication system
US7664214B2 (en) 2002-09-24 2010-02-16 Standard Microsystems Corporation System and method for transferring data among transceivers substantially void of data dependent jitter
CN2595091Y (en) * 2002-12-11 2003-12-24 上海贝岭股份有限公司 Digital vibrating attenuator circuit by applied digital phase-locking loop
CN101422005B (en) * 2003-04-30 2013-04-03 光波体系股份有限公司 High bandwidth data transport system
US6891417B2 (en) * 2003-07-02 2005-05-10 Intel Corporation Circuits and methods for alignment of signals in integrated circuits
US7042259B2 (en) * 2004-03-31 2006-05-09 Intel Corporation Adaptive frequency clock generation system
EP1783913A1 (en) * 2005-11-08 2007-05-09 Deutsche Thomson-Brandt Gmbh Switchable PLL circuit including two loops
US7961829B2 (en) * 2006-01-26 2011-06-14 Infra-Com Ltd. Low jitter clock recovery from a digital baseband data signal transmitted over a wireless medium
CN100379306C (en) 2006-02-22 2008-04-02 华为技术有限公司 Interface device for connecting dominant base and RRU
US9515843B2 (en) * 2006-06-22 2016-12-06 Broadcom Corporation Method and system for link adaptive Ethernet communications
ES2454198T3 (en) * 2006-07-07 2014-04-09 E-Blink Synchronization procedure of two electronic devices of a wireless link, particularly of a mobile telephone network and implementation system of this procedure
US7662214B1 (en) 2006-10-06 2010-02-16 Mark Wickham Disposable absorbent liner for use with refrigerator drawers and associated method
WO2008064027A2 (en) 2006-11-13 2008-05-29 Keystone Semiconductor, Inc. Fast locking feedback control loop
US7983368B2 (en) * 2006-12-11 2011-07-19 International Business Machines Corporation Systems and arrangements for clock and data recovery in communications
US20080170469A1 (en) 2007-01-16 2008-07-17 Aram Systems, Ltd. Stabilizing remote clocks in a network
US8737454B2 (en) 2007-01-25 2014-05-27 Adc Telecommunications, Inc. Modular wireless communications platform
CN101098328B (en) * 2007-06-29 2010-06-02 中兴通讯股份有限公司 Base band and RF system synchronization and time delay compensation process
WO2009053910A2 (en) 2007-10-22 2009-04-30 Mobileaccess Networks Ltd. Communication system using low bandwidth wires
US8205338B2 (en) 2009-08-20 2012-06-26 Eastman Kodak Company Method of making a multi-lobed nozzle
US8681917B2 (en) 2010-03-31 2014-03-25 Andrew Llc Synchronous transfer of streaming data in a distributed antenna system

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9509487B2 (en) 2010-03-31 2016-11-29 Commscope Technologies Llc Synchronous transfer of streaming data in a distributed antenna system
US9680634B2 (en) 2010-03-31 2017-06-13 Commscope Technologies Llc Synchronous transfer of streaming data in a distributed antenna system
US10027469B2 (en) 2010-03-31 2018-07-17 Commscope Technologies Llc Synchronous transfer of streaming data in a distributed antenna system
US10461919B2 (en) 2010-03-31 2019-10-29 Commscope Technologies Llc Synchronous transfer of streaming data in a distributed antenna system
WO2014127519A1 (en) * 2013-02-22 2014-08-28 Telefonaktiebolaget L M Ericsson(Publ) Time synchronous pluggable transceiver
US9960873B2 (en) 2013-02-22 2018-05-01 Telefonaktiebolaget Lm Ericsson (Publ) Time synchronous pluggable transceiver
CN108476415A (en) * 2016-02-03 2018-08-31 康普技术有限责任公司 Scheme is reconfigured priority-based for remote unit
WO2019125848A1 (en) * 2017-12-18 2019-06-27 Commscope Technologies Llc Synchronization and fault management in a distributed antenna system
US10805811B2 (en) 2017-12-18 2020-10-13 Commscope Technologies Llc Synchronization and fault management in a distributed antenna system
US11540149B2 (en) 2017-12-18 2022-12-27 Commscope Technologies Llc Synchronization and fault management in a distributed antenna system

Also Published As

Publication number Publication date
US10027469B2 (en) 2018-07-17
US20140177760A1 (en) 2014-06-26
EP2554015A2 (en) 2013-02-06
CN102823321A (en) 2012-12-12
BR112012024716A2 (en) 2017-07-18
US20110243291A1 (en) 2011-10-06
WO2011123635A3 (en) 2012-01-26
US8681917B2 (en) 2014-03-25
CN105530082A (en) 2016-04-27
US9077517B2 (en) 2015-07-07
US20170244541A1 (en) 2017-08-24
EP3448116A1 (en) 2019-02-27
US9509487B2 (en) 2016-11-29
KR20130009806A (en) 2013-01-23
US20150280900A1 (en) 2015-10-01
CN105530082B (en) 2018-12-18
EP2554015B2 (en) 2022-03-02
EP2554015B1 (en) 2018-10-17
KR101847631B1 (en) 2018-04-10
US20180343106A1 (en) 2018-11-29
US20160337116A1 (en) 2016-11-17
US10461919B2 (en) 2019-10-29
US9680634B2 (en) 2017-06-13
BR112012024716A8 (en) 2017-12-26
CN102823321B (en) 2016-03-16
EP3448116B1 (en) 2023-06-07

Similar Documents

Publication Publication Date Title
US10461919B2 (en) Synchronous transfer of streaming data in a distributed antenna system
US9246557B2 (en) Multiple data services over a distributed antenna system
EP3343820B1 (en) Distributing wireless communication signals over metropolitan telecommunication networks
US9219520B2 (en) Distributed antenna system using time division duplexing scheme
US9826410B2 (en) Distributed antenna system for wireless network systems
US11785564B2 (en) Communication node and communication system for performing clock synchronization
US8472578B2 (en) Radio apparatus, radio apparatus controller, and synchronization establishing method
BR112012024716B1 (en) DISTRIBUTED ANTENNA SYSTEM AND METHOD OF GENERATION OF A CLOCK SIGNAL FROM A STREAM OF CODED DATA TRANSMITTED THROUGH A COMMUNICATION MEDIA

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201180016515.5

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11713439

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 2011713439

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20127026847

Country of ref document: KR

Kind code of ref document: A

REG Reference to national code

Ref country code: BR

Ref legal event code: B01A

Ref document number: 112012024716

Country of ref document: BR

ENP Entry into the national phase

Ref document number: 112012024716

Country of ref document: BR

Kind code of ref document: A2

Effective date: 20120927