WO2011097021A3 - A read disturb free smt mram reference cell circuit - Google Patents
A read disturb free smt mram reference cell circuit Download PDFInfo
- Publication number
- WO2011097021A3 WO2011097021A3 PCT/US2011/000197 US2011000197W WO2011097021A3 WO 2011097021 A3 WO2011097021 A3 WO 2011097021A3 US 2011000197 W US2011000197 W US 2011000197W WO 2011097021 A3 WO2011097021 A3 WO 2011097021A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- smt mram
- current
- reference cell
- read
- cell circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Hall/Mr Elements (AREA)
- Mram Or Spin Memory Techniques (AREA)
Abstract
An array of SMT MRAM cells has a read reference circuit that provides a reference current that is the sum of a minimum current through a reference SMT MRAM cell programmed with a maximum resistance and a maximum current through an reference SMT MRAM cell programmed with a minimum resistance. The reference current forms an average reference voltage at the reference input of a sense amplifier for reading a data state from selected SMT MRAM cells of the array such that the reference SMT MRAM cells will not be disturbed during a read operation. The read reference circuit compensates for current mismatching in the reference current caused by a second order non matching effect.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012551977A JP5674819B2 (en) | 2010-02-04 | 2011-02-03 | Read disturb-free SMT-MRAM reference cell circuit |
EP11740139.8A EP2532004B1 (en) | 2010-02-04 | 2011-02-03 | A read disturb free smt mram reference cell circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/658,228 US8274819B2 (en) | 2010-02-04 | 2010-02-04 | Read disturb free SMT MRAM reference cell circuit |
US12/658,228 | 2010-02-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2011097021A2 WO2011097021A2 (en) | 2011-08-11 |
WO2011097021A3 true WO2011097021A3 (en) | 2014-03-27 |
Family
ID=44341539
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2011/000197 WO2011097021A2 (en) | 2010-02-04 | 2011-02-03 | A read disturb free smt mram reference cell circuit |
Country Status (4)
Country | Link |
---|---|
US (1) | US8274819B2 (en) |
EP (1) | EP2532004B1 (en) |
JP (1) | JP5674819B2 (en) |
WO (1) | WO2011097021A2 (en) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8693273B2 (en) * | 2012-01-06 | 2014-04-08 | Headway Technologies, Inc. | Reference averaging for MRAM sense amplifiers |
KR20130093394A (en) | 2012-02-14 | 2013-08-22 | 삼성전자주식회사 | Resistive memory device performing write operation using multi-mode switching current, memory system including the same, and method of writing data in a resistive memory device |
US9030906B2 (en) | 2012-06-06 | 2015-05-12 | Intel Corporation | Isolating, at least in part, local row or column circuitry of memory cell before establishing voltage differential to permit reading of cell |
KR102056853B1 (en) | 2013-01-18 | 2020-01-22 | 삼성전자주식회사 | Resistive memory device and control method thereof |
US9281039B2 (en) | 2013-07-30 | 2016-03-08 | Qualcomm Incorporated | System and method to provide a reference cell using magnetic tunnel junction cells |
US9153307B2 (en) | 2013-09-09 | 2015-10-06 | Qualcomm Incorporated | System and method to provide a reference cell |
KR102189824B1 (en) | 2014-08-04 | 2020-12-11 | 삼성전자주식회사 | Unit array of memory device, memory device and memory system including the same |
US9613691B2 (en) | 2015-03-27 | 2017-04-04 | Intel Corporation | Apparatus and method for drift cancellation in a memory |
US9824767B1 (en) | 2016-06-29 | 2017-11-21 | Intel Corporation | Methods and apparatus to reduce threshold voltage drift |
US10020040B2 (en) | 2016-09-13 | 2018-07-10 | Toshiba Memory Corporation | Semiconductor memory device |
KR102532204B1 (en) * | 2017-09-15 | 2023-05-16 | 삼성전자 주식회사 | Resistive memory device including reference cell and operating method thereof |
KR102510497B1 (en) * | 2018-09-17 | 2023-03-16 | 삼성전자주식회사 | Memory device for reducing leakage current |
US11031059B2 (en) * | 2019-02-21 | 2021-06-08 | Sandisk Technologies Llc | Magnetic random-access memory with selector voltage compensation |
JP6819843B1 (en) * | 2020-03-05 | 2021-01-27 | Tdk株式会社 | How to control magnetic recording arrays, neuromorphic devices and magnetic recording arrays |
JP2022044399A (en) * | 2020-09-07 | 2022-03-17 | キオクシア株式会社 | Magnetic memory |
KR20220139507A (en) * | 2021-04-07 | 2022-10-17 | 삼성전자주식회사 | Memory device which generates optimal read current according to size of memory cell |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070223150A1 (en) * | 2006-03-27 | 2007-09-27 | Kabushiki Kaisha Toshiba | Magnetoresistive effect element, magnetic head, and magnetic disk apparatus |
US20090135651A1 (en) * | 2006-07-10 | 2009-05-28 | Matsushita Electric Industrial Co., Ltd. | Current or voltage measurement circuit, sense circuit, semiconductor non-volatile memory, and differential amplifier |
US20090251951A1 (en) * | 2008-03-27 | 2009-10-08 | Masatoshi Yoshikawa | Magnetoresistive element and magnetic random access memory |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6791880B1 (en) | 2003-05-06 | 2004-09-14 | Fasl, Llc | Non-volatile memory read circuit with end of life simulation |
US6985383B2 (en) * | 2003-10-20 | 2006-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reference generator for multilevel nonlinear resistivity memory storage elements |
KR100528341B1 (en) * | 2003-12-30 | 2005-11-15 | 삼성전자주식회사 | Magnetic random access memory and method of reading data from the same |
US7576956B2 (en) * | 2004-07-26 | 2009-08-18 | Grandis Inc. | Magnetic tunnel junction having diffusion stop layer |
US7239537B2 (en) * | 2005-01-12 | 2007-07-03 | International Business Machines Corporation | Method and apparatus for current sense amplifier calibration in MRAM devices |
US7272034B1 (en) * | 2005-08-31 | 2007-09-18 | Grandis, Inc. | Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells |
US7405988B2 (en) | 2005-09-26 | 2008-07-29 | Silicon Storage Technology, Inc. | Method and apparatus for systematic and random variation and mismatch compensation for multilevel flash memory operation |
JP4987616B2 (en) * | 2006-08-31 | 2012-07-25 | 株式会社東芝 | Magnetic random access memory and resistive random access memory |
US8004880B2 (en) * | 2007-03-06 | 2011-08-23 | Qualcomm Incorporated | Read disturb reduction circuit for spin transfer torque magnetoresistive random access memory |
JP5135609B2 (en) * | 2008-03-27 | 2013-02-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
2010
- 2010-02-04 US US12/658,228 patent/US8274819B2/en active Active
-
2011
- 2011-02-03 JP JP2012551977A patent/JP5674819B2/en active Active
- 2011-02-03 EP EP11740139.8A patent/EP2532004B1/en active Active
- 2011-02-03 WO PCT/US2011/000197 patent/WO2011097021A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070223150A1 (en) * | 2006-03-27 | 2007-09-27 | Kabushiki Kaisha Toshiba | Magnetoresistive effect element, magnetic head, and magnetic disk apparatus |
US20090135651A1 (en) * | 2006-07-10 | 2009-05-28 | Matsushita Electric Industrial Co., Ltd. | Current or voltage measurement circuit, sense circuit, semiconductor non-volatile memory, and differential amplifier |
US20090251951A1 (en) * | 2008-03-27 | 2009-10-08 | Masatoshi Yoshikawa | Magnetoresistive element and magnetic random access memory |
Also Published As
Publication number | Publication date |
---|---|
US20110188305A1 (en) | 2011-08-04 |
US8274819B2 (en) | 2012-09-25 |
EP2532004B1 (en) | 2021-10-27 |
WO2011097021A2 (en) | 2011-08-11 |
EP2532004A2 (en) | 2012-12-12 |
JP5674819B2 (en) | 2015-02-25 |
JP2013532344A (en) | 2013-08-15 |
EP2532004A4 (en) | 2017-05-31 |
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