WO2011051786A2 - Interactive method and apparatus for detecting texted metal short circuits - Google Patents
Interactive method and apparatus for detecting texted metal short circuits Download PDFInfo
- Publication number
- WO2011051786A2 WO2011051786A2 PCT/IB2010/002740 IB2010002740W WO2011051786A2 WO 2011051786 A2 WO2011051786 A2 WO 2011051786A2 IB 2010002740 W IB2010002740 W IB 2010002740W WO 2011051786 A2 WO2011051786 A2 WO 2011051786A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- test result
- texted
- circuit design
- design
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
Definitions
- the present invention is related to a test method and device in circuit design, particularly to a method and device to test the texted metal short circuit in the circuit design.
- Physical design verification of an IC circuit is an important link in the flow process of circuit design.
- the step of physical design verification is one wherein whether an IC circuit is in conformity with all flow process rules will be confirmed.
- the geometric design rule is to check the relative position or syntax of the final layout of a circuit to ensure that said circuit can be manufactured correctly. However, the functional correctness test will be accomplished with the help of a simulator and verifier capable of maneuvering circuit action and behavior.
- the electrical rule check or design rule check it is for processing layout syntax and complicated behavior analysis.
- the electrical rule is a rule concerning the relevant attribute of a circuit, and it can be determined by the geometric and connecting relationship.
- testing of the position of the texted metal short circuit is an important subject.
- the test method using existing tools lists all polygons in a short circuit path, and then the user needs to check the listed polygons one by one. After said short circuit path check is completed, the verification tool is used again so as to get another short circuit path, and then the user once again checks the listed polygons one by one. The procedure is done repeatedly until the work of testing all short circuit positions is complete, thus costing too much time. Therefore, the industry of electronic design automation needs to have an efficient method and device to test the position of the texted metal short circuit, so as to reduce the time range for the design of the circuit.
- Provided in the present invention are methods and devices to test a texted metal short circuit and for detecting character labeled metal short circuit positions; to execute a verification program on said circuit design based on said specific check rule so as to obtain a first test result, wherein said first test result comprises all short circuit paths in said circuit design; and then based on said first rest result, to execute a pseudo-texted program using a fuzzy algorithm so as to obtain a second test result.
- the user can confirms the metal short position in sequence in light of said first test result and said second test result respectively, so as to speed up testing of the position of the texted metal short circuit in said circuit design.
- a method to test the texted metal short circuit as disclosed in an example of the present invention which comprises the following steps: To input a circuit design file, wherein said circuit design file comprises the data of the layout pattern of said circuit design, and said circuit design file format is a generic data stream format; to input a set of design rules; to select a specific check rule based on said set of design rules, wherein said specific check rule is for testing the texted metal short circuit in said circuit design; to execute a verification program on said circuit design based on said specific check rule so as to obtain a first test result, wherein said first test result comprises all short circuit paths in said circuit design; and based on said first rest result, to execute a pseudo-texted program using a fuzzy algorithm so as to obtain a second test result.
- Said first test result is a cell short test result, or a hierarchical short test result, or it comprises a cell test result and a hierarchical short test result at the same time, but the present invention is not to be limited by that.
- Said first test result also comprises information of the position of the texted metal short circuit.
- the verification program mentioned above is a design rule check program.
- the pseudo-texted program as mentioned above is a VDD and VSS texted program, but the present invention is not to be limited by that.
- Said input module is constructed to input a circuit design file and a set of design rules, wherein said circuit design file comprises data of the layout pattern, the file format of said circuit design is a generic data stream format, but the present invention is not to be limited by that.
- Said selecting cell is constructed to select a specific check rule based on said set of design rules.
- Said specific check rule is for testing at least one texted metal short circuit in said circuit design, but the present invention is not to be limited by that.
- Said executing cell is constructed to execute a verification program on said circuit design based on said specific check rule and to execute a pseudo-texted program using a fuzzy algorithm based on the result of said verification program.
- Said verification program is a design rule check program.
- Said pseudo-texted program is a VDD and VSS texted program, but the present invention is not to be limited by that.
- Said generating cell is constructed to generate a test result or a status to be confirmed, based on the result of said verification program or the result of said pseudo-texted program.
- Said test result is a cell short test result, or a hierarchical short test result, or it comprises a cell test result and a hierarchical short test result at the same time, but the present invention is not to be limited by that.
- Said test result also comprises information of the position of the texted metal short circuit.
- Said modifying cell is constructed to modify said circuit design based on said test result.
- Said confirming cell is constructed to obtain the information of confirmation of said status to be confirmed provided by a user.
- Said updating cell is constructed to update said test result or said status to be confirmed based on a modification result of said modifying cell.
- said display cell is constructed to display said test result or said status to be confirmed.
- Figure 1 is a flow chart of an example of the present invention of a method to test a texted metal short circuit
- FIG. 2 is a detailed step of Step 102
- FIG. 3 is a detailed step of Step 103;
- Figure 4 is a block view of another example of the present invention of a device to test a texted metal short circuit
- Figure 5 shows the unit short circuit position detecting window of an application example of the present invention.
- Figure 1 is a flow chart showing an example of the present invention of a method to test a texted metal short circuit.
- the flow process of the method to test a texted metal short circuit is illustrated below in association with Figure 1-3.
- Step 101 the flow process of the present example begins.
- Step 102 a circuit input by a user to be tested is verified.
- Step 103 this program to test the texted metal short circuit is executed in accordance with the verification result in Step 102.
- Step 104 the flow process of the present example ends.
- the file of a circuit design is input, wherein said circuit design file comprises data of the layout pattern, and the file format of said circuit design is a generic data stream format, but the present invention is not to be limited by that.
- Said circuit design for example, is an IC design.
- Step 202 a set of design rules are input.
- a specific check rule or examination rule is selected based on said set of design rules. Based on an example of the present invention, said specific check rule is for testing the texted metal short circuit in said circuit design. Said specific check rule will later be applied to, for example, a design rule check program.
- the texted metal short circuit in said circuit design is the texted metal short circuit for power distribution, input cell or output cell in said circuit design, but the present invention is not to be limited by that.
- a verification program or authentication program is executed on said circuit based on said specific check rule. Said verification program is a design rule check program.
- a test result or short circuit path detection result is generated based on the result of execution of said verification program, wherein said test result comprises all short paths in said circuit design.
- Said test result is a cell short test result, or hierarchical short test result, or comprises a cell short test result and a hierarchical short test result at the same time, but the present invention is not to be limited by that.
- These test results comprise information of the position of the texted metal short circuit.
- Step 301 the type of the short circuit is determined based on the test result from Step 205. If said test result is a cell short circuit, then Steps 302 - 304 are executed to complete the test of all texted metal short circuits. If said test result is a hierarchical short circuit, then Steps 306 - 31 1 are executed to complete the testing of all texted metal short circuits. If said test result comprises a cell short circuit and a hierarchical short circuit at the same time, then it needs to execute Steps 302 - 304 and Step 306 - 31 1 to complete the testing of all texted metal short circuits.
- said test result comprises a cell short circuit and a hierarchical short circuit at the same time.
- the circuit design is to be modified in Step 302 in sequence in light of the cell short circuits in the test result.
- Step 303 it is to determine whether the test of all cell short circuits is completed. If it is, then in Step 305, the testing of cell short circuits is ended. If it is not, then said circuit design is updated and said test result is updated in Step 304.
- Step 306 For a short circuit of the hierarchical short type, in Step 306, a pseudo-texted program is executed using the fuzzy algorithm in accordance with the hierarchical short circuit in the test result [sic], and a test result using the fuzzy algorithm is obtained.
- Step 307 it is determined whether there is something to be confirmed. For example, two polygons connected to each other or a two-dimensional pattern are texted differently. In this case, the user needs to confirm if the connection is correct. Therefore, if it needs to be confirmed by the user, then whether the connection is correct is to be confirmed in Step 308. After that, in Step 31 1, said circuit design is updated and said test result obtained using the fuzzy algorithm is updated. If the determination in Step 307 does not need to be confirmed by the user, then in Step 309, the circuit design is modified in light of the test result obtained using the fuzzy algorithm.
- Step 310 whether the testing of all texted metal short circuits has been completed is determined. If it is, then in Step 312, the testing of hierarchical short circuits is ended. If it is not, then said circuit design is updated and said test result is updated in Step 31 1.
- FIG. 4 is a block view showing another example of the device to test a texted metal short circuit.
- the device to test the texted metal short circuit 400 comprises an input module 401, a selecting cell 402, an executing cell 403, a generating cell 404, a modifying cell 405, a confirming cell 406, an updating cell 407, and a display cell 408.
- Said input module 401 is constructed to input a circuit design file and a set of design rules, wherein said circuit design file comprises data of the layout pattern, and the file format of said circuit design is a generic data stream format, but the present invention is not to be limited by that.
- Said circuit design for example, is an IC design.
- Said selecting cell 402 is constructed to select a specific check rule based on said set of design rules.
- Said specific check rule is for testing at least one texted metal short circuit in said circuit design, but the present invention is not to be limited by that.
- Said at least one texted metal short circuit in said circuit design is the texted metal short circuit for power distribution, input cell, or output cell in said circuit design, but the present invention is not to be limited by that.
- Said executing cell 403 is constructed to execute a verification program on said circuit design based on said specific check rule and to execute a pseudo-texted program using a fuzzy algorithm based on the result of said verification program.
- Said verification -program is a design rule check program.
- Said pseudo-texted program is a VDD and VSS texted program, but the present invention is not to be limited by that.
- Said generating cell 404 is constructed to generate a test result or a prompt status to be confirmed, based on the result of said verification program or the result of said pseudo-texted program.
- Said test result is a cell short test result, or a hierarchical short test result, or it comprises a cell test result and a hierarchical short test result at the same time, but the present invention is not to be limited by that.
- Said test result also comprises information of the position of the texted metal short circuit.
- Said modifying cell 405 is constructed to modify said circuit design based on said test result.
- Said confirming cell 406 is constructed to obtain the information of confirmation of said status to be confirmed provided by a user.
- Said updating cell 407 is constructed to update said test result or said status to be confirmed based on a modification result of said modifying cell.
- said display cell 408 is constructed to display said test result or said status to be confirmed.
- Figure 5 shows an example of short circuit position detecting window 500.
- the related information of the user regarding a unit short circuit path is provided based on that unit short circuit path and partial content of a prompt status, such as short finder window 51 , in the short circuit path detection result.
- the content of the prompt status includes, for example, shorted net information and the instruction information.
- the present invention is not limited to this.
- the shorted net information includes different kinds of polygonal information, such as patterns 501, 502, and 503. Their corresponding polygons in layout window 52 are 50 , 502', and 503', respectively.
- the user can obtain, for example, the net, unit, and hierarchy to which polygon 501' (the corresponding pattern is 501) belongs and the related coordinate information of polygon 50 ⁇ in layout window 52 from the shorted net information. Additionally, the user can obtain, for example, the fact that a short circuit is present between net test 1 and net test 2 in unit TOP from the instruction information. The user can also confirm that 503 and 503' belong to net test 1 or net test 2 based on the prompt in the instruction information. The instruction information also reminds the user of the position where the short circuit is present. The user can click on and select pattern 501, 502, or 503. As a result, the corresponding polygon in layout window 52 will be highlighted and displayed.
- An embodiment of an interactive method for detecting character labeled metal short circuit positions is characterized by including the following steps: providing a circuit design that includes the data of the layout pattern; providing a design rule group; selecting a specific examination rule based on this design rule group; executing an authentication program with respect to the circuit design based on the specific examination rule in order to obtain a first short circuit path detection result that includes all of the short circuit paths in this circuit design; and generating a first prompt status based on the first short circuit path detection result so that the user can confirm the first metal short circuit position in order to accelerate the detection of metal short circuit positions labeled with characters in this circuit design.
- the method can also include a step in which a fuzzy algorithm is used to execute a pseudo character labeling program based on the first short circuit path detection result in order to obtain a second short circuit path detection result.
- a second prompt status can abe generated based on the second short circuit path detection result so that the user can confirm the second metal short circuit position.
- a status to confirm can be generated based on the second short circuit path detection result.
- the method can also include a step in which a third short circuit path detection result is obtained based on the confirmation result provided by the user with respect to the status to confirm.
- the first short circuit path detection result, the second short circuit path detection result, and the third short circuit path detection result are unit short circuit path detection results, hierarchical short circuit path detection results, or simultaneously include unit short circuit path detection results and hierarchical short circuit path detection results.
- the method can be further characterized by the fact that the authentication program is a design rule examination program; by the fact that the pseudo character labeling program is a character program used for labeling VDD and VSS; by the fact that the file format of this circuit design is a common data stream format; by the fact that the circuit design is an integrated circuit design; and by the fact that the specific examination rule is used to detect at least one character labeled metal short circuit path in this circuit design.
- At least one character labeled metal short circuit path in the circuit design is the character labeled metal short circuit path of the power distribution, input unit or output unit in this circuit design.
- An embodiment of interactive device for detecting character labeled metal short circuit position is characterized by including an input module that is constructed to input a circuit design and a design rule group with the circuit design file including the data of the layout pattern; a selection unit that is constructed to select a specific examination rule based on the design rule group; an execution unit that is constructed to execute an authentication program with respect to the circuit design based on the specific examination rule or use a fuzzy algorithm to execute a pseudo character labeling program based on the result of the authentication program; a generation unit that is constructed to generate a short circuit path detection result based on the result of the authentication program or the result of the pseudo character labeling program; and an interaction unit that is constructed to a prompt status or a status to confirm based on the short circuit path detection result.
- the device can also include an update unit constructed to update the short circuit path detection result, the prompt status, or the status to confirm based on the reply information provided by the user with respect to the prompt status or the confirmation information provided by the user with respect to the status to confirm.
- a display unit can be included that is constructed to display the short circuit path detection result, the prompt status, or the status to confirm.
- the short circuit path detection result is a unit short circuit path detection result, a hierarchical short circuit path detection result, or simultaneously includes the unit short circuit path detection result and the hierarchical short circuit path detection result.
- the device can be characterized by the fact that the authentication program includes a design rule examination program; by the fact that the pseudo character labeling program is a character program used for labeling VDD and VSS; by the fact that the file format of this circuit design is a common data stream format; by the fact that the circuit design is an integrated circuit design; by the fact that the specific examination rule is used to detect at least one character labeled metal short circuit path in this circuit design; and by the fact that said at least one character labeled metal short circuit path in the circuit design is the character labeled metal short circuit path of the power distribution, input unit or output unit in this circuit design.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The present invention relates to a method and device to test the texted metal short circuit, and said method comprises the following steps: To input a circuit design file, wherein said circuit design file comprises the data of the layout pattern of said circuit design, the file format of said circuit design is a generic data stream format; to input a set of design rules; to select a specific check rule based on said set of design rules, wherein said specific check rule is for testing the texted metal short circuit in said circuit design; to execute a verification program [procedure] on said circuit design based on said specific check rule so as to obtain a first test result, wherein said first test result comprises all short circuit paths in said circuit design; and, based on said first test result, to execute a pseudo-texted program using fuzzy algorithm so as to obtain a second test result.
Description
INTERACTIVE METHOD AND APPARATUS FOR
DETECTING TEXTED METAL SHORT CIRCUITS
Technical Field
The present invention is related to a test method and device in circuit design, particularly to a method and device to test the texted metal short circuit in the circuit design.
Background
With continuous progress in the manufacturing technology of integrated circuits (IC), the minimum size of IC chips also keeps decreases. However, in the physical design with the tendency to reduce the chip size, it is more necessary to consider impact of manufacturability on the yield and reliability, while the problem of power loss in particular requires attention. A typical rule of treatment is to specify the ampere of the current borne by the wire [conductor] per unit width. On the other hand, limitation of the total power is also an important subject, and in terms of its extended problem of heat dissipation, for a single packaging design, it needs to have the capacity of heat dissipation before the device is damaged. A standard IC packaging is capable of dissipating a number of watts of heat. However, with the heat fin or other methods of heat dissipation, a novel packaging design has even better capacity of heat dissipation.
Physical design verification of an IC circuit is an important link in the flow process of circuit design. The step of physical design verification is one wherein whether an IC circuit is in conformity with all flow process rules will be confirmed. The geometric design rule is to check the relative position or syntax of the final layout of a circuit to ensure that said circuit can be manufactured correctly. However, the functional correctness test will be accomplished with the help of a simulator and verifier capable of maneuvering circuit action and behavior. For the electrical rule check or design rule check, it is for processing layout syntax and complicated behavior analysis. The electrical rule is a rule concerning the relevant attribute of a circuit, and it can be determined by the geometric and connecting relationship.
In the work of verification of an IC circuit design, testing of the position of the texted metal short circuit is an important subject. However, the test method using existing tools lists all polygons in a short circuit path, and then the user needs to check the listed polygons one by one. After said short circuit path check is completed, the verification tool is used again so as to get
another short circuit path, and then the user once again checks the listed polygons one by one. The procedure is done repeatedly until the work of testing all short circuit positions is complete, thus costing too much time. Therefore, the industry of electronic design automation needs to have an efficient method and device to test the position of the texted metal short circuit, so as to reduce the time range for the design of the circuit.
Summary
Provided in the present invention are methods and devices to test a texted metal short circuit and for detecting character labeled metal short circuit positions; to execute a verification program on said circuit design based on said specific check rule so as to obtain a first test result, wherein said first test result comprises all short circuit paths in said circuit design; and then based on said first rest result, to execute a pseudo-texted program using a fuzzy algorithm so as to obtain a second test result. The user can confirms the metal short position in sequence in light of said first test result and said second test result respectively, so as to speed up testing of the position of the texted metal short circuit in said circuit design.
A method to test the texted metal short circuit as disclosed in an example of the present invention, which comprises the following steps: To input a circuit design file, wherein said circuit design file comprises the data of the layout pattern of said circuit design, and said circuit design file format is a generic data stream format; to input a set of design rules; to select a specific check rule based on said set of design rules, wherein said specific check rule is for testing the texted metal short circuit in said circuit design; to execute a verification program on said circuit design based on said specific check rule so as to obtain a first test result, wherein said first test result comprises all short circuit paths in said circuit design; and based on said first rest result, to execute a pseudo-texted program using a fuzzy algorithm so as to obtain a second test result. Said first test result is a cell short test result, or a hierarchical short test result, or it comprises a cell test result and a hierarchical short test result at the same time, but the present invention is not to be limited by that. Said first test result also comprises information of the position of the texted metal short circuit. The verification program mentioned above is a design rule check program. The pseudo-texted program as mentioned above is a VDD and VSS texted program, but the present invention is not to be limited by that.
A device to test the texted metal short circuit as disclosed in an example of the present invention, which comprises an input module, a selecting cell, an executing cell, a generating cell, a modifying cell, a confirming cell, an updating cell, and a display cell. Said input module is constructed to input a circuit design file and a set of design rules, wherein said circuit design file comprises data of the layout pattern, the file format of said circuit design is a generic data stream format, but the present invention is not to be limited by that. Said selecting cell is constructed to select a specific check rule based on said set of design rules. Said specific check rule is for testing at least one texted metal short circuit in said circuit design, but the present invention is not to be limited by that. Said executing cell is constructed to execute a verification program on said circuit design based on said specific check rule and to execute a pseudo-texted program using a fuzzy algorithm based on the result of said verification program. Said verification program is a design rule check program. Said pseudo-texted program is a VDD and VSS texted program, but the present invention is not to be limited by that. Said generating cell is constructed to generate a test result or a status to be confirmed, based on the result of said verification program or the result of said pseudo-texted program. Said test result is a cell short test result, or a hierarchical short test result, or it comprises a cell test result and a hierarchical short test result at the same time, but the present invention is not to be limited by that. Said test result also comprises information of the position of the texted metal short circuit. Said modifying cell is constructed to modify said circuit design based on said test result. Said confirming cell is constructed to obtain the information of confirmation of said status to be confirmed provided by a user. Said updating cell is constructed to update said test result or said status to be confirmed based on a modification result of said modifying cell. And said display cell is constructed to display said test result or said status to be confirmed.
The technical features of the present invention have already been summarized above, for better understanding of the following detailed description of the present invention. Other technical features that constitute the object of the claims of the present invention will be described below. Regular technical personnel in the technical field to which the present invention belongs should understand that the concept and specific examples disclosed below as a basis can be easily modified or used to design another structure or manufacturing process to accomplish the same purpose of the present invention. Regular technical personnel in the technical field to which the present invention belongs should also understand that this kind of equivalent
constructs do not break away from the spirit and range of the present invention as suggested in the claims attached.
Brief Description of the Drawings
Figure 1 is a flow chart of an example of the present invention of a method to test a texted metal short circuit;
Figure 2 is a detailed step of Step 102;
Figure 3 is a detailed step of Step 103;
Figure 4 is a block view of another example of the present invention of a device to test a texted metal short circuit; and
Figure 5 shows the unit short circuit position detecting window of an application example of the present invention.
Detailed Description of Disclosed Embodiments
The direction of the present invention discussed here is a method and device to test a texted metal short circuit. For thorough understanding of the present invention, detailed steps and composition will be provided in the description below. It is obvious that the implementation of the present invention is not limited to the special details that technical personnel in circuit design are familiar with. On the other hand, the known composition or steps are not described in detail, to avoid unnecessary limitation of the present invention. A preferred example of the present invention will be described in detail below. However, besides these detailed descriptions, the present invention can also be extensively implemented in other examples, and the scope of the present invention is not limited, and is based on the claims above.
Figure 1 is a flow chart showing an example of the present invention of a method to test a texted metal short circuit. In order that regular technical personnel in the present field can implement the present invention through the present example, the flow process of the method to test a texted metal short circuit is illustrated below in association with Figure 1-3.
In Step 101, the flow process of the present example begins. In Step 102, a circuit input by a user to be tested is verified. In Step 103, this program to test the texted metal short circuit is executed in accordance with the verification result in Step 102. And in Step 104, the flow process of the present example ends.
Based on an example of the present invention, shown in Figure 2 is the detailed step of Step 102. In Step 201, the file of a circuit design is input, wherein said circuit design file comprises data of the layout pattern, and the file format of said circuit design is a generic data stream format, but the present invention is not to be limited by that. Said circuit design, for example, is an IC design. In Step 202, a set of design rules are input. In Step 203, a specific check rule or examination rule is selected based on said set of design rules. Based on an example of the present invention, said specific check rule is for testing the texted metal short circuit in said circuit design. Said specific check rule will later be applied to, for example, a design rule check program. The texted metal short circuit in said circuit design is the texted metal short circuit for power distribution, input cell or output cell in said circuit design, but the present invention is not to be limited by that. In Step 204, a verification program or authentication program is executed on said circuit based on said specific check rule. Said verification program is a design rule check program. In Step 205, a test result or short circuit path detection result is generated based on the result of execution of said verification program, wherein said test result comprises all short paths in said circuit design. Said test result is a cell short test result, or hierarchical short test result, or comprises a cell short test result and a hierarchical short test result at the same time, but the present invention is not to be limited by that. These test results comprise information of the position of the texted metal short circuit.
Based on an example of the present invention, Shown in Figure 3 is the detailed step of Step 103. In Step 301, the type of the short circuit is determined based on the test result from Step 205. If said test result is a cell short circuit, then Steps 302 - 304 are executed to complete the test of all texted metal short circuits. If said test result is a hierarchical short circuit, then Steps 306 - 31 1 are executed to complete the testing of all texted metal short circuits. If said test result comprises a cell short circuit and a hierarchical short circuit at the same time, then it needs to execute Steps 302 - 304 and Step 306 - 31 1 to complete the testing of all texted metal short circuits. Based on an example of the present invention, said test result comprises a cell short circuit and a hierarchical short circuit at the same time. For a short circuit of the cell short type, the circuit design is to be modified in Step 302 in sequence in light of the cell short circuits in the test result. In Step 303, it is to determine whether the test of all cell short circuits is completed. If it is, then in Step 305, the testing of cell short circuits is ended. If it is not, then said circuit design is updated and said test result is updated in Step 304.
For a short circuit of the hierarchical short type, in Step 306, a pseudo-texted program is executed using the fuzzy algorithm in accordance with the hierarchical short circuit in the test result [sic], and a test result using the fuzzy algorithm is obtained. Said pseudo-texted program is a VDD and VSS texted program, but the present invention is not to be limited by that. In Step 307, it is determined whether there is something to be confirmed. For example, two polygons connected to each other or a two-dimensional pattern are texted differently. In this case, the user needs to confirm if the connection is correct. Therefore, if it needs to be confirmed by the user, then whether the connection is correct is to be confirmed in Step 308. After that, in Step 31 1, said circuit design is updated and said test result obtained using the fuzzy algorithm is updated. If the determination in Step 307 does not need to be confirmed by the user, then in Step 309, the circuit design is modified in light of the test result obtained using the fuzzy algorithm. In Step 310, whether the testing of all texted metal short circuits has been completed is determined. If it is, then in Step 312, the testing of hierarchical short circuits is ended. If it is not, then said circuit design is updated and said test result is updated in Step 31 1.
Figure 4 is a block view showing another example of the device to test a texted metal short circuit. The device to test the texted metal short circuit 400 comprises an input module 401, a selecting cell 402, an executing cell 403, a generating cell 404, a modifying cell 405, a confirming cell 406, an updating cell 407, and a display cell 408. Said input module 401 is constructed to input a circuit design file and a set of design rules, wherein said circuit design file comprises data of the layout pattern, and the file format of said circuit design is a generic data stream format, but the present invention is not to be limited by that. Said circuit design, for example, is an IC design. Said selecting cell 402 is constructed to select a specific check rule based on said set of design rules. Said specific check rule is for testing at least one texted metal short circuit in said circuit design, but the present invention is not to be limited by that. Said at least one texted metal short circuit in said circuit design is the texted metal short circuit for power distribution, input cell, or output cell in said circuit design, but the present invention is not to be limited by that. Said executing cell 403 is constructed to execute a verification program on said circuit design based on said specific check rule and to execute a pseudo-texted program using a fuzzy algorithm based on the result of said verification program. Said verification -program is a design rule check program. Said pseudo-texted program is a VDD and VSS texted program, but the present invention is not to be limited by that. Said generating cell 404 is
constructed to generate a test result or a prompt status to be confirmed, based on the result of said verification program or the result of said pseudo-texted program. Said test result is a cell short test result, or a hierarchical short test result, or it comprises a cell test result and a hierarchical short test result at the same time, but the present invention is not to be limited by that. Said test result also comprises information of the position of the texted metal short circuit. Said modifying cell 405 is constructed to modify said circuit design based on said test result. Said confirming cell 406 is constructed to obtain the information of confirmation of said status to be confirmed provided by a user. Said updating cell 407 is constructed to update said test result or said status to be confirmed based on a modification result of said modifying cell. And said display cell 408 is constructed to display said test result or said status to be confirmed.
Figure 5 shows an example of short circuit position detecting window 500. The related information of the user regarding a unit short circuit path is provided based on that unit short circuit path and partial content of a prompt status, such as short finder window 51 , in the short circuit path detection result. The content of the prompt status includes, for example, shorted net information and the instruction information. The present invention, however, is not limited to this. The shorted net information includes different kinds of polygonal information, such as patterns 501, 502, and 503. Their corresponding polygons in layout window 52 are 50 , 502', and 503', respectively. The user can obtain, for example, the net, unit, and hierarchy to which polygon 501' (the corresponding pattern is 501) belongs and the related coordinate information of polygon 50 Γ in layout window 52 from the shorted net information. Additionally, the user can obtain, for example, the fact that a short circuit is present between net test 1 and net test 2 in unit TOP from the instruction information. The user can also confirm that 503 and 503' belong to net test 1 or net test 2 based on the prompt in the instruction information. The instruction information also reminds the user of the position where the short circuit is present. The user can click on and select pattern 501, 502, or 503. As a result, the corresponding polygon in layout window 52 will be highlighted and displayed.
An embodiment of an interactive method for detecting character labeled metal short circuit positions is characterized by including the following steps: providing a circuit design that includes the data of the layout pattern; providing a design rule group; selecting a specific examination rule based on this design rule group; executing an authentication program with respect to the circuit design based on the specific examination rule in order to obtain a first short
circuit path detection result that includes all of the short circuit paths in this circuit design; and generating a first prompt status based on the first short circuit path detection result so that the user can confirm the first metal short circuit position in order to accelerate the detection of metal short circuit positions labeled with characters in this circuit design.
The method can also include a step in which a fuzzy algorithm is used to execute a pseudo character labeling program based on the first short circuit path detection result in order to obtain a second short circuit path detection result. A second prompt status can abe generated based on the second short circuit path detection result so that the user can confirm the second metal short circuit position. A status to confirm can be generated based on the second short circuit path detection result.
The method can also include a step in which a third short circuit path detection result is obtained based on the confirmation result provided by the user with respect to the status to confirm. The first short circuit path detection result, the second short circuit path detection result, and the third short circuit path detection result are unit short circuit path detection results, hierarchical short circuit path detection results, or simultaneously include unit short circuit path detection results and hierarchical short circuit path detection results.
The method can be further characterized by the fact that the authentication program is a design rule examination program; by the fact that the pseudo character labeling program is a character program used for labeling VDD and VSS; by the fact that the file format of this circuit design is a common data stream format; by the fact that the circuit design is an integrated circuit design; and by the fact that the specific examination rule is used to detect at least one character labeled metal short circuit path in this circuit design. At least one character labeled metal short circuit path in the circuit design is the character labeled metal short circuit path of the power distribution, input unit or output unit in this circuit design.
An embodiment of interactive device for detecting character labeled metal short circuit position is characterized by including an input module that is constructed to input a circuit design and a design rule group with the circuit design file including the data of the layout pattern; a selection unit that is constructed to select a specific examination rule based on the design rule group; an execution unit that is constructed to execute an authentication program with respect to the circuit design based on the specific examination rule or use a fuzzy algorithm to execute a pseudo character labeling program based on the result of the authentication program; a
generation unit that is constructed to generate a short circuit path detection result based on the result of the authentication program or the result of the pseudo character labeling program; and an interaction unit that is constructed to a prompt status or a status to confirm based on the short circuit path detection result. The device can also include an update unit constructed to update the short circuit path detection result, the prompt status, or the status to confirm based on the reply information provided by the user with respect to the prompt status or the confirmation information provided by the user with respect to the status to confirm.
A display unit can be included that is constructed to display the short circuit path detection result, the prompt status, or the status to confirm. The short circuit path detection result is a unit short circuit path detection result, a hierarchical short circuit path detection result, or simultaneously includes the unit short circuit path detection result and the hierarchical short circuit path detection result.
The device can be characterized by the fact that the authentication program includes a design rule examination program; by the fact that the pseudo character labeling program is a character program used for labeling VDD and VSS; by the fact that the file format of this circuit design is a common data stream format; by the fact that the circuit design is an integrated circuit design; by the fact that the specific examination rule is used to detect at least one character labeled metal short circuit path in this circuit design; and by the fact that said at least one character labeled metal short circuit path in the circuit design is the character labeled metal short circuit path of the power distribution, input unit or output unit in this circuit design.
The technical content and technical features of the present invention have been disclosed as above, but those who are familiar with this technology, based on the instruction and disclosure of the present invention, can still make various replacements and modifications without deviating from the spirit of the present invention. Therefore, the scope of the claims of the present invention should not be restricted to what has been disclosed in the examples, but should include various replacements and modifications which do not deviate from the present invention, and are covered by the claims above.
Claims
1. A method to test the texted metal short circuit, which is characterized by that it comprises the following steps:
to input a circuit design file, wherein said circuit design file comprises the data of the layout pattern of said circuit design;
to input a set of design rules;
to select a specific check rule based on said set of design rules;
to execute a verification program on said circuit design based on said specific check rule so as to obtain a first test result, wherein said first test result comprises all short circuit paths in said circuit design; and
based on said first rest result, to execute a pseudo-texted program using a fuzzy algorithm so as to obtain a second test result.
2. A method as described in Claim 1, which also comprises a first status to be confirmed which is generated based on said second test result.
3. A method as described in Claim 2, which also comprises modification of said circuit design based on said first test result and obtaining a third test result.
4. A method as described in Claim 3, which also comprises obtaining a fourth test result based on the result of confirmation of said status to be confirmed.
5. A method as described in Claim 4, wherein said first test result, said second test result, said third test result, and said fourth test result are cell short test results, or hierarchical short test results, or comprise a cell short test result and a hierarchical short test result at the same time.
6. A method as described in Claim 4, wherein said first test result, said second test result, said third test result, and said fourth test result comprise information of the position of the texted metal short circuit.
7. A method as described in Claim 1, which is characterized by the fact that said verification program comprises execution of a design rule check program.
8. A method as described in Claim 1, which is characterized by the fact that said pseudo- texted program is a VDD and VSS texted program.
9. A method as described in Claim 1, which is characterized by the fact that wherein the file format of said circuit design is a generic data stream format.
10. A method as described in Claim 1, which is characterized by the fact that wherein said circuit design is an IC design.
1 1. A method as described in Claim 1 , which is characterized by the fact that wherein said specific check rule is for testing at least one texted metal short circuit in said circuit design.
12. A method as described in Claim 1, which is characterized by the fact that wherein said at least one texted metal short circuit in said circuit design is the texted metal short circuit for power distribution, input cell or output cell in said circuit design.
13. A device to test the texted metal short circuit, which is characterized in that it comprises:
an input module, constructed to input a circuit design file and a set of design rules, wherein said circuit design file comprises data of the layout pattern;
a selecting cell, constructed to select a specific check rule based on said set of design rules;
an executing cell, constructed to execute a verification program on said circuit design based on said specific check rule, and to execute a pseudo-texted program using a fuzzy algorithm based on the result of said verification program; and
a generating cell, constructed to generate a test result or a status to be confirmed, based on the result of said verification program or the result of said pseudo-texted program.
14. A device as described in Claim 13, which also comprises a modifying cell, constructed to modify said circuit design based on said test result.
15. A device as described in Claim 14, which also comprises a confirming cell, constructed to obtain the information of confirmation of said status to be confirmed provided by a user.
16. A device as described in Claim 15, which also comprises an updating cell, constructed to update said test result or said status to be confirmed based on a modification result of said modifying cell.
17. A device as described in Claim 16, which also comprises a display cell, constructed to display said test result or said status to be confirmed.
18. A device as described in Claim 13, which is characterized by the fact that wherein said test result is a cell short test result, or hierarchical short test results, or comprise a cell short test result and a hierarchical short test result at the same time.
19. A device as described in Claim 13, which is characterized by the fact that wherein said test result comprises the position information of the texted metal short circuit.
20. A device as described in Claim 13, which is characterized by the fact that wherein said verification program is a design rule check program.
21. A device as described in Claim 13, which is characterized by the fact that wherein said pseudo-texted program is a VDD and VSS texted program.
22. A device as described in Claim 13, which is characterized by the fact that wherein the file format of said circuit design is a generic data stream format.
23. A device as described in Claim 13, which is characterized by the fact that wherein said circuit design is an IC design.
24. A device as described in Claim 13, which is characterized by the fact that wherein said specific check rule is for testing at least one texted metal short circuit in said circuit design.
25. A device as described in Claim 13, which is characterized in that said at least one texted metal short circuit in said circuit design is the texted metal short circuit for power distribution, input cell or output cell in said circuit design.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/504,439 US20120221991A1 (en) | 2009-10-30 | 2010-10-27 | Interactive Method and Apparatus for Detecting Texted Metal Short Circuits |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910209626.2 | 2009-10-30 | ||
| CN2009102113751A CN102054076A (en) | 2009-10-30 | 2009-10-30 | Method and device for detecting character-labeled metal short circuit |
| CN2009102096262A CN102054062A (en) | 2009-10-30 | 2009-10-30 | Interactive method and device for detecting position of metal short circuit labelled with characters |
| CN200910211375.1 | 2009-10-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2011051786A2 true WO2011051786A2 (en) | 2011-05-05 |
| WO2011051786A3 WO2011051786A3 (en) | 2011-08-04 |
Family
ID=43922696
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/IB2010/002740 Ceased WO2011051786A2 (en) | 2009-10-30 | 2010-10-27 | Interactive method and apparatus for detecting texted metal short circuits |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20120221991A1 (en) |
| WO (1) | WO2011051786A2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102592599B1 (en) | 2016-05-12 | 2023-10-24 | 삼성전자주식회사 | Method for verifying a layout designed for semiconductor integrated circuit and a computer system perforing the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6282693B1 (en) * | 1998-12-16 | 2001-08-28 | Synopsys, Inc. | Non-linear optimization system and method for wire length and density within an automatic electronic circuit placer |
| US7149989B2 (en) * | 2004-09-22 | 2006-12-12 | Lsi Logic Corporation | Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design |
| JP4492398B2 (en) * | 2005-03-16 | 2010-06-30 | 日本電気株式会社 | Integrated circuit layout design system and program |
-
2010
- 2010-10-27 US US13/504,439 patent/US20120221991A1/en not_active Abandoned
- 2010-10-27 WO PCT/IB2010/002740 patent/WO2011051786A2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO2011051786A3 (en) | 2011-08-04 |
| US20120221991A1 (en) | 2012-08-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100527911B1 (en) | IC test software system for mapping logical functional test data of logic integrated circuits to physical representation | |
| US7308660B2 (en) | Calculation system of fault coverage and calculation method of the same | |
| CN103294842B (en) | Semiconductor device design method, system and computer-readable medium | |
| US7093216B2 (en) | Apparatus connectable to a computer network for circuit design verification, computer implemented method for circuit design verification, and computer program product for controlling a computer system so as to verify circuit designs | |
| Werner et al. | Reverse engineering of cryptographic cores by structural interpretation through graph analysis | |
| CN101286184A (en) | Method and system for generating integrated circuit test line | |
| KR101996120B1 (en) | System and method to diagnose integrated circuit | |
| JP7097587B2 (en) | Part Symbol Polarity Symbol Detection Methods, Systems, Computer-readable Storage Media and Devices | |
| WO2009108624A2 (en) | Integrated circuit (ic) design method, system and program product | |
| US20080244484A1 (en) | Circuit design verification system, method and medium | |
| CN103810316B (en) | The method for reducing parasitic mismatch | |
| Chang et al. | Experiences with layout-aware diagnosis—A case study | |
| CN114520504A (en) | Automated method for checking electrostatic discharge effects on a sacrificial device | |
| US20120221991A1 (en) | Interactive Method and Apparatus for Detecting Texted Metal Short Circuits | |
| TW583745B (en) | Methodology of locating faults of scan chains in logic integrated circuits | |
| US8065641B2 (en) | Automatically creating manufacturing test rules pertaining to an electronic component | |
| CN100385644C (en) | Method and apparatus for capturing and using design intent in integrated circuit fabrication | |
| TW201926092A (en) | Method for detecting unacceptable connection patterns | |
| CN114930339A (en) | Correlation between emission sites using CAD data combined with emission microscope images | |
| JP2018132877A (en) | Printed circuit board measurement point setting system, measurement point setting method, and measurement point setting program | |
| US8316336B1 (en) | Method and mechanism for modeling interconnect structures for integrated circuits | |
| CN117669460A (en) | An interactive file generation method and device for integrated circuits | |
| US8826219B2 (en) | Method and apparatus used for the physical validation of integrated circuits | |
| US8132135B2 (en) | Method and system for creating a boolean model of multi-path and multi-strength signals for verification | |
| TW201122872A (en) | Interactive method and apparatus for detecting texted metal short circuit location |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10826192 Country of ref document: EP Kind code of ref document: A1 |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 13504439 Country of ref document: US |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 10826192 Country of ref document: EP Kind code of ref document: A2 |