WO2011020122A1 - Heterojunction oxide non-volatile memory device - Google Patents

Heterojunction oxide non-volatile memory device Download PDF

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Publication number
WO2011020122A1
WO2011020122A1 PCT/US2010/045667 US2010045667W WO2011020122A1 WO 2011020122 A1 WO2011020122 A1 WO 2011020122A1 US 2010045667 W US2010045667 W US 2010045667W WO 2011020122 A1 WO2011020122 A1 WO 2011020122A1
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Prior art keywords
metal oxide
oxide layer
state
memory device
metal
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PCT/US2010/045667
Other languages
French (fr)
Inventor
Dongmin Chen
Original Assignee
4D-S Pty Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 4D-S Pty Ltd. filed Critical 4D-S Pty Ltd.
Priority to JP2012507481A priority Critical patent/JP2012525016A/en
Priority to KR1020117023456A priority patent/KR101392662B1/en
Priority to CN201080015470.5A priority patent/CN102365746B/en
Priority to EP10808880.8A priority patent/EP2465140A4/en
Publication of WO2011020122A1 publication Critical patent/WO2011020122A1/en
Priority to US13/396,404 priority patent/US8698120B2/en
Priority to US13/456,378 priority patent/US8378345B2/en
Priority to US14/186,273 priority patent/US9293201B2/en
Priority to US14/874,152 priority patent/US9520559B2/en
Priority to US15/367,902 priority patent/US10003020B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0097—Erasing, e.g. resetting, circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/028—Formation of switching materials, e.g. deposition of layers by conversion of electrode material, e.g. oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/31—Material having complex metal oxide, e.g. perovskite structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Definitions

  • the present invention relates generally to memory devices, and more particularly to a memory device that includes hetero junction oxide material.
  • Disk drives have been the dominant prime storage in terms of peak capacity, because storing individual domains (magnetic transition sites) on the disk drives unlike semiconductor memory cells disk memory sites do not require connections to get in and out of those domains.
  • semiconductor resolutions apply feature geometries with 90 nanometer feature resolutions progressing to 45 and 25 nanometer feature size sizes, with these feature capabilities, the memory cell size and chip capacity equation changes, furthermore, certain semiconductor memory technologies have applied a principal of geometric redundancy, where a multiple of data bits may be stored in a single cell. This property of a memory cell to support a multiple of values is sometimes referred to as its dynamic range. To date the for memory cells have abilities to support a dynamic range anywhere between 1 and 4 bits, gives you multiples of storage per memory cell.
  • Flash memory is hit the proverbial wall in increasing data capacity per unit cost, as the quantum limit is approached.
  • Flash memory But another issue with Flash memory is its limitations in write speeds. In order to compete with disk drive performance, the memory cells word structure is configured to switch in parallel. Another issue is the number of write cycle limitations the cell will tolerate before it permanently fails. Prior to the substantial reduction in cell size, it was approximately in the range of one million, however, as the foundry feature size resolutions reduced in size, rewrite cycle diminished to approximatelyl 00,000 write cycles. For most non-prime storage applications that may be practical. However, for SRAM and DRAM applications where you're actually exchanging data at substantial repetition rates, several times per microsecond.
  • a memory device comprises a first metal laver and a first metal oxide layer coupled to the first metal layer.
  • the memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer.
  • the formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.
  • Figure 1 illustrates a memory device in accordance with an embodiment.
  • Figure 2 is a graph showing resistance versus the Gibbs free energy for various metals.
  • Figure 3 is a graph showing current versus voltage loop for memory devices in accordance with embodiments.
  • Figure 4 is a graph showing hysteresis loops for the two types of memory devices.
  • FIG. 5 illustrates the classification of PCMO devices in accordance with embodiments.
  • Figure 6 illustrates the characteristics of the PCMO devices of Figure 5.
  • Figure 7A illustrates providing the metal 2 on a silicon surface.
  • Figure 7B illustrates sputtering metal 2 oxide onto the metal 2 surface.
  • Figure 7C illustrates metal oxide 1 forming spontaneously by providing metal 1 of the right energy level on the metal 2 oxide.
  • Figure 7C illustrates the metal oxide 1 sputtered on to the metal oxide 2 surface, and an inert metal is provided on top of the metal 2 oxide.
  • Figure 8 illustrates the operation of a switchable resistor that has a clockwise hysteresis of current versus voltage and a switchable resistor that has a counter clockwise hysteresis of current to voltage.
  • Figure 9 is a diagram of a back to back switching resistor in accordance with an embodiment.
  • Figure 10 is a diagram of the operation a tri-state back-to-back switching resistor device.
  • Figure 1 1 illustrate first method for addressing the tri-states of the back to back switching device of Figure 10.
  • Figure 12 is a diagram illustrating identifying the OO state vs. 01 , 10 state (nondestructive read).
  • Figure 13 is a diagram illustrating identifying a 10 state vs. an 01 state (destructive read, need to reinstall the state after read).
  • Figure 14 illustrates addressing single cell of an array in accordance with an embodiment.
  • Figure 15 illustrates creating asymmetry in the device to eliminate the need for resetting the device.
  • the present invention relates generally to memory devices, and more particularly to a memory device that includes a heterojunction oxide material.
  • the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
  • the present invention is directed to a memory device.
  • the memory device can be utilized in a variety of applications from a free standing nonvolatile memory to an embedded device in a variety of applications. These applications include but are not limited to embedded memory used in a wide range of SOC (system on chip), switches in programmable or configurable ASIC, solid state drive used in computers and servers, memory sticks used in mobile electronics like camera, cell phone, ipod etc.,
  • the memory device comprises a first metal layer and a first metal oxide layer coupled to the first metal layer.
  • the memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. These metal and metal oxide layers can be of a variety of types and their use will be within the spirit and scope of the present invention.
  • the embodiments disclosed herein will include PCMO as one of the metal oxide layers. It is well understood by one of ordinary skill in the art that the present invention should not be limited to this metal oxide layer or any other layer disclosed herein.
  • the key element is that the formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.
  • Figure 1 a is an illustration of a memory device 10 which includes a Platinum (Pt) bottom electrode 16, which in turn is coupled to a Praseodymium Calcium Manganese Oxide (PCMO) layer 14 which in turn is coupled to a top electrode 12 which is made of a metal.
  • PCMO Praseodymium Calcium Manganese Oxide
  • the top electrode metal 12 will spontaneously form a thin metal oxide 18 at the interface as shown in Fig 1 b.
  • the first metal oxide layer is preferably thinner than the second oxide layer.
  • the second metal oxide layer in this case PCMO
  • the second metal oxide layer is twenty to fifty times thicker than the first metal oxide layer.
  • the thickness of the first metal oxide layer is in the range of ten to fifty angstroms, and the thickness of the PCMO is 500 to 1000 angstroms.
  • FIG 2 what is shown is a graph showing resistance versus the Gibbs free energy free energy for various top metals coupled to PCMO, which is in turn coupled to a Pt bottom electrode.
  • elements such as gold, silver, and platinum, which have a higher oxidation Gibbs free energy than PCMO, will not spontaneously form oxide at the contact with the PCMO.
  • aluminum, titanium, and tantalum have a lower oxidation Gibbs free energy (more negative) than PCMO which allows for a spontaneously forming metal oxide upon contact there between.
  • Figure 3 is a set of
  • Electron micrographs 104-106 all illustrate the formation of a metal oxide when aluminum, titanium and tantalum respectively are interfaced with PCMO.
  • Figure 4 shows a method to classify various as-made "metal-PCMO- metal” devices into two types based on the relative value of the oxidation Gibbs free energy of the metal with relative to the oxidation Gibbs free energy of PCMO.
  • both the top and bottom metal electrode have a higher oxidation Gibbs free energy than the oxidation free energy of PCMO.
  • the device structure is metal-PCMO-metal or M/PCMO/M.
  • one of the metal electrode (top electrode) has a lower oxidation Gibbs free energy than the Gibbs free energy of PCMO.
  • a Type-ll device is a hetero junction metal oxide device.
  • the above rule of using the relative values of the oxidation free energy with respect to a base metal-oxide material can be generalized to any metal oxide.
  • Al, Ta and Ti can form TYPE-II device with a Tungsten Oxide which is coupled to Pt, Au or Ag as indicated in Figure 2.
  • FIG. 5 shows that the above type- 1 and type-ll devices yield different current-voltage (I-V) hysteresis curves.
  • a type-l device (202a, 202b and 202c yields a counter clock wise (CCW) hysteresis loop, while a type-ll device (204a, 204b and 204c) yields a clock wise hysteresis loop.
  • the hysteresis loop of the type-ll device is considerably larger than the hysteresis loop of type-l devices.
  • the CCW loop and CW loop will be swapped if the polarity of the bias is interchanged.
  • PCMO and metal-oxide are switchable resistors and a voltage with the correct polarity and amplitude can cause the resistor to switch from a low resistive state (LRS) to a high resistive state (HRS) (RESET), or from a HRS to a LRS (SET).
  • LRS low resistive state
  • HRS high resistive state
  • SET low resistive state
  • the lower oxidation Gibbs free energy will result in a more stable oxide structure which has a much higher resistance in HRS than the resistance of PCMO in HRS.
  • the metal oxide layer is much thinner than PCMO and its resistance at LRS is comparable to the resistance of PCMO at HRS. This feature is quite important.
  • Fi ⁇ ure 6 illustrates the characteristics of each of these types of devices. As is seen although both types can be utilized as memory devices the type 2 device is more effective and has better characteristics.
  • the key element is that the formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer. In so doing the two metal oxide layers provide a heterojunction that allows for the continual setting and resting of the device.
  • Figure 7A-7C illustrates the process of producing such a device.
  • Figure 7a illustrates providing the metal 2 on a silicon surface.
  • Figure 7B illustrates sputtering metal oxide 2 onto the metal 2 surface.
  • the next step is one of two alternative processes. Firstly, as seen in Figure 7C, metal oxide 1 is formed spontaneously by providing metal 1 on the metal oxide - 2, where the metal-1 has a lower oxidation free energy than that of metal - 2 so that metal oxide -1 can be form spontaneously between metal 1 and metal oxide 2. As an alternative as shown in Figure 7C ⁇ the metal oxide 1 is sputtered on to the metal oxide 2 surface, and an inert metal is provided on top of the metal 1 oxide.
  • a heterojunction oxide non-memory device can be provided that has characteristics that are significantly better than existing devices.
  • the heterojunction switchabie resistor can be used to construct high density memory array. Since it is a bipolar device, in general, it requires a transistor circuit to address (select, set, reset and read) individual device as in many prior arts. In a system in accordance with the present invention, back to back resistive devices are utilized to eliminate the need of the transistor circuit. This type of memory system will use less power, and fewer processing steps than conventional memory systems. More importantly it allows an easy way for form a multi stack memory eel! that further improves the cell density per unit source area.
  • Figure 8 illustrates a switchabie resistor 302 that has an idealized clockwise hysteresis of current versus voltage (I-V) 306 and a switchabie resistor 304 that has an idealized counter clockwise I-V hysteresis 308.
  • CW and CCW switching resistors 302 and 304 can be type-ll and type-l device shown in Figure 5 by the choice of the top metal electrode. They can also be constructed by using the same type device with top and bottom electrode reversed. In the ' " ' rill use the idealized I-V characteristics to illustrate an embodiment of a switching resistor device. It is clear to hysteresis one of ordinary skill in the art that a real device will have I-V curve that differs from the ideal ones used here. However, the principle remains valid even with a real device I-V
  • Figure 9 is a diagram of a back to back switching device 320 in
  • the I-V characteristics is due to the fact that when one resistor is switching from HRS to LRS, the other resistor is switching from LRS to HRS.
  • a switching voltage between the threshold voltages Va and Vb (with in positive side or negative side)
  • both resistors 302 and 304 can be switched into LRS.
  • Figure 10 shows that back-to-back switching device 320'can give rise to a tri-state.
  • resistor 302' or 304' is in HRS
  • the device 320 is in HRS. So there are two HRS, 01 or 10 state.
  • both resistors are in LRS, the device is in LRS, or 00 state.
  • the table 408 in Figure 1 1 illustrates a method for addressing the tri- states of the back to back switching device 320 of Figure 10.
  • 00 state can be set to 01 or 10 state and vise versa.
  • Figure 12 is a diagram illustrating a method to identify the 00 state 502 vs. 01 , 10 state 504.
  • the read voltage is within the two lower threshold voltage (Va- ⁇ V ⁇ Va+), therefore the device will remain in the original state. This is a nondestructive read.
  • the nondestructive read can only differentiate the 00 state (LRS) from either the 01 or 10 state (HRS state).
  • LRS 00 state
  • the polarity of the switching voltage Vb- ⁇ V ⁇ Va- or Va+ ⁇ V ⁇ Vb+
  • Vb- ⁇ V ⁇ Va- or Va+ ⁇ V ⁇ Vb+ needs to be tested that cause the switching of HRS resistor to LRS. Since this is a destructive read, an additional pulse is needed to reset the device to the initial state before the destructive read.
  • Figure 13 is a diagram illustrating a method for identifying a 10 state vs. an 01 state. It is readily apparent to one of ordinary skill in the art that many other voltage pulses and sequences can be generated to read the tri-state.
  • the addressable and readable tri-state of a back-to-back switching resistor device can be used to create a memory array that avoid the need of an active transistor circuit to perform the select and set/reset and read.
  • 01 and 10 states are two addressable and distinguishable HRS, they can be assigned to be the 0 or 1 state of a memory cell. Since both 0 and 1 state have high resistance, the system should have very low leakage current.
  • a positive or negative voltage greater than Vb+ or smaller than Vb- can set the device to 1 or rest the device to 0 state as shown in the table fo Figure 1 1 .
  • For read operation perform a test pulse to set the cell to 00 state and from the polarity of the bias to extract the 10 or 01 state. Note that the original state needs to be reinstalled after the read operation.
  • Figure 14 illustrates a diagram of biasing patterns that can fulfill this requirement when addressing single cell of an array in accordance with an embodiment.

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Abstract

A memory device is disclosed. The memory device comprises a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.

Description

HETEROJUNCTION OXIDE NON-VOLATILE MEMORY DEVICE
CROSS-REFERENCE TO RELATED APPLICATION
This application is claiming under 35 USC 1 19(e), the benefit of US provisional patent application serial no. 61/234,183, filed August 14, 2009.
FIELD OF THE INVENTION
The present invention relates generally to memory devices, and more particularly to a memory device that includes hetero junction oxide material.
BACKGROUND OF THE INVENTION
As Moore's Law has been predicting, the capacity of memory cells on silicon for the past 15-20 years has effectively doubled each year. Moore's Law is that every year the amount of structures or gates on a silicon wafer will double, but the price will essentially stay the same. And in some cases, the price will even erode. As these memory cells continue to shrink, the technology is starting to reach a barrier know as the quantum limit, that is, they are actually
approaching molecular boundaries, so the cells cannot get any smaller.
Disk drives have been the dominant prime storage in terms of peak capacity, because storing individual domains (magnetic transition sites) on the disk drives unlike semiconductor memory cells disk memory sites do not require connections to get in and out of those domains. Now, in recently history, semiconductor resolutions apply feature geometries with 90 nanometer feature resolutions progressing to 45 and 25 nanometer feature size sizes, with these feature capabilities, the memory cell size and chip capacity equation changes, furthermore, certain semiconductor memory technologies have applied a principal of geometric redundancy, where a multiple of data bits may be stored in a single cell. This property of a memory cell to support a multiple of values is sometimes referred to as its dynamic range. To date the for memory cells have abilities to support a dynamic range anywhere between 1 and 4 bits, gives you multiples of storage per memory cell. These combined properties of
semiconductors, have increased capacities and costs to now directly compete with disk drives. Another issue associated with semiconductor memory manufacturing has been the substantial costs of the semiconductor foundries which can run up to more than a billion dollars to establish with amortizing expenses inflating the unit cost of memory chips. In recent history this represented price barriers compared with cost per capacity of a disk drive file. Now, with advances in foundry resolutions enabling smaller cell sizes and the geometric redundancy of multiple bit-level per memory cell semiconductor memory is actually cheaper per unit cost, and substantially more rugged in terms of high G forces than memory files on a disk drive.
In Flash memories, there have been improvements in the Moore's Law effect but that has become a diminishing proposition because as the cells started getting smaller and smaller, write cycle limitations and ability to support dynamic ranges are diminished.
So basically, as characterized in recent press review, Flash memory is hit the proverbial wall in increasing data capacity per unit cost, as the quantum limit is approached.
But another issue with Flash memory is its limitations in write speeds. In order to compete with disk drive performance, the memory cells word structure is configured to switch in parallel. Another issue is the number of write cycle limitations the cell will tolerate before it permanently fails. Prior to the substantial reduction in cell size, it was approximately in the range of one million, however, as the foundry feature size resolutions reduced in size, rewrite cycle diminished to approximatelyl 00,000 write cycles. For most non-prime storage applications that may be practical. However, for SRAM and DRAM applications where you're actually exchanging data at substantial repetition rates, several times per microsecond.
Accordingly, what is desired is a memory system and method which overcomes the above-identified problems. The system and method should be easily implemented, cost effective and adaptable to existing storage applications. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A memory device is disclosed. The memory device comprises a first metal laver and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 illustrates a memory device in accordance with an embodiment.
Figure 2 is a graph showing resistance versus the Gibbs free energy for various metals.
Figure 3 is a graph showing current versus voltage loop for memory devices in accordance with embodiments.
Figure 4 is a graph showing hysteresis loops for the two types of memory devices.
Figure 5 illustrates the classification of PCMO devices in accordance with embodiments.
Figure 6 illustrates the characteristics of the PCMO devices of Figure 5.
Figure 7A illustrates providing the metal 2 on a silicon surface.
Figure 7B illustrates sputtering metal 2 oxide onto the metal 2 surface.
Figure 7C illustrates metal oxide 1 forming spontaneously by providing metal 1 of the right energy level on the metal 2 oxide.
Figure 7C illustrates the metal oxide 1 sputtered on to the metal oxide 2 surface, and an inert metal is provided on top of the metal 2 oxide.
Figure 8 illustrates the operation of a switchable resistor that has a clockwise hysteresis of current versus voltage and a switchable resistor that has a counter clockwise hysteresis of current to voltage.
Figure 9 is a diagram of a back to back switching resistor in accordance with an embodiment.
Figure 10 is a diagram of the operation a tri-state back-to-back switching resistor device.
Figure 1 1 illustrate first method for addressing the tri-states of the back to back switching device of Figure 10.
Figure 12 is a diagram illustrating identifying the OO state vs. 01 , 10 state (nondestructive read). Figure 13 is a diagram illustrating identifying a 10 state vs. an 01 state (destructive read, need to reinstall the state after read).
Figure 14 illustrates addressing single cell of an array in accordance with an embodiment.
Figure 15 illustrates creating asymmetry in the device to eliminate the need for resetting the device.
DETAILED DESCRIPTION
The present invention relates generally to memory devices, and more particularly to a memory device that includes a heterojunction oxide material. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
The present invention is directed to a memory device. The memory device can be utilized in a variety of applications from a free standing nonvolatile memory to an embedded device in a variety of applications. These applications include but are not limited to embedded memory used in a wide range of SOC (system on chip), switches in programmable or configurable ASIC, solid state drive used in computers and servers, memory sticks used in mobile electronics like camera, cell phone, ipod etc., The memory device comprises a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. These metal and metal oxide layers can be of a variety of types and their use will be within the spirit and scope of the present invention. More particularly, many of the embodiments disclosed herein will include PCMO as one of the metal oxide layers. It is well understood by one of ordinary skill in the art that the present invention should not be limited to this metal oxide layer or any other layer disclosed herein. The key element is that the formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.
Figure 1 a is an illustration of a memory device 10 which includes a Platinum (Pt) bottom electrode 16, which in turn is coupled to a Praseodymium Calcium Manganese Oxide (PCMO) layer 14 which in turn is coupled to a top electrode 12 which is made of a metal. If a Gibbs free energy for the formation of oxidation of the top electrode 12 is less (more negative) than a Gibbs free energy for the formation of oxidation of the PCMO layer 14, the top electrode metal 12 will spontaneously form a thin metal oxide 18 at the interface as shown in Fig 1 b. The first metal oxide layer is preferably thinner than the second oxide layer. In an embodiment, the second metal oxide layer (in this case PCMO) is twenty to fifty times thicker than the first metal oxide layer. For example, the thickness of the first metal oxide layer is in the range of ten to fifty angstroms, and the thickness of the PCMO is 500 to 1000 angstroms.
Referring now to Figure 2, what is shown is a graph showing resistance versus the Gibbs free energy free energy for various top metals coupled to PCMO, which is in turn coupled to a Pt bottom electrode. As is seen, elements such as gold, silver, and platinum, which have a higher oxidation Gibbs free energy than PCMO, will not spontaneously form oxide at the contact with the PCMO. However aluminum, titanium, and tantalum, have a lower oxidation Gibbs free energy (more negative) than PCMO which allows for a spontaneously forming metal oxide upon contact there between. Figure 3 is a set of
transmission electron micrographs that show the cross sections of formation of (or no formation of) metal oxide at of these two types of interfaces. As is seen in electron micrograph 102 which shows an interface between Platinum and PCMO there is no formation of a metal oxide. Electron micrographs 104-106 all illustrate the formation of a metal oxide when aluminum, titanium and tantalum respectively are interfaced with PCMO.
[002] Figure 4 shows a method to classify various as-made "metal-PCMO- metal" devices into two types based on the relative value of the oxidation Gibbs free energy of the metal with relative to the oxidation Gibbs free energy of PCMO. For TYPE-I devices, both the top and bottom metal electrode have a higher oxidation Gibbs free energy than the oxidation free energy of PCMO. The device structure is metal-PCMO-metal or M/PCMO/M. For TYPE-II devices, one of the metal electrode (top electrode) has a lower oxidation Gibbs free energy than the Gibbs free energy of PCMO. Due the spontaneous formation of the metal oxide at the contact with PCMO, the true device structure becomes metal- metal oxide-PCMO-metal, or M/MO/PCMO/M. Thus, a Type-ll device is a hetero junction metal oxide device. The above rule of using the relative values of the oxidation free energy with respect to a base metal-oxide material can be generalized to any metal oxide. For example, Al, Ta and Ti can form TYPE-II device with a Tungsten Oxide which is coupled to Pt, Au or Ag as indicated in Figure 2.
[003] Figure 5 shows that the above type- 1 and type-ll devices yield different current-voltage (I-V) hysteresis curves. A type-l device (202a, 202b and 202c yields a counter clock wise (CCW) hysteresis loop, while a type-ll device (204a, 204b and 204c) yields a clock wise hysteresis loop. Furthermore, the hysteresis loop of the type-ll device is considerably larger than the hysteresis loop of type-l devices. The CCW loop and CW loop will be swapped if the polarity of the bias is interchanged. These unique I-V characteristics can be utilized for various applications.
[004] The different hysteresis loops imply that both PCMO and metal-oxide are switchable resistors and a voltage with the correct polarity and amplitude can cause the resistor to switch from a low resistive state (LRS) to a high resistive state (HRS) (RESET), or from a HRS to a LRS (SET). Typically, the lower oxidation Gibbs free energy will result in a more stable oxide structure which has a much higher resistance in HRS than the resistance of PCMO in HRS. The metal oxide layer is much thinner than PCMO and its resistance at LRS is comparable to the resistance of PCMO at HRS. This feature is quite important. When the metal oxide is in HRS, most of the voltage applied to the type-ll device will drop across the metal oxide and hence create a high internal field that causes the switching from HRS to LRS (SET). On the other hand, when the metal oxide is in LRS, the voltage apply to the type-2 device will be shared in metal-oxide and in PCMO and hence allow field induced oxygen ion migrations in these metal oxide layers.
These concepts are used to advantage to provide a heterojunction nonvolatile memory device which can retain data over a significant period of time. Fiαure 6 illustrates the characteristics of each of these types of devices. As is seen although both types can be utilized as memory devices the type 2 device is more effective and has better characteristics. The key element is that the formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer. In so doing the two metal oxide layers provide a heterojunction that allows for the continual setting and resting of the device.
Figure 7A-7C illustrates the process of producing such a device. Figure 7a illustrates providing the metal 2 on a silicon surface. Figure 7B illustrates sputtering metal oxide 2 onto the metal 2 surface. The next step is one of two alternative processes. Firstly, as seen in Figure 7C, metal oxide 1 is formed spontaneously by providing metal 1 on the metal oxide - 2, where the metal-1 has a lower oxidation free energy than that of metal - 2 so that metal oxide -1 can be form spontaneously between metal 1 and metal oxide 2. As an alternative as shown in Figure 7C\ the metal oxide 1 is sputtered on to the metal oxide 2 surface, and an inert metal is provided on top of the metal 1 oxide.
Through the use of this system, a heterojunction oxide non-memory device can be provided that has characteristics that are significantly better than existing devices.
The heterojunction switchabie resistor can be used to construct high density memory array. Since it is a bipolar device, in general, it requires a transistor circuit to address (select, set, reset and read) individual device as in many prior arts. In a system in accordance with the present invention, back to back resistive devices are utilized to eliminate the need of the transistor circuit. This type of memory system will use less power, and fewer processing steps than conventional memory systems. More importantly it allows an easy way for form a multi stack memory eel! that further improves the cell density per unit source area.
Figure 8 illustrates a switchabie resistor 302 that has an idealized clockwise hysteresis of current versus voltage (I-V) 306 and a switchabie resistor 304 that has an idealized counter clockwise I-V hysteresis 308. CW and CCW switching resistors 302 and 304 can be type-ll and type-l device shown in Figure 5 by the choice of the top metal electrode. They can also be constructed by using the same type device with top and bottom electrode reversed. In the ' " ' rill use the idealized I-V characteristics to illustrate an embodiment of a switching resistor device. It is clear to hysteresis one of ordinary skill in the art that a real device will have I-V curve that differs from the ideal ones used here. However, the principle remains valid even with a real device I-V
Figure 9 is a diagram of a back to back switching device 320 in
accordance with an embodiment, and the I-V characteristics of such a combined device. These two resistors 302' and 304' have identical idealized I-V
characteristics but with opposite polarities. The I-V characteristics is due to the fact that when one resistor is switching from HRS to LRS, the other resistor is switching from LRS to HRS. By using a switching voltage between the threshold voltages Va and Vb (with in positive side or negative side), both resistors 302 and 304 can be switched into LRS.
Figure 10 shows that back-to-back switching device 320'can give rise to a tri-state. When either resistor 302' or 304' is in HRS, the device 320 is in HRS. So there are two HRS, 01 or 10 state. When both resistors are in LRS, the device is in LRS, or 00 state.
The table 408 in Figure 1 1 illustrates a method for addressing the tri- states of the back to back switching device 320 of Figure 10. In general, 00 state can be set to 01 or 10 state and vise versa.
Figure 12 is a diagram illustrating a method to identify the 00 state 502 vs. 01 , 10 state 504. Here the read voltage is within the two lower threshold voltage (Va- < V < Va+), therefore the device will remain in the original state. This is a nondestructive read.
The nondestructive read can only differentiate the 00 state (LRS) from either the 01 or 10 state (HRS state). To further differentiate 01 vs. 10 state, the polarity of the switching voltage (Vb-<V<Va- or Va+ < V < Vb+) needs to be tested that cause the switching of HRS resistor to LRS. Since this is a destructive read, an additional pulse is needed to reset the device to the initial state before the destructive read. Figure 13 is a diagram illustrating a method for identifying a 10 state vs. an 01 state. It is readily apparent to one of ordinary skill in the art that many other voltage pulses and sequences can be generated to read the tri-state.
The addressable and readable tri-state of a back-to-back switching resistor device can be used to create a memory array that avoid the need of an active transistor circuit to perform the select and set/reset and read. For example, since 01 and 10 states are two addressable and distinguishable HRS, they can be assigned to be the 0 or 1 state of a memory cell. Since both 0 and 1 state have high resistance, the system should have very low leakage current. A positive or negative voltage greater than Vb+ or smaller than Vb- can set the device to 1 or rest the device to 0 state as shown in the table fo Figure 1 1 . For read operation, perform a test pulse to set the cell to 00 state and from the polarity of the bias to extract the 10 or 01 state. Note that the original state needs to be reinstalled after the read operation.
In order to address a particular memory cell, proper voltage on the read and write line are required so that the state of other cells in the memory array are not affect. Figure 14 illustrates a diagram of biasing patterns that can fulfill this requirement when addressing single cell of an array in accordance with an embodiment.
The above discussions are base on two identical heterojunction oxide resistors. If the HRS states of the two switching resistors 702 and 704 have sizable differences as illustrated in Figure 15, than it is possible to perform a nondestructive read of a back-to-back resistor device. By so doing, we can eliminate the need for resetting the device after the read.
Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Claims

CLAIMS What is claimed is:
1 . A memory device comprises:
a first metal layer;
a first metal oxide layer coupled to the first metal layer;
a second metal oxide layer coupled to the first metal oxide layer;
a second metal layer coupled to the second metal oxide layer;
wherein a Gibbs free energy for the formation of the first metal oxide layer is lower than the Gibbs free energy for the formation of the second metal oxide layer.
2. The memory device of claim 1 , wherein the Gibbs free energy for the formation of the first metal oxide layer is two to three times the Gibbs free energy for the formation of the second metal oxide layer.
3. The memory device of claim 1 , wherein the first metal oxide comprises TiO2, Ta2O5, NiO, WO3, AI2O3, and the second metal oxide layer comprises PCMO.
4. The memory device of claim 1 , wherein the first metal oxide comprises AI2O3 and the second metal oxide comprises CuxOx.
5. The memory device of claim 1 , wherein the first metal oxide comprises AI2O3 and the second metal oxide comprises T1O2.
6. The memory device of claim 1 , wherein the first metal oxide comprises a first switchable resistance and the second metal oxide comprises a second switchable resistance.
7. The memory device of claim 1 , wherein to provide a large hysteresis in the device the high resistance state of the first metal oxide layer is much greater than the high resistance state of the second metal oxide layer and the low resistance state of the first metal oxide is on the order of the high resistance state of the second metal oxide layer.
8. The memory device of claim 1 , wherein the first metal oxide layer is thinner than the second metal oxide layer.
9. The memory device of claim 1 , wherein the second metal oxide layer is three to five times thicker than the first metal oxide layer.
10. A switching device comprising:
a first memory device; the first memory device comprising a first metal layer; a first metal oxide layer coupled to the first metal layer; a second metal oxide layer coupled to the first metal oxide layer; a second metal layer coupled to the second metal oxide layer; wherein a Gibbs free energy for the formation of the first metal oxide layer is lower than the Gibbs free energy for the formation of the second metal oxide layer; and
a second memory device coupled to the first memory device; the second memory device comprising a first metal layer; a second metal oxide layer coupled to the first metal layer; a second metal layer coupled to the second metal oxide layer; wherein a Gibbs free energy for the formation of the first metal oxide layer is higher the Gibbs free energy for the formation of the second metal oxide layer.
1 1 . The switching device of claim 10, wherein when the switching device has three states; the three states comprising 00 where the first and second memory devices are both in a low resistive state; 01 , where the first memory device is in the low resistive state and the second memory device is in a high resistive state and 10 where the first memory device is in the high resistive state and the second memory device is in a low resistive state.
12. The switching device of claim 1 1 , wherein it can be identified whether the switching device is in a 00 state vs. a 01 or a 10 state by performing a non destructive read.
13. The switching device of claim 1 1 , wherein it can be identified whether the switching device is in a 10 state vs. a 01 or a 10 state by performing a destructive read and reinstalling the state after the read.
14. A switching device comprising:
a first switching resistor which yields a clock wise current to voltage hysteresis loop; and
a second switching resistor coupled to the first switching resistor; wherein the second switching resistor yields a counter clock wise current to voltage hysteresis loop .
15. The switching device of claim 14, wherein when the switching device has three states; the three states comprising 00 where the first and second switching resistors are both in a low resistive state; 01 , where the first switching resistor is in the low resistive state and the second switching resistor is in a high resistive state and 10 where the first switching resistor is in the high resistive state and the second switching resistor is in a low resistive state.
16. The switching device of claim 15, wherein it can be identified whether the switching device is in a 00 state vs. a 01 or a 10 state by performing a non destructive read.
17. The switching device of claim 15, wherein it can be identified whether the switching device is in a 10 state vs. a 01 or a 10 state by performing a destructive read and reinstalling the state after the read.
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