WO2010151339A1 - In-line sputtering for improving thin film solar modules - Google Patents

In-line sputtering for improving thin film solar modules Download PDF

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Publication number
WO2010151339A1
WO2010151339A1 PCT/US2010/001836 US2010001836W WO2010151339A1 WO 2010151339 A1 WO2010151339 A1 WO 2010151339A1 US 2010001836 W US2010001836 W US 2010001836W WO 2010151339 A1 WO2010151339 A1 WO 2010151339A1
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thin film
solar cell
sputtering
film layers
cell fabrication
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PCT/US2010/001836
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French (fr)
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Paul H.J. Beatty
Jimin Ma
Willard Jones
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Sol Array Llc
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/032—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312
    • H01L31/0322—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312 comprising only AIBIIICVI chalcopyrite compounds, e.g. Cu In Se2, Cu Ga Se2, Cu In Ga Se2
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/042—Coating on selected surface areas, e.g. using masks using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/56—Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
    • C23C14/568—Transferring the substrates through a series of coating stations
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • H01L31/03923—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate including AIBIIICVI compound materials, e.g. CIS, CIGS
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • H01L31/03925—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate including AIIBVI compound materials, e.g. CdTe, CdS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0749—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type including a AIBIIICVI compound, e.g. CdS/CulnSe2 [CIS] heterojunction solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/541—CuInSe2 material PV cells

Definitions

  • Embodiments of this invention relate to fabrication methods of photovoltaic solar cell modules and their performance.
  • Thin film solar cells promise lower cost, large area arrays of efficient electricity generation for public utility usage.
  • CIGS copper indium gallium diselenide
  • the theoretical maximum of efficiency of 25% is limited to about 19% at best, for various reasons.
  • These include resistance paths and also shunting of the p-n junction, particularly in modules having cells connected in series as a monolithic structure.
  • films deposited by taking substrates out of a vacuum system are prone to reaction with oxygen and water, particularly under the effects of UV and visible illumination. This includes zinc oxide (ZnO) and CIGS, leading to issues of stress/adhesion and electrical resistance, reducing efficiency of the fabricated solar cell.
  • n-ZnO conducting top electrode
  • insulating layers of cadmium sulfide (CdS) and undoped (intrinsic) i-ZnO are deposited prior to the n-ZnO.
  • the n-ZnO is usually ZnO doped with Aluminum (Al), although other dopants are known and other transparent conducting oxides are also possible.
  • Molybdenum (Mo) as the bottom rear contact requires separation into separate areas. Conventionally, this is after it is deposited by breaking the vacuum and removing unwanted areas by photolithographic etching, lift-off photoresist, mechanical scribing or laser scribing.
  • the bottom contact of molybdenum [0008] According to one embodiment, the bottom contact of molybdenum
  • a rib of insulating material is patterned by printing or photolithography of material with sufficient height to ensure a discontinuous coverage of Mo as the sides of the rib are not covered.
  • An aperture mask is used over the sputtering target to ensure a somewhat vertical direction of sputtered atoms so avoiding coating the side walls of the insulator.
  • Patterning of subsequent films of CIGS, or other thin film solar cell materials is done with a specially constructed shadow mask consisting of taut wires, having a diameter to minimize the width of gaps required in these layers to join up cells in series as a module for higher output voltage. A minimum gap helps to raise module efficiency by avoiding dead space.
  • One embodiment includes the use of convex metal members to maintain the wires taut when their length expands during associated heating of the substrate during deposition. The convex shape becomes greater as the metal members themselves expand against a rigid ceramic frame.
  • the same or similar mask may be used to pattern the subsequent layers of insulating and conducting types of zinc oxide, ZnO.
  • i-ZnO helps to reduce shunting paths in CIGS pinholes, it prevents good electrical contact of n-ZnO and Mo for the link joining one cell to the other in series for higher output voltage.
  • a continuous flow is possible and also there are fewer pinholes in the CIGS layer as substrates are not removed from the vacuum system for scribing, or for deposition of CdS by the usual wet chemical bath of prior art.
  • a process chamber is used for sputtering and surrounded on both sides by a pair of smaller chambers used for transfer of substrates into the controlled pressure and gas environment used for sputtering.
  • FIG. 1 illustrates a side view inside a CIGS solar cell
  • FIG. 2 illustrates pinholes in the CIGS layer of the solar cell
  • FIG. 3 illustrates a mask for patterning a thin film layer
  • FIG. 4 illustrates a wire shadow mask for patterning a CIGS layer
  • FIG. 5 illustrates a side view inside a CIGS layer and a wire shadow mask
  • FIG. 6 illustrates one embodiment of an in-line sputtering system
  • FIG. 7 illustrates a convex strut wire tension shadow mask
  • FIG. 8 illustrates an embodiment having two wire shadow masks.
  • Figure 1 shows a side view inside a typical CIGS solar photovoltaic cell.
  • the photovoltaic cell may include (1) a glass substrate, preferably a soda lime glass substrate with a thickness typically 1.0 mm; (2) a thin film of Molybdenum (Mo) about 0.35 microns thick; (3) a thin film of CIGS about 0.5 to 1.5 microns thick, but typically 1.0 microns and shows grain sizes of similar size; (4) a layer of Cadmium Sulfide, CdS, 0.05 microns thick; (5) an intrinsic insulating zinc oxide, i-ZnO, about 0.1 microns thick; (6) a conductive n-ZnO:Al, about 0.35 microns thick; (7) a layer of Nickel, about 0.05 microns thick as part of a top grid to strengthen the top contact conductivity; (8) a layer of Aluminum Al, about 3.0 microns thick, also as part of the top grid; (9) a further
  • composition of the (3) thin film of CIGS may include substitutions with other suitable elements.
  • Zinc and Tin, (ZnSn) may be substituted for Indium.
  • Sulfur may be substituted for Selenium in the proper environment. Additional combinations or substitutions with other elements known in the art are considered well within the scope of the currently claimed techniques.
  • FIG. 2 is a schematic illustration of the patterning for a module of photovoltaic cells, whereby each cell is connected in series to its neighbor by leading the top transparent electrode (6) over the CIGS layer (3) to the bottom Mo contact (2) of the neighboring cell.
  • the patterned CIGS solar cell includes the layers of Fig. 1 and further include (1 1) a gap in Mo, the Pl gap; (12) a gap in CIGS, CdS and i-ZnO, the P2 gap and (13) a gap in n-ZnO and CIGS, the P3 gap.
  • the gaps in the Mo (Pl), CIGS, CdS, and i-ZnO (P2), and finally in all the layers above the Mo (P3) are done by mechanical or laser scribing.
  • the embodiments of the claimed method and system are similar to the fabrication of column cathodes in organic light-emitting diodes. Pillars of photoresist coated beforehand protrude as islands above the thickness of the film so that there is a natural break in sections of the deposited film. In conventional processing, this is known as a 'Pl ' scribe.
  • OLED Organic Light Emitting Diodes
  • OLED Organic Light Emitting Diodes
  • the thickness for the Mo electrode for CIGS is about 0.35 microns. Therefore, a thicker film of photoresist or other insulator is required and the layer of photoresist would remain in position within the device, with the layer of metal on top of the rib remaining isolated.
  • a second embodiment of this invention is to ink jet nano particles of insulator to about 0.5 microns thickness and of a width suitable for reliable electrical separation.
  • Possible insulators include may include materials such as glass, ceramics and the like.
  • Figure 3 illustrates an island shadow mask for Mo. As illustrated in
  • the photovoltaic cell includes the layers illustrated in Fig. 1 and further includes an island shadow mask, preferably (14) an insulating island by screen or ink jet printing, or photolithography processes.
  • an island shadow mask preferably (14) an insulating island by screen or ink jet printing, or photolithography processes.
  • One embodiment of this invention is an option for deposition of the bottom Mo contact as shown in Figure 3.
  • the Mo is deposited onto a rib shadow mask (14) in contact with the substrate without breaking vacuum.
  • One other advantage of the rib mask approach is obtaining a smaller width resulting in a solar cell with less dead area and improved energy conversion efficiency. Ink jet printed line width may even be as small as 10 microns.
  • the methods and system use an aperture over the sputtering target to ensure directional sputtered deposition between and on top of these islands, but not down their vertical side edges. In this way, there is less risk of exposing the Mo film to the atmosphere, so there is better chance of retained adhesion and electrical connection to subsequent films of CIGs and conducting n-ZnO:Al.
  • the photovoltaic cell includes the layers illustrated in Fig. 1 , a wire mask as referred to in Fig. 3 and further includes (15) a rigid support frame keeping wires in tension (16) a plurality of wires.
  • This geometry is compatible with use of a striped contact shadow mask as an embodiment of the claimed method and system to prevent deposition in the gap area, rather than have to remove deposited material by scribing.
  • Such masks may be etched flat metal, tensioned to avoid twisting and lack of contact.
  • the mask of Fig. 4 may include round wires (16) so any twist has no effect on the width of the gap masked off. This also provides strength and alleviates the need for bridging ties between the metal stripes to hold the wires flat.
  • sputtering without a directional aperture may produce a gap width narrower than the wire diameter, so reducing the dead space which otherwise reduces module efficiency. Using a directional aperture helps to direct sputtered material more perpendicular to the substrate and hence can widen the resulting gap if required.
  • the mask for this purpose would be some 5 inches x 5 inches of rigid frame for such size substrates.
  • Tensioned shadow masks for patterning the metal cathode in OLEDs may also be used as an alternative to the island approach mentioned above.
  • the tensioned shadow masks assist with deflecting the path of electrons more efficiently. Therefore, in the tensioned shadow mask, the stripes are isolated wires of round cross section strung under tension between the sides of a rigid metal frame. Typical diameter may be 50+/- 10 microns (some 2 thousands of an inch).
  • Wire material can be of any suitable metal or alloy, chosen for strength and ease of fabrication to take up slack during expansion when heated. Thus, during deposition of CIGs, substrates may be heated up to about 450 deg C.
  • tensioned shadow masks may include maintaining or replacing broken or distorted wires and removing any accumulation of thin film material on their top surface. The buildup of thin film material may be periodically removed avoiding any particulate contamination. Use of tensioned shadow masks may also include ensuring adequate registration, particularly of the wire mask, within say +/- 15 microns.
  • Figure 5 illustrates a side view inside the CIGS device and wire of the shadow mask.
  • the photovoltaic cell includes the layers illustrated in Fig. 1 and further includes (16) a wire or a plurality of wires as shown in Fig. 4.
  • Figure 6 illustrates an in-line sputtering system.
  • the in-line sputtering system comprising (17) a chamber 1 transfer; (18) a gate valve 1/2; (19) a chamber 2 transfer; (20) a gate valve 2/3; (21) a chamber 3 process; (22) a gate valve 3/4; (23) a chamber 4 transfer; (24) a gate valve 4/5; (25) a chamber 5 transfer.
  • FIG. 7 illustrates a convex strut wire tension shadow mask.
  • the convex strut wire tension shadow mask may include (16) a plurality of wires; (26) a set of convex metal struts and (27) a set of rigid ceramic struts.
  • a method is described for reducing wire slack by fabricating the frame with metal struts (26) having a sight outward curve relative to the module substrate. This ensures that the frame width becomes greater with heat during sputtering, so stretching the wire more to make up for the expansion of the wire itself.
  • Ceramic rigid frame members (27) ensure the ends of the convex metal struts (26) can push on those so that the expanding metal arches outwards.
  • Figure 8 illustrates an embodiment having two wire shadow masks.
  • a first shadow mask may be defined with a larger diameter wire, shown dotted, to delineate P2.
  • a second wire shadow masking having a smaller diameter wire, shown in full line, to delineate P3.
  • the CIGS and then CdS and i-ZnO can be deposited over the Mo leaving the further gap P2 next to Pl . Then, omitting the shadow mask, and without breaking vacuum, the conductive n-ZnO can be deposited to make good contact with the Mo joining cell to cell, and acting as a top electrode in contact with the CIGS.
  • gap 'P3' it can be scribed, mechanically or with lasers, outside of the vacuum deposition system at the end of the critical film deposition processes. Further metal films of aluminum (Al) and nickel (Ni) can be deposited subsequently in a separate operation using a similar sputtering system.
  • an inline sputtering system may include process chambers (22) separated by two transfer chambers (17, 19, 23, 25) on each side. Every chamber has an associated gate valve (18, 20, 22, 24) at each side.
  • the process chambers are longer, e.g. 6 feet, to allow pass-through, or annealing and even multiple targets.
  • Transfer chambers may be relatively smaller, preferably 2 feet long.
  • the sequence of steps for continuous sputtering using substrates on a moving carrier may include:
  • Valve 1/2 opens, so substrates are unaware of any environment change, and substrates go over to transfer chamber "2", with valve "1/2" shut behind them. This allows transfer chamber "1" to accept new substrates.
  • valve "2/3" opens, allowing substrates to enter process chamber"3".
  • the substrates are unaware of any change of environment as they enter process chamber "3". This may continue for as many film layers as required.
  • sputtering process chambers from left to right are continued for Mo, CIGs, CdS, i-ZnO and n-ZnO.
  • Argon gas is used for sputtering Mo, but at a carefully optimized pressure to ensure correct grain size and stress to allow through diffusion of sodium from the glass to help dope the CIGS p-type.
  • the ClGs itself also needs argon gas at some optimum pressure, and facility also for additional hydrogen selenide or hydrogen sulfide to correct excess copper non stoichiometry.
  • CdS uses argon.
  • the i-ZnO and n-ZnO can use some additional oxygen for optimal sputtering.
  • a single sputtering target for the CIGS layer may include copper, indium, gallium and selenium in proportions found to yield the highest solar cell efficiency.
  • Ga to In plus Ga content can be up to 30%.
  • Total composition should allow for losses of some elements during sputtering so the target composition itself results in approximately Cu at 19.618%; In at 22.23%, Ga at 6.40 % and Se at 51.74 %.
  • Substitution of sulfur (S) for a predetermined amount of the Se is also possible.
  • the aforementioned composition allows for unequal sputtering of elements and allows for a final film formula of atomic ratios such as Culno 7 sGao 25 Se 2 . Small variations are likely within processing margins of say x 1.2. Thus, for example Ga content might rise to Gao 30.
  • Alternatives arrangements may include dual sputtering targets, located in one of the process chambers, for simultaneous deposition of separate elements or mixture of elements. This may include Ga/In for instance, where a graded composition may be needed throughout the thickness of the film.
  • Substrate temperature for the CIGS layer can be between 400 deg C to 520 deg C, e.g. 450 deg C.
  • pulse mode DC sputtering is used for the ClGS, and RP sputtering for the ZnO and CdS layers.
  • avoiding toxic Cd may also be advantageous.
  • Using an inline deposition without breaking vacuum reduces the possibility of pin holes arising from trapped particles in the CIGS layer being removed to leave pin holes that then need the insulating layers such as CdS and i-ZnO.
  • the substrates can continue in a continuous manner for deposition of grid electrodes consisting of very thin Ni (0.05 microns), Al (3.0 microns) and further protecting Ni (0.05 microns).
  • two targets of Ni and Al can be mounted in one process chamber.
  • the carrier with substrates enters the process chamber the first bottom layer of Ni is sputtered onto that, whilst also sputtering the outgoing substrate with its final layer of Ni.
  • Al is sputtered.
  • argon gas may be used for these metal layers.
  • an alternative masking arrangement is shown.
  • the alternative masking arrangement may be used to delineate the P2 break in the CIGS layers.
  • the use of a larger diameter wire (28) in the shadow mask creates a wider gap to include the width of both P2 and P3, for example 50 + 50 microns.
  • a smaller wire mask (29) positioned alongside, the n-ZnO can be deposited to cover the P2 gap of exposed Mo, and the top of the CIGS layer, but not the area under the mask thus separating the CIGS cells. In this way, a completely continuous deposition of the most vulnerable films is possible without breaking vacuum, thus saving process time and contamination by the atmosphere.

Abstract

The technique described involves a method and system for sputtering thin film layers in solar cell fabrication and may include the steps of providing an initial vacuum state for depositing a plurality of thin film layers to a substrate; patterning a first landscape for a first layer with a mask and in-line sputtering the layers of thin film continuously while maintaining the initial vacuum state. The system for sputtering thin film layers in solar cell fabrication may include a carrier for loading a substrate through a main chamber; the main chamber having a process chamber for depositing a sputtering target in an initial vacuum state where the process chamber includes at least two associated transfer chambers for maintaining the initial vacuum state wherein each chamber includes an associated gate valve.

Description

DESCRIPTION TITLE
IN-LINE SPUTTERING FOR IMPROVING THIN FILM SOLAR MODULES
PRIORITY CLAIM
[0001] This application claims priority benefit from U.S. provisional application Ser. No. 61/220,576 filed on June 26, 2009, the entire disclosure of which is incorporated herein by reference for all purposes.
TECHNICAL FIELD
[0002] Embodiments of this invention relate to fabrication methods of photovoltaic solar cell modules and their performance.
BACKGROUND
[0003] Thin film solar cells promise lower cost, large area arrays of efficient electricity generation for public utility usage. In the case of copper indium gallium diselenide (CIGS) films, the theoretical maximum of efficiency of 25% is limited to about 19% at best, for various reasons. These include resistance paths and also shunting of the p-n junction, particularly in modules having cells connected in series as a monolithic structure. Moreover, films deposited by taking substrates out of a vacuum system are prone to reaction with oxygen and water, particularly under the effects of UV and visible illumination. This includes zinc oxide (ZnO) and CIGS, leading to issues of stress/adhesion and electrical resistance, reducing efficiency of the fabricated solar cell.
[0004] In addition, the in-rush of air, with exposure and handling, may lead to removal of contaminating particles resulting in physical holes. These holes can then be filled with conducting top electrode n-ZnO causing a short circuit shunt path which limits efficiency of the solar module. To avoid this, insulating layers of cadmium sulfide (CdS) and undoped (intrinsic) i-ZnO are deposited prior to the n-ZnO. The n-ZnO is usually ZnO doped with Aluminum (Al), although other dopants are known and other transparent conducting oxides are also possible. However, this slows down the fabrication and an atmospheric attack might occur on the i-ZnO layer deposited prior to the n-ZnO top electrode. Therefore, it would be advantageous to have an inline continuous process avoiding exposure to the local atmosphere during fabrication. It would also be advantageous to avoid yield losses in out-of- vacuum scribing operations designed to join cells together for higher voltage.
[0005] In conventional processing, it has been necessary to remove substrates from the vacuum system several times so that film layers can be scribed, mechanically or by laser, to separate sections for subsequent connection in series for the required output voltage, or in parallel for additional current. Thus, Molybdenum (Mo) as the bottom rear contact requires separation into separate areas. Conventionally, this is after it is deposited by breaking the vacuum and removing unwanted areas by photolithographic etching, lift-off photoresist, mechanical scribing or laser scribing.
[0006] Mechanical scribing can damage the glass substrate and other film layers beneath that being scribed. Laser scribing can also be difficult, prone to heat neighboring material, and is capital intensive. Furthermore, it has been time consuming to scribe through the CIGS layer to allow series connection from the top transparent electrode to the bottom Mo electrode of the adjacent cell for higher series voltage. This has involved breaking vacuum to do that scribe after i-ZnO and before n-ZnO is deposited. In part, this is due to use of an insulating layer of i-ZnO prior to the transparent top n-ZnO electrode to help reduce shunt currents in the CIGS pin holes. The novel technique here helps overcome both the problem of pin holes and the problems associated with break in vacuum during deposition of two types of ZnO.
SUMMARY
[0007] According to embodiments of the claimed method and system, using a fast in-line sputtering system, scribing of gaps between cells is avoided, and hence the associated yield, time and cost issues. Also, pin holes in the CIGS layer may be avoided by keeping the coated substrates in a vacuum system for the separating of individual cells, thus reducing shunt paths that lower module efficiency. Shadow masks may be used to avoid depositing films where gaps are needed between them. In prior art, this is done by various means of scribing that can reduce yield and slow down the manufacturing process.
[0008] According to one embodiment, the bottom contact of molybdenum
(Mo), a rib of insulating material is patterned by printing or photolithography of material with sufficient height to ensure a discontinuous coverage of Mo as the sides of the rib are not covered. An aperture mask is used over the sputtering target to ensure a somewhat vertical direction of sputtered atoms so avoiding coating the side walls of the insulator.
[0009] Patterning of subsequent films of CIGS, or other thin film solar cell materials, is done with a specially constructed shadow mask consisting of taut wires, having a diameter to minimize the width of gaps required in these layers to join up cells in series as a module for higher output voltage. A minimum gap helps to raise module efficiency by avoiding dead space. [00010] One embodiment includes the use of convex metal members to maintain the wires taut when their length expands during associated heating of the substrate during deposition. The convex shape becomes greater as the metal members themselves expand against a rigid ceramic frame.
[00011] The same or similar mask may be used to pattern the subsequent layers of insulating and conducting types of zinc oxide, ZnO. This avoids the usual break of vacuum and time consuming step of scribing a gap after depositing CIGS, CdS and i-ZnO layers prior to deposition of the top transparent conductor n-ZnO. Whereas i-ZnO helps to reduce shunting paths in CIGS pinholes, it prevents good electrical contact of n-ZnO and Mo for the link joining one cell to the other in series for higher output voltage. In this invention, a continuous flow is possible and also there are fewer pinholes in the CIGS layer as substrates are not removed from the vacuum system for scribing, or for deposition of CdS by the usual wet chemical bath of prior art.
[00012] Interestingly, the claimed method and technique allows fast in-line
• continuous sputtering of all film layers without breaking vacuum. Substrates travel on a carrier through a series of vacuum chambers. According to one embodiment, a process chamber is used for sputtering and surrounded on both sides by a pair of smaller chambers used for transfer of substrates into the controlled pressure and gas environment used for sputtering. BRIEF DESCRIPTION OF DRAWINGS
[00013] FIG. 1 illustrates a side view inside a CIGS solar cell;
[00014] FIG. 2 illustrates pinholes in the CIGS layer of the solar cell;
[00015] FIG. 3 illustrates a mask for patterning a thin film layer;
[00016] FIG. 4 illustrates a wire shadow mask for patterning a CIGS layer; [00017] FIG. 5 illustrates a side view inside a CIGS layer and a wire shadow mask;
[00018] FIG. 6 illustrates one embodiment of an in-line sputtering system;
[00019] FIG. 7 illustrates a convex strut wire tension shadow mask; and
[00020] FIG. 8 illustrates an embodiment having two wire shadow masks.
DESCRIPTION OF EMBODIMENTS
[00021] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details.
[00022] Figure 1 shows a side view inside a typical CIGS solar photovoltaic cell. As illustrated in Fig. 1, the photovoltaic cell may include (1) a glass substrate, preferably a soda lime glass substrate with a thickness typically 1.0 mm; (2) a thin film of Molybdenum (Mo) about 0.35 microns thick; (3) a thin film of CIGS about 0.5 to 1.5 microns thick, but typically 1.0 microns and shows grain sizes of similar size; (4) a layer of Cadmium Sulfide, CdS, 0.05 microns thick; (5) an intrinsic insulating zinc oxide, i-ZnO, about 0.1 microns thick; (6) a conductive n-ZnO:Al, about 0.35 microns thick; (7) a layer of Nickel, about 0.05 microns thick as part of a top grid to strengthen the top contact conductivity; (8) a layer of Aluminum Al, about 3.0 microns thick, also as part of the top grid; (9) a further layer of Nickel, about 0.05 microns thick, to protect the Aluminum and (10) a cover glass, preferably soda lime glass, about 1.0 mm thick. As will be apparent to those of skill in the art, the composition of the (3) thin film of CIGS may include substitutions with other suitable elements. For example, Zinc and Tin, (ZnSn) may be substituted for Indium. In addition, Sulfur may be substituted for Selenium in the proper environment. Additional combinations or substitutions with other elements known in the art are considered well within the scope of the currently claimed techniques.
[00023] Figure 2 is a schematic illustration of the patterning for a module of photovoltaic cells, whereby each cell is connected in series to its neighbor by leading the top transparent electrode (6) over the CIGS layer (3) to the bottom Mo contact (2) of the neighboring cell. As illustrated in Fig. 2 and with reference back to Fig. 1, the patterned CIGS solar cell includes the layers of Fig. 1 and further include (1 1) a gap in Mo, the Pl gap; (12) a gap in CIGS, CdS and i-ZnO, the P2 gap and (13) a gap in n-ZnO and CIGS, the P3 gap. In prior art, the gaps in the Mo (Pl), CIGS, CdS, and i-ZnO (P2), and finally in all the layers above the Mo (P3) are done by mechanical or laser scribing.
[00024] The embodiments of the claimed method and system are similar to the fabrication of column cathodes in organic light-emitting diodes. Pillars of photoresist coated beforehand protrude as islands above the thickness of the film so that there is a natural break in sections of the deposited film. In conventional processing, this is known as a 'Pl ' scribe. However, Organic Light Emitting Diodes (OLED) films are around 0.06 microns in thickness, whereas the thickness for the Mo electrode for CIGS is about 0.35 microns. Therefore, a thicker film of photoresist or other insulator is required and the layer of photoresist would remain in position within the device, with the layer of metal on top of the rib remaining isolated.
[00025] A second embodiment of this invention is to ink jet nano particles of insulator to about 0.5 microns thickness and of a width suitable for reliable electrical separation. Possible insulators include may include materials such as glass, ceramics and the like.
[00026] Figure 3 illustrates an island shadow mask for Mo. As illustrated in
Fig. 3 and with reference back to Fig. 1, the photovoltaic cell includes the layers illustrated in Fig. 1 and further includes an island shadow mask, preferably (14) an insulating island by screen or ink jet printing, or photolithography processes. One embodiment of this invention is an option for deposition of the bottom Mo contact as shown in Figure 3. The Mo is deposited onto a rib shadow mask (14) in contact with the substrate without breaking vacuum. One other advantage of the rib mask approach is obtaining a smaller width resulting in a solar cell with less dead area and improved energy conversion efficiency. Ink jet printed line width may even be as small as 10 microns.
[00027] According to another embodiment, the methods and system use an aperture over the sputtering target to ensure directional sputtered deposition between and on top of these islands, but not down their vertical side edges. In this way, there is less risk of exposing the Mo film to the atmosphere, so there is better chance of retained adhesion and electrical connection to subsequent films of CIGs and conducting n-ZnO:Al.
[00028] In the case of subsequent film layers CIGS, CdS and then i-ZnO, there is again need of a second (so-called 'P2') gap to remove these films down to the Mo electrode. As with the Pl gap, the width is preferably 50 microns and the spacing between the collection of gaps is about 5 to 20 mm, assuming an optimal n-ZnO top electrode having sheet resistance of some 40 Ohms/sq using a thickness of 0.150 microns. [00029] Figure 4 illustrates a wire shadow mask for patterning the CIGS layer.
As illustrated in Fig. 4 and with reference back to Fig. 1, the photovoltaic cell includes the layers illustrated in Fig. 1 , a wire mask as referred to in Fig. 3 and further includes (15) a rigid support frame keeping wires in tension (16) a plurality of wires.
[00030] This geometry is compatible with use of a striped contact shadow mask as an embodiment of the claimed method and system to prevent deposition in the gap area, rather than have to remove deposited material by scribing. (See Figure 3). Such masks may be etched flat metal, tensioned to avoid twisting and lack of contact. According to one embodiment, the mask of Fig. 4 may include round wires (16) so any twist has no effect on the width of the gap masked off. This also provides strength and alleviates the need for bridging ties between the metal stripes to hold the wires flat. Also, sputtering without a directional aperture may produce a gap width narrower than the wire diameter, so reducing the dead space which otherwise reduces module efficiency. Using a directional aperture helps to direct sputtered material more perpendicular to the substrate and hence can widen the resulting gap if required. Typically, the mask for this purpose would be some 5 inches x 5 inches of rigid frame for such size substrates.
[00031] Tensioned shadow masks for patterning the metal cathode in OLEDs may also be used as an alternative to the island approach mentioned above. The tensioned shadow masks assist with deflecting the path of electrons more efficiently. Therefore, in the tensioned shadow mask, the stripes are isolated wires of round cross section strung under tension between the sides of a rigid metal frame. Typical diameter may be 50+/- 10 microns (some 2 thousands of an inch). Wire material can be of any suitable metal or alloy, chosen for strength and ease of fabrication to take up slack during expansion when heated. Thus, during deposition of CIGs, substrates may be heated up to about 450 deg C.
[00032] Use of tensioned shadow masks may include maintaining or replacing broken or distorted wires and removing any accumulation of thin film material on their top surface. The buildup of thin film material may be periodically removed avoiding any particulate contamination. Use of tensioned shadow masks may also include ensuring adequate registration, particularly of the wire mask, within say +/- 15 microns.
[00033] Figure 5 illustrates a side view inside the CIGS device and wire of the shadow mask. As illustrated in Fig. 5 and with reference back to Fig. 1, the photovoltaic cell includes the layers illustrated in Fig. 1 and further includes (16) a wire or a plurality of wires as shown in Fig. 4.
[00034] Figure 6 illustrates an in-line sputtering system. The in-line sputtering system comprising (17) a chamber 1 transfer; (18) a gate valve 1/2; (19) a chamber 2 transfer; (20) a gate valve 2/3; (21) a chamber 3 process; (22) a gate valve 3/4; (23) a chamber 4 transfer; (24) a gate valve 4/5; (25) a chamber 5 transfer.
[00035] Figure 7 illustrates a convex strut wire tension shadow mask. As illustrated in Fig. 7 the convex strut wire tension shadow mask may include (16) a plurality of wires; (26) a set of convex metal struts and (27) a set of rigid ceramic struts. According to one embodiment, and with reference to Figure 7, a method is described for reducing wire slack by fabricating the frame with metal struts (26) having a sight outward curve relative to the module substrate. This ensures that the frame width becomes greater with heat during sputtering, so stretching the wire more to make up for the expansion of the wire itself. Ceramic rigid frame members (27) ensure the ends of the convex metal struts (26) can push on those so that the expanding metal arches outwards.
[00036] With suitable mechanics, good contact can be maintained against the substrate to ensure no deposition of CIGs, CdS and i-ZnO under the wire. This can be assisted in having an aperture close to the target so that the impinging stream of sputtered atoms is from a more vertical angle. One other advantage is in the resultant small width of gap, thus reducing dead space that otherwise detracts from module efficiency.
[00037] Figure 8 illustrates an embodiment having two wire shadow masks. As illustrated in Fig. 8, (28) a first shadow mask may be defined with a larger diameter wire, shown dotted, to delineate P2. Also illustrated in Fig. 8 is (29) a second wire shadow masking having a smaller diameter wire, shown in full line, to delineate P3.
[00038] According to one embodiment, shifting the mask, or using the same type of mask, as for the Pl gap in Mo, the CIGS and then CdS and i-ZnO can be deposited over the Mo leaving the further gap P2 next to Pl . Then, omitting the shadow mask, and without breaking vacuum, the conductive n-ZnO can be deposited to make good contact with the Mo joining cell to cell, and acting as a top electrode in contact with the CIGS. To provide gap 'P3', it can be scribed, mechanically or with lasers, outside of the vacuum deposition system at the end of the critical film deposition processes. Further metal films of aluminum (Al) and nickel (Ni) can be deposited subsequently in a separate operation using a similar sputtering system.
[00039] According to another embodiment and with reference to Fig. 6, an inline sputtering system may include process chambers (22) separated by two transfer chambers (17, 19, 23, 25) on each side. Every chamber has an associated gate valve (18, 20, 22, 24) at each side. The process chambers are longer, e.g. 6 feet, to allow pass-through, or annealing and even multiple targets. Transfer chambers may be relatively smaller, preferably 2 feet long. According to one embodiment, the sequence of steps for continuous sputtering using substrates on a moving carrier may include:
[00040] (a) Substrates are loaded onto a carrier and moved into transfer chamber "1". The valve 1/2 between transfer chamber 1 and transfer chamber 2 is closed, and substantially all the gas is removed.
[00041] (b) The valve "2/3" between chambers 1 and 2 is closed while transfer chamber "2" is prepared by drawing vacuum to match the environment in transfer chamber "1.
[00042] (c) Valve 1/2 opens, so substrates are unaware of any environment change, and substrates go over to transfer chamber "2", with valve "1/2" shut behind them. This allows transfer chamber "1" to accept new substrates.
[00043] (d) When substrates are in transfer chamber "2", and after the valve
"1/2" is shut behind them, process gas enters transfer chamber "2" to match that of process "3".
[00044] (e) When transfer chamber "2" and process chamber "3" achieve identical environments, valve "2/3" opens, allowing substrates to enter process chamber"3". Thus, the substrates are unaware of any change of environment as they enter process chamber "3". This may continue for as many film layers as required.
[00045] According to one embodiment and with reference to Fig. 6, sputtering process chambers from left to right are continued for Mo, CIGs, CdS, i-ZnO and n-ZnO. Argon gas is used for sputtering Mo, but at a carefully optimized pressure to ensure correct grain size and stress to allow through diffusion of sodium from the glass to help dope the CIGS p-type. The ClGs itself also needs argon gas at some optimum pressure, and facility also for additional hydrogen selenide or hydrogen sulfide to correct excess copper non stoichiometry. Likewise, CdS uses argon. The i-ZnO and n-ZnO can use some additional oxygen for optimal sputtering.
[00046] Ideally, a single sputtering target for the CIGS layer may include copper, indium, gallium and selenium in proportions found to yield the highest solar cell efficiency. Typically Ga to In plus Ga content can be up to 30%. Total composition should allow for losses of some elements during sputtering so the target composition itself results in approximately Cu at 19.618%; In at 22.23%, Ga at 6.40 % and Se at 51.74 %. Substitution of sulfur (S) for a predetermined amount of the Se is also possible. The aforementioned composition allows for unequal sputtering of elements and allows for a final film formula of atomic ratios such as Culno 7sGao 25Se2. Small variations are likely within processing margins of say x 1.2. Thus, for example Ga content might rise to Gao 30.
[00047] Alternatives arrangements may include dual sputtering targets, located in one of the process chambers, for simultaneous deposition of separate elements or mixture of elements. This may include Ga/In for instance, where a graded composition may be needed throughout the thickness of the film.
[00048] To improve operating control of the stoichiometry of the CIGS layer, hydrogen selenide or hydrogen sulfide gases may be admitted into at least one chamber. Substrate temperature for the CIGS layer can be between 400 deg C to 520 deg C, e.g. 450 deg C. Preferably, pulse mode DC sputtering is used for the ClGS, and RP sputtering for the ZnO and CdS layers.
[00049] In addition, avoiding toxic Cd may also be advantageous. Using an inline deposition without breaking vacuum reduces the possibility of pin holes arising from trapped particles in the CIGS layer being removed to leave pin holes that then need the insulating layers such as CdS and i-ZnO.
[00050] After the deposition of the n-ZnO electrode and annealing within or outside of the vacuum system, the substrates can continue in a continuous manner for deposition of grid electrodes consisting of very thin Ni (0.05 microns), Al (3.0 microns) and further protecting Ni (0.05 microns). In this case, two targets of Ni and Al can be mounted in one process chamber. As the carrier with substrates enters the process chamber, the first bottom layer of Ni is sputtered onto that, whilst also sputtering the outgoing substrate with its final layer of Ni. For substrates traveling within the center zone of the chamber, Al is sputtered. For these metal layers, argon gas may be used.
[00051] According to one embodiment and with reference to Fig. 8, an alternative masking arrangement is shown. The alternative masking arrangement may be used to delineate the P2 break in the CIGS layers. The use of a larger diameter wire (28) in the shadow mask creates a wider gap to include the width of both P2 and P3, for example 50 + 50 microns. Then, using a smaller wire mask (29), positioned alongside, the n-ZnO can be deposited to cover the P2 gap of exposed Mo, and the top of the CIGS layer, but not the area under the mask thus separating the CIGS cells. In this way, a completely continuous deposition of the most vulnerable films is possible without breaking vacuum, thus saving process time and contamination by the atmosphere. 52] Alternative materials to the examples mentioned are possible known to those skilled in the art. Just a few include other sunlight-absorbing materials such as cadmium telluride (CdTe), copper indium diselenide (CIS) and copper indium gallium diselenide/sulfide. Also, other so-called buffer layers can be used in place of or with CdS and i-ZnO; these include indium selenide, zinc indium selenide, indium sulfide and zinc magnesium oxide. These buffer layers may be deposited by vacuum deposition, or if necessary, by a breaking vacuum to do a chemical bath deposition. Equally, a chemical bath of cadmium salts, or vapor deposition of cadmium, without processing to the sulfide is also possible.

Claims

Claim 1 A method for sputtering thin film layers in solar cell fabrication, comprising: providing an initial vacuum state for depositing a plurality of thin film layers to a substrate; patterning a first landscape for a first layer with a mask; and in-line sputtering the layers of thin film continuously while maintaining the initial vacuum state.
Claim 2 The method for sputtering thin film layers in solar cell fabrication of claim 1, further comprising: loading the substrate on a carrier; advancing the substrate on the carrier through a pressure controlled chamber; and depositing a first conductive layer, an insulating layer, an absorbent layer and a second conductive layer while maintaining the initial vacuum state.
Claim 3 The method for sputtering thin film layers in solar cell fabrication of claim 1, wherein patterning the first landscape for the first layer further comprises: coating the substrate with photoresist to form a rib mask wherein coating includes applying a composition of insulating nanoparticles.
Claim 4 The method for sputtering thin film layers in solar cell fabrication of claim 1, wherein patterning the first landscape for the first layer further comprises: photolithographic printing of a first landscape pattern. Claim 5 The method for sputtering thin film layers in solar cell fabrication of claim 4, wherein the first landscape pattern includes a set of protrusions having an associated height and width, the set of protrusions naturally forming a complementary set of depressions, the set of depressions allowing the layers of thin film to maintain electrical communication.
Claim 6 The method for sputtering thin film layers in solar cell fabrication of claim 1, further comprising: patterning a first landscape for a first layer with a first mask, the first landscape including a first landscape pattern; and patterning a second landscape for a second layer with a second mask, the second landscape including a second landscape pattern.
Claim 7 The method for sputtering thin film layers in solar cell fabrication of claim 6, further comprising: depositing a sputtering target through an orthogonally oriented aperture while maintaining the initial vacuum state.
Claim 8 The method for sputtering thin film layers in solar cell fabrication of claim 6, further comprising: depositing a sputtering target through a directional aperture wherein deposition of the sputtering target is orthogonal to the substrate while maintaining the initial vacuum state. Claim 9 The method for sputtering thin film layers in solar cell fabrication of claim 6, wherein the second mask comprises a shadow mask having a rigid frame and a plurality of wires, the plurality of wires composed of a metal based alloy.
Claim 10 The method for sputtering thin film layers in solar cell fabrication of claim 9, further comprising: configuring the shadow mask according to the second landscape pattern; and depositing the second layer on the shadow mask wherein the second layer is an absorbent layer.
Claim 1 1 The method for sputtering thin film layers in solar cell fabrication of claim 9, further comprising: configuring the shadow mask according to the second landscape pattern wherein the shadow mask is a striped contact shadow mask; and depositing the second layer on the striped contact shadow mask wherein the second layer is an absorbent layer
Claim 12 The method for sputtering thin film layers in solar cell fabrication of claim 1 1, wherein the plurality of wires of the striped contact shadow mask are round wires having a predetermined diameter designed to form a set of depressions allowing the layers of thin film to maintain electrical communication.
Claim 13 The method for sputtering thin film layers in solar cell fabrication of claim 1 1, further comprising: shifting the striped contact shadow mask after depositing the second layer; and depositing a third layer wherein the layer is an insulating layer.
Claim 14 The method for sputtering thin film layers in solar cell fabrication of claim 9, further comprising: forming the rigid frame with a plurality of struts outwardly curved relative to the substrate, the plurality of struts configured to reduce slack in the plurality of wires during deposition.
Claim 15 A system for sputtering thin film layers in solar cell fabrication comprising: a carrier for loading a substrate through a main chamber; the main chamber having a process chamber for depositing a sputtering target in an initial vacuum state; and the process chamber having at least two associated transfer chambers for maintaining the initial vacuum state wherein each chamber includes an associated gate valve.
Claim 16 The system for sputtering thin film layers in solar cell fabrication of claim 15, further comprising: a plurality of process chambers; a first transfer chamber located at a proximal end of each one of the plurality of process chambers; and a second transfer chamber located at a distal end of each one of the plurality of process chambers. Claim 17 The system for sputtering thin film layers in solar cell fabrication comprising of claim 16, further comprising: a first process chamber configured for pulse mode direct current (DC) sputtering; and a second process chamber configured for radio frequency (RF) sputtering.
Claim 18 The system for sputtering thin film layers in solar cell fabrication of claim 15, wherein the process chamber further comprises: a dual sputtering target in the process chamber for simultaneous deposition of a plurality of elements forming an absorbent layer of thin film.
Claim 19 The system for sputtering thin film layers in solar cell fabrication of claim 18, wherein the dual sputtering target in the process chamber provides for a graded composition of the plurality of elements simultaneously deposited throughout the absorbent layer.
Claim 20 The system for sputtering thin film layers in solar cell fabrication of claim 18, wherein the absorbent layer is a composition of copper, indium, gallium and selenium.
Claim 21 The system for sputtering thin film layers in solar cell fabrication of claim 20, wherein a composition of zinc and tin (ZnSn) is substituted for indium. Claim 22 The system for sputtering thin film layers in solar cell fabrication of claim 20, wherein a composition of sulfur is substituted for selenium.
Claim 23 The system for sputtering thin film layers in solar cell fabrication of claim 16, wherein the gate valve associated with the process chamber is configured to allow a gas to enter at a predetermined pressure, the gas entering the process transfer chamber matching the environment of the second transfer chamber distal to the first process chamber.
Claim 24 The system for sputtering thin film layers in solar cell fabrication of claim 23 wherein the gas comprises argon.
Claim 25 The system for sputtering thin film layers in solar cell fabrication of claim 24 wherein the gas comprises hydrogen selenide.
Claim 26 The system for sputtering thin film layers in solar cell fabrication of claim 24 wherein the gas comprises hydrogen sulfide.
PCT/US2010/001836 2009-06-26 2010-06-26 In-line sputtering for improving thin film solar modules WO2010151339A1 (en)

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