WO2010143389A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2010143389A1
WO2010143389A1 PCT/JP2010/003752 JP2010003752W WO2010143389A1 WO 2010143389 A1 WO2010143389 A1 WO 2010143389A1 JP 2010003752 W JP2010003752 W JP 2010003752W WO 2010143389 A1 WO2010143389 A1 WO 2010143389A1
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WO
WIPO (PCT)
Prior art keywords
transparent member
resin
semiconductor element
substrate
semiconductor device
Prior art date
Application number
PCT/JP2010/003752
Other languages
English (en)
Japanese (ja)
Inventor
高山義樹
大広雅彦
丸尾哲正
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2010143389A1 publication Critical patent/WO2010143389A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention relates to a semiconductor device including light emitting / receiving elements.
  • Patent Document 1 proposes a structure in which a transparent member is directly attached to a light receiving region of a semiconductor element including a light receiving element with a transparent adhesive to reduce the size and thickness.
  • a transparent member is attached to the light receiving region via a transparent adhesive, and a semiconductor element having a plurality of bonding pads is die-bonded on the substrate. Each bonding pad and a plurality of connection terminals provided on the substrate are electrically connected by Au wires.
  • the side surface of the transparent member, the semiconductor element, and the Au wire are covered with a resin.
  • This structure eliminates the need for the area of the side wall portion where the conventional transparent member is bonded, and can reduce the size, and at the same time eliminates the space from the conventional chip to the transparent member, thereby reducing the thickness.
  • the surface of the upper mold portion of the mold (hereinafter referred to as the upper mold) is used so that the sealing resin does not protrude from the upper surface of the transparent member when resin molding is performed with the mold. It is necessary to increase the degree of adhesion between the transparent member and the upper surface of the transparent member.
  • the chip die-bonded on the substrate has a slight inclination with respect to the surface of the substrate
  • the transparent member bonded to the chip via a transparent adhesive also has a slight amount with respect to the surface of the chip. Since there is an inclination and the surface of the transparent member is slightly inclined with respect to the surface of the substrate, the surface of the upper mold and the upper surface of the transparent member are not sufficiently adhered.
  • the resin enters from the gap between the surface of the upper mold and the upper surface of the transparent member, adheres to the upper surface of the transparent member, and causes a problem that adversely affects the optical characteristics.
  • the present invention is less likely to cause the sealing resin to protrude from the upper surface of the transparent member in a semiconductor device including light emitting and receiving elements, thereby reducing the problems in optical properties, being small, and having a quality level. It is an object of the present invention to provide a high semiconductor device and a manufacturing method thereof.
  • a semiconductor device is die-bonded to a substrate, a protrusion provided on the substrate, and an upper surface of the protrusion, and at least one of a light receiving region and a light emitting region.
  • a semiconductor element having a transparent member attached to the light receiving region and the light emitting region, a side surface of the transparent member, and a resin covering the semiconductor element, and the area of the upper surface of the protrusion is The resin is filled in the gap between the lower surface of the semiconductor element and the substrate, which is smaller than the area of the lower surface of the semiconductor element.
  • the light receiving region and the light emitting region refer to regions having a light receiving function and a light emitting function, respectively, in the semiconductor element.
  • the gap between the lower surface of the semiconductor element and the substrate is filled with resin.
  • the protrusions are not limited in shape, size, and height, but in order to obtain good resin filling properties and sufficient push-up force from the lower direction,
  • the thickness is preferably 0.1 mm or more, and the area is preferably smaller than the area occupied by the transparent member on the semiconductor element.
  • the protrusion may be composed of a plurality of small protrusions.
  • the resin is also filled in the gap between the lower surface of the semiconductor element and the substrate.
  • 1A to 1C are a cross-sectional view and a back plan view of a semiconductor device according to an embodiment of the present invention.
  • 2A to 2H are cross-sectional views showing respective steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention.
  • each component is different from the actual dimensions from the viewpoint of easy understanding and drawing creation.
  • the number of components, such as electrodes and terminals is different from the actual number and is easy to show.
  • the material of each constituent member is not limited to the material described below.
  • FIG. 1A is a cross-sectional view and a back plan view of one embodiment of a semiconductor device according to an embodiment of the present invention.
  • a semiconductor element 2 having a light emitting / receiving region is die-bonded on a protrusion 10 of a substrate 3.
  • the semiconductor element 2 has the transparent member 1 attached to the light emitting / receiving area via the transparent adhesive 12 and has a plurality of bonding pads (not shown).
  • Each bonding pad and a plurality of connection terminals 6 provided on the substrate 3 are electrically connected by a bonding wire 5.
  • the side surface of the transparent member 1, the semiconductor element 2, and the bonding wire 5 are covered with a resin 4.
  • the upper surface of the transparent member 1 is exposed from the resin 4.
  • the feature of the semiconductor device according to the present embodiment is that the area of the protrusion 10 of the substrate 3 to which the semiconductor element 2 is die-bonded is smaller than the area of the lower surface of the semiconductor element 2.
  • the lower surface side of the semiconductor element 2 is also filled with resin.
  • the resin 4 is molded, when the resin is filled while pressing the upper surface of the transparent member 1 with the surface of the upper mold (not shown), the semiconductor 4 is filled with the resin 4 filled on the lower surface side of the semiconductor element 2. Since a force for pushing the element 2 upward is generated, the degree of adhesion between the upper mold surface and the upper surface of the transparent member is increased.
  • the shape of the upper surface of the protrusion 10 is not limited to the rectangle as shown in FIG. 1A, and may be a circle as shown in FIG. 1B, for example. Moreover, as shown in FIG.1 (c), the protrusion 10 may be comprised from the several small protrusion.
  • the height of the protrusion 10 is preferably 0.1 mm or more, and the area is preferably smaller than the area of the transparent member 1. Thereby, it is possible to obtain a good resin filling property and a sufficient pushing force from the lower surface side of the semiconductor element 2 upward.
  • the protrusion 10 may be formed by etching the substrate 3 or may be formed by adhering a resin member or a metal member to the substrate 3.
  • the material of the base material of the semiconductor element 2 may be, for example, silicon.
  • a light emitting diode, or the like for example, a III-V group compound or a II-VI group A compound or the like may be used.
  • the transparent member 1 has a size that can cover the entire surface of the light receiving and emitting region of the semiconductor element 2. Moreover, while the upper surface and lower surface of the transparent member 1 are processed into the mutually parallel optical plane, the side surface of the transparent member 1 is a plane perpendicular
  • the material of the transparent member 1 may be, for example, a borosilicate glass plate, or a quartz plate having birefringence characteristics in order to prevent moiré due to interference fringes in a specific direction or A low-pass filter made of calcite board may be used.
  • the material of the transparent member 1 may be a low-pass filter in which a quartz plate or a calcite plate is bonded to both sides of the infrared cut filter so that the birefringence characteristics are orthogonal to each other, or a transparent epoxy resin plate A transparent acrylic resin plate or a transparent alumina plate may be used.
  • the thickness of the transparent member 1 is set in the range of 200 ⁇ m to 1000 ⁇ m, preferably in the range of 300 ⁇ m to 700 ⁇ m.
  • the reason why the lower limit of the thickness of the transparent member 1 is set to 200 ⁇ m is that the mounting height at the time of mounting the semiconductor device composed of the transparent member 1, the transparent adhesive 12, the resin 4, the semiconductor element 2, etc. is set to 500 ⁇ m or less. This is for realizing a small size and a thin shape.
  • the reason why the upper limit of the thickness of the transparent member 1 is set to 1000 ⁇ m is to realize a transmittance of 90% or more for incident light having a wavelength of 500 nm.
  • the reason why the preferable range of the thickness of the transparent member 1 is set to a range from 300 ⁇ m to 700 ⁇ m is that the most stable semiconductor device can be produced by using the current manufacturing technology, and a low-cost general-purpose product as a constituent member This is because an inexpensive, small and thin semiconductor device is realized by using the above.
  • the thickness of the transparent member 1 when using a transparent alumina or transparent resin as a material of the transparent member 1, it is necessary to determine the thickness of the transparent member 1 in consideration of a difference in transmittance of each material constituting the transparent member 1.
  • quartz or calcite when quartz or calcite is used as the material of the transparent member 1, the distance between the double imaging due to birefringence is related to the thickness of the transparent member 1. It is necessary to determine the thickness of the transparent member 1 in consideration of the pixel interval in the light emitting / receiving area of the element 2.
  • the transparent adhesive 12 is an optically transparent adhesive used when the transparent member 1 is fixed on the light emitting / receiving region of the semiconductor element 2.
  • the material of the transparent adhesive 12 for example, an acrylic resin, or an epoxy resin or a polyimide resin in which a resin is blended so as not to have an absorption band within the wavelength range of visible light can be used.
  • the resin 4 is a light-shielding resin formed so as to cover a portion of the upper surface of the semiconductor element 2 excluding the light emitting / receiving region (that is, the region where the transparent member 1 is formed) and the side surface of the transparent member 1.
  • the upper surface of the resin 4 is flat, and the thickness of the resin 4 on the upper surface of the semiconductor element 2 is approximately the same as that of the transparent member 1.
  • an epoxy resin may be used, or low in order to reduce the thickness of the base material of the semiconductor element 2, improve the thermal shock resistance and moisture resistance of the semiconductor device, and the like.
  • An elastic cured product such as biphenyl resin or silicon resin may be used.
  • the resin 4 when the resin 4 is molded by transfer molding using a molding die, for example, the resin 4 is composed of an epoxy resin and a curing agent which are main materials in a state where the semi-cured powder resin is tableted.
  • a curing accelerator, silica powder as an inorganic filler, flame retardant, carbon black as a pigment, and a release agent are main materials in a state where the semi-cured powder resin is tableted.
  • the selection and blending amount of the inorganic filler and the pigment constituting the resin 4 are important for the warp and light shielding performance of the semiconductor device. Further, in order to reduce the water absorption rate of the curing agent and prevent disconnection failure due to the corrosion of the wiring of the semiconductor element 2, high-purity silica that has been melted to remove crystallinity is processed into spherical shapes of various diameters. Therefore, it is used by properly blending as a curing agent.
  • the pigment is blended as much as possible in the curing agent of the resin 4 within a range in which the electrical resistance in the curing agent of the resin 4 is lowered in a high temperature and high humidity environment and does not induce poor insulation of the semiconductor device.
  • the incident light around the transparent member 1 is prevented from entering the side surface of the transparent member 1 and becoming stray light.
  • carbon black having a high light-shielding color tone as the pigment, a part of incident light from the resin 4 passes through the side surface of the transparent member 1 and the upper surface (main surface) of the semiconductor element 2.
  • 2 (a) to 2 (h) are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • a plurality of semiconductor elements 2 having a plurality of bonding pads are die-bonded on a substrate 3.
  • the semiconductor elements 2 are arranged in a two-dimensional matrix at a predetermined interval.
  • the transparent member 1 is attached to each semiconductor element 2 in advance via a transparent adhesive 12 on the light emitting / receiving area.
  • each bonding pad on each semiconductor element 2 and a corresponding connection terminal 6 provided on the substrate 3 are electrically connected by a bonding wire 5.
  • the resin 4 that seals the side surface of the transparent member 1, the semiconductor element 2, and the bonding wire 5 while covering the upper surface (main surface) of the transparent member 1 with the release sheet 9. Perform molding.
  • a material of the release sheet 9 for example, a fluororesin is used.
  • a resin 4 is filled in a space between the semiconductor elements 2 arranged in a two-dimensional matrix on the substrate 3 and having the transparent member 1 attached thereto.
  • the upper mold 7 and the lower mold 8 are removed from the resin-sealed substrate 3.
  • FIG. 2F shows a state where the transparent member 1 side is attached to the dicing sheet 13
  • the substrate 3 side die pad side
  • dicing is performed by the dicing blade 11 on the substrate 3 on which the plurality of semiconductor elements 2 are arranged in a two-dimensional matrix.
  • the substrate 3 is divided into pieces for each semiconductor element 2, and a plurality of semiconductor devices can be formed in a lump.
  • each semiconductor device is separated from the dicing sheet 13 and cleaned.
  • a plurality of semiconductor devices can be collectively formed by cutting the substrate 3 and separating it into individual pieces for each semiconductor element 2 after resin sealing. Further, when the resin sealing is performed while clamping the substrate 3 with the release sheet 9 interposed between the surface of the upper mold 7 and the upper surface of the transparent member 1, the lower surface of the semiconductor element 2 is also filled with resin. . Therefore, a force to push upward from the lower surface side of the semiconductor element 2 is applied, the adhesion force between the surface of the upper mold 7 and the upper surface of the transparent member 1 is increased, and the upper surface of the transparent member 1 covered with the release sheet 9 is increased. Becomes difficult for the resin 4 to enter. Therefore, it is possible to realize a semiconductor device with few problems in optical characteristics due to the protrusion of the resin 4 on the upper surface of the transparent member 1 and the lower surface of the substrate 3.
  • the present invention is suitable for a semiconductor device and a manufacturing method thereof, for example, an image sensor such as a mobile phone, a digital camera, a digital video camera, and the manufacturing thereof.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Led Device Packages (AREA)

Abstract

L'invention porte sur un dispositif à semi-conducteur qui comprend : un élément à semi-conducteur (2) comprenant un organe transparent (1) fixé sur une zone de réception/émission de lumière et comprenant également de multiples plots de connexion ; un substrat (3) comprenant une saillie (10) à laquelle l'élément à semi-conducteur (2) est fixé par fixage de puce ; de multiples bornes de connexion (6) disposées sur le substrat (3) ; un fil de connexion (5) qui connecte électriquement les multiples plots de connexion aux bornes de connexion (6) correspondantes, respectivement ; et une résine (4) qui couvre une surface latérale de l'organe transparent (1), l'élément à semi-conducteur (2) et le fil de connexion (5). Dans le dispositif à semi-conducteur, la surface de la saillie (10) dans le substrat (3) est plus petite que celle de l'élément semi-conducteur (2).
PCT/JP2010/003752 2009-06-08 2010-06-04 Dispositif à semi-conducteur WO2010143389A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-137762 2009-06-08
JP2009137762A JP2010283311A (ja) 2009-06-08 2009-06-08 半導体装置

Publications (1)

Publication Number Publication Date
WO2010143389A1 true WO2010143389A1 (fr) 2010-12-16

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WO (1) WO2010143389A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9287472B2 (en) 2013-06-27 2016-03-15 Nichia Corporation Light emitting device and method of manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006179718A (ja) * 2004-12-22 2006-07-06 Sony Corp 青色光学素子パッケージ及び光学素子パッケージの製造方法
JP2007123481A (ja) * 2005-10-27 2007-05-17 Kyocera Corp 発光素子用配線基板ならびに発光装置
JP2008047834A (ja) * 2006-08-21 2008-02-28 Hamamatsu Photonics Kk 半導体装置および半導体装置製造方法
JP2008192710A (ja) * 2007-02-01 2008-08-21 Nichia Chem Ind Ltd 半導体発光素子

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006179718A (ja) * 2004-12-22 2006-07-06 Sony Corp 青色光学素子パッケージ及び光学素子パッケージの製造方法
JP2007123481A (ja) * 2005-10-27 2007-05-17 Kyocera Corp 発光素子用配線基板ならびに発光装置
JP2008047834A (ja) * 2006-08-21 2008-02-28 Hamamatsu Photonics Kk 半導体装置および半導体装置製造方法
JP2008192710A (ja) * 2007-02-01 2008-08-21 Nichia Chem Ind Ltd 半導体発光素子

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