WO2010086153A1

WO2010086153A1 - Graded well implantation for asymmetric transistors having reduced gate electrode pitches

Info

Publication number: WO2010086153A1
Application number: PCT/EP2010/000491
Authority: WO
Inventors: Robert Mulfinger; Andy Wei; Jan Hoentschel; Vassilios Papageorgiou
Original assignee: AMD Fab 36 LLC and Co KG; Advanced Micro Devices Inc; AMD Fab 36 LLC
Current assignee: GlobalFoundries Dresden Module One LLC and Co KG; Advanced Micro Devices Inc; AMD Fab 36 LLC
Priority date: 2009-01-30
Filing date: 2010-01-27
Publication date: 2010-08-05
Anticipated expiration: 2011-07-30

Abstract

In sophisticated semiconductor devices and asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.

Description

GRADED WELL IMPLANTATION FOR ASYMMETRIC TRANSISTORS HAVING REDUCED GATE ELECTRODE PITCHES

FIELD OF THE PRESENT DISCLOSURE

The present disclosure generally relates to the fabrication of integrated circuits and more particularly to the asymmetric field effect transistor elements and respective tilted implantation techniques so as to enhance transistor performance.

DESCRIPTION OF THE PRIOR ART

Integrated circuits typically include a large number of individual circuit elements, such as transistors, capacitors, resistors, and the like. These individual circuit elements are electrically connected according to the desired circuit layout by respective conductive lines, which are mainly formed in separate "wiring" layers that are typically referred to as metallization layers. For enhancing performance of the integrated circuit usually the number of individual circuit elements is increased, thereby obtaining a more complex functionality of the circuit, which in turn requires to reduce the feature sizes of the individual circuit elements. Generally, a plurality of process technologies are currently practiced wherein for logic circuitry, such as microprocessors, storage chips and the like, CMOS technology is presently the most promising approach due to the superior characteristics in view of operating speed and/or manufacturing costs and/or power consumption. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., n-channel transistors and p- channel transistors, are formed in and on an appropriate crystalline semiconductor material, wherein currently the vast majority of logic circuitry is fabricated on the basis of silicon. Typically, a MOS transistor, irrespective of whether an n-channel transistor or a p-channel transistor is considered, comprises so-called pn-junctions that are formed at an interface of highly doped drain and source regions with a channel region disposed between the drain region and the source region, wherein the channel region is at least partially inversely doped with respect to the drain and source regions. The conductivity of the channel region, which represents an essential device criterion as the reduced current drive capability of scaled devices has to, at least partially, be compensated by an increased conductivity, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region depends on the dopant concentration, the mobility of the charge carriers and - for a given dimension of the channel region in the transistor width direction - the distance between the source and drain regions, which is also referred to as channel length. In addition to the channel conductivity, the transistor performance is also significantly influenced by the capability of rapidly creating a conductive channel in the channel region upon application of a specified control voltage to the gate electrode, since usually the transistors are operated in a switched mode requiring a fast transition from the transistor on-state to the transistor off-state and vice versa. Moreover, other aspects have also to be taken into consideration when designing a transistor of high performance circuits. For instance, static and dynamic leakage currents may significantly affect the overall performance of an integrated circuit, as the achievable amount of heat dissipation that is required for transistor architectures producing high dynamic and/or static leakage currents, may restrict the maximum practical operating frequency. In other cases the controllability of the channel region may be degraded in devices with very short channel lengths, thereby requiring sophisticated dopant profiles in the drain and source regions.

With reference to Fig. 1a, a typical transistor architecture of a field effect transistor element will now be described in more detail in order to more clearly explain some of the problems encountered in currently used transistor designs. In Fig. 1a, a transistor element 100 comprises a substrate 101 , which may represent a bulk semiconductor substrate such as a silicon substrate, or any other appropriate substrate having formed thereon a crystalline semiconductor layer, which may typically be formed on the basis of silicon for logic circuitry. Thus, the substrate 101 is to be considered as a substrate having formed thereon a substantially crystalline semiconductor region 102, in which are formed a drain region 104 including a so-called extension region 104e. Similarly, a source region 103 is formed in the crystalline region 102 and includes an extension region 103e. The area disposed between the extension regions 103e and 104e is referred to as a channel region 105, since here typically a conductive channel is created during the on-state of the transistor 100, as will described later on. Located above the channel region 105 is a gate electrode structure 106 that includes a gate electrode 107 and sidewall spacers 108. Moreover, a gate insulation layer 109 is provided between the gate electrode 107 and the semiconductor region 102 so as to electrically insulate the gate electrode 107 from any conductive regions within the crystalline semiconductor region 102. Regarding the design and material composition of the gate electrode structure 106, it is to be noted that in principle the gate electrode 107 may be considered as a conductive line, the "width" dimension of which is referred to as gate length 107a, whereas the "length" of the line, extending in a direction perpendicular to the drawing plane, is referred to as the gate width (not shown in Fig. 1a). The gate electrode 107 may be comprised of any appropriate material and is typically formed in advanced silicon based integrated circuits of heavily doped polysilicon in combination with a highly conductive metal suicide, such as nickel suicide, cobalt suicide, and the like. However, depending on the process strategy and the design criteria, other materials such as metals may be used. The gate insulation layer 109 may be comprised of any appropriate insulating material such as silicon dioxide, silicon nitride, and/or high-k materials so as to provide for a required electrical insulation while maintaining a high capacitive coupling to the channel region 105. Hence, for well approved silicon dioxide based gate insulation layers a thickness of the gate insulation layer 109 is of the order of a few nanometres, for example 2 nm and less, thereby causing moderately high static leakage currents, which may amount up to approximately 30% or even more of the overall electrical losses of advanced transistor elements.

During the manufacturing process, the substrate 101 is treated so as to form the semiconductor region 102 with high crystalline quality which may be achieved by epitaxial growth and the like. Thereafter, photolithography, etch and deposition processes may be performed to define the dimensions of the semiconductor region 102 by providing appropriate isolation structures (not shown). Thereafter, implantation sequences may be carried out so as to position one or more dopants within the crystalline semiconductor region 102 to thereby form a specified vertical dopant profile (not shown) within the region 102, which may finally result in a specified vertical dopant profile in the channel region 105. Next, material layers for the gate insulation layer 109 and the gate electrode 107 may be formed, for instance by advanced oxidation and/or deposition techniques for the gate insulation material and by advanced low pressure chemical vapour deposition (CVD) for a polycrystalline silicon layer as a gate electrode material. Thereafter, highly sophisticated photolithography and etch techniques may be employed so as to pattern the gate electrode material and the gate insulation layer material to form the gate electrode 107 and the gate insulation layer 109 on the basis of the design gate length 107a. Thereafter, complex implantation cycles may be performed so as to create the drain and source regions 103, 104 and the corresponding extensions 103e, 104e wherein the gate electrode 107 partially in combination with the sidewall spacers 108 acts as an implantation mask. For example, according to one strategy, a so-called pre-amorphization implantation may be carried out, during which a heavy ion species, such as xenon ions and the like, may be implanted into the crystalline semiconductor region 102 so as to substantially completely destroy the crystalline lattice to a specified depth, which may enhance performance of subsequent implantation and anneal processes. During the pre-amorphization implantation, the ion beam may be tilted with respect to a direction 110 perpendicular to the substrate 101 so as to also amorphize an area of the region 102 corresponding to the extension regions 103e, 104e. Thereafter, a so-called halo or counter-doping implantation may be performed in which an ion species is introduced that represents the same conductivity type as is already present in the channel region 105 so as to enhance the dopant concentration of this ion species within specific halo regions, which are indicated as 111. Similarly to the pre- amorphization implantation, the halo implantation may be performed with respective tilt angles, such as α and -α so as to form the halo regions 111 at the drain side and the source side. Subsequently, a further implantation may be performed with an ion species having the opposite conductivity type with respect to the halo implantation so as to form the source extension 103e and the drain extension 104e, wherein possibly an additional offset spacer (not shown) may be formed on sidewalls of the gate electrode 107 prior to the implantation. Thereafter, the sidewall spacer 108 may be formed and may be used in a subsequent implantation process as an implantation mask so as to form the deep and heavily doped drain and source regions 104, 103. Thereafter, the transistor element 100 may be annealed, thereby activating the dopants introduced by the preceding implantation sequences, i.e., initiating a diffusion so as to place the dopants at lattice sites while substantially recrystallizing those portions of the region 102 that were damaged by the pre-amorphization and the subsequent implantation processes. During this anneal cycle, thermally induced diffusion of the dopants occurs in accordance with the respective concentration gradient of the dopant species under consideration, thereby substantially determining the finally obtained size and characteristics of the drain and source regions 104, 103 and the corresponding extension regions 104e, 103e as well as the characteristics of pn-junctions 103p and 104p defined as an interface area between the halo implantation region 111 and the respective drain or source region 104, 103. During the implantation cycles and/or during the subsequent anneal cycle, a certain amount of overlap, referred to as overlap regions 103o and 104o is created, which also significantly affects the transistor behaviour. Thereafter, the manufacturing process may be continued with the formation of metal suicide regions in the drain and source regions 104, 103 and in the gate electrode 107 followed by the formation of an interlayer dielectric and respective contacts to the drain and source regions 104, 103 and the gate electrode 107. For convenience, these components are not shown in Fig. 1a.

During operation typically a supply voltage is applied to the drain region 104 and the source region 103, for example 1 to 5 volts for typical CPUs, while a corresponding control voltage is applied to the gate electrode 107 so as to define the conductivity state of the channel region 105. For the following discussion the transistor 100 is considered to represent an n-channel enhancement type transistor in which the channel region 105 is p-doped and the drain and source regions 104, 103 and the corresponding extensions 104e, 103e are heavily n-doped. For a p-channel enhancement type transistor, the type of charge carriers involved and the conductivity type of the dopants may be inverted. Also, the following explanations in principle apply to depletion type transistors. Hence, upon application of a control voltage to the gate electrode 107 below a specific threshold voltage which is determined, among others, by the vertical dopant profile within the channel region 105, the transistor 100 is in the off-state, that is the pn-junction 104p is inversely biased and hence a current from the source region 103 through the channel region 105 to the drain region 104 is substantially suppressed. However, during the off- state the high electrical field prevailing at the overlap 104o may lead to tunnel currents into the gate electrode 107, especially when the gate insulation layer 109 is moderately thin, as is the case in sophisticated transistor devices. These currents may be considered as static leakage currents. Moreover, the overlap region 104o in combination with the overlying gate electrode 107 and the gate insulation layer 109 forms a capacitor, which has to be charged and discharged when operating the transistor 100 in a switched mode.

During application of a control voltage exceeding the threshold voltage, a conductive channel is formed in the channel region 105 originating from the source-side extension region 103e and terminating at the drain-side extension region 104e. For the building up of the conductive channel, in the present case created by electrons, the overlap region 103o as well as the relatively steep concentration gradient of the pn-junction 103p, created by the increased dopant concentration of the halo region 111 , is advantageous in obtaining a high on-current. Contrary thereto the steep concentration gradient at the pn- junction 104p may lead to enhanced currents into the substrate 101 , that is, in lower lying crystalline areas of the region 102, which may finally be drained off by a corresponding body contact, so that the dynamic leakage currents may also increase with an increase of the on-current. Moreover, during the building up of the conductive channel the parasitic capacitances caused by the overlaps 104o, 103o may require high currents for recharging the parasitic capacitor and may delay the start of the on-state, thereby degrading the raise and fall times during the switching operation.

As can be seen from the above discussion, in addition to the overall geometric configuration of the transistor 100, such as transistor length and width, as well as material compositions, dopant concentrations and the like, also the lateral and vertical dopant profiling within the semiconductor region 102 significantly affects the finally obtained transistor performance.

Due to the ongoing scaling of transistor elements, resulting in a continuously increased operation speed, tilted implantation processes may represent an important manufacturing strategy for obtaining the required complex dopant profiles. For example, as described above, the halo implantations may have to be performed with a specified tilt angle in order to precisely adjust the overall final dopant gradient at the pn junctions. Furthermore, as explained above, in sophisticated semiconductor devices an asymmetric transistor configuration may be implemented, for instance by selecting different overall dopant profiles at the drain side and source side so as to enhance overall drive current capability and channel controllability, for instance by increasing the overlap between the drain and source regions at one side, such as the source side, while reducing the overlap at the drain side, wherein also the corresponding dopant gradients may appropriately be adjusted. In other cases, an asymmetric configuration of drain and source regions may be accomplished by performing an asymmetric halo implantation, at least for specific transistor elements, depending on the overall device configuration. Consequently, during the complex manufacturing flow for defining the dopant profiles a plurality of masking and implantation steps may have to be performed, in which transistor areas of one type of transistor may have to be protected, while other transistors have to be exposed to a tilted implantation step. However, for extremely scaled transistor devices the distance between neighbouring transistor elements may be in the range of several hundred nanometers and significantly less, while at the same time the height of the gate electrode structures may not arbitrarily be reduced in view of the ion blocking capability during the drain and source implantation processes so that for reduced distances between neighbouring transistor elements, a certain degree of shadowing during a tilted implantation process may occur. This situation may even become more serious when certain transistors in densely spaced device regions may have to be masked during a tilted implantation process, since the corresponding implantation mask may further contribute to an increased shadowing effect, which may even prevent the ion species to reach the active region, thereby significantly contributing to transistor performance degradation. On the other hand, the overall thickness of the resist material used for providing the implantation masks may not arbitrarily be reduced, as will be explained with reference to Figs 1 b and 1 c.

Fig 1b illustrates a resist reflectivity versus a thickness of a typical resist material used in advanced photolithography techniques. As is shown, a typical swing curve with several minima, for instance at approximately 280 nm and 210 nm may be obtained. Since the overall performance of the lithography process may be influenced by the magnitude of reflectivity, in view of overall lithography performance it would be preferable to use increased resist thickness, for instance at approximately 280 nm, in order to provide for a reduced reflectivity. On the other hand, an increased resist thickness may not be compatible with performance during tilted implantation processes.

Fig 1c schematically illustrates the situation in sophisticated semiconductor devices. As illustrated, a semiconductor device 150 may comprise a plurality of transistors 100a

100d at an early manufacturing stage. The transistors 100a 100d may have substantially the same configuration as previously described wherein, however, the gate length 107a may be approximately 50 nm and less. Furthermore, the semiconductor device 150 is shown at a tilted implantation process 120, which may represent a tilted halo implantation and/or a tilted implantation process for defining drain and source extension regions, as previously explained. As discussed above, during the tilted implantation process 120 some of the transistors 100a, ..., 100d may have to be protected, such as the transistors 100a and 100c, for instance these transistors may represent transistors of different conductivity type or the basis dopant profile has to be adjusted differently compared to the non-masked transistors 100b, 100d. For this purpose, an implantation mask 121 , that is, a resist mask, is provided so as to cover the transistors 100a, 100c. For a given distance, indicated as D, that depends on the overall design rules for the device 150, and for a given tilt angle α, which may range between 20 and 30 degrees, the height of the resist mask 121 , indicated as 121 h, may result in a certain degree of shadowing of the active region of the transistors 100b, 10Od, as is indicated by the dashed lines. Consequently, an increased resist thickness, which may be desirable in view of enhancing the overall lithography performance due to a reduced reflectivity may not be compatible with the resulting shadowing effect. On the other hand, a certain minimum resist thickness may be required to provide for a sufficient lithography performance, for instance with respect to defining critical dimensions of the resist mask 121 and the like. For example, maintaining a reduced resist thickness above the gate electrode structures 107 may result in a significant difference in the photochemical behaviour of the resist material formed above the gate electrodes 107 and above other device regions without gate electrodes. For example, the photochemical reaction may proceed with significantly increased speed above the gate electrode structures 107, thereby causing a reduced line thickness of the masks 121 or the transistors 100a, 100c, which in turn may result in a reduced blocking effect during the tilted implantation process 120. As previously discussed, a significant reduction of the height of the gate electrodes 107 may not be a viable option since the ion blocking effect of the gate electrode 107 may have to be adapted to the requirements of an implantation process for defining the deep drain and source areas in a later manufacturing stage. Consequently, the height of the gate electrodes 107 may not be reduced in proportion to a reduction of the distance D during a further device scaling. On the other hand, reducing the tilt angle α may result in a significant degradation of performance of the transistors 100a, ... 100d. Consequently, for a given device geometry, that is, the distance D and the gate height, conventionally a compromise between the height 121h of the resist masks 121 and the tilt angle α is to be used, thereby causing a significantly less pronounced performance gain as would be desired for the technology standard under consideration.

In view of the situation described above, the present disclosure relates to techniques for providing for enhanced asymmetric dopant profiles in sophisticated transistors, while avoiding or at least reducing the effects of one or more of the problems identified above.

SUMMARY OF THE DISCLOSURE

Generally, the present disclosure relates to semiconductor devices and techniques for forming an asymmetric transistor configuration on the basis of a process technique that enables a high degree of scalability with respect to any advances in semiconductor manufacturing techniques that may require further reduced critical dimensions of the corresponding transistor elements. To this end, an asymmetric well dopant profile may be created in the source and drain areas of asymmetric transistors by using an appropriately designed implantation mask having a different ion blocking capability for the drain and source areas. Consequently, sophisticated tilted implantation processes, which may typically require a certain compromise between tilt angle and thickness of the implantation mask, may be avoided thereby increasing gain in performance of asymmetric transistor configurations for highly sophisticated transistor elements including devices with critical dimensions of approximately 50 nm and less. Moreover, the desired asymmetric configuration of high performance transistors may be accomplished on the basis of well-established circuit layouts, ie. on the basis of circuit layouts in which symmetric and asymmetric transistors may be provided in close proximity to each other, substantially without being constrained by gate height and gate pitch of neighbouring transistors as is typically the case for conventional strategies using a tilted implantation sequence for increasing the counter doping in the source areas of asymmetric transistors. In some illustrative aspects disclosed herein, the implantation mask providing for the different ion blocking capabilities may be formed in an early manufacturing stage on the basis of a superior device topography so that a corresponding mask configuration, such as a graded mask profile, may be provided on the basis of lithography techniques, etch techniques and the like.

One illustrative method disclosed herein comprises forming an implantation mask above a semiconductor region wherein the implantation mask has a first ion blocking capability above a first transistor internal area of a transistor and having a second ion blocking capability above a second transistor internal area of the transistor, and wherein the first and second ion blocking capabilities differ from each other. Moreover, the method comprises implanting a well dopant species into the first and second transistor internal areas on the basis of the implantation mask. Finally, the method comprises forming a gate electrode above a channel area of the semiconductor region, wherein the channel area laterally separates the first and second transistor internal areas.

A further illustrative method disclosed herein comprises forming a graded implantation mask above a first transistor internal area and a second internal area of a transistor, wherein the graded implantation mask provides a first ion blocking capability for the first transistor internal area and a second increased ion blocking capability for the second transistor internal area. The method additionally comprises introducing a well dopant species in the first and second transistor internal areas on the basis of the implantation mask. Moreover, the method comprises forming drain and source regions on the basis of the first and second transistor internal areas so as to obtain an asymmetric transistor configuration.

One illustrative semiconductor device disclosed herein comprises a gate electrode structure formed above a channel region. Moreover, a drain region and a source region are formed in a well region and are laterally separated by the channel region. Additionally, a dopant concentration of a well dopant species gradually increases in a lateral direction from the channel region to a periphery of the transistor at least at a source side of the transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

Further embodiments of the present disclosure are defined in the appended claims and will become more apparent with the following detailed description when taken with reference to the accompanying drawings, in which:

Fig 1a schematically illustrates a cross-sectional view of a typical conventional architecture of a field effect transistor with a complex dopant profile formed by tilted halo implantations;

Fig 1b schematically illustrates a swing curve of a resist material;

Fig 1c schematically illustrates a cross-sectional view of a semiconductor device including a plurality of extremely scaled transistor elements during a tilted implantation process and corresponding implantation masks requiring a compromise between resist thickness and tilt angle according to conventional strategies;

Figs 2a and 2b schematically illustrate a cross-sectional view and a top view, respectively, of a semiconductor device at an early manufacturing stage during a process sequence for defining a well dopant concentration in an active semiconductor region according to illustrative embodiments;

Fig 2c schematically illustrates the semiconductor device in a further advanced manufacturing stage in which a resist material may be exposed so as to obtain a graded lateral image according to illustrative embodiments;

Figs 2d and 2e schematically illustrate cross-sectional views of the semiconductor device that may be processed on the basis of a graded implantation mask for obtaining an asymmetric well dopant concentration at least in specific areas of the active semiconductor regions according to illustrative embodiments;

Fig 2f schematically illustrates a cross-sectional view of the semiconductor device in a further advanced manufacturing stage in which an asymmetric transistor and symmetric transistors may be formed in and above the common active semiconductor region according to illustrative embodiments;

Figs 2g - 2i schematically illustrate cross-sectional views of the semiconductor device according to still further illustrative embodiments in which an implantation mask having a graded thickness profile may be formed as a non-resist material according to still further illustrative embodiments; and

Fig 2j schematically illustrates the semiconductor device according to illustrative embodiments in which a graded implantation mask may be provided in an advanced manufacturing stage, ie. after forming corresponding gate electrode structures.

DETAILED DESCRIPTION

While the present disclosure is described with reference to the embodiments as illustrated in the following detailed description as well as in the drawings, it should be understood that the following detailed description as well as the drawings are not intended to limit the present disclosure to the particular illustrated embodiments disclosed, but rather the described illustrative embodiments merely exemplify various aspects of the present disclosure, the scope of which is defined by the appended claims. In general, the present disclosure provides techniques and semiconductor devices in which an asymmetric transistor configuration may be provided with a high degree of independence with respect to the overall device dimension, such as the length of gate electrodes and the pitch between adjacent symmetric and asymmetric transistor elements. For this purpose, an asymmetry may be introduced by providing an asymmetric well dopant concentration, which may thus have a similar effect compared to conventional asymmetric halo or counter doping implantation processes wherein, however, the asymmetric well dopant profile may be established without requiring sophisticated tilted implantation techniques. For this purpose, an appropriate implantation mask may be applied which results in different time blocking capabilities during a substantially non-tilted sequence for defining the well configuration of the transistor elements. For instance, a different thickness of the implantation mask may provide for a different degree of ion blocking capability above the source area compared to the drain area, thereby enabling, in combination with a corresponding additional non- masked well dopant process, if required, the desired basic doping of p-channel transistors and n-channel transistors. For instance, based on a reduced ion blocking capability above the source side of a transistor an increased concentration and thus overall amount of well dopant species may be incorporated, thereby generating increased field strength in combination with corresponding drain and source implantation dopant profiles. Since the asymmetric configuration of the basic well dopant concentration may be accomplished without requiring sophisticated tilted implantation sequences, at least for introducing the well dopant species, extremely delicate adaptations of resist thickness in view of gate height and gate pitch in sophisticated semiconductor devices may be avoided, thereby providing for enhanced overall process flexibility and also obtaining scalability of the asymmetric transistor configurations disclosed herein. Consequently, complex re-designs of basic circuit layouts may not be necessary, which may conventionally have to be contemplated in order to obtain a high performance gain based on the asymmetric transistor configuration when symmetric and asymmetric transistors may have to be provided in close proximity to each other.

As a consequence, superior design flexibility may be combined with enhanced transistor performance of an asymmetric transistor irrespective of the technology standard under consideration by using the principles disclosed herein. With reference to Figs 2a - 2j further illustrative embodiments will now be described in more detail, wherein reference also be made to Figs 1a - 1c, if required.

Fig 2a schematically illustrates a cross-sectional view of a semiconductor device 250, which may comprise a substrate 201 and a semiconductor layer 202. The substrate 201 may represent any appropriate carrier material for forming thereabove the semiconductor layer 202. For example, the substrate 201 may represent a semiconductor substrate, an insulating substrate and the like. The semiconductor layer 202 may represent a silicon- based material, that is, a material including a significant portion of silicon, wherein also other components such as germanium, carbon and the like may be incorporated in order to establish the overall electronic characteristics required for the device 250. It should be appreciated, however, that the semiconductor layer 202 may be comprised of any other appropriate semiconductor material, depending on the overall device requirements. Furthermore, in some cases the semiconductor layer 202 in combination with the substrate 201 may form an SOI (silicon on insulator) configuration, wherein a buried insulating layer (not shown) may be positioned between the substrate 201 and the semiconductor layer 202. In other cases, the semiconductor layer 202 may represent a part of a substantially crystalline semiconductor material of the substrate 201 , thereby defining a "bulk" configuration. In some illustrative embodiments an isolation structure 202b may be formed in the semiconductor layer 202 and may extend to a specific depth, thereby defining or delineating an active region 202a, which is to be understood as a semiconductor region in which appropriate dopant profiles are to be established so as to form drain and source regions for one or more transistor elements. The isolation structures 202b may, for instance, by provided in the form of a shallow trench isolation, which may extend down to a buried insulating layer, if provided. For this purpose, any appropriate dielectric material, such as silicon dioxide, silicon nitride and the like, may be used in accordance with well-established device configurations. In other illustrative embodiments (not shown in Fig 2a) the isolation structures 202b may have still to be formed in the semiconductor layer 202.

The semiconductor device 250 as illustrated in Fig 2a may be formed on the basis of appropriate manufacturing techniques and design strategies in order to appropriately define a size and shape of the active region 202a in accordance with overall device requirements. For instance, as previously explained, the active region 202a may be selected so as to accommodate symmetric and asymmetric transistors in close proximity to each other, as is also discussed above with reference to the semiconductor device 150 of Fig 1c. Moreover, if the isolation structures 202b are to be provided in the manufacturing stage as illustrated in Fig 2a, corresponding techniques including photo lithography, etch, deposition and planarization processes may be performed by using well-established device techniques. Thereafter, in some illustrative embodiments, an implantation process 215 may be performed in order to introduce desired well dopant species into the active region 202a at a desired concentration so as to establish, in combination with further implantation sequence based on a specifically designed implantation mask, at least locally within the region 202a, an asymmetric doping. It should be appreciated that in other illustrative embodiments the implantation process 215 may be performed in a later manufacturing stage, for instance after introducing an asymmetric dopant concentration, at least in a desired area of the active region 202a. The implantation process 215 may be performed on the basis of appropriately selected parameters, such as dose and energy for a given well dopant species, while other active regions requiring a different type of dopant species may be covered by a resist mask. Thereafter, the region 202a may be covered by a resist mask and other active regions may be exposed to an appropriate ion bombardment for introducing the required well dopant species therein.

Fig 2b schematically illustrates a top view of the semiconductor device 250, wherein the isolation structure 202b, if already provided, may laterally enclose the active region 202a, which may be dimensioned so as to accommodate at least one symmetric transistor device 200a and one asymmetric transistor device 200b positioned adjacent to each other. In the embodiment shown, a further transistor 200c may have to be formed in the active region 202a, which may also represent a symmetric transistor so that the asymmetric device 200b may be positioned between the two symmetric transistors 200a, 200c, which may conventionally result in a significantly reduced performance gain when establishing an asymmetric transistor configuration on the basis of a tilted implantation process using a corresponding resist mask, as previously explained with reference to Fig 1c.

Fig 2c schematically illustrates the semiconductor device 250 in a further advanced manufacturing stage in which a mask material 221 may be formed above the active region 202a, thereby covering the respective portions of the region 202a that may correspond to the transistors 200a, 200b, 200c still to be formed. In one illustrative embodiment the mask material 221 may be provided in the form of a radiation sensitive material, such as photo resist and the like, with an appropriate thickness so as to provide for the desired basic ion blocking capability with respect to an implantation process to be performed in a later manufacturing stage in order to introduce a well dopant species into the portion of the active region 202a corresponding to the transistor 200b in an asymmetric manner. For this purpose, in one illustrative embodiment, the device 250 may be subjected to an exposure process 222 in which the amount of radiation energy deposited in the mask material 221 above the active region of the transistor 200b may vary in a lateral direction, ie. in Fig 2c along the horizontal direction, so as to result in a varying degree of exposure of the corresponding resist material, thereby resulting in a varying degree of photochemical reaction in the mask material 221. For instance, as illustrated, a substantially gradual lateral variation may be accomplished during the exposure process 222 within the active region of the device 200b so that the accumulated exposure dose in the resist material 221 positioned above the first transistor internal area 251s of the transistor 200b may be greater compared to the accumulated exposure dose of the material 221 positioned above a second device internal area 251 d. As is well know, during lithography processes a lithography mask

(not shown) may typically be used so as to define exposed and non-exposed areas in a photo resist material, wherein the exposed or the non-exposed material portions may be removed, depending on the type of resist material used, ie. positive resist or negative resist. Thus, for the exposure 222 of the device 250, an appropriately designed lithography mask may be used in which areas corresponding to the transistors 200a,

200c may remain substantially non-exposed for a positive resist material in the layer 221 , while appropriate mask features in the lithography mask may be provided so as to obtain a different degree of exposure for the areas 251s, 251 d of the transistor 200b. For this purpose, one or more semi-transparent mask features may be provided and/or a grating may be defined in the lithography mask so as to finally obtain a desired variation of the exposure dose deposited within the material 221 during the exposure 222 on the basis of otherwise predefined exposure parameters. For instance, the exposure parameters in combination with other process parameters of pre-exposure and post-exposure treatments including the development process for removing exposed portions of the material 221 may be selected such that a substantially complete removal of material of the layer 221 may be accomplished at the outermost periphery of the region 251s, while the degree of material removal may gradually decrease towards the transistor internal area 251 d, which may result in substantially no material removal at the interface between the area 251 d and the portion of the active region 202a corresponding to the transistor 200c.

It should be appreciated that in the embodiment shown in Fig 2c the exposure process 222 may be performed on the basis of a superior overall device topography since any other device features may not yet be formed, which may cause a more or less pronounced surface topography. For instance, in one illustrative embodiment, the isolation structure 202b (cf. Fig 2b) may be formed in a later manufacturing stage when even a subtle variation of surface topography caused by the isolation structure 202b may be considered inappropriate.

Fig 2d schematically illustrates the semiconductor device 250 in which the material layer 221 is patterned into an implantation mask, which may also be referred to as implantation mask 221 , having a portion 221b in which the ion blocking capability may laterally vary so as to provide for a reduced ion blocking capability above the area 251s compared to the area 251 d of the transistor 200b. Moreover, in the embodiment shown, the implantation mask 221 may comprise corresponding portions 221a, 221c having a substantially constant ion blocking capability across the respective portions of the active region 202a corresponding to the transistors 200a, 200c. That is, the ion blocking capability of the mask portions 221a, 221c above transistor internal areas 251s, 251 d of the transistors 200a, 200c may substantially be equal so that a substantially symmetric dopant concentration may be accomplished in these transistor elements in a subsequent implantation process for introducing a well dopant species into the active region 202a on the basis of the implantation mask 221. It should be appreciated that the configuration of the implantation mask 221 may be selected differently, as long as an asymmetric configuration with respect to the areas 251s, 251 d of the transistor 200b may be obtained. For instance, a more "step-like" difference in thickness between the areas 251s, 251 d may be generated during the preceding exposure 222 and the subsequent exposure treatment and development instead of a substantially gradual thickness variation as illustrated in Fig 2d. For example, in some illustrative embodiments (not shown) a corresponding lithography pattern may be used in which at least the area 251 d of the transistor 200b may remain substantially unexposed, while the area 251s may receive a moderately high exposure dose which may not significantly vary across the area 251s, thereby finally obtaining a substantially step-like configuration. Thus, also in this case, a difference in thickness and thus ion blocking capability of the mask portion 221b with respect to the areas 251s, 251 d may be obtained.

Fig 2e schematically illustrates the semiconductor device 250 when subjected to an ion implantation process 220 in which an appropriate well dopant species, such as a p-type species for n-channel transistors or an n-type species for p-channel transistors may be introduced in a portion of the active region 202a on the basis of the implantation mask 221. For instance, the ion blocking capability of the mask portions 221a, 221c may be selected so as to substantially suppress significant penetration of implantation species into the underlying portions of the region 202a so that a corresponding desired basic well doping for the transistors 200a, 200c may be established on the basis of an additional implantation process, such as the implantation process 215 previously explained with reference to Fig 2a. In other cases, a corresponding additional well implantation process may be performed after the process 220 and after the removal of the implantation mask 221. In other cases, a certain degree of dopant penetration may be acceptable if this is compatible with the overall configuration of the transistors 200a, 200b and 200c. On the other hand, the mask portion 221 b having the varying thickness and thus ion blocking capability may result in a corresponding varying penetration of the well dopant species, thereby providing a well dopant concentration profile 220a in which penetration depth and the overall amount of dopant species incorporated during the process 220 may decrease from the area 251s toward the area 251 d, as indicated by the arrow 220b. Consequently, the overall amount of dopant species 220a contained in the portion of the active region 202a corresponding to the transistor 200b per unit length, ie. along the horizontal direction in Fig 2e, may decrease starting from area 251s with a moderately high concentration towards the area 251 d. Consequently, upon forming source and drain regions in the areas 251s, 251 d, the increased degree of counter doping in the area 251s may provide for an increased field strength at the vicinity of corresponding pn- junctions to be formed on the basis of the drain and source dopant and the well dopant species 220a so that a desired asymmetric transistor configuration may be obtained, which may thus provide for enhanced transistor performance, as previously explained.

Fig 2f schematically illustrates the semiconductor device 250 in a further advanced manufacturing stage. As illustrated, the transistors 20Oa₁ 200b and 200c may each comprise a gate electrode 207 formed on a corresponding gate insulation layer 209 which separates the gate electrode 207 from a channel region 205. The channel region 205 in turn laterally separates a source region 203 from a drain region 204, wherein the source and drain regions 203, 204 may comprise a source and drain extension region 203e, 204e, respectively. With respect to the various components of the transistors 200a, 200b and 200c, the same criteria may apply as previously explained with reference to the transistor 100 and the transistors 100a, 100b and 100c as explained in the context with Figs 1a and 1c. That is, well-established manufacturing techniques and materials may be used for the gate electrode 207 and the gate insulation layer 209, as previously explained. Furthermore, the drain and source regions 204, 203 may be formed on the basis of an appropriate spacer structure 206, which may comprise one or more individual spacer elements, depending on the desired complexity of the lateral and vertical profile of the drain and source regions 204, 203. Furthermore, with respect to a gate length and a distance between adjacent gate electrodes 207, the same criteria may apply, as previously explained with reference to the distance d and the gate length 107a, previously referred to in Figs 1a and 1c. Consequently, the symmetric transistors 200a, 200c may be positioned in close proximity to the asymmetric transistor 200b in which a desired performance gain may be accomplished on the basis of the varying well dopant concentration 220a, which may decrease in the direction 220b, as also previously explained. That is, a significant portion of the source region 203 and the source extension region 203e may be formed on the basis of an increased degree of counter doping compared to the drain region 204 and the extension region 204e, thereby obtaining the asymmetric field strength distribution for the transistor 200b. The degree of symmetry of the field strength may, however, contrary to conventional strategies based on tilted halo implantations, as previously explained, be adjusted on the basis of a non- critical substantially non-tilted implantation process in combination with the appropriately designed implantation mask 221 (cf. Fig 2e), the characteristics of which may be provided substantially without being affected by the actual gate height and gate pitch. That is, a delicate adjustment of resist mask height for a given gate height and gate pitch in combination with an appropriate tilt angle, which may typically have to be reduced with decreasing critical dimensions, may be avoided. In this respect, merely the overall extension of the transistor 200b along the length direction may have to be taken into consideration when appropriately adapting the implantation mask 221 (cf. Fig 2e) while in particular the implantation parameter may be non-critical and may thus be readily selected so as to obtain the desired degree of asymmetry of the well dopant concentration 220a. With reference to Figs 2g - 2i further illustrative embodiments will now be described in which an implantation mask comprised of non-resist material may be patterned on the basis of a less critical photolithography process so as to provide for the desired asymmetric ion blocking capability.

Fig 2g schematically illustrates the semiconductor device 250 with the mask material 221 formed above the semiconductor layer 202. The mask material 221 may be comprised of any appropriate material, such as silicon dioxide, silicon nitride and the like, which may thus represent well-established non-resist materials having an increased density and thus ion blocking capability compared to a resist material. Furthermore, in the manufacturing stage shown, an etch mask 223 such as a resist mask may be formed above the mask material 221 thereby exposing a portion thereof that may substantially correspond to the transistor 200b still to be formed in the layer 202. The mask material 221 may be formed on the basis of any appropriate deposition technique, such as CVD and the like, based on well-established process recipes. In some illustrative embodiments the mask material 221 may comprise an etch stop layer (not shown) which may provide for superior etch stop capabilities in a subsequent process sequence for removing a portion of the mask material 221. For instance, silicon dioxide may be used as an efficient etch stop material in combination with silicon nitride material, while in other cases silicon nitride may act as an etch stop material and silicon dioxide may be used as the bulk material for the layer 221. It should be appreciated, however, that any other appropriate material may be used, such as polymer material and the like, as long as an etch behaviour of the material 221 may efficiently be modified. For this purpose, the etch mask 223 may be formed, for instance on the basis of a photolithography process, which may be performed without sophisticated lithography techniques for obtaining a graded or different degree of exposure within the exposed portion of the material 221 , as previously explained. Furthermore, a thickness of the etch mask 223 may be selected so as to obtain a desired asymmetric patterning of an etch behaviour of the exposed portion of the layer 221 on the basis of a tilted implantation process 224, during which an appropriate species, such as xenon, germanium, silicon and the like, may be introduced into the material 221 , thereby significantly modifying the overall etch behaviour. It should be appreciated that although the implantation process 224 may be performed on the basis of a tilt angle, increased flexibility in selecting an appropriate thickness of the mask 223 and the tilt angle 224 may be accomplished compared to conventional strategies for forming asymmetric transistor configurations, as previously explained with reference to Figs 1a - 1c, since for example a penetration of the implantation species into covered portions of the material 221 may be less critical since the mask 223 may be maintained during a subsequent etch process so that a corresponding modification of the etch behaviour of covered portions of the material 221 may not unduly affect the patterning of the exposed portion of the layer 221. Furthermore, implantation energy of the process 224 may be selected in any appropriate manner so as to avoid undue dopant penetration of the semiconductor layer 202, if considered inappropriate. Thus, even if the implantation species may be reliably stopped within the material 221 , a corresponding efficient modification of etch behaviour of the upper portion of the material layer 221 may result in a corresponding difference in advance of the etch front, which may finally result in an appropriately designed implantation mask.

Fig 2h schematically illustrates the semiconductor device 250 when exposed to an etch ambient 225 designed to remove material of the layer 221 selectively to the semiconductor layer 202 or to a corresponding etch stop layer (not shown). Due to the previously introduced implantation species, the removal rate during the process 225 may be higher in areas having received an increased dose of implantation species so that the corresponding etch front may advance faster above the area 251s compared to the area 251d.

Fig 2i schematically illustrates the device 250 in a further advanced manufacturing stage, ie. after completing the etch process 225 and removing the etch mask 223 (cf. Fig 2h). Consequently, the material 221 may now be patterned so as to represent an implantation mask having the portion 221b with a varying ion blocking capability, as previously explained. On the other hand, the portions 221a, 221c may provide for a desired high ion blocking capability, as previously explained. Thus, upon performing the ion implantation process 220, the well dopant concentration 220a may be achieved with the desired degree of asymmetry on the basis of the mask portion 221b. Thereafter, the material 221 may be removed, for instance on the basis of well-established selective etch recipes, wherein the corresponding removal process may be controlled on the basis of an etch stop layer (not shown), which may then be removed by applying well- established recipes. For instance, silicon nitride may efficiently be removed selectively to silicon dioxide, which in turn may be removed selectively to a silicon material on the basis of well-established techniques. Thereafter, the further processing may be continued as previously described. Consequently, the mask portion 221b may be accomplished on the basis of less critical lithography conditions, while nevertheless providing for enhanced design and process flexibility compared to conventional strategies.

Fig 2j schematically illustrates the semiconductor device 250 according to further illustrative embodiments in which the asymmetric configuration of the well doping may be accomplished in a later manufacturing stage, ie. after forming gate electrodes. That is, the gate electrodes 207 in combination with the gate insulation layers 209 may be formed on the basis of conventional manufacturing strategies. Thereafter, the mask material 221 may be provided, for instance in the form of a resist material, a polymer material or any other appropriate mask material, such as well-established dielectric materials and the like. The material 221 may be deposited by spin-on techniques and the like wherein, if required, a planarity of the material 221 may be enhanced by performing an additional planarization process, such as a CMP (chemical mechanical polishing) process and the like. Thereafter, the material 221 may be patterned so as to obtain the portion 221 b having the desired asymmetry with respect to ion blocking capability, as previously explained. For this purpose, in some illustrative embodiments, sophisticated exposure techniques may be used, as for instance explained with reference to the exposure process 222 (cf. Fig 2c), when the material 221 is provided in the form of a radiation sensitive resist material. In other illustrative embodiments, an additional etch mask may be provided in combination with an appropriate treatment for locally modifying the etch behaviour, as is for instance explained with reference to Figs 2g and 2h. Hence, also in this case the graded portion 221b may be obtained and may subsequently be used for incorporating a well dopant species in an asymmetric manner. Hence, during the implantation process 220 the dopant concentration 220a may be obtained as a graded profile in the areas 251s, 251 d, while the channel region 205 may exhibit a substantially well doping concentration along a length direction of the transistor 200b due to the ion blocking effect of the gate electrode 207. After the implantation process 220, the material 221 may be removed, for instance by any appropriate etch process wherein also an etch stop material may be used (not shown) in order to reduce damage at exposed portions of the layer 202 and the gate electrodes 207. Thereafter, the further processing may be continued by forming the source and drain regions in the areas 251s, 251 d, as previously explained. As a result, the present disclosure provides semiconductor devices and techniques in which an asymmetric configuration of transistors may be accomplished with enhanced design and process flexibility compared to conventional strategies. That is, the well dopant concentration may be provided in an asymmetric manner with respect to the drain and source areas of asymmetric transistors by using a substantially non-tilted implantation process and using a specifically designed implantation mask having an asymmetric ion blocking capability. Consequently, the asymmetric configuration may be established substantially without being affected by device dimensions, such as gate height, gate pitch and the like, thereby providing for scalability of the asymmetric configuration of transistors.

Further modifications and variations of the present disclosure will be apparent to those skilled in the art in view of this description. Accordingly, the description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the present disclosure. It is to be understood that the forms shown and described herein are to be taken as the presently preferred embodiments.

Claims

1. A method comprising:

forming an implantation mask above a semiconductor region, said implantation mask having a first ion blocking capability above a first transistor internal area of a transistor and having a second ion blocking capability above a second transistor internal area of said transistor, said first and second ion blocking capabilities differing from each other;

implanting a well dopant species into said first and second transistor internal areas on the basis of said implantation mask; and

forming a gate electrode above a channel area of said semiconductor region, said channel area laterally separating said first and second transistor internal areas.

2. The method of claim 1 , wherein forming said implantation mask comprises forming an ion blocking material with a varying thickness above said first and second transistor internal areas.

3. The method of claim 2, wherein said ion blocking material comprises a resist material.

4. The method of claim 2, wherein said ion blocking material comprises a non-resist material.

5. The method of claim 4, wherein forming said ion blocking material comprises depositing said non-resist material, locally varying an etch behaviour of said non- resist material and removing material of said non-resist material on the basis of said locally varying etch behaviour.

6. The method of claim 5, wherein locally varying said etch behaviour comprises forming a resist mask above said non-resist material and performing an implantation process using a tilt angle so as to introduce an implantation species locally varying said etch behaviour.

7. The method of claim 1 , further comprising forming an isolation structure prior to forming said implantation mask, wherein said isolation structure laterally delineates said semiconductor region.

8. The method of claim 1 , further comprising forming an isolation structure after forming said implantation mask, wherein said isolation structure laterally delineates said semiconductor region.

9. The method of claim 1 , wherein said first ion blocking capability is less than said second ion blocking capability and wherein said first transistor internal area corresponds to a source region.

10. The method of claim 1 , wherein said implantation mask covers a first transistor internal area and a second transistor internal area of a second transistor and wherein a ion blocking capability of said implantation mask above said first transistor internal area of said second transistor is substantial equal to an ion blocking capability of said implantation mask above said second transistor internal area of said second transistor.

11. The method of claim 10, wherein said first and second transistor internal areas of said transistors and said first and second transistor internal areas of said second transistor are formed in said semiconductor region without providing an intermediate isolation structure between said transistor and said second transistor.

12. The method of claim 1 , further comprising implanting an additional portion said well dopant species into said first and second transistor internal areas without using said implantation mask.

13. The method of claim 1 , wherein said gate electrode is formed to have a length of approximately 50 nanometer (nm) or less.

14. A method comprising: forming a graded implantation mask above a first transistor internal area and a second transistor internal area of a transistor, said graded implantation mask providing a first ion blocking capability for said first transistor internal area and a second increased ion blocking capability for said second transistor internal area, wherein said second ion blocking capability is greater than said first ion blocking capability;

introducing a well dopant species in said first and second transistor internal areas on the basis of said implantation mask; and

forming drain and source regions on the basis of said first and second transistor internal areas so as to obtain an asymmetric transistor configuration.

15. The method of claim 14, further comprising forming a gate electrode after forming said graded implantation mask.

16. The method of claim 14, further comprising forming a gate electrode prior to forming said graded implantation mask.

17. The method of claim 14, wherein a source region is formed in said first transistor internal area.

18. A semiconductor device comprising:

a gate electrode structure formed above a channel region;

a drain region and a source region formed in a well region, said drain region and said source region being laterally separated by said channel region, a dopant concentration of a well dopant species gradually increasing in a lateral direction from said channel region to a periphery of said transistor at least at a source side of said transistor.

19. The semiconductor device of claim 18, wherein the concentration of said well dopant species gradually varies in a lateral direction within said channel region.

20. The semiconductor device of claim 18, wherein an overall amount of well dopant species is higher in said source region compared to said drain region.

21. The semiconductor device of claim 18, wherein a gate length of said gate electrode structure is approximately 50 nanometers or less.

22. The semiconductor device of claim 18, further comprising drain and source regions of a second transistor formed in said well region, wherein said drain and source regions of said second transistor have a substantially equal configuration with respect to a well dopant species provided at a source side and a drain side of said second transistor.