WO2010056511A3 - Technique for promoting efficient instruction fusion - Google Patents

Technique for promoting efficient instruction fusion

Info

Publication number
WO2010056511A3
WO2010056511A3 PCT/US2009/062219 US2009062219W WO2010056511A3 WO 2010056511 A3 WO2010056511 A3 WO 2010056511A3 US 2009062219 W US2009062219 W US 2009062219W WO 2010056511 A3 WO2010056511 A3 WO 2010056511A3
Authority
WO
Grant status
Application
Patent type
Prior art keywords
technique
instruction
promoting efficient
efficient instruction
instruction fusion
Prior art date
Application number
PCT/US2009/062219
Other languages
French (fr)
Other versions
WO2010056511A2 (en )
Inventor
Ido Ouziel
Lihu Rappoport
Robert Valentine
Ron Gabor
Pankaj Raghuvanshi
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3853Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution of compound instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016Decoding the operand specifier, e.g. specifier format
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017Runtime instruction translation, e.g. macros
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30196Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45Caching of specific data in cache memory
    • G06F2212/452Instruction code
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62Details of cache specific to multiprocessor cache arrangements
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/14Interconnection, or transfer of information or other signals between, memories, peripherals or central processing units
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/15Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply acting upon peripherals
    • Y02D10/151Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply acting upon peripherals the peripheral being a bus

Abstract

A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.
PCT/US2009/062219 2008-10-30 2009-10-27 Technique for promoting efficient instruction fusion WO2010056511A3 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12290395 US9690591B2 (en) 2008-10-30 2008-10-30 System and method for fusing instructions queued during a time window defined by a delay counter
US12/290,395 2008-10-30

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011534680A JP2012507794A5 (en) 2009-10-27
KR20117007623A KR101258762B1 (en) 2008-10-30 2009-10-27 Technique for promoting efficient instruction fusion

Publications (2)

Publication Number Publication Date
WO2010056511A2 true WO2010056511A2 (en) 2010-05-20
WO2010056511A3 true true WO2010056511A3 (en) 2010-07-08

Family

ID=42063260

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/062219 WO2010056511A3 (en) 2008-10-30 2009-10-27 Technique for promoting efficient instruction fusion

Country Status (6)

Country Link
US (4) US9690591B2 (en)
JP (1) JP5902285B2 (en)
KR (1) KR101258762B1 (en)
CN (2) CN101901128B (en)
DE (1) DE102009051388A1 (en)
WO (1) WO2010056511A3 (en)

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JP5491071B2 (en) * 2009-05-20 2014-05-14 エヌイーシーコンピュータテクノ株式会社 Instruction fusion calculation device and instruction fusion calculation method
US9223578B2 (en) * 2009-09-25 2015-12-29 Nvidia Corporation Coalescing memory barrier operations across multiple parallel threads
US8856496B2 (en) 2010-04-27 2014-10-07 Via Technologies, Inc. Microprocessor that fuses load-alu-store and JCC macroinstructions
US8843729B2 (en) 2010-04-27 2014-09-23 Via Technologies, Inc. Microprocessor that fuses MOV/ALU instructions
US20130081001A1 (en) * 2011-09-23 2013-03-28 Microsoft Corporation Immediate delay tracker tool
US9672037B2 (en) * 2013-01-23 2017-06-06 Apple Inc. Arithmetic branch fusion
US9483266B2 (en) * 2013-03-15 2016-11-01 Intel Corporation Fusible instructions and logic to provide OR-test and AND-test functionality using multiple test sources
US9886277B2 (en) 2013-03-15 2018-02-06 Intel Corporation Methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources
US9329848B2 (en) * 2013-03-27 2016-05-03 Intel Corporation Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programs
US9792121B2 (en) 2013-05-21 2017-10-17 Via Technologies, Inc. Microprocessor that fuses if-then instructions
US9348596B2 (en) 2013-06-28 2016-05-24 International Business Machines Corporation Forming instruction groups based on decode time instruction optimization
US9372695B2 (en) 2013-06-28 2016-06-21 Globalfoundries Inc. Optimization of instruction groups across group boundaries
US9911508B2 (en) 2014-09-18 2018-03-06 Via Alliance Semiconductor Co., Ltd Cache memory diagnostic writeback

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US6889318B1 (en) * 2001-08-07 2005-05-03 Lsi Logic Corporation Instruction fusion for digital signal processor

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Also Published As

Publication number Publication date Type
CN103870243B (en) 2018-02-02 grant
CN101901128B (en) 2016-04-27 grant
DE102009051388A1 (en) 2010-05-06 application
US20100115248A1 (en) 2010-05-06 application
CN103870243A (en) 2014-06-18 application
WO2010056511A2 (en) 2010-05-20 application
KR101258762B1 (en) 2013-04-29 grant
US20170003965A1 (en) 2017-01-05 application
US20160378487A1 (en) 2016-12-29 application
KR20110050715A (en) 2011-05-16 application
JP5902285B2 (en) 2016-04-13 grant
US9690591B2 (en) 2017-06-27 grant
JP2015072707A (en) 2015-04-16 application
CN101901128A (en) 2010-12-01 application
JP2012507794A (en) 2012-03-29 application
US20160246600A1 (en) 2016-08-25 application

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