Connect public, paid and private patent data with Google Patents Public Datasets

Technique for promoting efficient instruction fusion

Info

Publication number
WO2010056511A2
WO2010056511A2 PCT/US2009/062219 US2009062219W WO2010056511A2 WO 2010056511 A2 WO2010056511 A2 WO 2010056511A2 US 2009062219 W US2009062219 W US 2009062219W WO 2010056511 A2 WO2010056511 A2 WO 2010056511A2
Authority
WO
Grant status
Application
Patent type
Prior art keywords
instruction
fusible
iq
embodiment
cache
Prior art date
Application number
PCT/US2009/062219
Other languages
French (fr)
Other versions
WO2010056511A3 (en )
Inventor
Ido Ouziel
Lihu Rappoport
Robert Valentine
Ron Gabor
Pankaj Raghuvanshi
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3853Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution of compound instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016Decoding the operand specifier, e.g. specifier format
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/3017Runtime instruction translation, e.g. macros
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30196Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45Caching of specific data in cache memory
    • G06F2212/452Instruction code
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62Details of cache specific to multiprocessor cache arrangements
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BINDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B60/00Information and communication technologies [ICT] aiming at the reduction of own energy use
    • Y02B60/10Energy efficient computing
    • Y02B60/12Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply
    • Y02B60/1228Interconnection, or transfer of information or other signals between, memories, peripherals or central processing units
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BINDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B60/00Information and communication technologies [ICT] aiming at the reduction of own energy use
    • Y02B60/10Energy efficient computing
    • Y02B60/12Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply
    • Y02B60/1232Acting upon peripherals
    • Y02B60/1235Acting upon peripherals the peripheral being a bus
    • Y02D10/14
    • Y02D10/151

Abstract

A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.

Description

TECHNIQUE FOR PROMOTING EFFICIENT INSTRUCTION FUSION

Field of the Invention

Embodiments of the invention relate generally to the field of information processing and more specifically, to the field of instruction fusion in computing systems and microprocessors.

Background

Instruction fusion is a process that combines two instructions into a single instruction which results in a one operation (or micro-operation, "uop") sequence within a processor. Instructions stored in a processor instruction queue (IQ) may be "fused" after being read out of the IQ and before being sent to instruction decoders or after being decoded by the instruction decoders. Typically, instruction fusion occuring before the instruction is decoded is referred to as "macro-fusion", whereas instruction fusion occuring after the instruction is decoded (into uops, for example) is referred to as "micro- fusion". An example of macro-fusion is the combining of a compare ("CMP") instruction or test instruction ("TEST") ("CMP/TEST") with a conditional jump ("JCC") instruction. CMP/TEST and JCC instruction pairs may occur regularly in programs at the end of loops, for example, where a comparison is made and, based on the outcome of a comparison, a branch is taken or not taken. Since macro-fusion may effectively increase instruction throughput, it may be desireable to find as many opportunities to fuse instructions as possible.

For instruction fusion opportunities to be found in some prior art processor microarchitectures, both the CMP/TEST and JCC instructions may need to reside in the IQ concurrently so that they can be fused when the instructions are read from the IQ. However, if there is a fusible CMP/TEST instruction in the IQ and no further instructions have been written to the IQ (i.e. the CMP/TEST instruction is the last instruction in the IQ), the CMP/TEST instruction may be read from the IQ and sent to the decoder without being fused, even if the next instruction in program order is a JCC instruction. An example where a missed fusion opportunity may occur is if the CMP/TEST and the JCC happen to be across a storage boundary (e.g., 16 byte boundary), causing the CMP/TEST to be written in the IQ in one cycle and the JCC to be written the following cycle. In this case, if there are no stalling conditions, the JCC will be written in the IQ at the same time or after the CMP/TEST is being read from the IQ, so a fusion opportunity will be missed, resulting in multiple unnecessary reads of the IQ, reduced instruction throughput and excessive power consumption.

Brief Description of the Drawings

Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

Figure 1 illustrates a block diagram of a microprocessor, in which at least one embodiment of the invention may be used;

Figure 2 illustrates a block diagram of a shared bus computer system, in which at least one embodiment of the invention may be used;

Figure 3 illustrates a block diagram a point-to-point interconnect computer system, in which at least one embodiment of the invention may be used;

Figure 4 illustrates a block diagram of a state machine, which may be used to implement at least one embodiment of the invention; Figure 5 is a flow diagram of operations that may be used for performing at least one embodiment of the invention.

Figure 6 is a flow diagram of operations that may be performed in at least one embodiment.

Detailed Description Embodiments of the invention may be used to improve instruction throughput in a processor and/or reduce power consumption of the processor. In one embodiment, what would be otherwise missed opportunities for instruction fusion or found and instruction fusion may occur as a result. In one embodiment, would-be missed instruction fusion opportunities are found by delaying reading of a last instruction from an instruction queue (IQ) or the issuance of the last instruction read from the IQ to a decoding phase for a threshold number of cycles, so that any subsequent fusible instructions may be fetched and stored in the IQ (or at least identified without necessarily being stored in the IQ) and subsequently fused with the last fusible instruction. In one embodiment, delaying the reading or issuance of a first fusible instruction by a threshold number of cycles may improve processor performance, since doing so may avoid two, otherwise fusible, instructions being decoded and processed separately rather than as a single instruction.

The choice of the threshold number of wait cycles may depend upon the microarchitecture in which a particular embodiment is used. For example, in one embodiment, the threshold number of cycles may be two, whereas in other embodiments, the threshold number of cycles may be more or less than two. In one embodiment, the threshold number of wait cycles provides the maximum amount of time to wait on a subsequent fusible instruction to be stored to the IQ while maintaining an overall latency/performance advantage in waiting for the subsequent fusible instruction over processing the fusible instructions as separate instructions. In other embodiments, where power is more critical, for example, the threshold number of wait cycles could be higher in order to ensure that extra power is not used to process the two fusible instructions separately, even though the number of wait cycles may cause a decrease (albeit temporarily) in instruction throughput.

Figure 1 illustrates a microprocessor in which at least one embodiment of the invention may be used. In particular, Figure 1 illustrates microprocessor 100 having one or more processor cores 105 and 110, each having associated therewith a local cache 107 and 113, respectively. Also illustrated in Figure 1 is a shared cache memory 115 which may store versions of at least some of the information stored in each of the local caches 107 and 113. In some embodiments, microprocessor 100 may also include other logic not shown in Figure 1 , such as an integrated memory controller, integrated graphics controller, as well as other logic to perform other functions within a computer system, such as I/O control. In one embodiment, each microprocessor in a multi-processor system or each processor core in a multi-core processor may include or otherwise be associated with logic 119 to enable interrupt communication techniques, in accordance with at least one embodiment. The logic may include circuits, software or both to enable more efficient fusion of instructions than in some prior art implementations.

In one embodiment, logic 119 may include logic to reduce the likelihood of missing instruction fusion opportunities. In one embodiment, logic 119 delays the reading of a first instruction (e.g., CMP) from the IQ, when there is no subsequent instruction stored in the IQ or other fetched instruction storage structure. In one embodiment, the logic 119 causes the reading or issuance of a first fusible instruction for a threshold number of cycles (e.g., two cycles) before reading the IQ or issuing the first fusible instruction to a decoder or other processing logic, such that if there is a second fusible instruction that can be fused with the first instruction not yet stored in the IQ (due, for example, to the two fusible instructions being stored in a memory or cache in different storage boundaries), the opportunity to fuse the two fusible instructions may not be missed. In some embodiments, the threshold may be fixed, whereas in other embodiments, the threshold may be variable, modifiable by a user or according to user- independent algorithm. In one embodiment, the first fusible instruction is a CMP instruction and the second fusible instruction is a JCC instruction. In other embodiments, either or both of the first and second instruction may not be a CMP or JCC instruction, but any fusible instructions. Moreover, embodiments if the invention may be applied to fusing more than two instructions.

Figure 2, for example, illustrates a front-side-bus (FSB) computer system in which one embodiment of the invention may be used. Any processor 201, 205, 210, or 215 may access information from any local level one (Ll) cache memory 220, 225, 230, 235, 240, 245, 250, 255 within or otherwise associated with one of the processor cores 223, 227, 233, 237, 243, 247, 253, 257. Furthermore, any processor 201, 205, 210, or 215 may access information from any one of the shared level two (L2) caches 203, 207, 213, 217 or from system memory 260 via chipset 265. One or more of the processors in Figure 2 may include or otherwise be associated with logic 219 to enable improved efficiency of instruction fusion, in accordance with at least one embodiment.

In addition to the FSB computer system illustrated in Figure 2, other system configurations may be used in conjunction with various embodiments of the invention, including point-to-point (P2P) interconnect systems and ring interconnect systems. The P2P system of Figure 3, for example, may include several processors, of which only two, processors 370, 380 are shown by example. Processors 370, 380 may each include a local memory controller hub (MCH) 372, 382 to connect with memory 32, 34. Processors 370, 380 may exchange data via a point-to-point (PtP) interface 350 using PtP interface circuits 378, 388. Processors 370, 380 may each exchange data with a chipset 390 via individual PtP interfaces 352, 354 using point to point interface circuits 376, 394, 386, 398. Chipset 390 may also exchange data with a high-performance graphics circuit 338 via a high- performance graphics interface 339. Embodiments of the invention may be located within any processor having any number of processing cores, or within each of the PtP bus agents of Figure 3. In one embodiment, any processor core may include or otherwise be associated with a local cache memory (not shown). Furthermore, a shared cache (not shown) may be included in either processor outside of both processors, yet connected with the processors via p2p interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode. One or more of the processors or cores in Figure 3 may include or otherwise be associated with logic 319 to enable improved efficiency of instruction fusion, in accordance with at least one embodiment.

In at least one embodiment, a second fusible instruction may not be stored into an IQ before some intermediate operation occurs (occuring between a first and second fusible instruction), such as an IQ clear operation, causing a missed opportunity to fuse the two otherwise fusible instructions. In one embodiment, in which a cache (or a buffer) stores related sequences of decoded instructions (after they were read from the IQ and decoded) or uops (e.g., "decoded stream buffer" or "DSB", "trace cache", or "TC") that are to be scheduled (perhaps multiple times) for execution by the processor, a first fusible uop (e.g., CMP) may be stored in the cache without a fusible second uop (e.g., JCC) within the same addressable range (e.g., same cache way). This may occur, for example, where JCC is crossing a cache line (due to a cache miss) or crossing page boundary (due to a translation look-aside buffer miss), in which case the cache may store the CMP without the JCC. Subsequently, if the processor core pipeline is cleared (due to a "clear" signal being asserted, for example) after the CMP was stored but before the JCC is stored in the cache, the cache store only the CMP in one of its ways without the JCC.

On subsequent lookups to the cache line storing the CMP, the cache may interpret the missing JCC as a missed access and the JCC may be marked as the append point for the next cache fill operation. This append point, however, may not be found since the CMP+ JCC may be read as fused from the IQ. Therefore, the requested JCC may not match any uop to be filled, coming from the IQ, and thus the cache will not be able to fill the missing JCC, but may continually miss on the line in which the fused CMP+ JCC is expected. Moreover, in one embodiment in which a pending fill request queue (PFRQ) is used to store uop cache fill requests, an entry that was reserved for a particular fused instruction fill may not deallocate (since the expected fused instruction fill never takes place) and may remain useless until the next clear operation. In one embodiment, a PFRQ entry lock may occur every time the missing fused instruction entry is acessed, and may therefore prevent any subsequent fills to the same location. In order to prevent an incorrect or undesireable lock of the PFRQ entry, a state machine, in one embodiment, may be used to monitor the uops being read from the IQ to detect cases, in which a region that has a corresponding PFRQ entry (e.g., a region marked for a fill) was completely missed, due for example, to the entry's last uop being reached without the fill start point being detected. In one embodiment, the state machine may cause the PFRQ entry to be deallocated when this condition is met. In other embodiments, an undesireable PFRQ entry lock may be avoided by not creating within the cache a fusible instruction that may be read from the IQ without both fusible instructions present. For example, if a CMP is followed by a non-JCC instruction, a fused instruction entry may be created in the cache, but only if the CMP is read out of the IQ alone (after the threshold wait time expires, for example), is the fused instruction entry not filled to the cache. In other embodiments, the number of times the state machine has detected a fill region that was skipped may be counted, a cache flush or invalidation operation may be performed after some threshold count of times the fill region was skipped. The fill region may then be removed from the cache, and the fused instruction may then be re-filled.

Figure 4 illustrates a state machine, according to one embodiment, that may be used to avoid unwanted PFRQ entry lock conditions due to a missed fusible instruction in the IQ. At state 401, in which the instructions in the IQ are not in a region marked for fill, a "fill region start" signal indicating that the IQ is about to process an instruction that is mapped to a fill-region (an instruction from the fill region according to the cache hashing) but does not start at the linear instruction pointer saved in the PFRQ ("lip") 405. this may cause the state machine to move to state 410. If the next instruction in the IQ (that will soon be decoded) ends a fill region (e.g. ends a line as hashed by the cache, or is a taken branch), then the state machine causes the deallocation 415 of the corresponding PFRQ entry and the state machine returns to state 401. If, however, the fill pointer is equal to the fill region lip 430 while either in state 401 or state 410, the state machine enters state 420, in which the access is within the fill region and after fill start point. From state 420, a last uop in the fill region indication will return 425 the state machine to state 401 without deallocation the corresponding PFRQ entry. The state machine of Figure 4 may be implemented in hardware logic, software, or some combination thereof. In other embodiments, other state machines or logic may be used.

Figure 5 illustrates a flow diagram of operations that may be used in conjunction with at least one embodiment of the invention. At operation 501, it is determined whether the currently accessed instruction in the IQ is fusible with any subsequent instruction. If not, then at operation 505, the next instruction is accessed from the IQ and the delay count is reset. If so, then at operation 510, a delay counter is incremented and at operation 515 it is determined whether the delay count threshold is reached. If it isn't, then at operation 520, no instruction fusion of the currently accessed instruction is performed. If it is, then the next instruction is accessed from the IQ and the delay count is reset at operation 505. In other embodiments, other operations may be performed to improve the efficiency of instruction fusion. Figure 6 illustrates a flow diagram of operations that may be performed in conjunction with at least one embodiment. In order to perform one embodiment in processors having a number of decoder circuits, it may be helpful to ensure that the first fusible instruction is to be decoded on a particular decoder circuit, which is capable of decoding the fused instruction. In Figure 6, it is determined whether a particular instruction can be a first of a fused pair of instructions at operation 601. If not, then the fused instructions are issued at operation 605. If so, then it is determined whether the first fusible instruction is followed by a valid instruction in the IQ at operation 610. If so, then the fused instructions are issued at operation 610. If not, then at operation 615, it is determined whether the first fusible instruction is to be issued to a decoder capable of supporting the fused instruction. In one embodiment, decoder-0 is capable of decoding the fused instructions. If the first fusible instruction was not issued to decoder-0, then at operation 620, the first fusible instruction is moved, or "nuked", to a different decoder until it corresponds to decoder-0. At operation 625, a counter is set to an initial value, N and at operation 630, if the instruction is followed by a valid instruction or the counter is zero, then the fused instructions are issued at operation 635. Otherwise, at operation 640, the counter is decremented and the invalid instruction is nuked. In other embodiments, the counter may increment to a final value. In other embodiments, other operations, besides a nuke operation may clear the invalid instruction.

One or more aspects of at least one embodiment may be implemented by representative data stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as "IP cores" may be stored on a tangible, machine readable medium ("tape") and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

Thus, a method and apparatus for directing micro-architectural memory region accesses has been described. It is to be understood that the above description is intended to be illustrative and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

CLAIMSWhat is claimed is:
1. An apparatus comprising: an instruction queue (IQ); logic to delay processing of a first fusible instruction for a threshold amount of time, such that a second fusible instruction, fusible with the first fusible instruction, may be fused with the first fusible instruction if the second fusible instruction is stored within the IQ within the threshold amount of time.
2. The apparatus of claim 1, wherein the first fusible and the second fusible instructions are stored across a fetch boundary prior to being stored in the IQ.
3. The apparatus of claim 1, wherein the logic is to delay processing of the first fusible instruction only if the first fusible instruction is the last instruction stored in the IQ.
4. The apparatus of claim 1, wherein the logic includes a counter to be incremented once for each cycle after the first fusible instruction is stored in the IQ and is the last instruction in the IQ until a threshold number of cycles corresponding to the threshold amount of time is reached.
5. The apparatus of claim 1, further comprising a state machine to prevent a fill buffer request queue (FBRQ) from locking an entry corresponding to the first and second fusible instructions, if an intermediate instruction is performed between the first fusible instruction being stored in the IQ and the second fusible instruction being stored in the IQ.
6. The apparatus of claim 5, wherein the intermediate instruction is to cause the IQ to be cleared.
7. A method comprising: determining whether the currently accessed instruction within an instruction queue
(IQ) is fusible with any subsequent instruction to be stored in the IQ; accessing a next instruction from the IQ and resetting the delay counter if the currently accessed instruction is not fusible with a subsequent instruction to be stored in the IQ; incrementing the delay counter if a currently accessed instruction is fusible and is the last instruction in the IQ.
8. The method of claim 7 further comprising fusing the currently accessed instruction with the subsequent instruction if the first and second instructions are fusible and the delay counter has not reached a threshold value.
9. The method of claim 8, further comprising processing the currently accessed instruction separately from the subsequent instruction if the first and second instructions are not fusible.
10. The method of claim 8, further comprising processing the currently accessed instruction separately from the subsequent instruction the delay counter has reached the threshold value.
11. The method of claim 7, further comprising preventing a fill buffer request queue
(FBRQ) from locking an entry corresponding to the currently accessed instruction and the subsequent instructions if they are fusible and an intermediate event is performed before subsequent instruction is stored in a cache and after the currently accessed instruction is stored in the cache.
12. A system comprising: a storage to store a first and second fusible instruction within a first and second access boundary, respectively; a processor having fetch logic to fetch the first and second fusible instruction into an instruction queue (IQ); delay logic to delay reading of the first fusible instruction from the IQ for a threshold amount of cycles; instruction fusion logic to fuse the first and second fusible instructions if the second fusible instruction is stored in the IQ after the first fusible instruction and before the threshold amount of cycles has been reached.
13. The system of claim 12, further comprising a counter to increment if the first fusible instruction is the only instruction in the IQ and to stop counting when the threshold amount of cycles has been reached.
14. The system of claim 13, wherein the counter is to reset if the second fusible instruction is stored in the IQ before the threshold amount of cycles has been reached.
15. The system of claim 13, wherein the counter is to reset if the second fusible instruction is stored in the IQ before the threshold amount of cycles has been reached.
16. The system of claim 12, wherein the storage includes an instruction cache and the first and second boundary sizes are each 64 bytes.
17. The system of claim 12, wherein the storage includes a dynamic random-access memory and the first and second boundary sizes are each 4096 bytes.
18. The system of claim 12, wherein the first fusible instruction is a CMP/TEST instruction and the second fusible instruction is a JCC instruction.
19. The system of claim 18, wherein the threshold number of cycles is two.
20. The system of claim 12, further including a state machine to prevent a fill buffer request queue (FBRQ) from locking an entry corresponding to the first and second fusible instructions, if an intermediate event is performed between the first fusible instruction being stored in the cache and the second fusible instruction being stored in the cache.
PCT/US2009/062219 2008-10-30 2009-10-27 Technique for promoting efficient instruction fusion WO2010056511A3 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12290395 US9690591B2 (en) 2008-10-30 2008-10-30 System and method for fusing instructions queued during a time window defined by a delay counter
US12/290,395 2008-10-30

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011534680A JP2012507794A5 (en) 2009-10-27
KR20117007623A KR101258762B1 (en) 2008-10-30 2009-10-27 Technique for promoting efficient instruction fusion

Publications (2)

Publication Number Publication Date
WO2010056511A2 true true WO2010056511A2 (en) 2010-05-20
WO2010056511A3 true WO2010056511A3 (en) 2010-07-08

Family

ID=42063260

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/062219 WO2010056511A3 (en) 2008-10-30 2009-10-27 Technique for promoting efficient instruction fusion

Country Status (6)

Country Link
US (4) US9690591B2 (en)
JP (1) JP5902285B2 (en)
KR (1) KR101258762B1 (en)
CN (2) CN101901128B (en)
DE (1) DE102009051388A1 (en)
WO (1) WO2010056511A3 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140208073A1 (en) * 2013-01-23 2014-07-24 Apple Inc. Arithmetic Branch Fusion
GB2512725A (en) * 2013-03-15 2014-10-08 Intel Corp Fusible instructions and logic to provide or-test and and-test functionality using multiple test sources
GB2512726A (en) * 2013-03-15 2014-10-08 Intel Corp Methods and apparatus for fusing instructions to provide or-test and and-test functionality on multiple test sources
WO2014208054A1 (en) * 2013-06-28 2014-12-31 International Business Machines Corporation Optimization of instruction groups across group boundaries
WO2016042353A1 (en) * 2014-09-18 2016-03-24 Via Alliance Semiconductor Co., Ltd. Cache management request fusing
US9348596B2 (en) 2013-06-28 2016-05-24 International Business Machines Corporation Forming instruction groups based on decode time instruction optimization

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8090931B2 (en) * 2008-09-18 2012-01-03 Via Technologies, Inc. Microprocessor with fused store address/store data microinstruction
JP5491071B2 (en) * 2009-05-20 2014-05-14 エヌイーシーコンピュータテクノ株式会社 Instruction fusion calculation device and instruction fusion calculation method
US9223578B2 (en) * 2009-09-25 2015-12-29 Nvidia Corporation Coalescing memory barrier operations across multiple parallel threads
US8856496B2 (en) 2010-04-27 2014-10-07 Via Technologies, Inc. Microprocessor that fuses load-alu-store and JCC macroinstructions
US8843729B2 (en) 2010-04-27 2014-09-23 Via Technologies, Inc. Microprocessor that fuses MOV/ALU instructions
US20130081001A1 (en) * 2011-09-23 2013-03-28 Microsoft Corporation Immediate delay tracker tool
US9329848B2 (en) * 2013-03-27 2016-05-03 Intel Corporation Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programs
US9792121B2 (en) 2013-05-21 2017-10-17 Via Technologies, Inc. Microprocessor that fuses if-then instructions

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040128485A1 (en) * 2002-12-27 2004-07-01 Nelson Scott R. Method for fusing instructions in a vector processor
US20040139429A1 (en) * 2000-12-29 2004-07-15 Ronny Ronen System and method for fusing instructions
US6889318B1 (en) * 2001-08-07 2005-05-03 Lsi Logic Corporation Instruction fusion for digital signal processor

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2834171B2 (en) * 1989-02-06 1998-12-09 株式会社日立製作所 How to compile
US5392228A (en) * 1993-12-06 1995-02-21 Motorola, Inc. Result normalizer and method of operation
US5860154A (en) * 1994-08-02 1999-01-12 Intel Corporation Method and apparatus for calculating effective memory addresses
US6006324A (en) * 1995-01-25 1999-12-21 Advanced Micro Devices, Inc. High performance superscalar alignment unit
JP3113792B2 (en) * 1995-04-27 2000-12-04 松下電器産業株式会社 Optimization device
US6151618A (en) * 1995-12-04 2000-11-21 Microsoft Corporation Safe general purpose virtual machine computing system
US6041403A (en) * 1996-09-27 2000-03-21 Intel Corporation Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction
US5860107A (en) * 1996-10-07 1999-01-12 International Business Machines Corporation Processor and method for store gathering through merged store operations
US5957997A (en) * 1997-04-25 1999-09-28 International Business Machines Corporation Efficient floating point normalization mechanism
US5903761A (en) * 1997-10-31 1999-05-11 Preemptive Solutions, Inc. Method of reducing the number of instructions in a program code sequence
US6112293A (en) 1997-11-17 2000-08-29 Advanced Micro Devices, Inc. Processor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead result
US6282634B1 (en) * 1998-05-27 2001-08-28 Arm Limited Apparatus and method for processing data having a mixed vector/scalar register file
US6247113B1 (en) * 1998-05-27 2001-06-12 Arm Limited Coprocessor opcode division by data type
US6018799A (en) * 1998-07-22 2000-01-25 Sun Microsystems, Inc. Method, apparatus and computer program product for optimizing registers in a stack using a register allocator
US6742110B2 (en) * 1998-10-06 2004-05-25 Texas Instruments Incorporated Preventing the execution of a set of instructions in parallel based on an indication that the instructions were erroneously pre-coded for parallel execution
US6338136B1 (en) * 1999-05-18 2002-01-08 Ip-First, Llc Pairing of load-ALU-store with conditional branch
US6647489B1 (en) 2000-06-08 2003-11-11 Ip-First, Llc Compare branch instruction pairing within a single integer pipeline
US6832307B2 (en) 2001-07-19 2004-12-14 Stmicroelectronics, Inc. Instruction fetch buffer stack fold decoder for generating foldable instruction status information
US20030023960A1 (en) 2001-07-25 2003-01-30 Shoab Khan Microprocessor instruction format using combination opcodes and destination prefixes
US6718440B2 (en) 2001-09-28 2004-04-06 Intel Corporation Memory access latency hiding with hint buffer
US7051190B2 (en) * 2002-06-25 2006-05-23 Intel Corporation Intra-instruction fusion
US6920546B2 (en) * 2002-08-13 2005-07-19 Intel Corporation Fusion of processor micro-operations
US7355601B2 (en) 2003-06-30 2008-04-08 International Business Machines Corporation System and method for transfer of data between processors using a locked set, head and tail pointers
KR101076815B1 (en) 2004-05-29 2011-10-25 삼성전자주식회사 Cache system having branch target address cache
US8082430B2 (en) * 2005-08-09 2011-12-20 Intel Corporation Representing a plurality of instructions with a fewer number of micro-operations
US7937564B1 (en) 2005-09-28 2011-05-03 Oracle America, Inc. Emit vector optimization of a trace
US7676513B2 (en) 2006-01-06 2010-03-09 Microsoft Corporation Scheduling of index merges
US7958181B2 (en) * 2006-09-21 2011-06-07 Intel Corporation Method and apparatus for performing logical compare operations
US7917568B2 (en) 2007-04-10 2011-03-29 Via Technologies, Inc. X87 fused multiply-add instruction

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040139429A1 (en) * 2000-12-29 2004-07-15 Ronny Ronen System and method for fusing instructions
US6889318B1 (en) * 2001-08-07 2005-05-03 Lsi Logic Corporation Instruction fusion for digital signal processor
US20040128485A1 (en) * 2002-12-27 2004-07-01 Nelson Scott R. Method for fusing instructions in a vector processor

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140208073A1 (en) * 2013-01-23 2014-07-24 Apple Inc. Arithmetic Branch Fusion
US9672037B2 (en) * 2013-01-23 2017-06-06 Apple Inc. Arithmetic branch fusion
GB2512725A (en) * 2013-03-15 2014-10-08 Intel Corp Fusible instructions and logic to provide or-test and and-test functionality using multiple test sources
GB2512726A (en) * 2013-03-15 2014-10-08 Intel Corp Methods and apparatus for fusing instructions to provide or-test and and-test functionality on multiple test sources
GB2512726B (en) * 2013-03-15 2016-02-10 Intel Corp Methods and apparatus for fusing instructions to provide or-test and and-test functionality on multiple test sources
US9483266B2 (en) 2013-03-15 2016-11-01 Intel Corporation Fusible instructions and logic to provide OR-test and AND-test functionality using multiple test sources
GB2512725B (en) * 2013-03-15 2016-08-03 Intel Corp Fusible instructions and logic to provide or-test and and-test functionality using multiple test sources
US9348596B2 (en) 2013-06-28 2016-05-24 International Business Machines Corporation Forming instruction groups based on decode time instruction optimization
CN105593807A (en) * 2013-06-28 2016-05-18 格罗方德半导体公司 Optimization of instruction groups across group boundaries
US9361108B2 (en) 2013-06-28 2016-06-07 International Business Machines Corporation Forming instruction groups based on decode time instruction optimization
US9372695B2 (en) 2013-06-28 2016-06-21 Globalfoundries Inc. Optimization of instruction groups across group boundaries
US9678757B2 (en) 2013-06-28 2017-06-13 International Business Machines Corporation Forming instruction groups based on decode time instruction optimization
US9477474B2 (en) 2013-06-28 2016-10-25 Globalfoundries Inc. Optimization of instruction groups across group boundaries
GB2530454A (en) * 2013-06-28 2016-03-23 Global Foundries Inc Optimization of instruction groups across group boundaries
WO2014208054A1 (en) * 2013-06-28 2014-12-31 International Business Machines Corporation Optimization of instruction groups across group boundaries
US9678756B2 (en) 2013-06-28 2017-06-13 International Business Machines Corporation Forming instruction groups based on decode time instruction optimization
WO2016042353A1 (en) * 2014-09-18 2016-03-24 Via Alliance Semiconductor Co., Ltd. Cache management request fusing

Also Published As

Publication number Publication date Type
CN101901128B (en) 2016-04-27 grant
DE102009051388A1 (en) 2010-05-06 application
US20100115248A1 (en) 2010-05-06 application
CN103870243A (en) 2014-06-18 application
WO2010056511A3 (en) 2010-07-08 application
KR101258762B1 (en) 2013-04-29 grant
US20170003965A1 (en) 2017-01-05 application
US20160378487A1 (en) 2016-12-29 application
KR20110050715A (en) 2011-05-16 application
JP5902285B2 (en) 2016-04-13 grant
US9690591B2 (en) 2017-06-27 grant
JP2015072707A (en) 2015-04-16 application
CN101901128A (en) 2010-12-01 application
JP2012507794A (en) 2012-03-29 application
US20160246600A1 (en) 2016-08-25 application

Similar Documents

Publication Publication Date Title
US5941981A (en) System for using a data history table to select among multiple data prefetch algorithms
US6430657B1 (en) Computer system that provides atomicity by using a tlb to indicate whether an exportable instruction should be executed using cache coherency or by exporting the exportable instruction, and emulates instructions specifying a bus lock
US5907702A (en) Method and apparatus for decreasing thread switch latency in a multithread processor
US6018786A (en) Trace based instruction caching
US6457119B1 (en) Processor instruction pipeline with error detection scheme
US7039794B2 (en) Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processor
US6609193B1 (en) Method and apparatus for multi-thread pipelined instruction decoder
US6944746B2 (en) RISC processor supporting one or more uninterruptible co-processors
US7676655B2 (en) Single bit control of threads in a multithreaded multicore processor
US6357016B1 (en) Method and apparatus for disabling a clock signal within a multithreaded processor
US20030005266A1 (en) Multithreaded processor capable of implicit multithreaded execution of a single-thread program
US20020095553A1 (en) Trace cache filtering
US20060179439A1 (en) Leaky-bucket thread scheduler in a multithreading microprocessor
US7178062B1 (en) Methods and apparatus for executing code while avoiding interference
US6971103B2 (en) Inter-thread communications using shared interrupt register
US7219185B2 (en) Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache
US20070260942A1 (en) Transactional memory in out-of-order processors
US20060095741A1 (en) Store instruction ordering for multi-core processor
US20070061548A1 (en) Demapping TLBs across physical cores of a chip
US6378023B1 (en) Interrupt descriptor cache for a microprocessor
US20090222625A1 (en) Cache miss detection in a data processing apparatus
US20080270758A1 (en) Multiple thread instruction fetch from different cache levels
US20080263373A1 (en) Token based power control mechanism
US8301849B2 (en) Transactional memory in out-of-order processors with XABORT having immediate argument
US20110066811A1 (en) Store aware prefetching for a datastream

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09826540

Country of ref document: EP

Kind code of ref document: A2

ENP Entry into the national phase in:

Ref document number: 2011534680

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2011534680

Country of ref document: JP

ENP Entry into the national phase in:

Ref document number: 20117007623

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase in:

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09826540

Country of ref document: EP

Kind code of ref document: A2

ENP Entry into the national phase in:

Ref document number: PI0920782

Country of ref document: BR

Kind code of ref document: A2

Effective date: 20110401