WO2010043804A1

WO2010043804A1 - Integrated circuit comprising a matrix of electronic cells and pixel-based detector comprising such a circuit

Info

Publication number: WO2010043804A1
Application number: PCT/FR2009/051933
Authority: WO
Inventors: Bernard Dinkespiler
Original assignee: Centre National De La Recherche Scientifique (C.N.R.S)
Priority date: 2008-10-13
Filing date: 2009-10-12
Publication date: 2010-04-22
Also published as: FR2937159B1; FR2937159A1

Abstract

This integrated circuit comprising a matrix of electronic cells distributed in columns of cells is characterized in that each cell comprises a data input/output register (12), the input/output registers (12) of the cells of each column being connected in series so as to cause a propagation of the data from cell to cell in each column.

Description

Integrated circuit comprising an array of electronic cells and pixel detector comprising such a circuit

The present invention relates to an integrated circuit comprising an array of electronic cells. Such an integrated circuit is, for example, part of a pixel detector organized according to an architecture, for example a two-dimensional array of rows and columns of pixels.

Each pixel then contains an analog part responsible for amplifying and processing the weak signal resulting from the photon-electron conversion of the pixel.

Beside this very sensitive analog part, there is, in each pixel, a digital part consisting of counters, configuration registers and clock distribution, etc.

For practical reasons, it is not possible to shift the digital part out of the pixel array. However, the cohabitation of these digital circuits with adjacent analog circuits, extremely sensitive, poses mutual interference problems that often prohibit their simultaneous operation.

A first problem, a source of analog / digital interference, lies in the presence of row and column selection rails used to address the pixels to be read.

A second problem lies in the presence of a "data bus" which carries the data to be extracted from the matrix. In practice, it is a large number of equipotential lines that cross the matrix from one side to the other and undergo intense electromagnetic activity during the reading.

In practice, the pixel detectors operate according to a time-sharing operational scheme between a phase of capturing an image on the one hand and detector configuration and data transfer phases to the pixels of the matrix. somewhere else. Therefore, in current pixel detectors, data transfer never occurs during the image capture phase.

This constraint results in the existence of a dead time that is detrimental under certain experimental conditions, particularly in the case of sensitive applications. By way of example, in crystallography, certain experiments require continuous recording of the images, without dead time. In medical imaging, the dead time is equivalent to a higher radiation dose for the patient, all other things being equal.

It is therefore useful and even essential to conduct a particular experiment to have a pixel detector devoid of dead time. The object of the invention is to solve the problems mentioned above about cell matrices to reduce the dead time.

For this purpose, the subject of the invention is an integrated circuit comprising a matrix of electronic cells distributed by columns of cells, characterized in that each cell comprises a data input / output register, the input / output registers of the cells of each column being connected in series to cause cell-to-cell data propagation in each column.

According to other aspects of the invention, the integrated circuit comprises one of the following characteristics: it comprises means for transmitting incoming data to / out of the matrix, integrated in an electrical circuit of the bottom of columns of the matrix ,

the means for transmitting the incoming data to the matrix comprise a data input bus connected to the first of a plurality of serial input registers each associated with a column of the matrix and each connected to the input register; output of the first cell of the corresponding column,

the means for transmitting the outgoing data of the matrix comprise a data output bus connected to the last of a plurality of serial output registers each associated with a column of the matrix and each connected to the input / output register of the first cell of the corresponding column, - it comprises an input of at least a first control signal and means forming a retarder of the first control signal are interposed between the successive columns and / or the successive cells of each column of the matrix to cause spatio-temporal propagation of the first control signal through the array, - the first control signal is a clock signal,

each column comprises an input of a second control signal for enabling / blocking the operation of the input / output registers of the cells of this column to validate / block the propagation of the data in said column,

the first and second control signals are associated through a logical AND gate before being applied to the cells,

each cell comprises means for processing a signal and each column comprises an input of a third control signal for enabling / blocking the operation of the cell processing means of this column to enable / block the signal processing in said column, and the cells are formed of pixels and the processing means of each pixel comprise a photon counter. The invention also relates to a pixel detector comprising such an integrated circuit.

Thus, the invention makes it possible to eliminate the dead time problem by using an architecture making it possible to simultaneously operate the analog and digital circuits during certain reading and / or configuration phases of the pixel detector.

The solution proposed by the invention also makes it possible to optimize, as a function of the level of electromagnetic disturbance acceptable in the intended application, the dead time and the reading speed of the detector. Embodiments of the invention will now be described in a more precise but nonlimiting manner with reference to the appended drawings, in which:

FIG. 1 illustrates a pixel matrix structure to which the invention can be applied;

FIG. 2 illustrates an elementary pixel of this matrix; FIG. 3 is a block diagram illustrating the structure of the digital part of this elementary pixel;

FIG. 4 is a block diagram illustrating the operation of the digital part of this elementary pixel according to the invention;

FIG. 5 is a block diagram illustrating the structure and operation of the circuit according to the invention;

FIG. 6 is a block diagram illustrating the structure and operation of the circuit according to a first embodiment of the invention;

FIG. 7 is a block diagram illustrating the structure and operation of the circuit according to a second embodiment of the invention; FIG. 8 is a block diagram illustrating the structure and operation of the circuit according to a third embodiment of the invention; and

- Figure 9 is a block diagram illustrating the structure and operation of the circuit according to a fourth embodiment of the invention.

As mentioned above, the invention relates to an array of electronic cells distributed by cell columns.

In the remainder of the description, an exemplary embodiment based on a matrix of pixels will be described.

Such a structure is illustrated in FIG. 1, in which a matrix circuit designated by the general reference 1 in this figure is recognized, comprising a matrix of pixels designated by the general reference 2, divided into columns of pixels, which are associated with electronic means of bottom of columns designated by the general reference 3.

These electronic means of bottom of columns contain circuits common to the pixels in a conventional manner. More precisely, the constitution of an elementary pixel of this circuit 1 is illustrated in FIG. 2, where it can indeed be observed that such a pixel comprises a digital part designated by the general reference 4 in this figure, associated with an analog part designated by general reference 5.

As can be seen from this figure, the digital portion is generally carefully separated from the analog portion to limit mutual influences.

However, this matrix structure leads to a certain inevitable proximity between the analog and digital parts of the pixels, with the disadvantages mentioned above.

The structure of the digital part 4 of the pixel is detailed in FIG. 3. This digital part 4 comprises means for processing a signal 6 named "photon" transmitted by the analog part 5 when an incident photon is detected by the detector. to pixels.

The photon processing means comprise a counter 8 whose content is incremented each time an incident photon is detected. The counter 8 is generally accessible at least in read mode and possibly in write mode for test purposes for example.

The digital part 4 of the pixel also comprises a configuration register 10 making it possible to adjust certain parameters of the image taking individually for each pixel. This configuration register 10 serves, by way of example, to individually correct the setting of a parameter of the shooting to obtain uniformity of adjustment for all the pixels of the matrix 2. It is also used to "mask" a pixel whose behavior is not correct. This configuration register 10 is accessible for reading and writing. The digital portion 4 of the pixel comprises, according to the invention, an associated input / output register 12, through an information transmission link 13, to a multiplexer 14 of data wired in such a way that the operations can be performed. following:

to load the contents of the counter 8 into the input / output register 12 through an information transmission link 16, - load the content of the configuration register 10 into the input / output register

12 through an information transmission link 18;

- load the input / output register 12 in the configuration register 10 through an information transmission link 20; - Shifting a bit in a rising direction of the data placed in the input / output register 12 through chaining means 22 with the next pixel in the same column; and

performing a one-bit downward shift of the data placed in the input / output register 12 through chaining means 24 with the preceding pixel in the same column.

By way of example, FIG. 4 illustrates the operation of the digital part 4 to carry out the functions described above.

This operation is illustrated for 3 consecutive bits i-1, i and i + 1 in the pixel. In this example the multiplexer 14 has four data inputs and one input of a selection signal "SEL".

The selection signal "SEL" makes it possible to choose, from among the four following possibilities, the data that will be loaded into the input / output register 12 during a next clock pulse applied to a CLK input of the input register / exit 12:

the data bit of counter 8 of the same rank denoted Cpti, the configuration data bit of the same rank denoted Cfgi,

the output bit of the input / output register 12 of the next pixel in the same column denoted Rci + 1; and

the output bit of the input / output register 12 of the preceding pixel in the same column denoted Rci-1. Thus the least significant bit of each pixel is chained to the most significant bit of the preceding pixel of the same column and the most significant bit of each pixel is chained to the least significant bit of the next pixel of the same column.

Thus, all the bits of the input / output registers 12 of the pixels of the same column are chained so as to form a single chain. The least significant bit of the first pixel of the column is connected to a register located in the lower column electronic circuit 3 of the matrix as will be described in more detail with reference to FIG.

FIG. 5 represents the structure of the pixel matrix according to the invention. In this figure 5 are thus represented the first three pixels ("pixel 0", "pixel 1", "pixel 2") of the first four columns of the matrix as well as means for transmitting incoming data to / out of these pixels integrated in the electronic circuit of the bottom of columns of the matrix 2.

According to the invention, the means for transmitting the incoming data to the matrix 2 comprise a data input bus connected to the first of a plurality of input registers 32, in series, each associated with a column of the matrix. and each connected to the input / output register 12 of the first pixel "pixel 0" of the corresponding column.

Similarly, the outgoing data transmission means of the matrix comprise a data output bus 34 connected to the last of a plurality of output registers 36, in series, each associated with a column of the matrix and each connected to the input / output register 12 of the first pixel "pixel 0" of the corresponding column.

This mode of exchange of data by serial offsets between the inside and the outside of the pixel matrix makes it possible to avoid the traditional use of a random addressing by line and column which involves the use of line selection rails and columns that pass through the matrix of pixels from one side to the other and which, when these signals are active, can seriously disturb the analog circuits in operation.

The use of serial offsets to enter and exit the information in the pixel array avoids this major disadvantage of random addressing. In addition, the "data bus" of the state of the art has also been eliminated.

Indeed, according to the architecture proposed by the present invention, the data propagates inside the matrix 2 by series shift. The data thus extracted from the pixels of the matrix 2 are collected by the bottom column registers 36 which provisionally store them and transmit them out of the matrix through the output bus 34.

Thus, the reading of the matrix 2 happens in two distinct phases. The first phase is to load the registers 36 of bottom of columns with the data of the matrix 2 by serial shift of the data of the pixels in each column.

The second phase consists in evacuating the data of the registers 36 towards the outside of the circuit.

In practice, the second phase relates to only a part of the data, namely the data from the first pixel ("pixel 0") of each column of pixels. This operation is repeated until the total reading of the matrix 2.

This second phase is harmless for the analog circuits of the matrix because the bottom circuit of columns 3 is physically separated from the matrix all the more when the feeding of this bottom circuit of columns 3 is separated from that of the digital part 4.

A similar operation is implemented for writing data in the pixels. Thus, the most restrictive phase from the point of view of electromagnetic disturbances is the first phase.

The dead time of reading is thus dominated by this first phase.

Figure 6 illustrates an embodiment of the operation of the pixel counters. This operation is controlled by a control signal named "CEN" which is sent to an input 40 of each column of pixels and then propagated to all the pixels of this column.

According to the embodiment of FIG. 6, the "CEN" control signal is common to all the pixels and comes from a global control signal "CEN _G ".

Thus, all the counters 8 of all the pixels are controlled simultaneously to trigger or stop the count.

In the state of the art, it is forbidden to count during the data acquisition phase. This results in a dead time typically of the order of 50% of the total operating time of the pixel detector.

Thanks to the invention, the counters count permanently except for the phases during which the serial shift of the data in the matrix takes place and the phases during which the data are stored in the input / output registers.

12. The resulting dead time is typically of the order of 10% maximum of the total operating time of the pixel detector.

This time of 10%, although much lower than that of the state of the art, can nevertheless be troublesome for certain sensitive applications. The embodiments described in the following description with reference to FIGS. 7 to 9 aim at further reducing this dead time.

A first way of reducing this dead time consists, as illustrated in FIG. 7, in minimizing the simultaneous switching of the cells of the matrix, that is to say, in the example illustrated, pixels.

Indeed, in this FIG. 7, a matrix of pixels is identified which is designated by the general reference 50 and which therefore comprises several columns such as, for example, the columns 51, 52 and 53, of pixels such as the pixels designated by the references 54 , 55 and 56 for column 51. Note that in the remainder of the description, the use of the term matrix may cover the overall structure of the matrix globally or different parts thereof, in which the different pixels are associated in the form of a matrix. submatrix.

Thus, this matrix or this part of matrix comprises a single input for a control signal such as for example the signal designated S in this figure and bearing the reference 57 thereon, which is intended to be distributed to the various pixels of this matrix.

For this purpose, means forming a retarder such as for example the retarder 58 are interposed in series between the different columns 51, 52 and 53. These means forming a retarder are for example integrated in the electrical circuit of the bottom of columns of the matrix.

Likewise, retarders such as for example the self-timer designated by the general reference 59 can be integrated in the pixels of each column, these being also connected in series. Thus, any control signal intended for a large number of pixels and possibly all, such as for example any driving pulse, is transmitted by each pixel to the neighboring pixel of the top in its column, after passing through a delay circuit whose function is therefore to delay the propagation of this pulse, from a single point of entry. Similarly, the propagation of this control signal from one column to the next of the matrix is delayed by a similar retarder located at the bottom of the column.

This then results in a propagation of the control signal through the matrix, according to a spatio-temporal pattern, in the manner of a wave-like wavefront, schematized by the line W moving in the direction D according to a spatio-temporal pattern. a diagonal of the matrix.

Thus, by taking an example of a circuit in which a control pulse is sent on 12 flip-flops of 9600 pixels of each circuit, the change of state of approximately 1 10000 flip-flops is potentially triggered.

Without the delay device described above, these switches would take place in a very short time of the order of 200 ps.

Thanks to the integration of the retarders, these switches can be spread over time over about 100 ns and in the plane defined by the matrix, the wavefront of the wave thus generated moving approximately along the diagonal of the pixel matrix. . Thus, the inrush currents due to these switches are distributed regularly over time and according to the power pads, classically distributed along the circuit. This propagation in wave is then adapted to the discretion of the designer of the circuit for all the signals which it considers potentially troublesome in the context indicated previously.

More particularly, the use of this wave propagation is adapted in a particular embodiment to the "CLK" clock signal.

Since the clock switches of the input / output registers 12 are thus spread according to the wave W, the serial offsets of the data are also spread over time.

Thus, it is no longer necessary to prohibit counting during data offsets. The dead time then corresponds in this case only to the data storage time in the input / output registers 12. This dead time is negligible.

A second way of reducing this dead time is, as illustrated in FIG. 8, to perform the series offsets only on a subset of columns among the columns of the matrix. This is implemented in one embodiment of the invention using a control signal "CLK EN" which allows for each column to enable / block the operation of the input / output registers 12 of the pixels of FIG. this column to validate / block the propagation of data in the column.

The control signal "CLK EN" is input to an input 60 of the circuit and it is stored in registers 62 of the bottom of columns associated with the columns of the matrix, each register comprising the value of this control signal for the column concerned.

Thus, for a given column "i", the value stored in the register 62 concerned is "CLK EN i".

In a particular embodiment of the invention, the clock signal "CLK" and the signal "CLK EN i" are associated through a logic "AND" gate 64 before being applied to the pixels of the matrix.

Thus, in the case where the clock "CLK" is propagated according to the wave W, the serial data offsets for the validated columns are also spread.

By way of example, the signal "CLK EN" validates the operation of the input / output registers 12 of one column out of 10, ie the columns 0, 10, 20, ... while blocking the operation of the registers d I / O 12 of all the other columns then it validates the operation of the input / output registers 12 of the columns 1, 1 1, 21, ... while blocking the operation of the input / output registers 12 of all the other columns, etc., until all the columns are exhausted. The combination of wave-wave propagation and multiplexing of serial data offsets between the columns further reduces the level of electromagnetic disturbance of the pixel detector.

However, this solution has the drawback of lengthening the duration of reading (or writing) of the data of the matrix. This lengthening of the duration is however not generally troublesome in the majority of the applications.

A third method to improve the dead time is illustrated in FIG. 9.

This method aims to multiplex the counting between the columns. Thus, counting is allowed only for a subset of columns and forbidden for other columns that are more bothered by reading / writing data. This has the consequence of having a dead time per column rather than an overall dead time for the entire circuit.

This method is implemented in one embodiment of the invention using the CEN control signal which allows for each column to enable / block the count of photons in the pixels of this column.

The signal "CEN" is input to an input 70 of the circuit and it is stored in registers 72 of the bottom of columns associated with the columns of the matrix, each register comprising the value of this control signal for the column concerned. Thus, for a given column "i", the value stored in the register 72 is "CEN i". In a particular embodiment of the invention, the global count control signal "CEN _G " in the matrix is associated with the signal "CEN i" through a logic "AND" gate 74 before being applied to the pixels of FIG. the matrix.

The various embodiments described above thus allow the user to program the dead time and the read / write speed of data in the matrix of cells according to the desired application.

Of course, other embodiments can still be envisaged.

Claims

1. An integrated circuit comprising an array of electronic cells distributed by columns of cells, characterized in that each cell comprises an input / output register (12) of data, the input / output registers (12) of the cells of each column being connected in series to cause cell-to-cell data propagation in each column.

2. An integrated circuit according to claim 1, characterized in that it comprises means for transmitting incoming data to / out of the matrix, integrated in an electric circuit bottom of columns (3) of the matrix.

3. The integrated circuit as claimed in claim 2, characterized in that the means for transmitting the incoming data to the matrix comprise a data input bus (30) connected to the first of a plurality of input registers (32). in series each associated with a column of the matrix and each connected to the input / output register (12) of the first cell of the corresponding column.

4. An integrated circuit according to claim 2 or 3, characterized in that the means for transmitting data leaving the matrix comprise a data output bus (34) connected to the last of a plurality of output registers (36). in series each associated with a column of the matrix and each connected to the input / output register (12) of the first cell of the corresponding column.

5. An integrated circuit according to any one of the preceding claims, characterized in that it comprises an input (57) of at least a first control signal (S) and in that delay means (58, 59 ) of the first control signal (S) are interposed between the successive columns and / or the successive cells of each column of the matrix, to cause a spatio-temporal propagation of the first control signal (S) through the matrix.

6. An integrated circuit according to claim 5, characterized in that the first control signal (S) is a clock signal (CLK).

7. Integrated circuit according to any one of the preceding claims, characterized in that each column comprises an input of a second control signal (CLK EN) for enabling / blocking the operation of the input / output registers of the cells of this column to validate / block the propagation of data in said column.

8. An integrated circuit according to claim 5 or 6 and claim 7, characterized in that the first (CLK) and second (CLK EN) control signals are associated through a logical AND gate (64) before being applied. to the cells.

9. Integrated circuit according to any one of the preceding claims, characterized in that each cell comprises means for processing a signal and in that each column comprises an input of a third validation control signal (CEN). / blocking the operation of the cell processing means of this column to enable / block the signal processing in said column.

10. An integrated circuit according to claim 9, characterized in that the cells are formed of pixels and in that the processing means of each pixel comprise a counter (8) of photons.

1. Pixel detector comprising an integrated circuit according to any one of the preceding claims.