WO2010040398A1

WO2010040398A1 - Chip interconnection

Info

Publication number: WO2010040398A1
Application number: PCT/EP2008/063459
Authority: WO
Inventors: Per Ligander; Katarina B0Ustedt
Original assignee: Telefonaktiebolaget L M Ericsson (Publ)
Priority date: 2008-10-08
Filing date: 2008-10-08
Publication date: 2010-04-15

Abstract

The present invention relates to a chip interconnection (10A). It comprises a carrier substrate (1A) comprising a thin film with an upper and a lower side. At least one of said upper and lower sides comprises a metal pattern with a plurality of metal connection elements (3A 1 3A 61). An opening (2A) with a given area is provided in said thin film carrier substrate and at least some of the metal connection elements are disposed adjacent to the border of the opening (2A). The thin film carrier substrate (1A) is adapted to be located on a chip such that at least some of the metal connection elements are colocated by means of an overlap with chip pad interconnects for interconnection with said chip pad interconnects.

Description

Title:

CHIP INTERCONNECTION

FIELD OF THE INVENTION

The present invention relates to chip interconnection. It particularly relates to a chip interconnection as such but also to structure comprising one or more coplanar chips and a chip interconnection. Most particularly the invention relates to an arrangement with a chip adapted to be connected to a radiating element. The invention also relates to a method for chip interconnection .

STATE OF THE ART

Chip interconnection is a complicated issue. A well established technique is to connect a chip to a carrier, a substrate, by means of wire bonding. Then the chip is provided with pads and by means of a bonding wire the pads are connected to the carrier substrate. Another known technique for chip interconnection is to use solder bumps (flip-chip) . It can in practice only be used for a silicon chip. If solder balls or bumps are used, the active surface of the chip has to face down to the carrier which means that underfill will be necessary to guarantee the reliability of the chip interconnection.

It is a problem that a chip with bumps connected to a carrier must be additionally secured to the carrier to assure mechanical strength. Normally the chip is then additionally glued on to the carrier, e.g. by means of epoxy underfill. This however negatively affects the electrical properties. It is becoming more and more attractive to use high frequency chips for various implementations. Wire bonding is however not suitable for high frequency applications, for example for frequencies of about 60-70 GHz and higher. For silicon chips, a sort of bumps can be used at microwave frequencies. The problems associated with underfilling referred to above become even more pronounced at high frequencies.

Generally, with increasing frequencies several technical problems become more difficult to solve the higher the frequency. One reason is that the dimensions of components and constituent parts become smaller. This in turn means that mounting becomes difficult. Another reason (also due to the smaller sizes) is that the tolerances become increasingly important since a smaller difference in size might easily lead to a bad functioning or no functioning at all. Size variations, non acceptable tolerances etc may also give rise to performance problems .

GaAs (Galliumarsenide) high frequency chip interconnection is a particularly complicated issue. For example, it is difficult to use solder bumps for GaAs chip interconnection. The main reason for that is that GaAs is thin and brittle, e.g. in comparison with SiGe, which means that it is sensitive to thermal expansion. If solder bumps are soldered on to GaAs, tensions are created, which requires a matching between the coefficients of thermal expansion of GaAs and solder bumps. Solder bumps of Au and thermo compression is also problematic, since the bumps are on the backside of the chip and therefore exposed to friction against the substrate.

It is particularly difficult to interconnect high frequency chips to a radiating element, for example an antenna or a probe structure, without the production process affecting performance, mainly due to losses and reflections in the interface chip- antenna or chip waveguide and interface chip-carrier.

Today there are no satisfactory solutions to the problems of interconnecting a high frequency chip, particularly for frequencies between 70-80 GHz or even considerably higher. For lower frequencies, for example 40 GHz, the involved components are often encapsulated.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide for improved chip interconnection. It is partiularly an object to provide a chip interconnection suitable for high frequency chips, most particularly adapted to operate at frequencies about 70-90 GHz or more, but also for chips adapted to operate at much lower frequencies, such as about 20 GHz, or anything therebetween.

It is most particularly an object to enable connection of a high frequency chip to an antenna or a probe structure such that a high performance can be provided and wherein tolerances are a less critical issue than for known connection methods.

It is also an object to provide a method for connecting a high frequency chip to a carrier substrate which to the lowest possibly extent affects the performance. Particularly it is an object to provide a structure which can be easily assembled, which is reliable and which enables a high performance. Most particularly it is an object to provide a structure comprising a chip and a chip interconnection wherein a proper impedance matching can be achieved between the chip output and a radiating arrangement such as an antenna or a probe structure. Therefore a chip interconnection is provided which comprises a carrier substrate, said carrier substrate comprising a thin film with an upper and a lower side. At least one of said upper and lower sides comprises a metal pattern with a plurality of metal connection elements. The film carrier also comprises an opening with a given area provided in the thin film. At least some of the metal connection elements are disposed adjacent to the border of the opening, in a border area. The thin film carrier is adapted to be located on (on top of or below) a chip such that the chip substantially covers the opening, and such that an overlap is produced with the border area. At least some of the metal connection elements are co-located, by means of said overlap, with chip pad interconnects for interconnection with said chip pad interconnects. Particularly the chip is a high frequency chip.

A structure is also provided which comprises one or more planar chips and a chip interconnection which is adapted to be connected to one or more radiating elements. The chip interconnection comprises a carrier substrate comprising a thin film with an upper and lower side and at least one of said upper and lower side comprises a metal pattern with a plurality of metal connection elements. An opening with a given area is provided in the thin film carrier. At least some of the metal connection elements are disposed adjacent to the border of said opening, in a border area. The carrier is connected to the chip, the chip substantially being located at the opening by means of the metal interconnection elements being co-located with chip pad interconnects comprising metallized pads by means of an overlap. The chip interconnection comprises or is integrated with a radiating element in a preferred embodiment. The invention also provides a method for interconnecting a chip and a carrier substrate, most particularly a chip and a radiating element. It comprises the steps of, for connection to a radiating element; providing a chip interconnection consisting of a carrier substrate comprising a thin film with an opening, providing a metal structure provided on said film wherein said metal structure comprises a plurality of metal connection elements of which at least some are located adjacent said opening in a border area. Preferably the chip interconnection comprises or is integrated with a radiating element. A chip is provided which comprises a plurality of metallized pads of which at least some are localized at relative positions in a manner corresponding to the relative locations of some of the interconnecting elements of the chip interconnection; placing the chip interconnection on the chip such that the chip substantially covers, and extends beyond, the opening such that at least some of the metal connections and metal pads are co- located and overlap; and connecting the co-located metal pads to the metal connecting elements. Substantially the chip is a high frequency chip operating at for example 40 GHz or more, most particulary at 60-90 GHz. Different and advantageous embodiments are given by the appended subclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will in the following be further described, in a non-limiting manner, and with reference to the accompanying drawings, in which:

Fig. 1 shows a chip and chip interconnection according to the state of the art,

Fig. 2 shows another state of the art chip and chip interconnection, Fig. 3 shows a first embodiment of a chip interconnection comprising a thin film carrier with an opening according to the present invention,

Fig. 4A shows a second embodiment of a chip interconnection also comprising a matching structure and an antenna,

Fig. 4B is a simplified view in cross-section taken along A-A in Fig. 4A,

Fig. 5 shows a third embodiment of a chip interconnection also comprising a matching structure and a waveguide probe,

Fig. 6 shows an exemplary embodiment of a high frequency chip according to the invention,

Fig. 7 shows the chip of Fig. 6 mounted in a substrate (motherboard) ,

Fig. 8A shows an embodiment of a structure according to the invention comprising a chip interconnection with an antenna, connected on top of the chip and motherboard of Fig. 7,

Fig. 8B is a schematical cross-sectional view taken along B-B of the structure in Fig. 8A,

Fig. 9 shows another embodiment of a chip interconnection according to the invention comprising also a radiating element which consists of a waveguide probe, Fig. 10 shows the structure of Fig. 9 disposed on a waveguide structure in cross-section taken along C-C in Fig. 9,

Fig. 11 is a schematical flow diagram describing interconnection of a chip and a radiating element according to a first particular embodiment, and

Fig. 12 is a schematical flow diagram describing an alternative implementation of a procedure for interconnecting a chip and a radiating element.

DETAILED DESCRIPTION

Fig. 1 very schematically illustrates a chip 2O₀ connected to a carrier substrate 3O₀ by means of a bond wire I₀ which is connected to chip pads. As referred to earlier, wire bonding is not suitable for high frequency chips.

Fig. 2 shows a chip 2O₀' connected to a carrier substrate 30' ₀ by means of solder bumps l'o- The chip is connected face down, with the active surface facing the carrier and on top of the substrate. Underfill is required, which affects the electrical properties in a negative manner, as also discussed earlier.

Fig. 3 is a top view of a chip interconnection according to a first embodiment of the present invention. The chip interconnection 1OA comprises a thin film carrier. The thin film may for example consist of polyimid, LCP (Liquid Crystal Polymer) or some other suitable material. It may particularly have a thickness of about 5-100 μm, particularly 25-50 μm. It may be thinner as well as thicker. According to the invention the thin film carrier substrate 1OA has a metal pattern on the upper and/or the lower side, here it is supposed to be on the lower side. The metal pattern comprises a plurality of metal connection elements 3Ai, 3An, 3A₂, 3A_2i, 3A₃, 3A_3i, 3A₄, 3A_4i, 3A₅, 3A₅i, 3A₆, 3A₆i, 3A₇, 3A₈, 3A₈i (not all provided with reference numerals in Fig. 3 for reasons of clarity) . An opening 2A with a given area is provided in the thin film carrier substrate and at least some of the metal connection elements are disposed adjacent to the border of the opening, in a border area, cf. elements 3A₁, 3A₂, 3A₃, 3A₄, 3A₅, 3A₆, 3A₇, 3A₈. The thin film carrier is adapted to be located on a chip (not shown in this figure) such that at least some of the metal connection elements are co-located with corresponding chip pad interconnnects for interconnection therewith. Preferably the interconnection 1OA is located, in this embodiment, on top of a chip such that the center of the chip substantially correspond to the center of the opening, with an overlap between chip interconnection border area containing the metal connection elements 3Ai, 3A₂,... as referred to above and chip for enabling connection between the metal connection element and the chip pad interconnects. Metal connection element 3A₇ comprises a high frequency interface whereas metal connection element 3A_8i is a low frequency interface (input or output depending on whether the chip operates in reception or transmission) . The thin film carrier substrate is illustrated as transparent for reasons of clarity.

Fig. 4A is a top view of a second embodiment of a chip interconnection 1OB. As in Fig. 3 the thin film carrier 1OB is provided with metal connection elements 3Bi, ..., 3B₇₂, only some of which being indicated with reference numbers in the figures since the numbering scheme corresponds to that of Fig. 3 but with the letter B instead of A. As in Fig. 3 the metal connection elements are located on the lower side of the thin film carrier 1OB, which therefore is illustrated as transparent. The thin film carrier 1OB comprises a opening 2B. In this embodiment, however, the chip interconnection also comprises an antenna 4B, here a dipole antenna 4B and two high frequency interfaces 3B₇i, 3B₇₂. It also comprises a low or intermediate frequency interface 3B₈, 3B₈i . As far as dimensions, materials etc are concerned, reference is made to the description of Fig. 3. In this embodiment the chip interconnection is supposed to have a size of about 3x4 to 3x6 mm, although it can be made larger as well as smaller. It should be noted that a direct connection is enabled between a chip high frequency output pads (not shown in this figure) and a radiating element, for example an antenna or a waveguide probe, here particularly a dipole antenna 4B. Direct connection here means that there is no connection via any chip motherboard or substrate on which the chip is mounted, which is extremely advantageous. This means that a chip can be connected directly to in principle every kind of radiating element or antenna (by means of the chip interconnection) including radiating element as well as preferably a matching structure.

Fig. 4B is a crossectional view of the arrangement in Fig. 4A along line A-A showing metal connection elements 3B₄, 3B₅, 3B₆ and part of the dipole antenna 4B. The interconnecting arrangement 1OB also includes an impedance matching structure 5B.

Fig. 5 schematically illustrates a further embodiment of a chip interconnection 1OC according to the present invention. It comprises a thin film carrier 1C with an opening 2C and a plurality of metal connection elements 3Ci, 3Cn,..., 3C₆i, high frequency interface 3C₇₂ for connection to a radiating element, here comprising a waveguide probe 4C, which hence also forms part of the chip interconnection. Low or intermediate frequency interfaces 3C₈i, 3C₈i are provided as in the preceding figures. Connection elements 3Ci, 3C₂, 3C₃, 3C₄, 3C₅, 3C₆, 3C₈, 3C_7i, 3C₇₃ are adapted to be connected to chip pads (not shown) . As in the preceding figures the metal connection element 3Cn, 3C₂i,..., 3C₆i, are adapted to be connected to a chip motherboard or the chip substrate as will be more thoroughly explained below. It should be clear that the size, shape, location of the metal connection elements and relation between metal connection elements to be connected to the chip and to the chip substrate respectively do not have to be as illustrated herein, there may also be more connection elements for connection to the chip and to the motherboard or fewer. They do also not have to be located in such a manner as illustrated herein, any variation is in principle possible. There are also no restrictions as to the shapes or sizes of the opening and of the chip respectively, other than that they have to be adapted to each other such that the concept works, i.e. a certain overlap leaving room for connection elements and chip pad interconnects, materials possible to join etc. It should be clear that the invention is not limited to a chip interconnection comprising a radiating element, e.g. an antenna or a waveguide probe, although such an arrangement represents an extremely advantageous implementation. There may also be more than one chip, with an opening for each chip or a common opening. The chip interconnection may also comprise more than one radiating element.

Fig. 6 schematically illustrates a high frequency chip 20. Chip 20 comprises a plurality of chip pad interconnects 13Bi, 13B₂, ..., 13B₆, 13B₈. It also comprises a high frequency output 13B₇i, 13B₇₂. The chip 20 is somewhat larger than the opening in chip interconnection 1OA, 1OB, 1OC and the chip pad interconnects are arranged and located in a similar manner as the metal connection elements of the chip interconnection.

Fig. 7 schematically illustrates a chip 20 mounted in a chip motherboard or chip substrate 30 in a conventional manner. Chip pad interconnects 13Bi and substrate interconnect 13Bn respectively are illustrated which are adapted to be interconnected with the metal connection elements of the chip interconnection, for example 1OA, 1OB or 1OC. 13B₈i here corresponds to intermediate or low frequency interface (the chip can be adapted to be used for reception and/or for transmission) . According to the present invention it becomes possible to make a direct connection of the chip high frequency interface, particularly output pads, to an antenna or waveguide probe, or more generally a radiating element, without any intermediate steps and without any connection passing via the chip substrate or motherboard.

Fig. 8A shows an embodiment of the present invention with a chip interconnection 1OB comprising an antenna, 4B, cf Fig. 4A, and a matching structure 5B. It comprises a plurality of metal connecting elements. The chip interconnection 1OB is here mounted on top of a chip 2B and the thin film carrier IB is transparent for reasons of clarity. The metal connection elements are here welded or soldered to the chip and chip substrate interconnects, illustrated with the tiny circles in the figure. According to one embodiment the chip interconnection may first be connected to the chip and the chip substrate. It is however also possible to first connect the chip interconnection and the chip and then assemble the chip interconnection with the chip and the chip substrate. Thus, when chip interconnection 1OB, as in Fig. 8A, comprises a radiating element, here an antenna 4B, a direct interconnection is provided between the chip 2B and the antenna 4B. In this embodiment also a matching structure 5B is provided through which it becomes possible to provide a proper impedance matching between the chip output/input and the antenna structure. Ideally the impedance is the same all the way from the chip to the radiating element, to avoid reflections and to allow as much as possible of the energy generated on the chip to be irradiated.

Fig. 8B is a cross-sectional view taken along line B-B in Fig. 8A. It can be seen how the chip 20 is mounted in the chip substrate 30 on top of which is provided the chip interconnection 1OB with the opening 2B arranged in a centralized manner on top of the chip 20. An overlap between chip and chip interconnection border allows for interconnection between for example interconnection element 3B₈ and corresponding chip pad interconnect 13B₈ on the chip, and metal connection element 3B_8i of the chip interconnection 1OB and corresponding chip substrate interconnect 13B₈i etc.

Fig. 9 shows a structure with a chip interconnection 1OC similar to the one described in Fig. 5. The structure also comprises a radiating element which is in the form of a waveguide probe. The structure comprises a chip interconnection 1OC with an opening 2C and a chip 20' mounted in a substrate or a motherboard 30' . The chip in motherboard is mounted on the interconnecting structure 1OC such that the chip becomes substantially located over and surrounding the opening 2C with an overlap as discussed above such that connecting elements as described in Fig. 5 can be welded or soldered to the chip pad interconnects as also discussed above.

Thus, in this case the chip 20' and the substrate 30' are mounted on top of the chip interconnection and they are therefore here made transparent for reasons of clarity. The structure here comprises a waveguide structure, cf. cross- sectional view of Fig. 10 where the probe 4C is located opposite to an opening in the waveguide structure on which the entire interconnecting structure is mounted. The probe 4C is shown in Fig. 10 although it should not be visible with regard to the location of the cross-section. As far as the chip interconnection is concerned, reference is made to Fig. 5 and corresponding reference numerals, not all of which are shown for reasons of clarity, are used. Only the chip and the chip substrate are given different reference numbers (20' and 30' respectively) . Thus, the inventive concept can be implemented for chip interconnections or interconnecting structures comprising a radiating element, e.g. any antenna or even a probe. It should however be clear that the invention is not limited to interconnecting structures including a radiating element. Independently of whether a radiating element is provided, the chip interconnection or the interconnecting structure may or may not be provided with a matching structure. The metal connecting elements and the chip or a substrate pads can be interconnected using different techniques, for example based on the use of heat, pressure or ultrasound. In advantageous embodiments the interconnecting elements and the chip interconnect pads comprise gold (Au) , but the invention is not limited to the use of Au. In one embodiment thermo compression bonding is implemented which is a bonding in for example gold on atomic level. It is also possible to use laser soldering. Then it is in principle possible to use also for example copper (Cu) . It is also possible to use a solder which may contain Pb or not. A laser can be used which generates no heat in the plastic (polyimide, e.g. LCP or similar) but melts the metal. Glueing and other appropriate techniques can also be used.

In preferable or advantageous implementations the chip comprises a GaAs chip. In other implementations it comprises a SiGe chip. It is also possible to implement CMOS technology or CMOS chips. For coplanar waveguide implementations, preferably a SiGe or an Si chip (CMOS thechnology) is used whereas for microstrip implementations most advantageously GaAs is used.

Fig. 11 is a schematical flow diagram describing the procedure of interconnecting a chip with a radiating element, i.e. according to the invention through providing a specific chip interconnection. It is supposed that a chip interconnection comprising a thin film carrier is provided with an opening, 100. Materials, dimensions etc have been discussed earlier in the application. The chip interconnection comprises, at least on one side, a metal structure comprising metal connection elements which are provided adjacent to the opening and the radiating element on the thin film, 101. The thin film carrier is then located on a high frequency chip mounted in a motherboard or substrate such that the connection elements of the interconnecting structure become co-located with chip pad interconnects close to the chip perifery and also to connector pads provided on the substrate, 102. Finally, the metal connection elements and the connector pads on chip and substrate are interconnected by welding, soldering or similar, 103.

Fig. 12 shows an alternative implementation for interconnecting a chip with a radiating element. Steps 200 and 201 correspond to steps 100 and 101 of Fig. 11. In step 202 the thin film carrier substrate is located on a high frequency chip such that the metal connection elements become co-located with connector pads (chip and interconnects) close to the chip periphery by means of an overlap. Subsequently the metal connecting elements and the connector pads on the chip are connected by welding, soldering or similar, 203. Finally the chip hence connected to the chip interconnection is mounted in a cavity in a substrate and additional metal connecting elements are connected with connector pads on the chip substrate by means of soldering or welding etc, 204. Thus, the connecting steps can be performed in a different order.

It is an advantage of the invention that a reliable high frequency chip interconnection is provided. It is also an advantage that it becomes possible to directly interconnect a high frequency chip to an antenna or a probe structure, more generally a radiating element, without having to pass the chip substrate, which is extremely advantageous and which has as consequence that a high performance is provided and tolerances become less critical. It is also an advantage that it becomes possible to provide a matching structure for a proper impedance matching between the chip output and an antenna or a probe structure. It is also an advantage that an interconnecting structure, particularly with a radiating element, and also a matching structure, can be assembled in a fast and easy manner and also that it can be mounted to a high frequency chip using an ordinary pick and place process. Further it is an advantage that the fabrication process does not substantially affect the performance .

It should be clear that the invention is not limited to the specifically illustrated embodiments, but that it can be varied in a number of ways within the scope of the appended claims.

Claims

1. A chip interconnection (1OA; 1OB; 10C) , c h a r a c t e r i z e d i n that it comprises a carrier substrate (IA; IB; 1C) comprising a thin film with an upper and a lower side, that at least one of said upper and lower sides comprises a metal pattern with a plurality of metal connection elements (3Ai-3A₆i; 3Bi-3B₇₂; 3Ci-3C₇₃) , an opening (2A;2B;2C) with a given area being provided in said thin film, at least some of the metal connection elements being disposed adjacent to the border of the opening in a border area, and in that the thin film carrier substrate is adapted to be located on a chip (20;20') such that at least some of the metal connection elements are co-located with chip pad interconnects by means of an overlap between the border area and said chip pad interconnects, for interconnection with said chip pad interconnects .

2. A chip interconnection (1OA; 1OB; 10C) according to claim 1, c h a r a c t e r i z e d i n that the carrier substrate (IA; IB; 1C) comprises a thin film of polyimide, LCP or a material with similar properties.

3. A chip interconnection (1OA; 1OB; 10C) according to claim 1 or 2, c h a r a c t e r i z e d i n that it further comprises a radiating element (4B;4C) .

4. A chip interconnection (10B) according to claim 3, c h a r a c t e r i z e d i n that the radiating element comprises an antenna (4B) .

5. A chip interconnection (10C) according to claim 3, c h a r a c t e r i z e d i n that the radiating element comprises a waveguide probe (4C) .

6. A chip interconnection according to any one of the preceding claims, c h a r a c t e r i z e d i n that at least one of the metal connection elements

(3A₇; 3B₇i, 3B₇₂; 3C₇₂) comprises a high frequency interface.

7. A chip interconnection (1OA; 1OB; 10C) according to any one of the preceding claims, c h a r a c t e r i z e d i n that the metal connection elements (3Ai-3A₆i; 3Bi-3B₇₂; 3Ci-3C₇₃) are adapted to be welded, soldered or glued or similar to chip pad interconnects or connected thereto by means of thermo- compression .

8. A chip interconnection (1OB; 10C) according to any one of the preceding claims, c h a r a c t e r i z e d i n that the metal pattern further comprises an impedance matching structure (5B) .

9. A structure comprising a chip interconnection (1OA; 1OB; 10C) and one or more planar chips (20;20') adapted to be connected to a radiating element, c h a r a c t e r i z e d i n that the chip interconnection (1OA; 1OB; 10C) comprises a carrier substrate comprising a thin film with an upper and a lower side, that at least one of said upper and lower sides comprises a metal pattern with a plurality of metal connection elements (3Ai- 3A₆i,- 3Bi-3B₇₂; 3Ci-3C₇₃) , an opening with a given area being provided in said thin film, that at least some of the metal connection elements are disposed adjacent to the border of said opening in a border area, and in that the carrier substrate

(IB, 1C) is connected to the chip (20;20') by means of the metal interconnection elements co-located with and connected to the chip pad interconnects (13Bi, ... , 13B₈) comprising metallized pads through an overlap between the border area and the chip pad interconnects, and in that the chip interconnection

(1OA; 1OB; 10C) comprises or is integrated with the radiating element or elements (4B;4C) .

10. A structure according to claim 9, c h a r a c t e r i z e d i n that the chip interconnection (1OB; 10C) further comprises or is integrated with an impedance matching network (5B) .

11. A structure according to claim 9 or 10, c h a r a c t e r i z e d i n that the chip interconnection (1OB; 10C) is adapted to directly interconnect the chip and the radiating element or elements.

12. A structure according to any one of claims 9-11, c h a r a c t e r i z e d i n that it further comprises a chip motherboard substrate (30;30') and in that the chip (20;20') is arranged in a cavity in said motherboard substrate.

13. A structure according to any one of claims 9-12, c h a r a c t e r i z e d i n that the chip is a high frequency chip for frequencies at or above 60 GHz, particularly for frequencies between 60 and 90 GHz.

14. A structure according to any one of claims 9-13, c h a r a c t e r i z e d i n that the thin film carrier substrate (IA; IB; 1C) of the chip interconnection has a thickness of approximately 5-100 μm.

15. A structure according to any one of claims 9-13, c h a r a c t e r i z e d i n that the carrier substrate comprises a thin film of polyimide, LPC or a material with similar properties.

16. A structure according to any one of claims 9-15, c h a r a c t e r i z e d i n that a plurality of the metal connection elements (3Ai-3A₆i; 3Bi- 3B₇₂; 3Ci-3C₇₃) are disposed adjacent to and surrounding the opening (2A;2B;2C), that the metallized chip connector pads are disposed at the periphery of and surrounding the chip (20;20'), and in that the chip interconnection is disposed on the chip in such a manner that the plurality of metal connection elements are located such that they face the metallized connector pads of the chip, said metallized connector pads and metal connection elements being soldered, welded or glued to each other or being interconnected by means of thermo compression or similar.

17. A structure according to claim 16, c h a r a c t e r i z e d i n that at least one of the metallized connector pads (13B₇i,- 13B₇₂) forms a high frequency output pad, a corresponding metal connection element or elements (3A₇; 3B_7i; 3B₇₂) of the chip interconnection forming a high frequency interface and in that the at least one chip high frequency output pad is directly connected to the radiating element.

18. A structure according to claim 17, c h a r a c t e r i z e d i n that the radiating element comprises an antenna (4B), e.g. a dipole antenna.

19. A structure according to claim 18, c h a r a c t e r i z e d i n that the chip interconnection (1OA; 10B) is connected on top of the chip (20) and a chip motherboard (30) .

20. A structure according to any one of claims 9-17, c h a r a c t e r i z e d i n that the radiating element comprises a waveguide probe (4C) and in that the chip interconnection (10C) is connected to a waveguide structure (40) such that the chip (20) is located on a side of the chip interconnection opposite to the wave guide structure (40) .

21. A structure according to any one of claims 9-18, c h a r a c t e r i z e d i n that the chip is a GaAs chip.

22. A structure according to any one of claims 9-20, c h a r a c t e r i z e d i n that the chip is a SiGe chip or a CMOS chip.

23. A method for interconnecting a chip and a radiating element, c h a r a c t e r i z e d i n that it comprises the steps of: providing a chip interconnection consisting of a carrier substrate comprising a thin film with an opening, a metal structure being provided on said thin film, and said metal structure comprising a plurality of metal connection elements, of which at least some are located adjacent to said opening in a border area, and a radiating element, providing a chip with a plurality of metallized pads at least some localized at relative positions in a manner corresponding to the relative locations of some of the interconnecting elements of the chip interconnection such that there is an overlap with the border area, placing the chip interconnection on the chip or vice versa, such that the chip substantially covers and overlaps the opening borders and at least some of the metal connections and metal pads are co-located, connecting the co-located metal pads and the metal connecting elements .

24. A method according to claim 23, c h a r a c t e r i z e d i n that the connecting step comprises: soldering, welding by using laser or thermo compression or ultra sound or glueing.

25. A method according to claim 23 or 24, c h a r a c t e r i z e d i n that the placing step comprises: co-locating a high frequency output of the chip and a corresponding metal connection element of the chip interconnection which is connected to the radiating element such that the radiating element is directly connected to the high frequency output of the chip.

26. A method according to any one of claims 23-25, c h a r a c t e r i z e d i n that the chip is a high frequency chip operating at e.g. 40 GHz or more, particularly at 60-90 GHz.

27. A method according to any one of claims 23-26, c h a r a c t e r i z e d i n that the radiating element is an antenna.

28. A method according to any one of claims 23-26, c h a r a c t e r i z e d i n that the radiating element comprises a waveguide probe, and in that the method comprises the step of: arranging the chip interconnection on a waveguide structure, such that the chip interconnection is disposed between the chip and the waveguide structure.