WO2010038387A1 - 回路設計方法、回路設計システム及び記録媒体 - Google Patents
回路設計方法、回路設計システム及び記録媒体 Download PDFInfo
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- G06F30/30—Circuit design
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- the present invention relates to a circuit design method, a circuit design system, and a recording medium, and more particularly to automatic generation of interconnections between a plurality of modules using a circuit design tool.
- a circuit is divided into functional blocks (modules), and each divided module is designed by a plurality of designers, and the designed individual modules are then connected to each other according to a predetermined correspondence relationship.
- the designed individual upper modules are then connected to each other according to a predetermined correspondence relationship, and a higher one module can be designed. In this way, it is possible to sequentially generate upper layers and finally achieve the circuit design of the entire semiconductor chip.
- RTL Register ⁇ TransferLLevel
- Verilog-HDL or VHDL is mainly used as a tool for achieving such circuit design, but in recent years, an abstract level model higher than RTL is used.
- High-level design high-level synthesis designed from the beginning has been adopted. According to the high-level design, it is possible to describe only the function along a predetermined processing flow and automatically generate an RTL model from the algorithm description using a high-level synthesis tool (behavior synthesis tool).
- CWB Cyber Work Bench
- Modules when connecting each designed module, if each module is different from each other, the input / output port name of the module is determined according to a predetermined correspondence relationship, Modules can be automatically connected based on information on only the input / output port names. However, if there are multiple identical modules among the modules to be connected, the input / output port names are usually the same between the same modules, so the modules are automatically connected with each other using only the input / output port name information. It is not possible to connect the modules manually. In such manual work, human connection errors are unavoidable, and the quality of the model may be degraded. Further, when there is a connection mistake, it is difficult to find the mistake on the spot. For example, a mistake may be found for the first time in the logic verification step, resulting in a problem that design productivity is lowered.
- timing generators such as a timing generator, a pattern generator, a waveform shaper, and a logical comparator are integrated into one chip in order to test the IC under test.
- a timing generator for timing generators, pattern generators, and waveform shapers, it is necessary to provide more than 1,000 identical functional blocks in one semiconductor test equipment system, so identical functional blocks in one chip It is required to provide a plurality. Therefore, it is important to solve the above problem particularly in an ASIC used for a semiconductor test apparatus.
- an object of the present invention is to provide a circuit design method capable of solving the above-described problems. This object is achieved by a combination of features described in the independent claims.
- the dependent claims define further advantageous specific examples of the present invention.
- One aspect of a circuit design method is a circuit design method for connecting a plurality of modules to each other, and acquiring port information including input ports and output ports of the plurality of modules; Obtaining the instance information indicating that there is a module having a plurality of instances having the same function among the plurality of modules, and connecting the plurality of modules to each other based on the port information and the instance information. Associating the input port with the output port.
- the instance information can include instance number information indicating the number of instances.
- the instance information can include instance identification information for identifying a plurality of instances.
- the associating step generates temporary port information from the port information based on the instance information, and sets the plurality of modules based on the temporary port information. Associating input ports and output ports to connect to each other can be included.
- the step of acquiring common connection information indicating that an output port of a predetermined module is commonly connected to each input port of the plurality of instances is further provided.
- the associating step generates the temporary port information from the port information based on the instance information and the common connection information, and connects the plurality of modules to each other based on the temporary port information.
- Corresponding output ports can be included.
- the step of acquiring information on a higher-level module generated by connecting the plurality of modules to each other is further included. Can be included.
- circuit design method it is possible to further include a step of storing the associated connection information as a connection information database after the associating step.
- the circuit design method according to the aspect of the invention may further include, after the associating step, a step of generating a source file of an upper module generated by connecting the plurality of modules to each other. .
- the method may further include displaying output port connection information.
- circuit design method it can be applied to the circuit design of a semiconductor device used in a semiconductor test apparatus.
- One aspect of a circuit design system is a circuit design system for connecting a plurality of modules to each other, and port information acquisition means for acquiring port information including input ports and output ports of the plurality of modules. And an instance information acquisition means for acquiring instance information indicating that there is a module having a plurality of instances having the same function among the plurality of modules, and the plurality of modules based on the port information and the instance information. And associating means for associating the input port with the output port so as to connect each other.
- the term “means” does not simply mean a physical means, but also includes a case where the function of the means is realized by software. Further, the function of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means.
- One aspect of a computer-readable recording medium storing a program according to the present invention is for connecting a plurality of modules to each other, and acquires port information including input ports and output ports of the plurality of modules.
- Associating the input port with the output port so as to be connected to each other.
- FIG. 3 is a diagram showing an aspect of a higher layer module with respect to FIGS. It is a figure which shows the function structure of the circuit design system concerning this embodiment. It is a block diagram which shows the hardware constitutions of the circuit design system concerning this embodiment. It is a figure which shows the outline of the circuit design method concerning this embodiment. It is a figure explaining STEP100 of FIG. It is a figure explaining STEP102 of FIG. It is a figure explaining STEP102 of FIG. It is a figure explaining STEP104 of FIG. It is a figure explaining STEP106 of FIG.
- the circuit design tool according to this embodiment connects a plurality of modules divided for each function and automatically generates one upper module.
- the circuit design tool according to the present embodiment can be applied to software having a function of automatically generating a program according to a predetermined program language.
- BDL Behavior Description Language
- FIGS. 1 and FIG. 2 show one aspect of a plurality of modules connected to each other in the present embodiment
- FIG. 1 shows a state before the plurality of modules are connected to each other
- FIG. 2 shows the plurality of modules connected to each other. The later state is shown.
- FIG. 3 is a diagram illustrating an aspect of the upper layer module with respect to FIGS. 1 and 2.
- a module (module name: model_abcd) 100 is provided with a plurality of modules (module names: model_a, model_b, model_c, model_d) 110, 120, 130, and 140.
- Modules 110, 120, 130, and 140 are obtained by subdividing the module 100 for each function.
- the former is referred to as a lower module (or lower hierarchy) and the latter is referred to as an upper module (or higher hierarchy).
- Can do In the relationship between the two, the former is referred to as a lower module (or lower hierarchy) and the latter is referred to as an upper module (or higher hierarchy). Can do.
- a plurality of lower modules 110, 120, 130, and 140 belonging to the upper module 100 are designed, and a plurality of lower modules are used using the circuit design tool according to the present embodiment.
- the modules 110, 120, 130, and 140 are associated with each other so as to be connected to each other, and one upper module 100 can be automatically generated as shown in FIG.
- the automatically generated module 100 can be associated with another module 102 so as to be connected to each other, for example, as shown in FIG. In this way, the upper layers are sequentially generated, and finally the circuit design of the entire semiconductor chip is achieved.
- Each lower module 110, 120, 130, 140 has a port used for data transmission / reception.
- the ports can include a reference clock port and a reference reset port as well as an input port and an output port.
- the lower module 110 has an input port (port information: i_a1, i_a2) and an output port (port names: a, b_1, b_2)
- the lower module 120 has an input port (port name: a, b) and an output port (port information: c)
- the lower module 130 has an input port (port information: c) and an output port (port information: d)
- the lower module 140 has an input port (port information: port information: c).
- the port information (port name) is attached to the port.
- ports that transmit and receive different data are individually provided with ports, and port information is also given different names.
- the plurality of lower modules 110, 120, 130, and 140 are arranged in order from the signal input side to the output side, and input / output ports between adjacent modules are connected according to a predetermined correspondence relationship.
- a plurality of lower modules are connected to each other.
- the input ports (port information: i_a1, i_a2) of the lowermost upstream module 110 correspond to the input ports of the upper module 100
- the output ports (port information: o_d1, o_d2) of the lowermost downstream module 140 Corresponds to the output port of the upper module 100.
- At least one of the plurality of lower modules has a plurality of instances having the same function.
- an instance is for specifying each of a plurality of modules having the same function, and the development of a plurality of modules having the same function in this way can be called instance expansion.
- the module 120 has a plurality of instances 120A and 120B
- the module 130 has a plurality of instances 130A and 130B.
- the plurality of instances 120A and 120B (or 130A and 130B) having the instance expansion have the same port and the same port information.
- the modules 120 and 130 have a plurality of instances
- the modules 110 and 140 each have one instance.
- the instance-expanded module may be the first or Nth at least one module, or the second to (N ⁇ 1) th at least one module. It may be present (the example shown in FIG. 1 is applicable) or a combination thereof.
- the mode of the modules shown in FIGS. 1 to 3 is merely an example, and the number of all modules, the number of modules to be expanded into instances, the number of multiple instances when the instances are expanded, the number of ports of each module, etc. It is not limited to the example mentioned above.
- FIG. 4 is a diagram illustrating a functional configuration of the circuit design system according to the present embodiment.
- FIG. 5 is a block diagram showing a hardware configuration of the circuit design system according to the present embodiment.
- a circuit design system 200 in which a program for performing circuit design is installed has, as main components, control means 210 for controlling circuit design processing, and information necessary for circuit design processing.
- a general-purpose computer including a CPU 201, a ROM 202, a RAM 203, an external storage device 204, a user interface 205, a display 206, a printer 207, and a communication interface 208 as shown in FIG. 5 can be applied to the circuit design system 200.
- the circuit design system 200 may be configured by a single computer or may be configured by a plurality of computers distributed on a network.
- the CPU 201 executes a predetermined program stored in the ROM 202, RAM 203, external storage device 204, or the like or downloaded via a communication network (a program defining the circuit design processing according to the present embodiment).
- a predetermined program stored in the ROM 202, RAM 203, external storage device 204, or the like or downloaded via a communication network (a program defining the circuit design processing according to the present embodiment).
- the circuit design system 200 is caused to function as various function realizing means (see FIG. 4) or various steps described later.
- control unit 210 shown in FIG. 4 includes, as main components, a higher module information acquisition unit 212, a port information acquisition unit 214, an instance information acquisition unit 216, a common connection information acquisition unit 218, an input port and an output port association unit. 220, an upper module source file generation unit 222, and a predetermined information display unit 224.
- the various function realization means are connected to the storage means 230, whereby information necessary for the circuit design processing processed by the respective means can be stored in the storage means 230 or read from the storage means 230.
- the various mechanism realization means reference can be made to the explanation of the various steps of the circuit design method described later.
- circuit design method according to the present embodiment can be performed using the circuit design system 200 (see FIGS. 4 and 5) described above.
- each step (including a partial step not attached with a reference numeral) in a flowchart to be described later can be executed in any order or in parallel within a range in which there is no contradiction in the processing contents.
- FIG. 6 is a diagram showing an outline of the circuit design method according to the present embodiment
- FIGS. 7 to 14 are diagrams for explaining details at each step of the circuit design method according to the present embodiment. It is.
- the processing described below with reference to each drawing is performed by executing steps specified in a predetermined program read from the storage unit 230 (for example, the RAM 203) based on the control of the control unit 210 (for example, the CPU 201). Can be realized.
- the upper module information acquisition unit 212 acquires necessary information about the generated upper module 100 (STEP 100).
- a predetermined menu screen may be displayed on the display 206, and the processing of STEP 100 may be started by performing an input for prompting the processing of STEP 100 from the menu screen.
- a plurality of icons corresponding to the processing of STEPs 100 to 110 shown in FIG. 6 are displayed on the display 206, and an input may be performed by clicking the icon corresponding to the processing of STEP 100 from the display.
- the above-described example is not limited to this step, and can be applied to other steps.
- an upper module setting screen 300 that prompts input of necessary information about the upper module is displayed on the display 206.
- necessary information about the upper module as shown in FIG. 7, for example, a module name, reference clock information (Mater) Clock), reference reset information (Master Reset), and the like can be cited.
- model_abcd, clk, and rst are entered in the respective fields.
- the user can click the setting end icon and proceed to the next step.
- the information acquired by the upper module information acquisition unit 212 can be stored in the storage unit 230 in order to read it in the steps described later.
- the port information acquisition means 214 acquires the port information of the lower modules 110, 120, 130, and 140 (STEP 102).
- a lower module setting screen 310 that prompts input of information necessary for the lower module is displayed on the display 206.
- the lower module setting screen 310 displays a list of all lower modules (model_a, model_b, model_c, model_d) 110, 120, 130, and 140 necessary for generating the upper module 100.
- the subordinate modules displayed in the list are selected one by one, the source file 312 of each subordinate module is opened, and the data of the source file 312 is read into the storage unit 230 (for example, the RAM 203).
- Such data reading may be performed according to the flowchart shown in FIG. 9, for example.
- a predetermined lower module is selected from the setting screen 310, and the source file 312 is opened (STEP 200).
- the program described in the file is read line by line from the top (STEP 202), input port (in declaration), output port (out declaration), reference clock (clock declaration), reference reset ( The description of “reset declaration” is recognized (STEPs 204 to 210), and if the description exists, each information is acquired (STEP 212).
- the reading of the data of the source file 312 is completed. Note that the information acquired by the port information acquisition unit 214 can be stored in the storage unit 230 in order to be read in a step described later.
- the instance information acquisition unit 216 and the common connection information acquisition unit 218 acquire the instance information and common connection information of the lower modules 110, 120, 130, and 140 (STEP 104).
- a lower module setting screen 314 that prompts input of instance information and common connection information in the lower module is displayed on the display 206 as shown in FIG.
- the lower module setting screen 314 displays a list of all lower modules (model_a, model_b, model_c, model_d) 110, 120, 130, and 140 necessary for generating the upper module 100.
- the modules 120 and 130 having a plurality of instances are selected one by one from the displayed lower modules.
- the module (model_b) 120 is selected, and the lower module information display screen 316 is opened.
- an instance information input area 318 and a common connection information input area 320 are displayed together with the port information of the lower module 120 acquired in STEP 102 and data information indicating the type of data.
- the user inputs the instance information in the instance information input area 318 and the common connection information in the common connection information input area 318 based on port information related to the lower module and a predetermined design rule.
- the instance information is information indicating that there is at least a module having a plurality of instances having the same function.
- Instance number information indicating the number of instances and instance identification for identifying the plurality of instances respectively.
- Information can be included.
- information for example, numbers, symbols, or character strings
- information “1” for identifying the instance is input to the first cell
- information “2” for identifying the instance is input to the second cell. . In this way, both instance number information and instance identification information can be input simultaneously.
- the information input as the instance identification information is port information (for example, “signal name_expansion value”) of the output port of the module 110 on the upstream side of the module 120 in which the instance is expanded or downstream from the module 130 in which the instance is expanded It can be determined based on port information (for example, “signal name_expanded value”) of the input port of the module 140 on the side. That is, as shown in FIG. 2, the output port of the module 110 has ports (port information: b_1, b_2) corresponding to each of the plurality of modules 120A and 120B that are instance-deployed.
- port information for example, “signal name_expansion value”
- the information input as the instance identification information in advance is the development value of the port information (for example, the information “1” and “2” following the underbar). You may match.
- the input port of the module 140 has ports (port information: d_1, d_2) corresponding to each of the plurality of modules 130A and 130B that are instance-deployed.
- Information input in advance as instance identification information may be matched with the expansion value of the port information so that the information matches each other.
- the instance identification information is not necessarily limited to match the expanded value of the port information as long as the ports described later can be associated with each other, and numbers, symbols, or characters that are different from the expanded value of the port information. You can enter a column.
- the common connection information is information indicating that an output port of a predetermined module is commonly connected to each input port of a plurality of instances. That is, as shown in FIG. 2, the output port (port information: a) of the module 110 is commonly connected to the input ports (port information: a) of the plurality of modules 120A and 120B that are instance-deployed.
- predetermined information for example, a number, a symbol, or a character string
- predetermined information is input to the cell corresponding to the port information a in the item “common connection information” in the common connection information input area 320.
- “1N” is input to the cell corresponding to the port information a in the item “common connection information”.
- the information input as the common connection information is not limited to the character string described above as long as it can be identified that the port is commonly connected.
- the information acquired by the instance information acquisition unit 216 and the common connection information acquisition unit 218 can be stored in the storage unit 230 in order to read out in the steps described later.
- STEP 104 an example in which both instance information and common connection information are acquired has been described.
- the instance information acquisition unit 216 may acquire the instance information of the lower modules 110, 120, 130, and 140.
- the input port and output port association means 220 associates the input ports and output ports of the lower modules 110, 120, 130, and 140 (STEP 106).
- FIG. 11 is a flowchart for explaining STEP 106 in more detail.
- necessary information previously stored in the storage unit 230 by the input port / output port association unit 220 is read, and based on the instance information and the common connection information acquired in STEP 104, STEP 102 is read.
- Temporary port information is generated from the port information acquired at (STEP 302).
- Table 1 shows an input information database in which temporary port information is generated from port information related to input ports
- Table 2 shows an output information database in which temporary port information is generated from port information related to output ports.
- the instance information and the common connection information are not given to those that have not been expanded, so the same information as the port information is the temporary port information.
- provisional port information i_a1, i_a2, d_1, d_2, o_d1, o_d2).
- temporary port information is generated based on the instance information for the instance expanded (temporary port information: b_1, b_2, c_1, c_2).
- the port information is changed to different temporary port information based on the instance information.
- the temporary port information can be matched between the ports to be associated with each other.
- temporary port information is generated on the basis of the common connection information (provisional port information: a) for the instances in which the common connection information is input in the instance expanded. That is, changing the port information to different temporary port information is hindered by the common connection information, and the port information is displayed as temporary port information as it is.
- the input information database (Table 1) and the output information database (Table 2) are created, and each database is stored in the storage unit 230, for example.
- the input port and the output port are associated with each other based on the generated temporary port information (STEP 304).
- the ports to be associated with each other have the same tentative port information. Therefore, the association between the input port and the output port is determined based on whether or not the tentative port information matches. Can do.
- the temporary port information in the output information database (Table 2) is read one by one and compared with the temporary port information in the input information database (Table 1). It is determined that they are associated so as to be connected, and the associated connection information is registered as a connection information database.
- Table 3 shows one aspect of the connection information database. As shown in Table 3, information to be registered as the connection information database includes output-side instance name and port information, input-side instance name and port information, input port and output port connection information, and the like.
- the generated connection information database can be finally stored in the storage unit 230.
- connection information database shown in Table 3 may be displayed on the display 206.
- the user may be able to visually recognize information based on the connection information database as a list.
- the display mode to be output to the display 206 is not limited. For example, at least information indicating an instance name, port name (port information), and connection information of an input port and an output port for connecting a plurality of modules to each other are included. Can be included.
- FIG. 12 is a diagram showing a flowchart of the upper module source file generation process.
- FIG. 13 shows an example of the upper module source file generated according to the flowchart of FIG.
- the upper module source file 400 includes a lower module reading unit 402, an input / output signal declaration unit 404, and an internal signal connection unit 406 as main components. Any configuration can be generated based on the information or database stored in the storage unit 230 in the steps described so far.
- such a source file 400 first generates a reading unit for the lower modules 110, 120, 130, and 140 (STEP 500), and then generates an input / output declaration unit for the upper module 100 (STEP 600). Finally, it can be generated by generating the internal signal connection part of the upper module 100 (STEP 700).
- the lower module name is read and output to the file (STEP 502), and then the port information of the lower module is read (STEP 504). Then, the port information (clock / reset / in / out) is identified and the declaration is output to the file (STEP 506). When the processing of all the port information is completed (STEP 508), the instance name is output to the file (STEP 510). It is confirmed that all lower modules have been called (STEP 512). In this way, the source file of the lower module reading unit 402 shown in FIG. 13 can be generated.
- connection information one line in the example of Table 3 is read from the connection information database (see Table 3) (STEP 602), and whether or not the read connection information is an external input / output signal. Judgment is made (STEP 604). As a result, if it is an external input / output signal, it is output to the file as an external input / output declaration (STEP 606). If it is not an external input / output signal, it is determined whether or not all connection information has been read (STEP 608). If there is still remaining connection information, the process returns to STEP 604 and the above-described procedure is repeated. Thus, by finally reading all connection information, the source file of the input / output signal declaration unit 404 shown in FIG. 13 can be generated.
- the upper module name is read and output to the file (STEP 702).
- one connection information is read from the connection information database (see Table 3) (STEP 704). Is the connection information between the insides (STEP 706). As a result, if the connection information is internal, the information is output to the file (STEP 708). If the connection information is not internal connection information, it is next determined whether the connection information is external connection information (STEP 710). If the connection information is external connection information, the information is output to the file. (STEP712). Alternatively, if the connection is not external, it is determined whether or not all connection information has been read (STEP 714). If there is still remaining connection information, the process returns to STEP 704 and the above-described procedure is repeated. Thus, by finally reading all connection information, the source file of the portion of the internal signal connection unit 406 shown in FIG. 13 can be generated.
- the upper module 100 can be automatically generated, so that the quality of the model to be designed and the design productivity can be improved.
- circuit design according to this embodiment can be applied to the circuit design of a semiconductor device (for example, ASIC) used in a semiconductor test apparatus.
- a semiconductor device for example, ASIC
- the semiconductor device 502 used in the semiconductor test apparatus 500 includes a plurality of modules such as a timing generator 510, a pattern generator 520, a waveform shaper / timing generator 530, and a logic comparator 540 in order to test the IC 600 under test.
- the waveform shaper and timing generator 530 and the logical comparator 540 are expanded into a plurality of instances, that is, a plurality of modules 530A to C and 540 to C having the same function.
- the waveform shaper and timing generator 530 and the logical comparator 540 each include a large number of instances. .
- the upper module is automatically generated very easily. Therefore, it is possible to improve the model quality and the design productivity more effectively.
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Abstract
Description
まず、図1~図3を参照して、本実施形態で処理するモジュールについて説明する。図1及び図2が、本実施形態において相互に接続する複数のモジュールの一態様を示し、図1が複数のモジュールを相互に接続する前の状態、図2が複数のモジュールを相互に接続した後の状態を示している。図3は、図1及び図2に対する上位階層のモジュールの一態様を示す図である。
次に、図4及び図5を参照して、本実施形態にかかる回路設計システムの概要を説明する。ここで、図4は、本実施形態にかかる回路設計システムの機能構成を示す図である。また、図5は、本実施形態にかかる回路設計システムのハードウェア構成を示すブロック図である。
次に、図6~図14を参照して、本実施形態にかかる回路設計方法の具体例について説明する。本実施形態にかかる回路設計方法は、上述した回路設計システム200(図4及び図5参照)を用いて行うことができる。なお、後述するフローチャートにおける各ステップ(符号が付されていない部分的なステップを含む)は処理内容に矛盾を生じない範囲で任意に順番を変更して又は並列に実行することができる。
次に、図15を参照して、本実施形態にかかる回路設計の適用例について説明する。本実施形態にかかる回路設計は半導体試験装置に用いられる半導体デバイス(例えばASIC)の回路設計に適用することができる。
生成することができるため、より効果的にモデルの品質の向上及び設計生産性の向上を図ることができる。
Claims (12)
- 複数のモジュールを相互に接続するための回路設計方法であって、
前記複数のモジュールの入力ポート及び出力ポートを含むポート情報を取得するステップと、
前記複数のモジュールのうち、同一機能を有する複数のインスタンスを備えるモジュールがあることを示すインスタンス情報を取得するステップと、
前記ポート情報及び前記インスタンス情報に基づいて、前記複数のモジュールを相互に接続するように入力ポートと出力ポートを対応付けるステップと、
を含む、方法。 - 前記インスタンス情報は、複数のインスタンスの個数を示すインスタンス個数情報を含む、請求項1記載の方法。
- 前記インスタンス情報は、複数のインスタンスをそれぞれ識別するインスタンス識別情報を含む、請求項1記載の方法。
- 前記対応付けるステップは、前記インスタンス情報に基づいて前記ポート情報から仮ポート情報を生成し、当該仮ポート情報に基づいて前記複数のモジュールを相互に接続するように入力ポートと出力ポートを対応付けることを含む、請求項1記載の方法。
- 所定のモジュールの出力ポートが、前記複数のインスタンスの各入力ポートに共通に接続されることを示す共通接続情報を取得するステップをさらに含み、
前記対応付けるステップは、前記インスタンス情報及び前記共通接続情報に基づいて前記ポート情報から仮ポート情報を生成し、当該仮ポート情報に基づいて前記複数のモジュールを相互に接続するように入力ポートと出力ポートを対応付けることを含む、請求項1記載の方法。 - 前記ポート情報を取得するステップの前に、前記複数のモジュールを相互に接続して生成される上位モジュールに関する情報を取得するステップをさらに含む、請求項1記載の方法。
- 前記対応付けるステップの後に、前記対応付けられた接続情報を接続情報データベースとして記憶するステップをさらに含む、請求項1記載の方法。
- 前記対応付けるステップの後に、前記複数のモジュールを相互に接続して生成される上位モジュールのソースファイルを生成するステップをさらに含む、請求項1記載の方法。
- 前記対応付けるステップの後に、少なくとも、インスタンス名を示す情報、前記ポート情報、及び、前記複数のモジュールを相互に接続するための入力ポートと出力ポートの接続情報を表示するステップをさらに含む、請求項1記載の方法。
- 半導体試験装置に用いられる半導体デバイスの回路設計に適用される、請求項1から9のいずれかに記載の方法。
- 複数のモジュールを相互に接続するための回路設計システムであって、
前記複数のモジュールの入力ポート及び出力ポートを含むポート情報を取得するポート情報取得手段と、
前記複数のモジュールのうち、同一機能を有する複数のインスタンスを備えるモジュールがあることを示すインスタンス情報を取得するインスタンス情報取得手段と、
前記ポート情報及び前記インスタンス情報に基づいて、前記複数のモジュールを相互に接続するように入力ポートと出力ポートを対応付ける対応付け手段と、
を含む、システム。 - 複数のモジュールを相互に接続するためのプログラムを格納したコンピュータ読取り可能な記録媒体であって、
前記複数のモジュールの入力ポート及び出力ポートを含むポート情報を取得するステップと、
前記複数のモジュールのうち、同一機能を有する複数のインスタンスを備えるモジュールがあることを示すインスタンス情報を取得するステップと、
前記ポート情報及び前記インスタンス情報に基づいて、前記複数のモジュールを相互に接続するように入力ポートと出力ポートを対応付けるステップと、
を実行させるプログラムを格納したコンピュータ読取り可能な記録媒体。
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US13/121,829 US20110191739A1 (en) | 2008-09-30 | 2009-09-25 | Circuit design method, circuit design system, and recording medium |
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