WO2010032830A1 - Digital phase comparator and method - Google Patents

Abstract

A digital phase comparator of high resolution is provided without increasing the circuit area and the power consumption.  A delay circuit array (21_1 to 21_n–1) generates delayed signals (CK_C(1) to CK_C(n–1)) obtained by delaying an input signal (CLK2) by equal intervals.  Hold circuits (22_1 to 22_n) use the delayed signals (CK_C(1) to CK_C(n–1)) to sample an input signal (CLK1).  An OR circuit (24) outputs OR of output signals of the hold circuits (22_1 to 22_n) as FCLK1.  A delay circuit array (11_1 to 11_n–1) generates delayed signals (D_C(1) to D_C(n)) obtained by delaying CLK1 by equal intervals.  Hold circuits (23_1 to 23_n) use the delayed signals (D_C(1) to D_C(n)) to sample CLK2.  An OR circuit (25) outputs OR of output signals of the hold circuits (23_1 to 23_n) as FCLK2.  A delay circuit array (51_1 to 51_m) generates delayed signals (D_F(1) to D_F(m)) obtained by delaying FCLLK1 by equal intervals.  A delay circuit array (52_1 to 52_m) generates delayed signals (CK_F(1) to CK_F(m)) obtained by delaying FCLLK2 by equal intervals that are different from the delay time intervals of the delay circuit array (51_1 to 51_m).  Hold circuits (53_1 to 53_m) use the delayed signals (CK_F(1) to CK_F(m)) to sample the respective delayed signals (D_F(1) to D_F(m)).  Hold circuits (12_1 to 12_n) use CLK2 to sample CLK1 and the delayed signals thereof (D_C(1) to D_C(n–1)).  Sampling results (Q_C(1) to Q_C(n)) of the hold circuits (12_1 to 12_n) and sampling results (Q_F(1) to Q_F(m)) of the hold circuits (53_1 to 53_m) are outputted to logic circuits (1, 5), respectively, as values corresponding to the phase difference between CLK1 and CLK2.

Description

Digital phase comparator and method

(Description of related applications)
The present invention is based on the priority claims of Japanese patent applications: Japanese Patent Application No. 2008-241171 (filed on September 19, 2008) and Japanese Patent Application No. 2009-059903 (filed on March 12, 2009), The entire contents of this application are incorporated herein by reference.
The present invention relates to a phase comparator, and more particularly to a digital phase comparator and method for detecting a phase difference and converting it into a digital signal.

In recent years, integration of wireless communication LSIs (Large Scale Integrated Circuits) to which a fine CMOS (Complementary MOS (Metal-Oxide-Semiconductor)) process is applied has been promoted. In a conventional wireless communication LSI, an analog PLL circuit is generally used as a PLL (Phase Locked Loop) circuit.

In an analog PLL circuit, phase difference information is output as a pulse width from a phase comparator (PD), and charge output according to the pulse width is converted into voltage information by a loop filter in a charge pump circuit (CP). Then, the oscillation frequency is controlled by inputting the voltage to a control voltage terminal of a VCO (Voltage Controlled Oscillator).

Such an analog PLL uses resistance and capacitance elements such as a loop filter, and therefore cannot benefit from miniaturization such as circuit miniaturization and cost reduction.

Also, due to the reduction in voltage due to miniaturization, characteristic degradation due to the influence of power supply noise and the like can be cited as problems.

On the other hand, in recent years, research and development of an all-digital PLL circuit in which the PLL circuit is configured in a digital configuration has been advanced.

In the all-digital PLL circuit, the frequency is controlled by digitally switching the minute varactor as the VCO control.

Therefore, instead of a phase comparator that outputs the phase difference information used in the conventional analog method as a pulse width, a digital phase comparator that outputs a digital value is required.

As a configuration of such a digital phase comparator, for example, a configuration as shown in FIG. 19 is known (see, for example, Patent Document 1). FIG. 20 is a timing chart for explaining the operation of the circuit of FIG. Digital phase comparison that outputs the phase difference as a digital value by sequentially delaying the output CLK1 of the VCO by cascaded inverter rows and capturing the output signal of each stage of the inverter row by a flip-flop using the reference signal CLK2 as a clock Realize the vessel. The results Q _c (1) to Q _c (8) (Q _c (1: 8) in FIG. 20) obtained by sampling the output signal of each stage of the inverter train at the rising edge of CLK2 are the comparison results. The logic circuit detects a change in logic of Q _c (1) to Q _c (8) and outputs a digital code.

Further, as another configuration of the digital phase comparator, there is a configuration as shown in FIG. 21 (Patent Document 2). In the configuration of FIG. 21, in addition to the first inverter train that sequentially delays the signal CLK1 from the VCO, the reference signal CLK2 is also sequentially delayed by the second inverter train and fetched into the flip-flop. The outputs D _F (1), D _F (2),..., D _F (n) of each stage of the first inverter row are used as the outputs CK _F (1), CK _F (2) of each stage of the second inverter row. , To CK _F (n) (sampled with flip-flops using odd-numbered stages such as 1, 3,... Rising edge, and even- numbered stages 2, 4,... Falling edge). Q _F (1), Q _F (2), and Q _F (n) are output. As shown in the timing chart of FIG. 22, the phase comparison is performed with the resolution of the delay time difference between the first inverter row and the second inverter row. The logic circuit detects the logic change of Q _F (1) to Q _F (8) (Q _F (1), Q _F (2) is 1, Q _F (3) to Q _F (8) is 0) And output a digital code.

JP 2002-077686 JP 2007-110370 A

The entire disclosures of Non-Patent Documents 1 and 2 are incorporated herein by reference.
The following is an analysis of the related art according to the present invention.

In the configuration of FIG. 19, since the signal input to the inverter train is a high-speed signal output from the VCO, power consumption in the inverter train is increased. Further, since the time resolution of the detected phase difference is determined by the delay time of the inverter, the inverter delay must be significantly reduced in order to increase the resolution.

When the signal frequency of the VCO is high, there is a problem that power consumption increases or the resolution is insufficient.

Further, in the configuration of FIG. 21, the number of stages of the inverter train and flip-flop increases remarkably in order to cover a desired phase difference range, so that the circuit area and power consumption increase.

Therefore, an object of the present invention is to provide a high-resolution digital phase comparator and method without causing an increase in circuit area and power consumption.

In the first aspect of the present invention, a plurality of stages of delay elements are connected in cascade to delay the first pulse input signal sequentially, and the first delay element array OR operation between the first holding circuit group composed of a plurality of holding circuits and sequentially taking the second pulse signal in accordance with the delay signal transition timing and the output of the first holding circuit group, with each delay signal as a clock input By doing so, a first OR operation circuit that extracts the first delay output timing output immediately after the transition timing of the second pulse input signal, and a delay having the same delay time as the first delay element array By connecting the elements in a plurality of stages in cascade, each delay signal of the second delay element array for sequentially delaying the second pulse signal is used as a clock input, and the delay signal transitions in advance according to the transition timing of the delay signal. By performing a logical OR operation on the output of the second holding circuit group composed of a plurality of holding circuits that sequentially capture the first pulse signal and the second data holding circuit group, the first OR circuit A second OR operation circuit that outputs a signal maintaining a phase relationship between the second pulse input signal and the first delayed output immediately after the transition timing of the second pulse input signal with respect to the output; A first time-to-digital conversion circuit that outputs a digital value indicating a relative phase difference between the first pulse signal and the second pulse signal with a delay time accuracy of the first delay element; By connecting the elements in a plurality of stages in cascade, a third delay element array for sequentially delaying the output of the first OR circuit and a delay element having a delay time different from that of the third delay element array Previous by connecting in cascade A fourth delay element array for sequentially delaying the output of the second OR circuit and the delay output of the third delay element array are sequentially taken in accordance with the transition timing of the delay output of the fourth delay element array; A third holding circuit group composed of a plurality of holding circuits, and a relative phase difference between the output of the first OR operation circuit and the output of the second OR operation circuit, The delay time difference between the third delay element array and the fourth delay element array is based on the number of stages required until the phase relationship between the delay output of the delay element array and the delay output of the fourth delay element array is reversed. A second time digital conversion circuit that outputs a digital value with accuracy, wherein the second pulse input signal is used as a clock in the first time digital conversion circuit and is sequentially delayed by the first delay element array. Delayed output A fourth holding circuit group including a plurality of holding circuits that are captured in accordance with the transition timing of the second pulse input signal, and the output of the fourth holding circuit is the first pulse signal and the second pulse; Output as a digital value indicating the relative phase difference of the signal.

According to the present invention, since the accuracy of the time resolution in the second time digital conversion circuit depends on the delay time difference between the third delay element array and the fourth delay element array, the first time digital conversion circuit Compared to the delay time accuracy of the first delay element array, a minute phase difference can be compared. The relative phase difference between the output of the first OR circuit and the output of the second OR circuit is the relative phase difference between the first pulse signal and the second pulse signal. Since the phase difference is sufficiently small, the phase comparison can be performed with high accuracy without increasing the number of stages of the delay element row and the holding circuit group of the second time digital conversion circuit, resulting in an increase in circuit area and power consumption. It is possible to provide a high-resolution digital phase comparator without any problems.

In the second aspect of the present invention, in the first time digital conversion circuit, the digital phase comparator outputs the first holding signal and the second pulse signal to the output of the first holding circuit group. Is output as a digital value indicating the relative phase difference.

According to the present invention, it becomes possible to serve both as a phase comparison of the delay time accuracy of the first delay element array and a circuit for extracting a phase difference less than the delay time, further reducing the circuit area and power consumption. A resolution digital phase comparator can be provided.

In the third aspect of the present invention, the time digital conversion circuit of the first aspect can be obtained by a retiming operation using the second signal instead of the second pulse signal. The third pulse signal synchronized with the transition timing of the second pulse signal is input.

According to the present invention, when the first pulse signal is a relatively slow signal and the second pulse signal is a fast signal, the retimed third pulse signal is the first pulse signal. Therefore, an increase in power consumption of the entire digital phase comparator can be suppressed.

In the fourth aspect of the present invention, an input / output signal of at least one stage of delay elements of the first delay element array is taken out, and a plurality of delay elements having the same delay time as the third delay element array are provided. By cascading a plurality of stages, a fifth delay element array that sequentially delays the output signal and a delay element having the same delay time as the fourth delay element array are used to connect the input signal. A sixth delay element array that sequentially delays and a delay output of the fifth delay element array that is sequentially fetched in accordance with a transition timing of the delay output of the sixth delay element array; A relative phase difference in the input / output signals of the delay elements in the first delay element array, and the delay output of the fifth delay element array and the delay of the sixth delay element array. The phase relationship of the output is A third time digital conversion circuit that outputs a digital value with a delay time difference accuracy between the fifth delay element array and the sixth delay element array based on the number of stages required until the first time A first logic circuit that digitizes a digital value that is output from a digital conversion circuit and that indicates a relative phase difference between the first pulse signal and the second pulse signal, and the second time digital conversion circuit A second logic circuit that digitizes a digital value indicating a relative phase difference between the output of the first OR operation circuit and the output of the second OR operation circuit, which is output from the first OR circuit; A third logic circuit that digitizes a digital value that is output from the time digital conversion circuit and that indicates a relative phase difference in the input / output signals of the delay elements in the first delay element array, and 2nd and 3rd logical times Quantified results based on the, correcting the relative phase difference of said are digitized by the first logic circuit, said first pulse signal and the second pulse signal.

According to the present invention, the third time digital conversion circuit converts the delay time of the first delay element array to the third and fourth delay element arrays and the fifth and sixth delay element arrays. Since the delay time difference can be expressed, the design accuracy required for the delay time of the first delay element array is relaxed.

In the fifth aspect of the present invention, the time-to-digital conversion circuit according to the first aspect uses the fourth pulse signal as a clock input to each delay signal of the first delay element array, and the transition timing of the delay signal. First, immediately after the transition timing of the fourth pulse input signal, a logical sum operation is performed on the output of the sixth holding circuit group composed of a plurality of holding circuits sequentially fetched in accordance with the output of the sixth data holding circuit group. A third OR operation circuit for extracting the output delay output timing and a delay element having the same delay time as the first delay element array are connected in a plurality of stages, and the fourth pulse signal is sequentially delayed. Each of the delay signals of the seventh delay element array to be clocked is used as a clock input, and a seventh data consisting of a plurality of stages of holding circuits for sequentially taking in the first pulse signal according to the transition timing of the delay signal. By performing a logical OR operation on the output of the holding circuit group and the seventh data holding circuit group, the fourth pulse input signal and the fourth pulse input signal are output with respect to the output of the third OR circuit. A fourth OR operation circuit that outputs a signal maintaining a phase relationship with the first delay output immediately after the transition timing of the pulse input signal, and the first delay element with the delay time accuracy of the first delay element. A time-to-digital conversion circuit for further outputting a digital value indicating a relative phase difference between the first pulse signal and the fourth pulse signal, wherein a plurality of delay elements having the same delay time as the third delay element array are provided. By connecting in cascade, an eighth delay element array that sequentially delays the output of the third OR circuit and a delay element having the same delay time as the fourth delay element array are connected in a plurality of stages. The fourth A 9th delay element array that sequentially delays the output of the logical sum operation circuit and a delay output of the 8th delay element array are fetched in accordance with the transition timing of the delay output of the 9th delay element array, and a plurality of stages are held. An eighth holding circuit group composed of a circuit, and the relative phase difference between the output of the third logical sum operation circuit and the output of the fourth logical sum operation circuit is defined as the eighth delay element array. Based on the number of stages required to invert the phase relationship between the delay output of the ninth delay element array and the delay output of the ninth delay element array, the digital value with the delay time difference accuracy of the eighth delay element array and the ninth delay element array A fourth time digital conversion circuit that outputs a delay output that is sequentially delayed by the first delay element array using the fourth pulse input signal as a clock in the first time digital conversion circuit, The fourth pulse input A ninth holding circuit group including a plurality of stages of holding circuits that captures according to the signal transition timing, and outputs the ninth holding circuit relative to the first pulse signal and the fourth pulse signal; Output as a digital value indicating phase difference.

According to the present invention, it is possible to simultaneously perform phase comparison of two pulse signals with respect to the first pulse signal.

According to a sixth aspect of the present invention, in the time phase conversion circuit according to the first aspect, the digital phase comparator outputs the output of the sixth holding circuit group as the first pulse signal and the fourth pulse. Are output as digital values indicating the relative phase difference of the pulse signals.
According to the present invention, in the time-to-digital conversion circuit according to the first aspect, it is possible to serve as a circuit for comparing the phase of the fourth pulse signal and extracting a phase difference less than the delay time. It is possible to provide a high-resolution digital phase comparator that further suppresses the above.
In a seventh aspect of the present invention, the fourth pulse signal is obtained by retiming the first pulse signal from an inverted signal of the second pulse signal, and the second pulse signal is inverted. The first logic circuit is a signal synchronized with the signal transition timing, and the first logic circuit outputs a relative position of the first pulse signal and the fourth pulse signal output from the first time digital conversion circuit. A digital value indicating a phase difference is further digitized, and a relative phase difference between the output of the third OR operation circuit and the output of the fourth OR operation circuit, which is output from the fourth time digital conversion circuit. A fourth logic circuit that digitizes a digital value indicating the first value, and is digitized by the first logic circuit based on the digitization results of the third and fourth logic circuits. Pulse signal and the fourth pulse signal , The relative phase difference between the first pulse signal and the third pulse signal, and the relative phase difference between the first pulse signal and the fourth pulse signal. The half period of the second pulse signal is obtained from the difference between the first pulse signal and the third pulse signal, or the first pulse signal and the fourth pulse signal. Normalize the relative phase difference of.

According to the present invention, when the first pulse signal is a relatively slow signal and the second pulse signal is a fast signal, the retimed fourth pulse signal is also the first pulse signal. Therefore, an increase in power consumption of the entire digital phase comparator can be suppressed. Further, since normalization is performed with the period of the second pulse signal, it is not necessary to use an accurate value of the delay time in the first to ninth delay element arrays, so that the demand for design accuracy of the delay time is eased. Is done.

In still another aspect of the present invention,
(A) A delay signal group is generated by delaying the first input signal at equal intervals, and the second input signal is delayed by delaying the first input signal and the first input signal at equal intervals. Each sampled by a signal group, a predetermined logical operation (for example, logical sum operation) is performed on the plurality of sampled signals to synthesize a first signal,
(B) generating a delayed signal group in which the second input signal is delayed at equal intervals by the same unit delay time as the first input signal, and the first input signal is converted to the second input signal. The signal and the second input signal are respectively sampled by delay signal groups obtained by delaying at equal intervals, and a predetermined logical operation (for example, logical sum operation) is performed on the plurality of sampled signals to obtain the second signal. Synthesize
(C) A delayed signal group in which a delayed signal group is generated by delaying the first signal at equal intervals, and the second signal is delayed at equal intervals by a unit delay time different from that of the first signal. Each of the delay signals of one delay signal group among the delay signal group obtained by delaying the first signal at equal intervals and the delay signal group obtained by delaying the second signal at equal intervals. The signal sampled by the corresponding delay signal of the other delay signal group, respectively, the signal sampled in (a) or (b) and the signal sampled in (c), the first input signal and the first A phase comparison method is provided which is used as a value representing a phase difference between two input signals.

In still another aspect of the present invention, the delay signal of each stage of the fourth delay element array of the second time-to-digital conversion circuit is changed to the transition of the delay signal of the corresponding stage of the third delay element array. A fifth holding circuit group including a plurality of holding circuits that sequentially captures according to timing;
A third OR operation circuit receiving the output of the fifth holding circuit group;
A fourth OR operation circuit receiving the output of the third holding circuit group;
In addition,
A fifth delay element array in which a plurality of delay elements are connected in cascade, the output of the third OR operation circuit is input to the first stage, and a plurality of delay signals are sequentially delayed;
A plurality of delay elements having a delay time different from that of the fifth delay element array are connected in cascade, and the output of the fourth OR circuit is input to the first stage to output a plurality of delay signals sequentially delayed. 6 delay element rows;
A sixth holding circuit group including a plurality of holding circuits, which sequentially captures the delay signal of each stage of the fifth delay element array according to the transition timing of the delay signal of the corresponding stage of the sixth delay element array; , And the output of the sixth holding circuit group is used as a digital value indicating a relative phase difference between the first pulse input signal and the second pulse input signal. It is done. The fifth delay element array and the sixth delay element array have a delay time difference that is smaller than the delay time difference between the third delay element array and the fourth delay element array. The third time digital conversion circuit outputs a relative phase difference between the outputs of the third and fourth logical sum operation circuits as a digital value with a delay time difference accuracy of the fifth and sixth delay element arrays. .

According to the present invention, since the third time digital conversion circuit can compare a smaller phase than the second time digital conversion circuit, a more accurate phase comparison is possible. In other words, in other words, the third time digital conversion circuit can relax the time resolution setting required for the first and second time digital conversion circuits. To provide a digital phase comparator with high time resolution capable of reducing the number of stages of delay element arrays and holding circuit groups in the first and second time digital conversion circuits, resulting in further reduced circuit area and power consumption. Is possible.

According to the present invention, in a digital phase comparator that detects a phase difference and converts it into a digital signal, it is possible to provide a high-resolution digital phase comparator without causing an increase in circuit area and power consumption. .

It is a figure which shows the structure of the digital phase comparator of the 1st Embodiment of this invention. It is a timing chart for demonstrating the operation example of the digital phase comparator of the 1st Embodiment of this invention. It is a figure which shows the structure of the digital phase comparator of the 2nd Embodiment of this invention. It is a timing chart for demonstrating the operation example of the digital phase comparator of the 2nd Embodiment of this invention. It is a figure which shows the structure of the digital phase comparator of the 3rd Embodiment of this invention. It is a timing chart for demonstrating the operation example of the digital phase comparator of the 3rd Embodiment of this invention. It is a figure which shows the structure of the digital phase comparator of the 4th Embodiment of this invention. It is a timing chart for demonstrating the operation example of the digital phase comparator of the 4th Embodiment of this invention. It is a figure which shows the structure of the digital phase comparator of the 5th Embodiment of this invention. It is a timing chart for demonstrating the operation example of the time digital converter 10 'of the digital phase comparator of the 5th Embodiment of this invention. It is a timing chart for demonstrating the operation example of the small phase difference detector 20 and the time digital converter 50 of the digital phase comparator of the 5th Embodiment of this invention. It is a timing chart for demonstrating the operation example of the small phase difference detector 30 and the time digital converter 60 of the digital phase comparator of the 5th Embodiment of this invention. It is a timing chart for demonstrating the operation example of the time digital converter 70 of the digital phase comparator of the 5th Embodiment of this invention. It is a figure which shows the structure of the digital phase comparator of the 6th Embodiment of this invention. It is a timing chart for demonstrating the operation example of the time digital converter 40 of the digital phase comparator of the 6th Embodiment of this invention. It is a timing chart for demonstrating the operation example of the time digital converter 50 of the digital phase comparator of the 6th Embodiment of this invention. It is a timing chart for demonstrating the operation example of the time digital converter 60 of the digital phase comparator of the 6th Embodiment of this invention. It is a timing chart for demonstrating the operation example of the time digital converter 70 of the digital phase comparator of the 6th Embodiment of this invention. It is a figure which shows the structure of the digital phase comparator of related technology (patent document 1). It is a timing chart for demonstrating the operation example of the digital phase comparator of related technology (patent document 1). It is a figure which shows the structure of the digital phase comparator of related technology (patent document 2). It is a timing chart for demonstrating the operation example of the digital phase comparator of related technology (patent document 2). It is a figure which shows the structure of the time digital converter 50 of the digital phase comparator of the 7th Embodiment of this invention. It is a timing chart for demonstrating the operation example of the digital converter 50 of the digital phase comparator time of the 7th Embodiment of this invention. It is a timing chart for demonstrating the operation example of the time digital converter 50 of the digital phase comparator of the 7th Embodiment of this invention.

Embodiments of the present invention will be described in detail with reference to the drawings.

First, the basic configuration of the present invention will be described. In one mode of the present invention, referring to FIG. 3, in the holding circuit group (22_1 to 22_n), the first input signal (CLK1) is changed to the second input signal (CLK2) and the second input signal. The signal (CLK2) is sampled by a second delayed input signal group (CK _c (1) to CK _c (n−1)) obtained by delaying the signal (CLK2) at equal intervals. A first signal (FCLK1) synthesized by performing a logical operation (for example, a logical sum operation) is output (corresponding to the “first circuit unit” in claim 1).

In the holding circuit group (23_1 to 23_n), the second input signal (CLK2), the first input signal (CLK1), and the first input signal (CLK1) are unit delay of the second delayed input signal group. Sampled by the first delayed input signal group (D _c (1) to D _c (n−1)) delayed at equal intervals by the same unit delay time as the time, the sampled signal (Q _c (1 ) To Q _c (n)) and outputs a second signal (FCLK2) synthesized by performing a predetermined logical operation (for example, a logical sum operation) (corresponding to “second circuit unit” of claim 1) ). The first and second circuit units are collectively referred to as a “time digital converter”.

A second delay signal group (CK _F (1) to CK _F (m)) obtained by delaying the second signal (FCLLK2) at equal intervals by delay element rows (52_1 to 52_m) in which delay elements are connected in cascade. ) And the delay element array (51_1 to 51_m), the first signal (FCLK1) and the delay signal group (CK _F (1) to CK _F (m)) of the second signal (FCLK2) First delay signal groups (D _F (1) to D _F (m)) delayed at equal intervals by different unit delay times are generated, and the first delay signal group is generated in the holding circuit groups (53_1 to 53_m). Each delay signal of (D _F (1) to D _F (m)) is sampled by a corresponding delay signal of the second delay signal group (CK _F (1) to CK _F (m)), respectively. 1 corresponding to “third circuit unit”). The third circuit unit is also collectively referred to as a “time digital converter”. The signals (Q _c (1) to Q _c (n)) sampled by the holding circuit groups (23_1 to 23_n) and the signals (Q _F (1) to Q _F ) sampled by the holding circuit groups (53_1 to 53_m). (M)) is used as a value representing the phase difference between the first input signal (CLK1) and the second input signal (CLK2), and is input to the logic circuit (4) and the logic circuit (5), respectively.

The first circuit unit includes a delay element array (21_1 to 21_n) that generates a second delayed input signal group obtained by delaying the second input signal at equal intervals. The second circuit unit generates a first delay input signal group in which the first input signal is delayed at equal intervals by the same unit delay time as the second delay input signal group ( 11_1 to 11_n) (corresponding to claim 2).

Alternatively, in another aspect of the present invention, referring to FIG. 1, the first circuit unit generates a second delay input signal group (second delay input signal group obtained by delaying the second input signal at equal intervals ( 21_1 to 21_n). First delay input signal groups (D _C (1) to D _C (n)) obtained by delaying the first input signal (CLK1) at equal intervals by the delay element arrays (11_1 to 11_n−1) are generated and held. The circuit group (12_1 to 12_n) samples the first input signal (CLK1) and the delayed signal group (D _c (1) to D _c (n−1)) with the second input signal (CLK2). Sample results (Q _c (1) to Q _c (n) in the holding circuit group (12_1 to 12_n) and sample results (Q _F (1) to Q _F (m) in the holding circuit group (53_1 to 53_m) )) Is used as a value representing the phase difference between the first input signal (CLK1) and the first input signal (CLK2) (Claim 3) and the delay element array (11_1 to 11_n-1) and holding The circuit group (12_1 to 12_n) is collectively referred to as “time digital conversion. It is also called “vessel”.

That is, referring to FIG. 1, in the holding circuit groups (23_1 to 23_n), the second input signal (CLK2) is sampled by the first delayed input signals (D _C (1) to D _C (n)), respectively. To do. The OR circuit (25) outputs an OR operation result of the plurality of signals sampled by the holding circuit groups (23_1 to 23_n) as a signal (FCLK2). A second delay input signal group (CK _c (1) to CK _c (n-1)) is generated by delaying the second input signal (CLK2) at equal intervals by the delay element array (21_1 to 21_n-1). To do. The holding circuit groups (22_1 to 22_n) sample the first input signal (CLK1) by the delay signal groups (CK _c (1) to CK _c (n−1)), respectively. The OR circuit (24) outputs the OR operation result of the signals sampled by the holding circuit groups (22_1 to 22_n) as the first signal (FCLK1). The above circuit group is also collectively referred to as a “small phase difference detector”.

In addition, a first delay signal group (D _F (1) to D _F (m)) is generated by delaying the first signal (FCLK1) at equal intervals in the delay element arrays (51_1 to 51_m−1). In the delay element array (52_1 to 52_m), the second signal (FCLK2) is delayed at equal intervals by a unit delay time different from the unit delay time of the delay element array (51_1 to 51_m-1). Delay signal groups (CK _F (1) to CK _F (m)) are generated. In the holding circuit group (53_1 to 53_m), each delay signal of the first delay signal group (D _F (1) to D _F (m)) is used as the second delay signal group (CK _F (1) to CK _F ). (M)) are respectively sampled by the corresponding delay signals, and sample results (Q _F (1) to Q _F (m)) are output. The circuit group is also collectively referred to as a “time digital converter”.

In still another aspect of the present invention, the reference signal (REF) is used as the first input signal (CLK1), and the first input signal is responded to the output of the oscillator (VCO) as the second input signal (CLK2). The output sampled by the holding circuit (102) may be used (see claim 4 and FIG. 7).

Alternatively, in still another aspect of the present invention, the input signal (CLK1) is sampled every half cycle of the oscillation frequency of the clock oscillator to generate two signals, and one of the input signal and the two signals is obtained. The first and second circuit units that are input as the first and second input signals, the set of the third circuit units, and the other of the input signal and the two signals, respectively. It is good also as a structure provided with the said 1st, 2nd circuit unit input as 2 input signals, and another group of the said 3rd circuit unit (Claim 5).

In the present invention, referring to FIG. 9, a small phase difference detector (20) and a time digital converter (50) for inputting one of the input signal and the two signals as the first and second input signals. A small phase difference detector (30) for inputting the other of the input signal and the two signals as the first and second input signals, and a time digital converter (60). It is good also as a structure provided with the time digital converter (10 ') input as said 1st, 2nd input signal (refer Claim 6, FIG. 9).

That is, the first input signal (REF) is sampled every half cycle of the oscillation frequency of the clock oscillator (101) to generate the second and third input signals (REFT, REFC). In the time digital converter (10 '), a delay signal group is generated by delaying the first input signal (REF) at equal intervals by the delay element arrays (11_1 to 11_n-1). In the holding circuit groups (12_1 to 12_n), the first input signal (REF) and the delayed signal group obtained by delaying the first input signal at equal intervals are set as one of the second input signals (REFT). Sample in common in response to transition edges (eg rising edges). In the holding circuit group (13_1 to 13_n), the first input signal (REF) and the delayed signal group obtained by delaying the first input signal at equal intervals are used as the third input signal (REFC). Sample in common in response to other transition edges (eg, falling edges).

For the set of the first and second input signals (REF, REFT), in the small phase difference detector (20), the delay element array (21_1 to 21_n−1 in FIG. 1) uses the second input. A delay signal group is generated by delaying the signal (REFT) at equal intervals with the same unit delay time as the first input signal. In the holding circuit group (22_1 to 22_n in FIG. 1), the first input signal (REF) is a delayed signal group obtained by delaying the second input signal (REFT) and the second input signal at equal intervals. And a plurality of sampled signals are combined by an OR circuit (24 in FIG. 1) to generate a first signal (TFCLK1). In the holding circuit group (23_1 to 23_n in FIG. 1), the second input signal (REFT) is a delay obtained by delaying the first input signal (REF) and the first input signal at equal intervals. Each sampled signal is sampled, and the plurality of sampled signals are combined with an OR circuit (25 in FIG. 1) to generate a second signal (TFCLK2).

In the time digital conversion circuit (50), in the delay element array (51_1 to 51_m in FIG. 9), a delay signal group is generated by delaying the first signal (TFCLK1) at equal intervals. 52_1 to 52_m) generates a delayed signal group obtained by delaying the second signal (TFCLK2) at equal intervals with a unit delay time different from that of the first signal (TFCLK1). In the holding circuit group (53_1 to 53_m in FIG. 9), each delay signal of the delay signal group obtained by delaying the first signal (TFCLK1) at equal intervals is delayed at the second signal (TFCLK2) at equal intervals. Each of the delayed signal groups is sampled by the corresponding delayed signal.

Further, in the small phase difference detector (30) with respect to the set of the first and third input signals (REF, REFC), the delay element array (21_1 to 21_n−1 in FIG. 1) A delay signal group is generated by delaying the input signal (REFC) at equal intervals with the same unit delay time as the first input signal. In the holding circuit group (22_1 to 22_n in FIG. 1), the first input The signal (REF) is sampled by each of the third input signal (REFC) and a delay signal group obtained by delaying the third input signal at equal intervals, and the plurality of sampled signals are ORed (in FIG. 1). 24) to generate a third signal (CFCLK1). In the holding circuit group (23_1 to 23_n in FIG. 1), the third input signal (REFC) is a delay obtained by delaying the first input signal (REF) and the first input signal at equal intervals. Each sampled signal is sampled, and the plurality of sampled signals are combined with an OR circuit (25 in FIG. 1) to generate a fourth signal (CFCLK2).

In the time digital conversion circuit (60), the delay element array (61_1 to 61_m in FIG. 9) generates a delay signal group obtained by delaying the third signal (CFCLK1) at equal intervals, and the delay element array (FIG. 9). 62_1 to 62_m) generates a delayed signal group obtained by delaying the fourth signal (CFCLK2) at equal intervals with a unit delay time different from that of the third signal (CFCLK1). In the holding circuit group (63_1 to 63_m in FIG. 9), each delay signal of the delay signal group obtained by delaying the third signal (CFCLK1) at equal intervals is delayed at the fourth signal (CFCLK2) at equal intervals. Each of the delayed signal groups is sampled by the corresponding delayed signal.

Further, in the time digital conversion circuit (70), the first input signal (REF) is further converted into a unit more than the delay signal group of the first input signal (delay output of the delay element arrays 11_1 to 11_n−1). A fifth signal delayed by the delay time (output D _c (n) of the delay element 11 — n) and a sixth signal (output D _c (n + 1) of the delay element 11 — n + 1) obtained by delaying the fifth signal by a unit delay time. ) And a delay signal group (D _FD (1) to D _FD () in which the sixth signal (D _c (n + 1)) is delayed at equal intervals by a delay element array (71_1 to 71_m in FIG. 9). m)). In the delay element array (72_1 to 72_m in FIG. 9), the fifth signal (D _c (n)) is delayed by a unit delay time different from that of the sixth signal at equal intervals (CK _FD (1) to CK _FD (m)) are generated. In the holding circuit group (73_1 to 73_m in FIG. 9), each of the delayed signal groups (D _FD (1) to D _FD (m)) obtained by delaying the sixth signal (D _c (n + 1)) at equal intervals. The delayed signals are sampled by the corresponding delayed signals of the delayed signal group (CK _FD (1) to CK _FD (m)) obtained by delaying the fifth signal (D _c (n)) at equal intervals.

Alternatively, in still another aspect of the present invention, the input signal (CLK1) is sampled every half cycle of the oscillation frequency of the clock oscillator to generate two signals, and one of the input signal and the two signals is obtained. First and second time digital converters that are input as the first and second input signals, and the other of the input signal and the two signals is input as the first and second input signals. The second time digital converter may be provided (see claim 7 and FIG. 14). That is, a circuit is provided that generates second and third input signals (REFT, REFC) obtained by sampling the first input signal (REF) every half cycle of the oscillation frequency of the clock oscillator (for example, the voltage controlled oscillator 101). Yes. Further, with respect to the set of the first and second input signals (REF, REFT), in the delay element array (21_1 to 21_n), a delay signal group obtained by delaying the second input signal (REFT) at equal intervals. Is generated. In the holding circuit groups (22_1 to 22_n), the first input signal (REF) is sampled by a delay signal group obtained by delaying the second input signal (REFT) and the second input signal at equal intervals, respectively. Then, the plurality of sampled signals are combined by the OR circuit (24) to generate the first signal (TFCKL1). The delay element array (11_1 to 11_n) generates a delay signal group obtained by delaying the first input signal (REF) at equal intervals, and the holding circuit group (23_1 to 23_n) generates the second input signal (REFT). ) Are respectively sampled by a delay signal group obtained by delaying the first input signal and the first input signal at equal intervals, and a plurality of sampled signals are synthesized by an OR circuit (25), A signal (TFCLK2) is generated. In the delay element array (51_1 ~ 51_m), generating said first signal (TFCLK1) delay signal group delayed at regular intervals _{(D FT (1) ~ D} FT (m)). In the delay element array (52_1 to 52_m), the delay signal group (CK _FC (1) to CKFC (1) to CKFC2) is obtained by delaying the second signal (TFCLK2) at equal intervals by a unit delay time different from that of the first signal TFCLK1). CK _FC (m)) is generated. In the holding circuits (53_1 ~ 53_m), said first signal (TFCLK1) delay signal group delayed at equal intervals of _{(D FT (1) ~ D} FT (m)), said second signal (TFCLK2 ) Are delayed by equal intervals and sampled by corresponding delay signals of the delay signal group (CK _FC (1) to CK _FC (m)).

Further, with respect to the set of the first and third input signals (REF, REFC), the delay element array (41_1 to 41_n) delays the third input signal (REFC) at equal intervals. Group, and in the holding circuit groups (42_1 to 42_n), the first input signal (REF) is delayed by delaying the third input signal (REFC) and the third input signal at equal intervals. Each sampled signal is sampled, and the plurality of sampled signals are combined by an OR circuit (44) to generate a third signal (CFCLK1). In the holding circuit group (43_1 to 43_n), the third input signal (REFC) is sampled by a delay signal group obtained by delaying the first input signal (REF) and the first input signal at equal intervals. The plurality of sampled signals are combined by the OR circuit (45) to generate the fourth signal (CFCLK2). In the delay element array (61_1 to 61_m), a delay signal group (D _FC (1) to D _FC (m)) obtained by delaying the third signal (CFCLK1) at equal intervals is generated. In the delay element array (62_1 to 62_m), a delay signal group (CK _FC (1)) in which the fourth signal (CFCLK2) is delayed at equal intervals by a unit delay time different from that of the third signal (CFCLK1). ~ CK _FC (m)) is generated. In the holding circuit groups (42_1 to 42_n), the delay signals of the delay signal groups (D _FC (1) to D _FC (m)) obtained by delaying the third signal (CFCLK1) at equal intervals are supplied to the fourth circuit. The signal (CFCLK2) is sampled by the corresponding delay signal of the delay signal group (CK _FC (1) to CK _FC (m)) obtained by delaying the signal (CFCLK2) at equal intervals.

Alternatively, in another aspect of the present invention, referring to FIG. 23, a second time digital conversion circuit that receives signals (FCLK1, FCLK2) output from the logic circuit (OR circuits 24, 25) of FIG. (50), the delay signals (CK _F (1) to CK _F (m)) of the respective stages of the fourth delay element arrays (52_1 to 52_m) in the second time digital conversion circuit (50) Fifth holding circuit group having a plurality of holding circuits sequentially fetching according to the transition timings of the delay signals (D _F (1) to D _F (m)) of the corresponding stages of the three delay element arrays (51_1 to 51_m) (54_1-54_m),
A third OR operation circuit (55) for receiving the outputs (Q _F2 (1) to Q _F2 (m)) of the fifth holding circuit group (54_1 to 54_m), and a second time digital conversion circuit (50 ) Of the third holding circuit group (53_1 to 53_m), and a fourth OR operation circuit (56). Further, a plurality of delay elements are connected in cascade, and a plurality of delay signals (D _F2 (1) to D _F2 (D _F2 (1) to D _F2 ( l)), a fifth delay element array (81_1 to 81_l),
Delay elements having delay times different from those of the fifth delay element array (81_1 to 81_1) are connected in cascade, and the output (F2CLK2) of the fourth OR operation circuit (56) is input to the first stage and sequentially A sixth delay element array (82_1 to 82_l) that outputs a plurality of delayed signals (CK _F2 (1) to CK _F2 (l));
A plurality of holding circuits that sequentially take in the delay signals of each stage of the fifth delay element array (81_1 to 81_l) according to the transition timing of the delay signal of the corresponding stage of the sixth delay element array (82_1 to 82_l) A sixth holding circuit group (83_1 to 83_l) including:
And a third time digital converter (80). The outputs (Q _F3 (1) to Q _F3 (m)) of the sixth holding circuit group (83_1 to 83_l) are such that the output of the sixth holding circuit group is the first pulse input signal and the second pulse input signal. The digital value indicating the relative phase difference of the pulse input signal is input to the logic circuit (8). The delay time difference between the unit delay times in the fifth delay element array (81_1 to 81_1) and the sixth delay element array (82_1 to 82_l) is the third delay element array (51_1 to 51_m) and the fourth delay element array (51_1 to 51_m). The delay element row (52_1 to 52_m) is set to be smaller than the delay time difference of the unit delay times. Each embodiment will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a diagram showing a configuration of a digital phase comparator according to the first embodiment of the present invention. Referring to FIG. 1, the digital phase comparator of the present embodiment is
(A) a time digital converter 10 including inverter arrays (delay element arrays) 11_1 to 11_n and a plurality of data holding circuits (holding circuit groups) 12_1 to 12_n;
(B) logic circuit 1;
(C) Small phase difference detector 20 including inverter rows (delay element rows) 21_1 to 21_n, a plurality of data holding circuits (holding circuit groups) 22_1 to 22_n, and a plurality of data holding circuits (holding circuit groups) 23_1 to 23_n. When,
(D) a time digital converter 50 including inverter arrays (delay element arrays) 51_1 to 51_m + 1, inverter arrays (delay element arrays) 52_1 to 52_m + 1, and a plurality of data holding circuits (holding circuit groups) 53_1 to 53_m;
(E) logic circuit 5;
It has.

In the time digital converter 10, the first input signal CLK1 is sequentially delayed by n stages of cascaded inverter arrays 11_1 to 11_n. The outputs of the first input signal CLK1 and the inverter trains 11_1, 11_2,..., 11_ (n−1) are respectively supplied to the data input terminals of the corresponding data holding circuits 12_1, 12_2, 12_3,. The first input signal CLK1 and the second input signal CLK2 that are input and taken in at the timing (rising edge) of the second input signal CLK2 that is input in common to the respective clock terminals, from the data holding circuits 12_1 to 12_n. Are input to the logic circuit 1 as digital signals Q _C (1) to Q _C (n). The logic circuit 1 detects changes in the values of Q _C (1) to Q _C (n) (changes in adjacent bits) and outputs a digital code.

Since the data holding circuits 12_1 to 12_n match the logic of the output signals, the odd-numbered data holding circuits 12_1 to 12_3,... Are positive logic, and the even-numbered data holding circuits 12_2, 12_4,. Takes out the output with negative logic (inverted signal of the data output terminal).

In the small phase difference detector 20, the first input signal CLK1 is commonly input to the data input terminals of the data holding circuits 22_1 to 22_n, and the data holding circuits 22_1 to 22_n receive the first input signal CLK1 as the second input signal CLK1. The input signal CLK2 and the second input signal CLK2 are captured at the edges (rising edges) of the signals CK _C (1) to CK _C (n−1) sequentially delayed by the n-stage inverter rows 21_1 to 21_n. The outputs of the data holding circuits 22_1 to 22_n are input to an n-input OR circuit 24, and the output of the OR circuit 24 is output as FCLK1.

The second input signal CLK2 is input in common to the data input terminals of the data holding circuits 23_1 to 23_n. The data holding circuits 23_1 to 23_n are input signals D of the respective stages of the inverter trains 11_1 to 11_n of the time digital converter 10. _C (1) to D _C (n−1) are input to the clock terminal to capture CLK2. The outputs of the data holding circuits 23_1 to 23_n are input to the n-input OR circuit 25, and the output of the OR circuit 25 is output as FCLK2.

The data holding circuits 22_1 to 22_n and the data holding circuits 23_1 to 23_n input each clock terminal with positive logic at the odd-numbered stage and negative logic at the even-numbered stage in order to match the data fetching logic. . The data holding circuits at odd stages such as the data holding circuits 22_1, 22_3,... Capture at the rising edge of CLK2 and its delay signal (output of the inverter 21_2,...), And the data holding circuits 22_2, 22_4. The even-numbered data holding circuit takes in the falling edge of CLK2 and its delay signal (output of inverter 21_1,...). The data holding circuits at odd stages such as the data holding circuits 23_1, 23_3,... Capture at the rising edge of CLK1 and its delay signal (output of the inverter 11_2,...), And the data holding circuits 23_2, 23_4. The even-numbered data holding circuit captures at the falling edge of CLK2 and its delay signal (output of inverter 11_1,...).

The delay time of each stage of the inverter trains 21_1 to 21_n is set to be the same as the delay time of the inverter trains 11_1 to 11_n. The outputs of the final stage inverters 11_n and 21_n of the inverter rows 11_1 to 11_n and 21_1 to 21_n are opened.

In the time digital converter 50, FCLK1 is input to the first stage of the m-stage cascaded inverter strings 51_1 to 51_m, and FCLK2 is input to the first stage of the m-stage cascaded inverter strings 52_1 to 52_m. The outputs of the final stage inverters 51_m and 52_m of the inverter arrays 51_1 to 51_m and 52_1 to 52_m are opened.

The data holding circuits 53_1 to 53_m input FCLK1 and D _F (1) to D _F (m), which are input signals of the inverter arrays 51_1 to 51_m + 1, to the respective data input terminals, and input of the inverter arrays 52_1 to 52_m. The signals FCLK2 and CK _F (1) to CK _F (m−1) are input to the clock terminal, and the signal of the data input terminal is captured at the edge of the clock terminal. The phase difference between FCLK1 and FCLK2 is input to the logic circuit 5 as output digital signals Q _F (1) to Q _F (m) from the data holding circuits 53_1 to 53_m. The logic circuit 1 detects changes in the values of Q _F (1) to Q _F (m) (changes in adjacent bits) and outputs a digital code.

Note that in the data holding circuits 53_1 to 53_m, in order to match the logic of the output signal and the clock terminal input signal, the logic of the output and the clock terminal is set to negative logic in the odd stages and positive logic in the even stages. The odd-numbered data holding circuit 53_1 takes in D _F (1) at the falling edge of FCLK2 and outputs the inverted output of the data output terminal as Q _F (1). The even-numbered data holding circuit 53_2 takes in D _F (2) at the rising edge of FCLK2 and outputs the output data of the data output terminal as Q _F (2).

At this time, the phase difference ΔT _F1 of each stage of the inverter trains 51_1 to 51_m and the phase difference ΔT _F2 of each stage of the inverter trains 52_1 to 52_m are:
ΔT _F1 > ΔT _F2
It has become a relationship.

[Example]
Next, specific examples relating to the embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows a timing chart when n = 4 and m = 4 in FIG. At this time, the first input signal CLK1 the phase difference between the second input signal CLK2 and _{T C.} In FIG. 1, the digital phase comparator of this embodiment includes a time digital converter 10 including inverter rows 11_1 to 11_4 and data holding circuits 12_1 to 12_4, and a small phase difference detector 20 includes inverter rows 21_1 to 21_4 and data. The holding digital circuits 22_1 to 22_4 and 23_1 to 23_4 are provided, and the time digital converter 50 includes inverter rows 51_1 to 51_4, 52_1 to 52_4, and data holding circuits 53_1 to 53_4. In FIG. 2, the output _D C (1) of the inverter 11_1 to inverted output to input CLK1 is illustrated as a signal which rises after the rise of CLK1 of [Delta] T _C, as described above, negative logic (positive This is because the logic 0 and 1 are handled as 1 and 0, respectively. Falling data holding circuit 23_2 in the edge of the output _D C of the inverter 11_1 (1) is a sample, the data holding circuit 12_2, a logic 1 when sampled on the rising edge of the Low CLK1 output _D C of the inverter 11_1 (1) Is output. The same applies to CK _F (1) to CK _F (3).

In time-digital converter 10, the input signal CLK1 of the data holding circuits 12_1 ~ 12_4 are to the data _{terminal, D C (1), D} C (2), D C (3), D C (4) is to clock terminal When the input signal CLK2 (sampling clock) transits earlier in time, logic “1” is output. At this time, the respective delay times of the inverter array 11_1 ~ 11_4 to [Delta] T _C. To the first input signal CLK1, the output DC (1) of the inverter array 11_1 ~ 11_4 respectively output-DC (3), is delayed by ΔT _C ~ 3ΔT _C, at the output point of the third-stage inverter 11_3, The phase relationship with the second input signal CLK2 is reversed.

Therefore, the logic “1” is output up to the third stage and the logic “0” is output from the fourth stage to the outputs Q _C (1) to Q _C (4) of the data holding circuits 12_1 to 12_4. At this time, as the inverter train, the phase relationship _TC is reversed through three stages of the inverter trains 11_1 to 11_4. It found to be between _{(2ΔT C <T C <3ΔT} C), using the CLK2 signal, the phase difference TF between inverter output _D C (3),
T _C = 3ΔT _C -T _F
It is expressed.

In the small phase difference detector 20, the data holding circuits 23_1 ~ 23_4 is input to the common second input signal CLK2 to the data terminal, the input signal CLK1 to the inverter array 11_1 ~ 11_4 of the time-to-digital converter _{10, D} C ( 1), D _C (2),..., D _C (n−1) are input to the clock terminal, so the phase relationship between the input signal to the data terminal and the input signal to the clock terminal is The data holding circuits 12_1 to 12_4 of the time digital converter 10 have a reverse relationship.

Therefore, logic “1” is output in synchronization with the falling edge (rising edge in FIG. 2) of the output signal D _C (3) of the third-stage inverter 11_3. The outputs of the data holding circuits 23_1 to 23_4 are input to the 4-input OR circuit 25. From the output FCLK2, the inversion timing of the inverter trains 11_1 to 11_4 output immediately after the second input signal CLK2 of the time digital converter 10 is input. Will be extracted.

Further, the inverter arrays 21_1 to 21_4 and the data holding circuits 22_1 to 22_4 have the same configuration as the circuit configured by the data holding circuits 23_1 to 23_4 and the inverter arrays 11_1 to 11_4 of the time digital converter 10, and input signals Is replaced. That is, in the data holding circuit 22_1, the rising edge timing of CLK2, and in the data holding circuits 22_2, 22_3, and 22_4, CLK1 is set at the rising, rising, and falling edges obtained by inverting and delaying CLK2 in the inverter rows 21_1 to 21_3. The result obtained by ORing the sampled result by the 4-input OR circuit 24 is output as FCLK1. Since the phase of the first input signal CLK1 is advanced with respect to the second input signal CLK2, the logic “1” is sequentially output from the data holding circuits 22_1 to 22_4, and the output FCLK1 of the 4-input OR circuit 24 is Therefore, the rising timing of the second input signal CLK2 is extracted. At this time, since the circuit configuration and the load state are equal, the delay from the second input signal CLK2 to FCLK1 output from the OR circuit 24 and the inverter train immediately after the second input signal CLK2 is input. The delay time of the circuit from the inverted signal of the outputs 11_1 to 11_4 to FCLK2 output from the OR circuit 25 becomes equal. Small phase difference detector 20, the rise of the phase difference _{T F} of the second immediately after the input signal CLK2 and CLK2 signal input inverter row 11_1 ~ 11_4 inverted signal of the output (rising and _D C (3 of CLK2 in FIG. 2) Output signals FCLK1 and FCLK2 that maintain the edge phase difference) are output.

In the time digital converter 50, signals D _F (1) to D _{F obtained} by sequentially delaying the signal FCLK1 output from the small phase difference detector 20 via the inverter arrays 51_1 to 51_4 in the data holding circuits 53_1 to 53_4. The signal CK _F (1) to CK _F (4) obtained by sequentially delaying the output signal FCLK2 of the small phase difference detector 20 via the inverter rows 52_1 to 52_4 is sequentially taken in as a clock signal. The data holding circuits 53_1 to 53_4 are used when the phases of the input signals D _F (1) to D _F (4) to the data terminal are ahead of the input signals CKF (1) to CKF (4) to the clock terminal. , Output logic “1”.

The output time of the small phase difference detector 20, FCLK1 is a relationship advanced phase only _{T F} than FCLK2, each stage of the inverter array 51_1 ~ phase difference [Delta] T _F1 and inverter row 52_1 ~ 52_4 of each stage of the 51_4 The phase difference ΔT _F2 of
ΔT _F1 > ΔT _F2
It has become a relationship. For this reason, each time it passes through each stage of the inverter trains 52_1 to 52_4, the phase difference decreases by ΔT _F1 −ΔT _F2 .

In FIG. 2, up to the second stage data holding circuit 53_2, since the phase of the data input D _F (2) is advanced with respect to the clock input C _F (2), logic “1” is output. The phase relationship is reversed when the third stage inverter 51_3 is passed. That is, D _F (3) is delayed in phase from C _F (3). For this reason, the output of the data holding circuit in the third stage and thereafter becomes logic “0”, and it can be seen that the phase difference TF is between two stages and three stages of the delay difference ΔT _F1 -ΔT _F2 of the inverter train. That is, the relationship of 2 (ΔT _F1 −ΔT _F2 ) <T _F <3 (ΔT _F1 −ΔT _F2 ) is established.

From the decoding results in logic circuit 1 and logic circuit 5,
T _C = 3ΔT _C −T _F is
3ΔT _c −3 (ΔT _F1 −ΔT _F2 ) <T _c <3ΔT _c −2 (ΔT _F1 −ΔT _F2 )
It can be seen that it is.

As described above, by using the small phase difference detector 20 and the time digital converter 50, a minute phase difference that cannot be detected by the time digital converter 10 can be detected. A digital phase comparator with higher resolution than the conventional configuration described in Patent Document 1 can be realized.

In addition, the time digital converter 50 in this embodiment is configured to compare only the phase difference of one stage or less of the inverter delay of the time digital converter 10, so that the other conventional configuration described in Patent Document 2 is used. On the other hand, the power consumption and the circuit area can be significantly reduced by reducing the number of stages of the inverter array and the data holding circuit group as a whole.

[Second Embodiment]
FIG. 3 is a diagram showing the configuration of the digital phase comparator according to the second embodiment of the present invention. Referring to FIG. 3, the digital phase comparator according to the present embodiment eliminates the data holding circuits 12_1 to 12_n of the time digital converter 10 from the digital phase comparator shown in FIG. With the configuration in which the outputs from the data holding circuits 23_1 to 23_n are connected to the logic circuit 4, the time digital converter 40 detects the phase difference between the input signals CLK1 and CLK2, and is less than the resolution due to the delay time of the inverter train. It is the structure which serves also as a detection of a phase difference.

[Example]
Next, specific examples of the second embodiment will be described in detail with reference to the drawings. FIG. 4 shows a timing chart when n = 4 and m = 4 in the second embodiment of FIG. At this time, the first input signal CLK1 the phase difference between the second input signal CLK2 and _{T C.} In the time digital converter 40, the data holding circuits 23_1 to 23_4, when the phase of the input signal to the data terminal is ahead of the input signal to the clock terminal, as in the first embodiment shown in FIG. Output logic "1".

At this time, the respective delay times of the inverter array 11_1 ~ 11_4 to [Delta] T _C. The outputs D _C (1) to D _C (3) of the inverter rows 11_1 to 11_4 with respect to the first input signal CLK1 are delayed by ΔT _C to 3ΔT _C , respectively, and the output time point of the third-stage inverter 11_3 Thus, the phase relationship with the second input signal CLK2 is reversed.

In other words, the outputs Q _C (1) to Q _C (4) of the data holding circuits 23_1 to 23_4 output a logic “0” up to the third stage and a logic “1” at the fourth stage. At this time, the inverter train, among the inverters 11_1 ~ 11_4 four stages, since it passes through the three stages is occurring reversed phase relationship, the phase difference T _C by counting the number of logic "0" It can be seen that the delay is between two and three delay stages of the inverter train. Even in this configuration, the phase difference _TF between the CLK2 signal and D _C (3) is used,
T _C = 3ΔT _C -T _F
It is expressed.

Outputs Q _C (1) to Q _C (4) of the data holding circuits 23_1 to 23_4 are connected to the logic circuit 4 and also to the OR circuit 25, and the output signal of the third-stage inverter 11_3. As a result of the output of logic “1” in synchronization with the falling edge of D _C (3) (the rising edge in FIG. 4), the output FCLK2 of the OR circuit 25 receives an inverter train immediately after the rising timing of the input signal CLK2. The inversion timings of the outputs 11_1 to 11_4 are extracted. Further, since the inverter arrays 21_1 to 21_4 and the data holding circuits 22_1 to 22_4 have the same configuration as the small phase difference detector 20 in the digital phase comparator shown in FIG. 1, the output FCLK1 of the OR circuit 24 is The rising timing of the second input signal CLK2 is extracted.

Therefore, also in the configuration of the present embodiment, the output signals FCLK1 and FCLK2 that maintain the phase difference _TF between the second input signal CLK2 and the inverted signal of the inverter trains 11_1 to 11_4 output immediately after the CLK2 signal is input are output.

Since the time digital converter 50 has the same configuration as the small phase difference detector 20 in the digital phase comparator shown in FIG. 1, the same result as the configuration shown in FIG. 2 is obtained. The output of the data holding circuit after the third stage becomes logic “0”, and it can be seen that the phase difference _TF is between two stages and three stages of the delay difference ΔT _F1 -ΔT _F2 of the inverter train. That is,
2 (ΔT _F1 −ΔT _F2 ) <T _F <3 (ΔT _F1 −ΔT _F2 )
The relationship holds.

From the decoding result in the logic circuits 4 and 5,
T _C = 3ΔT _C −T _F is
3ΔT _C −3 (ΔT _F1 −ΔT _F2 ) <T _C <3ΔT _C −2 (ΔT _F1 −ΔT _F2 )
It can be seen that it is.

As described above, even with the digital phase comparator according to the present embodiment, it is possible to realize a high-resolution digital phase comparator in which power consumption and circuit area are greatly reduced compared to the conventional configuration. Further, in this embodiment, the power consumption and the circuit area can be further reduced by the amount not using the data holding circuits 12_1 to 12_n in the first embodiment.

[Third Embodiment]
FIG. 5 is a diagram illustrating a configuration of a digital phase comparator according to the third embodiment of the present invention. Referring to FIG. 5, in the digital phase comparator according to the present embodiment, a signal CLKV from the VCO 101 and a reference signal REF are input. The reference signal REF is captured by the data holding circuit 102 at the rising edge of the VCO output signal CLKV, and the retimed signal REFT is output.

The retiming signal REFT holds phase information of the rising edge of the output signal CLKV of the VCO 101. Therefore, by using the phase difference information of the retiming signal REFT with respect to the reference signal REF, the phase comparison between the reference signal REF and the output signal CLKV of the VCO 101 can be performed.

The reference signal REF and the retiming signal REFT are input to the time digital converter 10 and the same operation as the digital phase comparator described in the first embodiment shown in FIG. 1 is performed.

[Example]
Next, specific examples of the third embodiment will be described in detail with reference to the drawings. FIG. 6 shows a timing chart when n = 4 and m = 4 in the third embodiment of FIG. At this time, when the phase difference between the output signal CLKV and the reference signal REF of the VCO 101 and _{T C,} the reference signal REF, since captured at the rising edge output signal CLKV of by the data holding circuit 102 VCO 101 as a clock, Li The timing signal REFT is a signal synchronized with the output signal CLKV of the VCO 101, and the phase comparison between the reference signal REF and the retiming signal REFT enables the phase comparison between the reference signal REF and the output signal CLKV of the VCO 101. The phase comparison operation between the reference signal REF and the retiming signal REFT after the time digital converter 10 is the same as the operation in the digital phase comparator of the first embodiment shown in FIG.

As described above, even with the digital phase comparator according to the present embodiment, it is possible to realize a high-resolution digital phase comparator in which power consumption and circuit area are greatly reduced compared to the conventional configuration. Even when a high-speed signal such as the signal CLKV from the VCO is compared with the reference signal REF, only the data holding circuit (FF) 102 that operates as a retiming circuit operates at high speed. Since only comparison using a low-speed signal of the reference signal REF is performed, the overall power consumption can be reduced.

[Fourth Embodiment]
FIG. 7 is a diagram illustrating a configuration of a digital phase comparator according to the fourth embodiment of the present invention. Referring to FIG. 7, the digital phase comparator according to the present embodiment receives the output signal CLKV of the VCO 101 and the reference signal REF, similarly to the digital phase comparator according to the third embodiment shown in FIG. The reference signal REF is captured by the data holding circuit 102 at the rising edge of the output signal CLKV of the VCO 101, and the retimed signal REFT is output. The reference signal REF and the retiming signal REFT are input to the time digital converter 40, and the same operation as the digital phase comparator described in the second embodiment shown in FIG. 3 is performed.

[Example]
Next, specific examples of the fourth embodiment will be described in detail with reference to the drawings. FIG. 8 shows a timing chart when n = 4 and m = 4 in the fourth embodiment of FIG. At this time, when the phase difference between the output signal CLKV and the reference signal REF of the VCO 101 and _{T C,} the reference signal REF, since captured at the rising edge output signal CLKV of by the data holding circuit 102 VCO 101 as a clock, Li The timing signal REFT is a signal synchronized with the output signal CLKV of the VCO 101, and the phase comparison between the reference signal REF and the retiming signal REFT enables the phase comparison between the reference signal REF and the output signal CLKV of the VCO 101. The phase comparison operation between the reference signal REF and the retiming signal REFT after the time digital converter 40 is the same as the operation in the digital phase comparator of the second embodiment shown in FIG.

As described above, even with the digital phase comparator according to the present embodiment, it is possible to realize a high-resolution digital phase comparator in which power consumption and circuit area are significantly reduced compared to the conventional configuration. Further, in the present embodiment, similarly to the second embodiment, the power consumption and the circuit area can be further reduced by the amount not using the data holding circuits 12_1 to 12_n in the third embodiment. Further, even when a high-speed signal such as the signal CLKV from the VCO is compared with the reference signal REF, only the retiming circuit 102 operates at high speed, and the entire circuit uses a low-speed signal about the reference signal REF. Therefore, the overall power consumption can be reduced.

[Fifth Embodiment]
FIG. 9 is a diagram illustrating a configuration of a digital phase comparator according to the fifth embodiment of the present invention. Referring to FIG. 9, in the digital phase comparator according to the present embodiment, a signal CLKV from the VCO 101 and a reference signal REF are input. The reference signal REF is taken in at the rising and falling edges of the output signal CLKV of the VCO 101 by the data holding circuits 102 and 103, and outputs retimed signals REFT and REFC, respectively. The retiming signals REFT and REFC respectively hold the rising and falling phase information of the output signal CLKV of the VCO 101, and the phase difference between the retiming signals REFT and REFC is a phase difference corresponding to a half cycle of the output signal CLKV of the VCO 101. Keep information.

Therefore, by using the phase difference information of the retiming signals REFT and REFC with respect to the reference signal REF, it becomes possible to compare the phase of the reference signal REF and the VCO output CLKV and normalize the phase comparison result in the VCO output signal cycle. .

The reference signal REF and the retiming signals REFT and REFC are input to the time digital converter 10 '. The time digital converter 10 'is configured by adding data holding circuits 13_1 to 13_n to the time digital converter 10 shown in FIG. The data holding circuits 12_1 to 12_n are the retiming signals REF and signals (Dc (1) to Dc (n-1)) obtained by sequentially delaying the reference signal REF by the inverter rows 11_1 to 11_ (n-1). REFT is captured as a clock signal. The data holding circuits 13_1 to 13_n retiming the reference signal REF and signals (Dc (1) to Dc (n-1)) obtained by sequentially delaying the reference signal REF by the inverter rows 11_1 to 11_ (n-1). The signal REFC is captured as a clock signal.

The data holding circuits 12_1 to 12_n output the phase difference between the reference signal REF and the retiming signal REFT as digital signals TQ _C (1) to TQ _C (n), and the data holding circuits 13_1 to 13_n perform the retiming with the reference signal REF. The phase difference of the signal REFC is output as digital signals CQ _C (1) to CQ _C (n), and the result is input to the logic circuit 1 ′.

The small phase difference detector 20 includes the reference signal REF, the retiming signal REFT, and the outputs D _C (1) to D _C (n−1) of the inverter trains 11_1 to 11_ (n−1) of the time digital converter 10 ′. Are output, and output signals TFCLK1 and TFCLK2 that maintain the phase difference between the retiming signal REFT and the inverted output of the inverter trains 11_1 to 11_ (n−1) immediately after the input of the REFT signal are output.

Similarly, the small phase difference detector 30 receives the reference signal REF, the retiming signal REFC, and the outputs D _C (1) to D _C (n−1) of the inverter array of the time digital converter 10 ′. Output signals CFCLK1 and CFCLK2 that maintain the phase difference between the retiming signal REFC and the inverted output signal of the inverter trains 11_1 to 11_ (n−1) immediately after the REFC signal is input are output. The small phase difference detector 20 and the small phase difference detector 30 have the same circuit configuration, and the delay time in the inverter row is the same.

In the time digital converter 50, the phase comparison between TFCLK and TFCLK2 is performed with the resolution of the delay time difference between the inverter trains 51_1 to 51_m and 52_1 to 52_m, as in the first embodiment.

Similarly, in the time digital converter 60, the phase comparison between CFCLK and CFCLK2 is performed with the resolution of the delay time difference between the inverter trains 61_1 to 61_m and 62_1 to 62_m, as in the first embodiment.

Also, in the time digital converter 70, the output signals of the inverter trains 11_n and 11_n + 1 in the time digital converter 10 'are input, and the delay time difference for one stage of the inverter train is measured. The time digital converters 50, 60, and 70 have the same circuit configuration, and the delay time difference between the inverter trains is the same.

[Example]
Next, specific examples of the fifth embodiment will be described in detail with reference to the drawings. 10 to 13 show timing charts when n = 8 and m = 8 in the fifth embodiment of FIG.

FIG. 10 shows a timing chart of the time digital converter 10 ′. At this time, the phase difference between the reference signal REF and the retiming signal REFT is T _C , and the phase difference between the reference signal REF and the retiming signal REFC is T _CC .

When the delay times of the inverter array 11_1 ~ 11_8 in the time-digital converter 10 'and [Delta] T _C, the phase of the input and output signals in the inverter array 11_1 ~ 11_7 is gradually delayed by [Delta] T _C during each pass through the inverter. The phase relationship of the retiming signal REFT with respect to the signals D _C (1) to D _C (7) sequentially delayed by the inverter rows 11_1 to 11_7 is reversed at the output time of the third-stage inverter 11_3, and the data holding circuits 12_1 to 12_8. In the outputs TQ _C (1) to TQ _C (8), logic “1” is output until the third stage, and logic “0” is output after the fourth stage.

That is, it can be seen that the phase difference T _CT is between two and three delay stages of the inverter train, and using the phase difference T _FT between the retiming signals REFT and D _C (3),
T _CT = 3ΔT _C -T _FT
It is expressed.

Similarly, the phase relationship of the retiming signal REFC with respect to the signals D _C (1) to D _C (7) sequentially delayed by the inverter rows 11_1 to 11_7 is reversed at the output time of the seventh stage inverter 11_7, and the data holding circuit In the outputs CQ _C (1) to CQ _C (8) of 13_1 to 13_8, logic “1” is output up to the seventh stage, and logic “0” is output from the eighth stage.

That is, it can be seen that the phase difference T _CC is between the delay stage 6 and 7 stages of the inverter train, and using the phase difference T _FC between the retiming signals REFT and D _C (7),
T _CT = 7ΔT _C -T _FC
It is expressed.

FIG. 11 shows a timing chart in the small phase difference detector 20 and the time digital converter 50.

In the small phase difference detector 20, as in the first embodiment, the output signal TFCLK1 that maintains the phase difference TFT between the retiming signal REFT and the output signal D _C (3) of the inverter 11_3 immediately after the input of REFT, and TFCLK2 is output.

In the time digital converter 50, the phase difference between TFCLK1 and TFCLK2 is measured with the delay time difference accuracy between the inverter trains 51_1 to 51_8 and the inverter trains 52_1 to 52_8. At this time, since the phase of the data input is advanced with respect to the clock input up to the second stage data holding circuit 53_2, a logic “1” is output. Since reverse rotation occurs, the output of the data holding circuit after the third stage is logic “0”, and the phase difference T _FT is between the delay stage ΔT _F1 -ΔT _F2 of the inverter stage and the third stage. Recognize.

FIG. 12 shows a timing chart in the small phase difference detector 30 and the time digital converter 60.

In the small phase difference detector 30, as in the small phase difference detector 20, the output signal CFCLK1 that maintains the phase difference TFC between the retiming signal REFC and the output signal D _C (7) of the inverter 11_7 immediately after REFC input. And CFCLK2 are output. In the time digital converter 60, the phase difference between CFCLK1 and CFCLK2 is measured with a delay time difference accuracy between the inverter trains 61_1 to 61_8 and the inverter trains 62_1 to 62_8. At this time, since the phase of the data input is advanced with respect to the clock input up to the first-stage data holding circuit 63_2, the logic “1” is output. Since the phase relationship is reversed, the outputs Q _FC (2) to Q _FC (8) of the data holding circuits 53_2,... 53_8 in the second and subsequent stages are logic “0”, and the phase difference T _FC is It can be seen that the delay difference ΔT _F1 -ΔT _{F2 of the} inverter train is between one stage and two stages.

FIG. 13 shows a timing chart in the time digital converter 70.

The time to digital converter 70, is inputted time-digital converter 10 inverter row 11_8 and the output signal _D C (8) and _D C (9) of 11_9 of ', the delay time [Delta] T _C of the inverter array is measured . At this time, since the phase of the data input is advanced with respect to the clock input up to the fifth-stage data holding circuit 73_5, the logic “1” is output, but the stage that has passed through the sixth-stage inverter row 11_6. Since the phase relationship is reversed, the outputs of the data holding circuits 73_6 and 73_7_73_8 in the sixth and subsequent stages are logic “0”, and the phase difference T _FC is equal to the delay difference ΔT _F1 −ΔT _F2 of the inverter stage and 6 stages. It turns out that it is between steps.

From the above, the phase difference T _CT between the reference signal REF and the retiming signal REFT is expressed by the following equation.

T _CT = 3ΔT _C -T _FT
= 3 × 5 (ΔT _F1 −ΔT _F2 ) −2 (ΔT _F1 −ΔT _F2 )
= 13 (ΔT _F1 −ΔT _F2 ) (Formula 1)

Similarly, the phase difference T _CC between the reference signal REF and the retiming signal REFC is expressed by the following equation.

T _CC = 7ΔT _C -T _FC
= 7 × 5 (ΔT _F1 −ΔT _F2 ) − (ΔT _F1 −ΔT _F2 )
= 34 (ΔT _F1 −ΔT _F2 ) (Expression 2)

Therefore, the phase difference normalized by the VCO output signal period in this case is expressed as follows.

T _CT −2 × (T _CC −T _CT ) = 13/34 (Formula 3)

Therefore, in the digital phase comparator of the present embodiment, the phase difference between the retiming signals REFT and REFC with respect to the reference signal REF is measured, the phase comparison between the reference signal REF and the VCO output CLKV, and the VCO output signal period of the phase comparison result is performed. It can be seen that it is possible to normalize.

Further, by using such a configuration, even when a high-speed signal such as the signal CLKV from the VCO 101 is compared with the reference signal REF, the retiming circuit (data holding circuit) 102 is operated at high speed. 103, and only the comparison using the low-speed signal of the reference signal REF is performed as a whole circuit, so that the power consumption can be reduced as a whole.

[Sixth Embodiment]
FIG. 14 is a diagram illustrating a configuration of a digital phase comparator according to the sixth embodiment of the present invention. Referring to FIG. 7, the digital phase comparator according to the present embodiment also receives the input of the signal CLKV from the VCO 101 and the reference signal REF as in the case of the digital phase comparator of the fifth example shown in FIG. By using the phase difference information of the retiming signals REFT and REFC with respect to the reference signal REF, the phase comparison between the reference signal REF and the VCO output CLKV and the normalization of the phase comparison result in the VCO output signal cycle are performed.

Further, the time digital converter 40 ′ has the same configuration as that of the time digital converter 40 shown in FIG. 3, and detects the phase difference between the reference signal REF and the retiming signal REFT and the REFT that is less than the resolution due to the delay time of the inverter train. An operation that also serves as detection of inversion timing in the inverter trains 11_1 to 11_n immediately after signal input is performed. Further, by adding inverter rows 41_1 to 41_n, data holding circuits 42_1 to 42_n, data holding circuits 43_1 to 43_n, OR circuit 44 and OR circuit 45, phase difference detection between the reference signal REF and the retiming signal REFC, An operation that also serves as detection of the inversion timing in the inverter trains 11_1 to 11_n immediately after the REFC signal input with a resolution equal to or lower than the resolution of the train delay time is performed.

[Example]
Next, specific examples of the sixth embodiment will be described in detail with reference to the drawings. 15 to 18 show timing charts when n = 8 and m = 8 in the sixth embodiment shown in FIG.

FIG. 15 shows a timing chart of the time digital converter 40 ′. At this time, the phase difference between the reference signal REF and the retiming signal REFT is T _C , and the phase difference between the reference signal REF and the retiming signal REFC is T _CC . 'If the delay times of the inverter array 11_1 ~ 11_8 in the [Delta] T _C, the time to digital converter 40' time-to-digital converter 10 in the data holding circuits 23_1 ~ 23_8, the phase of the input signal to the data terminal to the clock terminal If you are delayed from the input signal, since the output a logic "1", when the delay times of the inverter array 11_1 ~ 11_8 to [Delta] T _C, with respect to the reference signal REF, the outputs _{D C} of the inverter array 11_1 ~ 11_7 (1) _to the output of the _D C (7), respectively, delayed by ΔT _C ~ 7ΔT _C, at the output point of the third-stage inverter 11_3, the phase relationship between the retiming signal REFT is reversed.

That is, the output Q _C (1) to Q _C (8) of the data holding circuits 23_1 to 23_8 outputs a logic “0” until the third stage, and outputs a logic “1” after the fourth stage. . At this time, the phase difference T _CT is calculated by counting the number of stages of logic “0” because the phase relationship is reversed through three stages of the seven stages of inverters 11_1 to 11_7. It can be seen that the delay is between two and three stages of delay of the inverter train, and the phase difference TFT between the retiming signal REFT and DC (3) is used. T _CT = 3ΔT _C -T _FT
It is expressed.

At the same time, the OR circuits 24 and 25 maintain the phase difference T _FT between the retiming signal REFT and the output signal D _C (3) of the inverter 11_3 immediately after REFT input, as in the second embodiment. Output signals TFCLK1 and TFCLK2 are output.

Similarly, the phase relationship of the retiming signal REFC with respect to the signals D _C (1) to D _C (7) sequentially delayed by the inverter rows 11_1 to 11_7 is reversed at the output time of the seventh stage inverter 11_7, and the data holding circuit In the outputs CQ _C (1) to CQ _C (8) of 43_1 to 43_8, logic “0” is output up to the seventh stage, and logic “1” is output from the eighth stage.

That is, it can be seen that the phase difference T _CC is between the delay stage 6 stages and 7 stages of the inverter row, and using the phase difference T _FC between the retiming signal REFT and DC (7),
T _CT = 7ΔT _C -T _FC
It is expressed.

The OR circuits 44 and 45 output the output signals CFCLK1 and CFCLK2 that maintain the phase difference T _FC between the retiming signal REFC and the output signal D _C (7) of the inverter train 11_7 immediately after the REFC is input.

16 to 18 show timing charts of the time digital conversion circuits 50, 60, and 70, respectively. The time digital conversion circuits 50, 60 and 70 have the same configuration as that of the fifth embodiment shown in FIG. 9, and the operation thereof is the same as that shown in FIGS. Therefore, explanation is omitted.

With the above operation, the digital phase comparator of this embodiment also measures the phase difference between the retiming signals REFT and REFC with respect to the reference signal REF, compares the phase of the reference signal REF and the output signal CLKV of the VCO 101, and the phase comparison result. Can be normalized with the VCO output signal period. Even when a high-speed signal such as the output signal CLKV from the VCO 101 is compared with the reference signal REF, only the retiming circuits 102 and 103 operate at high speed, and the circuit as a whole is as low as the reference signal REF. Since only comparison using signals is performed, overall power consumption can be reduced.

Furthermore, in this embodiment, the power consumption and the circuit area can be further reduced by the amount not using the data holding circuit (12_1 to 12_n) in the third embodiment.

[Seventh Embodiment]
FIG. 23 is a diagram showing the configuration of the seventh exemplary embodiment of the present invention. In FIG. 23, the first time digital converter 40 of FIG. 1 or 3 is omitted, and the second time digital converter 50 of FIG. 23 is the second time digital converter of FIG. This corresponds to the converter 50. Referring to FIG. 23, the digital phase comparator according to the present embodiment includes a second time digital converter 50 (output signals FCLK1 from OR circuits 24, 25) of the digital phase comparator shown in FIG. FCLK2 is input), and data holding circuits 54_1 to 54_m and m-input OR circuits 55 and 56 are added. The output of the data holding circuits 53_1 to 53_m is input to the OR circuit 55, and the output is output as F2CLK2. The data holding circuits 54_1 to 54_m input the outputs CK _F (1) to CK _F (m) of the inverter arrays 52_1 to 52_m to the respective data input terminals, and output the outputs D _F (1) of the inverter arrays 51_1 to 51_m. ˜D _F (m) is input to the clock terminal, the signal of the data input terminal is captured at the edge of the clock terminal, the outputs of the data holding circuits 54_1 to 54_m are input to the OR circuit 56, and the output of the OR circuit 56 is F2CLK2. Is output. The phase difference between the output signals F2CLK1 and F2CLK2 of the OR circuit 55 and the OR circuit 56 is the same as that of the time digital converter 50, and the inverter train 51_1 to 51_m and the inverter train having a smaller delay time difference than the inverter trains 52_1 to 52_m, It is detected and digitally encoded by a time digital converter 80 having 81_1-81_1 and 82_1-82_1.

Note that the output signals of the data holding circuits 53_1 to 53_m are the normal output of the data terminal in order to match the logic. Further, in order to match the logic of the output signal and the clock terminal input signal, the data holding circuits 54_1 to 54_m set the logic of the output and the clock terminal to negative logic in the odd stages and positive logic in the even stages. The odd-numbered stage i data holding circuit 53_i captures D _F (i) at the falling edge of CCK _F (i), and outputs the inverted output of the data output terminal as Q _F1 (i). The data holding circuit 53_j of the even-numbered stage j takes in D _F (j) at the rising edge of CK _F (j) and outputs the output data of the data output terminal as Q _F1 (j).

[Example]
Next, specific examples of the seventh embodiment will be described in detail with reference to the drawings. 24 and 25 show timing charts when n = 4, m = 4, and l = 4 in the seventh embodiment of the present invention shown in FIG. 24 shows the operation of generating the signal F2CLK1 from the OR circuit 55 that receives the outputs QF2 (1) to QF2 (4) of the data holding circuits 54_1 to 54_m, and FIG. 25 shows the output Q _{F1 of the} data holding circuits 53_1 to 53_m. An example of the operation of generating the signal F2CLK2 from the OR circuit 56 having (1) to Q _F1 (4) as inputs is shown.

24 and 25, the operation of the time digital converter 80 is the same as the operation of the time digital converter 50 of the digital phase comparator of the first embodiment shown in FIG. That is, the operation of the time digital converter 80 is the same as that shown in FIG. 2 with respect to FCLK1, FCLK2, CK _F (1) to CK _F (4), D _F (1) to D _F (4), Q _F (1). ) To Q _F (4), the timing waveforms of F2CLK1, F2CLK2, CK _F2 (1) to CK _F2 (4), D _F2 (1) to D _F2 (4), and Q _F3 (1) to Q in FIG. _It may be replaced with _F3 (4).

The time digital converter 50 of FIG. 23 obtains the same results except that the output is inverted from the configuration example shown in FIGS. 1 and 2, and the first and second stage data holding circuits 53_1, 53_2 outputs (Q _F1 (1), Q _F1 (2)) are logic “0”, and the outputs (Q _F1 (3), Q _F1 (4)) of the data holding circuits 53_3, 53_4 in the third and subsequent stages are Since the logic is “1”, it can be seen that the phase difference TF is between two and three stages of the delay difference ΔTF1−ΔTF2 of the inverter train. That is,
2 (ΔTF1-ΔTF2) <TF <3 (ΔTF1-ΔTF2)
The relationship holds.

Outputs Q _F2 (1) to Q _{F2 (} 4) of the data holding circuits 54_1 to 54_4 are connected to the OR circuit 55, and the output D _F (3) of the third-stage inverter 51_3 falls (in FIG. 24). As a result of the logic “1” being output in synchronization with the rising edge), the rising timing of D _F (3) is extracted from the output F2CLK1 of the OR circuit 55. The outputs of the data holding circuits 53_1 to 53_4 are connected to the logic circuit 5 and also to the 4-input OR circuit 56, and the output signal CK _F (3) of the third-stage inverter 52_3 rises. As a result of the output of logic “1” in synchronization with the falling edge (rising edge in FIG. 24), the rising timing of CK _F (3) is extracted from the output F2CLK2. By comparing the two extracted outputs F2CLK1 and F2CLK2 by the time digital converter 80, it becomes possible to detect a further minute phase difference that cannot be detected by the time digital converter 50.

In other words, according to the present embodiment, it is possible to relax the time resolution setting in the time digital converter 10 and the time digital converter 50 before the time digital converter 80. As a result, the circuit area can be reduced and the power consumption can be reduced.

Furthermore, the configuration of the time digital converter 80 is the same as that of the time digital converter 50 in the digital phase comparator of the present embodiment, so that even a minute phase difference that cannot be detected by the time digital converter 80 can be detected. It is obvious that a simple configuration may be used. Note that the operation of the time digital converter 80 is the same as the operation of the time digital converter 50 shown in FIG.

It should be noted that the disclosures of the above patent documents and non-patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the examples and the examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1, 1 ′, 4, 4 ′, 5, 6, 7, 8 Logic circuit 10, 10 ′, 40, 40 ′, 50, 60, 70, 80 Time digital converter 20, 30 Small phase difference detector 11_1˜ 11_n, 11_n + 1, 11_n + 2, 21_1 to 21_n, 41_
1-41_n, 51_1-51_m + 1, 52_1-52_m + 1, 61_1-6
1_m + 1, 62_1 to 62_m + 1, 71_1 to 71_m + 1, 72_1 to 72_m + 1, 81_1 to 81_l + 1, 82_1 to 82_l + 1 Inverter (delay element)
12_1 to 12_n, 13_1 to 13_n, 22_1 to 22_n, 23_1 to 23
_N, 42_1 to 42_n, 43_1 to 43_n, 53_1 to 53_m, 54_1
54_m, 63_1-63_m, 73_1-73_m, 83_1-83_l Data holding circuit (flip-flop)
24, 25, 44, 45, 55, 56 OR circuit (OR operation circuit)
101 VCO (Voltage Controlled Oscillator)
102, 103 Retiming circuit (data holding circuit)

Claims (29)

1. The first input signal is sampled by each of the second input signal and the second delayed input signal group obtained by delaying the second input signal at equal intervals. A first circuit unit that performs a logical operation to generate a first signal;
   A first delayed input signal group obtained by delaying the second input signal at equal intervals by the same unit delay time as the second delayed input signal group, the first input signal and the first input signal. A second circuit unit that samples each of the plurality of sampled signals and performs a predetermined logical operation on the sampled signals to generate a second signal;
   Receiving the first and second signals generated by the first and second circuit units, respectively, and generating a first delayed signal group obtained by delaying the first signal at equal intervals; Are generated at equal intervals with a unit delay time different from that of the first delay signal group, and the first delay signal group, the second delay signal group, A third circuit unit that samples each delay signal of one of the delay signal groups by a corresponding delay signal of the other delay signal group;
   With
   The phase difference between the first input signal and the second input signal is the signal sampled in the first circuit unit or the second circuit unit and the signal sampled in the third circuit unit. A digital phase comparator used as a value corresponding to.
2. The first circuit unit includes a circuit that receives the second input signal and generates the second delayed input signal group obtained by delaying the second input signal at equal intervals.
   The second circuit unit receives the first input signal, and delays the first input signal at equal intervals by the same unit delay time as the second delayed input signal group. The digital phase comparator according to claim 1, further comprising a circuit that generates a group of delayed input signals.
3. The first circuit unit includes a circuit that receives the second input signal and generates a second delayed input signal group obtained by delaying the second input signal at equal intervals.
   The first input signal is input, and a first delayed input signal group is generated by delaying the first input signal at equal intervals by the same unit delay time as the second delayed input signal group, A fourth circuit unit that samples the first input signal and the first delayed input signal group in common with the second input signal;
   As a value corresponding to the phase difference between the first input signal and the second input signal, the signal sampled in the fourth circuit unit instead of the signal sampled in the first or second circuit unit. The digital phase comparator according to claim 1, wherein a signal and a signal sampled in the third circuit unit are used.
4. In the third circuit unit, each delay signal of the other delay signal group used as a sampling signal of each delay signal of the one delay signal group is changed by a corresponding delay signal of the one delay signal group, respectively. A fifth circuit unit that samples and performs a predetermined logic operation on the plurality of sampled signals to generate a third signal;
   A circuit that performs a predetermined logical operation on the plurality of signals sampled in the third circuit unit to generate a fourth signal;
   The third and fourth signals are received, a third delayed signal group is generated by delaying the third signal at equal intervals, and the fourth signal is generated in the first circuit unit in the third circuit unit. A fourth delay signal group is generated in which the unit delay time difference is smaller than the unit delay time difference of the second delay signal group and is delayed at equal intervals by a unit delay time different from that of the third delay signal group. And a sixth circuit for sampling each delay signal of one of the third delay signal group and the fourth delay signal group by a corresponding delay signal of the other delay signal group, respectively. Unit,
   With
   The signal sampled in the sixth circuit unit is further used as a value corresponding to the phase difference between the first input signal and the second input signal, according to any one of claims 1 to 3. The digital phase comparator described.
5. Using a reference signal as the first input signal,
   4. The digital phase comparator according to claim 1, wherein an output signal obtained by sampling the first input signal by a holding circuit in response to an output of an oscillator is used as the second input signal. 5.
6. A circuit that samples the input signal every half cycle of the oscillation frequency of the clock oscillator and generates two signals,
   A set of the first and second circuit units that inputs one of the input signal and the two signals as the first and second input signals, respectively, and the third circuit unit;
   The first and second circuit units for inputting the other of the input signal and the two signals as the first and second input signals, respectively, and another set of the third circuit unit;
   The digital phase comparator according to claim 1, further comprising:
7. A circuit that samples the input signal every half cycle of the oscillation frequency of the clock oscillator and generates two signals,
   The input signal is a first input signal, one of the two signals is a second input signal, and the other of the two signals is a third input signal,
   A first delayed input signal group is generated by delaying the first input signal at equal intervals, and the first input signal and the first delayed input signal group are set to the first of the second input signals. A circuit that samples in common at the transition edges of
   A circuit for commonly sampling the first input signal and the first delayed input signal group at a second transition edge of the third input signal;
   With
   For the set of first and second input signals,
   A second delayed input signal group is generated by delaying the second input signal at equal intervals by the same unit delay time as the first delayed input signal group, and the first input signal is A circuit that samples each of the two input signals and the second delayed input signal group, and performs a predetermined logical operation on the plurality of sampled signals to generate a first signal;
   The second input signal is sampled by the first input signal and the first delayed input signal group, respectively, and a predetermined logical operation is performed on the plurality of sampled signals to obtain the second signal. A circuit to generate,
   A first delay signal group is generated by delaying the first signal at equal intervals, and the second signal is delayed at equal intervals by a unit delay time different from that of the first delay signal group. Two delay signal groups are generated, and each delay signal of one delay signal group among the first delay signal group and the second delay signal group is represented by a corresponding delay signal of the other delay signal group. Each with a circuit to sample,
   For the set of first and third input signals,
   A third delayed input signal group is generated by delaying the third input signal at equal intervals with the same unit delay time as the first delayed input signal group, and the first input signal is A circuit that samples each of the three input signals and the third delay input signal group, and performs a predetermined logical operation on the plurality of sampled signals to generate a third signal;
   A circuit that samples the third input signal by the first input signal and the first delayed input signal group, respectively, and performs a predetermined logical operation on the plurality of sampled signals to generate a fourth signal. When,
   A third delay signal group is generated by delaying the third signal at equal intervals, and the fourth signal is delayed at equal intervals by a unit delay time different from that of the third delay signal group. 4 delay signal groups are generated, and among the third delay signal group and the fourth delay signal group, each delay signal of one delay signal group is represented by a corresponding delay signal of the other delay signal group. The digital phase comparator according to claim 1, further comprising a circuit for sampling.
8. A circuit that samples the input signal every half cycle of the oscillation frequency of the clock oscillator and generates two signals,
   The input signal is a first input signal, one of the two signals is a second input signal, and the other of the two signals is a third input signal,
   For the set of first and second input signals,
   A second delayed input signal group is generated by delaying the second input signal at equal intervals, and the first input signal is sampled by the second input signal and the second delayed input signal group, respectively. A circuit that performs a predetermined logical operation on the plurality of sampled signals to generate a first signal;
   A first delayed input signal group is generated by delaying the first input signal at equal intervals, and the second input signal is sampled by the first input signal and the first delayed input signal group, respectively. A circuit that performs a predetermined logical operation on the plurality of sampled signals to generate a second signal;
   A first delay signal group is generated by delaying the first signal at equal intervals, and the second signal is delayed at equal intervals by a unit delay time different from that of the first delay signal group. Two delay signal groups are generated, and each delay signal of one delay signal group among the first delay signal group and the second delay signal group is replaced with a corresponding delay signal of the other delay signal group. Each circuit to sample,
   With
   For the set of first and third input signals,
   A third delayed input signal group is generated by delaying the third input signal at equal intervals, and the first input signal is sampled by the third input signal and the third delayed input signal group, respectively. A circuit that performs a predetermined logical operation on the plurality of sampled signals to generate a third signal;
   The third input signal is sampled by the first input signal and the first delayed input signal group, respectively, and a predetermined logical operation is performed on the plurality of sampled signals to generate a fourth signal. A circuit to
   A third delay signal group is generated by delaying the third signal at equal intervals, and the fourth signal is delayed at equal intervals by a unit delay time different from that of the third delay signal group. 4 delay signal groups are generated, and among the third delay signal group and the fourth delay signal group, each delay signal of one delay signal group is represented by a corresponding delay signal of the other delay signal group. The digital phase comparator according to claim 1, further comprising a circuit for sampling.
9. A fifth signal obtained by further delaying the first input signal by a unit delay time than the delayed signal group of the first input signal, and a sixth signal obtained by delaying the fifth signal by a unit delay time. And generate a fifth delay signal group obtained by delaying the fifth signal at equal intervals, and the sixth signal is equally spaced at a unit delay time different from that of the fifth delay signal group. A sixth delay signal group that is delayed in the first delay signal group, the fifth delay signal group, and the sixth delay signal group. 9. A digital phase comparator according to claim 7 or 8, comprising a circuit for sampling each with a corresponding delay signal.
10. (A) A first delayed input signal group obtained by delaying the first input signal at equal intervals is generated, and the second input signal is set at equal intervals from the first input signal and the first input signal. Each sampled by the delayed first delayed input signal group, and a predetermined logic operation is performed on the plurality of sampled signals to generate a first signal;
    (B) generating a second delayed input signal group in which the second input signal is delayed at equal intervals by the same unit delay time as the first delayed input signal group, and the first input signal is Each sampled by the second input signal group and the second delayed input signal group, and a predetermined logical operation is performed on the plurality of sampled signals to generate a second signal,
    (C) generating a first delay signal group obtained by delaying the first signal at equal intervals, and delaying the second signal at equal intervals with a unit delay time different from that of the first delay signal group A second delayed signal group is generated, and each of the delayed signal groups of the first delayed signal group and the second delayed signal group corresponds to the other delayed signal group. Each sampled with a delayed signal,
    (D) The signal sampled in (a) or (b) and the signal sampled in (c) are used as values representing the phase difference between the first input signal and the second input signal. Phase comparison method.
11. A first delay element array in which a plurality of delay elements are connected in cascade, a first pulse input signal is input to the first stage, and a first delay signal group composed of a plurality of delay signals sequentially delayed at each stage is output;
    A plurality of holding circuits that sequentially take in the first pulse input signal according to the transition timing of the first delay signal group, using the first delay signal group output from the first delay element array as a clock input, respectively. A first holding circuit group comprising:
    A first OR operation circuit receiving the output of the first holding circuit group;
    A plurality of delay elements having the same delay time as the delay elements of the first delay element array are connected in cascade, and a second pulse input signal is input to the first stage, and a second delay signal is sequentially delayed. A second delay element array that outputs a delay signal group;
    A plurality of holding circuits which sequentially take in the first pulse input signal according to the transition timing of the second delay signal group, each of which has a second delay signal group output from the second delay element array as a clock input; A second holding circuit group provided;
    A second OR operation circuit that receives the output of the second data holding circuit group;
    With
    A first time digital conversion circuit that outputs an output of the first holding circuit group as a value indicating a relative phase difference between the first pulse input signal and the second pulse input signal;
    A third delay element array in which a plurality of delay elements are connected in cascade, and an output of the first OR operation circuit is input to the first stage and a third delay signal group including a plurality of delay signals sequentially delayed is output; ,
    A delay element having a delay time different from that of the third delay element array is connected in a plurality of stages, and the output of the second OR circuit is input to the first stage and a fourth delay signal is sequentially delayed. A fourth delay element array that outputs a delay signal group of:
    The delay signal of each stage of the third delay signal group from the third delay element array is the transition timing of the delay signal of the corresponding stage of the fourth delay signal group from the fourth delay element array. A third holding circuit group including a plurality of holding circuits, which are sequentially captured according to
    With
    The relative phase difference between the output of the first logical sum operation circuit and the output of the second logical sum operation circuit is determined from the output of the third holding circuit group as a delay signal of the third delay element array. And the delay time difference accuracy between the third delay element array and the fourth delay element array is output based on the number of stages required until the phase relationship between the delay signals of the fourth delay element array and the fourth delay element array is inverted. A time digital conversion circuit;
    A digital phase comparator comprising:
12. The first OR circuit is first output from the first delay element array immediately after the transition timing of the second pulse input signal by the OR operation of the output of the first holding circuit group. Extract the output timing of the delay signal,
    The second logical sum operation circuit performs the logical sum operation on the output of the second data holding circuit group and outputs the second pulse input signal to the output of the first logical sum operation circuit, 12. The digital phase comparator according to claim 11, wherein a signal maintaining a phase relationship with the output timing of the first delay signal immediately after the transition timing of the second pulse input signal is output.
13. In the first time digital conversion circuit,
    A holding circuit having a plurality of stages, wherein the second pulse input signal is used as a clock, and a first delay signal group sequentially delayed by the first delay element array is fetched in accordance with a transition timing of the second pulse input signal; A fourth holding circuit group including the output of the fourth holding circuit group as a digital value indicating a relative phase difference between the first pulse input signal and the second pulse input signal. The digital phase comparator according to claim 11.
14. In the first time digital conversion circuit,
    The output of the first holding circuit group is output as a digital value indicating a relative phase difference between the first pulse input signal and the second pulse input signal. Digital phase comparator.
15. The first time-to-digital conversion circuit has a transition of the second pulse input signal obtained by a retiming operation of the first pulse input signal instead of the second pulse input signal. 15. The digital phase comparator according to claim 11, wherein a third pulse input signal synchronized with timing is input.
16. A plurality of holding circuits for sequentially taking in the delay signals of the respective stages of the fourth delay element array of the second time digital conversion circuit according to the transition timing of the delay signals of the corresponding stages of the third delay element array; A fifth holding circuit group provided;
    A third OR operation circuit receiving the output of the fifth holding circuit group;
    A fourth OR operation circuit receiving the output of the third holding circuit group;
    In addition,
    A fifth delay element array in which a plurality of delay elements are connected in cascade, and an output of the third OR operation circuit is input to the first stage and a fifth delay signal group including a plurality of delay signals sequentially delayed is output; ,
    A delay element having a delay time different from that of the fifth delay element array is connected in a plurality of stages, and the output of the fourth logical sum operation circuit is input to the first stage, and a sixth delay signal is sequentially delayed. A sixth delay element array that outputs a delay signal group of:
    The delay signal of each stage of the fifth delay signal group from the fifth delay element array is the transition timing of the delay signal of the corresponding stage of the sixth delay signal group from the sixth delay element array. A sixth holding circuit group including a plurality of holding circuits, which are sequentially captured according to
    A third digital time conversion circuit comprising:
    12. The digital device according to claim 11, wherein an output of the sixth holding circuit group is used as a digital value indicating a relative phase difference between the first pulse input signal and the second pulse input signal. Phase comparator.
17. 12. The unit delay times of the fifth and sixth delay element arrays have a delay time difference smaller than the delay time difference between the third delay element array and the fourth delay element array. 15. The digital phase comparator according to any one of 1 to 14.
18. Extracting input / output signals of at least one delay element of the first delay element array;
    A fifth delay element array that sequentially delays the output signal by connecting a plurality of delay elements having the same delay time as the third delay element array;
    A delay element having the same delay time as the fourth delay element array, and a plurality of stages of cascaded delay elements, thereby delaying the input signal sequentially;
    A fifth holding circuit group including a plurality of holding circuits, which sequentially captures the delay output of the fifth delay element array in accordance with the transition timing of the delay output of the sixth delay element array;
    With
    The relative phase difference in the input / output signals of the delay elements in the first delay element array is
    Based on the number of stages required until the phase relationship between the delay output of the fifth delay element array and the delay output of the sixth delay element array is reversed, the fifth delay element array and the sixth delay element array 16. The digital phase comparator according to claim 11, further comprising a third time digital conversion circuit that outputs a digital value with a delay time difference accuracy of.
19. A first logic circuit that digitizes a digital value that is output from the first time digital conversion circuit and that indicates a relative phase difference between the first pulse input signal and the second pulse input signal;
    A second digital value that is output from the second time digital conversion circuit and that represents a relative phase difference between the output of the first OR operation circuit and the output of the second OR operation circuit; And the logic circuit of
    A third logic circuit that digitizes a digital value that is output from the third time digital conversion circuit and that indicates a relative phase difference in the input / output signals of the delay elements in the first delay element array;
    With
    Relative phase difference between the first pulse input signal and the second pulse input signal, which is quantified by the first logic circuit, based on the quantification results of the second and third logic circuits. The digital phase comparator according to claim 11, wherein the digital phase comparator is corrected.
20. The first time digital conversion circuit comprises:
    A sixth holding circuit group including a plurality of holding circuits that sequentially take in the fourth pulse input signal according to the transition timing of the delay signal using each delay signal of the first delay element array as a clock input;
    A third OR operation circuit for extracting a delay output timing first output immediately after a transition timing of the fourth pulse input signal by performing an OR operation on the output of the sixth data holding circuit group;
    A plurality of delay elements having the same delay time as the first delay element array are connected in cascade, and each delay signal of the seventh delay element array that sequentially delays the fourth pulse input signal is used as a clock input. A seventh data holding circuit group including a plurality of holding circuits that sequentially take in the first pulse input signal according to a signal transition timing;
    By performing a logical OR operation on a plurality of outputs from the seventh data holding circuit group, the fourth pulse input signal and the fourth pulse input are output with respect to the output of the third OR circuit. A fourth OR operation circuit that outputs a signal maintaining a phase relationship with the first delay output immediately after the signal transition timing;
    Further comprising
    Outputting a digital value indicating a relative phase difference between the first pulse input signal and the fourth pulse input signal with a delay time accuracy of the first delay element;
    An eighth delay element array for sequentially delaying the output of the third OR operation circuit by cascading a plurality of delay elements having the same delay time as the third delay element array;
    A delay element having the same delay time as that of the fourth delay element array, and a ninth delay element array for sequentially delaying the output of the fourth OR circuit by connecting a plurality of stages in cascade;
    An eighth holding circuit group including a plurality of holding circuits that captures the delay output of the eighth delay element array in accordance with the transition timing of the delay output of the ninth delay element array;
    The relative phase difference between the output of the third logical sum operation circuit and the output of the fourth logical sum operation circuit is expressed as the delay output of the eighth delay element array and the delay output of the ninth delay element array. A fourth time digital conversion circuit that outputs a digital value with a delay time difference accuracy between the eighth delay element array and the ninth delay element array based on the number of stages required until the phase relationship of
    The digital phase comparator according to claim 11, further comprising:
21. In the first time digital conversion circuit,
    A ninth stage including a holding circuit having a plurality of stages, wherein the fourth pulse input signal is used as a clock, and a delay output sequentially delayed by the first delay element array is fetched in accordance with a transition timing of the fourth pulse input signal; A holding circuit group, and outputs the output of the ninth holding circuit as a digital value indicating a relative phase difference between the first pulse input signal and the fourth pulse input signal. The digital phase comparator according to claim 19.
22. In the first time digital conversion circuit,
    The output of the sixth holding circuit group is output as a digital value indicating a relative phase difference between the first pulse input signal and the fourth pulse input signal. The digital phase comparator described.
23. The fourth pulse input signal is obtained from the retiming operation of the first pulse input signal by the inverted signal of the second pulse input signal, and is synchronized with the transition timing of the inverted signal of the second pulse input signal. The digital phase comparator according to any one of claims 19 to 21, wherein the digital phase comparator is a digital signal.
24. The first logic circuit comprises:
    A digital value indicating a relative phase difference between the first pulse input signal and the fourth pulse input signal output from the first time digital conversion circuit is further quantified;
    A digital value representing a relative phase difference between the output of the third logical sum operation circuit and the output of the fourth logical sum operation circuit, which is output from the fourth time digital conversion circuit; And the logic circuit of
    With
    Based on the quantification results of the third and fourth logic circuits, the relative positions of the first pulse input signal and the fourth pulse input signal that are quantified by the first logic circuit. The digital phase comparator according to any one of claims 19 to 22, wherein a phase difference is corrected.
25. Due to the relative phase difference between the first pulse input signal and the third pulse input signal and the relative phase difference between the first pulse input signal and the fourth pulse input signal, Obtaining a half period of the second pulse input signal;
    Normalizing a relative phase difference between the first pulse input signal and the third pulse input signal, or a relative phase difference between the first pulse input signal and the fourth pulse input signal 24. The digital phase comparator according to claim 23, wherein:
26. A first logic circuit that digitizes a digital value that is output from the first time digital conversion circuit and that indicates a relative phase difference between the first pulse input signal and the second pulse input signal;
    A second digital value that is output from the second time digital conversion circuit and that represents a relative phase difference between the output of the first OR operation circuit and the output of the second OR operation circuit; And the logic circuit of
    A third digital value that is output from the third time digital conversion circuit and that indicates a relative phase difference between the output of the third OR operation circuit and the output of the fourth OR operation circuit; And the logic circuit of
    The digital phase comparator according to claim 17, comprising:
27. The digital phase comparator according to any one of claims 11 to 25, wherein a delay element in the delay element array is an inverter.
28. The digital phase comparator according to any one of claims 11 to 26, wherein the holding circuit in the holding circuit group is a flip-flop.
29. A semiconductor device comprising the digital phase comparator according to any one of claims 1 to 28.

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