WO2010029672A1

WO2010029672A1 - Semiconductor device having electrostatic discharge protection circuit

Info

Publication number: WO2010029672A1
Application number: PCT/JP2009/003247
Authority: WO
Inventors: 藪洋彰; 荒井勝也; 甲上歳浩
Original assignee: パナソニック株式会社
Priority date: 2008-09-11
Filing date: 2009-07-10
Publication date: 2010-03-18
Also published as: US20100207163A1; JP2010067846A

Abstract

A semiconductor device includes a protected circuit and an electrostatic discharge protection circuit. The electrostatic discharge protection circuit includes semiconductor substrate (11) on which the following are formed: a first conductive type first well (12) and a second conductive type second well (13) which are formed in contact with each other; a first conductive type first impurities diffusion layer (21A) and a second conductive type impurities diffusion layer (21B) which are formed separately from each other in the first well (12); and a second conductive type second impurities diffusion layer (31A) and a first conductive type fourth impurities diffusion layer (31B) which are formed separately from each other in the second well (13). The second impurities diffusion layer (31A) and the third impurities diffusion layer (21B) are formed adjacent to each other while sandwiching an element separation region (15) formed to cross the boundary between the first well and the second well.

Description

Semiconductor device having electrostatic discharge protection circuit

The present invention relates to a semiconductor device including an electrostatic discharge protection circuit that protects a circuit to be protected from electrostatic discharge.

In recent years, semiconductor devices have been highly integrated in accordance with miniaturization and high density of elements. With higher integration, the resistance of semiconductor devices to electrostatic discharge (hereinafter referred to as “surge”) is decreasing. For example, there is a high possibility that elements such as an input circuit, an output circuit, and an internal circuit are destroyed or a performance of the element is deteriorated due to a surge entering from an external connection terminal. For this reason, in order to protect the input circuit, output circuit, input / output circuit or internal circuit from a surge, the semiconductor device is provided with an electrostatic discharge (Electro-Static Discharge: ESD) protection circuit connected to the external connection terminal. It has been.

The ESD protection circuit is required to have a high discharge capacity. In other words, it must have an amperage-order current capability with respect to a surge with an application time of several hundred nanoseconds or less and be capable of low impedance operation. On the other hand, from the viewpoint of manufacturing cost, it is required to reduce the occupation area of the ESD protection circuit. A thyristor (SCR) type ESD protection circuit is used as an ESD protection circuit that satisfies these requirements and can impart high electrostatic discharge tolerance (ESD tolerance) to a semiconductor device. (For example, see Patent Document 1).

In the conventional SCR type ESD protection circuit, as shown in FIG. 13, a P type semiconductor layer 144 is formed on a substrate, and an N type well 146 is formed in the P type semiconductor layer 144. In the N-type well 146, an N ⁺ region 150 and a P ⁺ region 148 are formed. An N ⁺ region 152 and a P ⁺ region 154 are formed in the P-type semiconductor layer 144. P ⁺ region 148 is connected to pad 112 and N ⁺ region 150 is connected to pad 112 to form a resistive connection between pad 112 and N-type well 146. N ⁺ region 152 and P ⁺ region 154 are grounded. The P ⁺ region 154 is connected to a resistance component formed by the P-type semiconductor layer 144.

When a surge enters from the pad 112, the SCR parasitic NPN transistor breaks down. As a result, a current flows through the base of the parasitic NPN transistor, and the collector-emitter becomes conductive. Thereby, the collector current of the parasitic NPN transistor becomes the base current of the parasitic PNP transistor, and the parasitic PNP transistor is turned on. By turning on the parasitic PNP transistor, positive feedback is generated that further promotes the conduction of the parasitic NPN transistor. Therefore, a low-impedance discharge path is formed between the pad 112 and the ground, and is maintained until the voltage becomes lower than the holding voltage of the SCR. As a result, the surge current is released to the ground, so that the internal circuit can be protected.

Japanese Patent Publication No. 5-065061

However, the conventional SCR type ESD protection circuit has a problem that the holding voltage of the SCR is very low. When the SCR holding voltage is lower than the normal operating voltage of the semiconductor device, latch-up occurs during normal operation. When latch-up occurs, a large current continues to flow between the power source and the ground, resulting in overcurrent breakdown.

¡In order to improve the latch-up tolerance, the SCR holding voltage needs to be higher than the normal operating voltage. As a method of increasing the holding voltage of the SCR, a method of reducing the current amplification factor of the parasitic transistor by widening the interval between the anode and the cathode of the SCR can be considered. However, when the distance between the anode and cathode of the SCR is increased, the occupied area of the SCR increases. Moreover, the malfunction that current capability falls or an impedance increases arises.

Another method for increasing the SCR holding voltage is to increase the area of the P ⁺ region formed in the P-type layer. Increasing the area of the P ⁺ region is expected to reduce the base resistance of the parasitic NPN transistor and increase the holding voltage. However, also in this case, the area occupied by the SCR increases.

An object of the present disclosure is to solve the above problems and to realize a semiconductor device including an electrostatic discharge protection circuit having high latch-up resistance and a small occupied area.

In order to achieve the above object, the present disclosure provides an electrostatic discharge protection circuit for a semiconductor device in which a second conductivity type impurity diffusion layer formed in a first conductivity type well and a second conductivity type well formed in a second conductivity type well. The conductive impurity diffusion layer is adjacent to the element isolation region.

Specifically, the exemplary semiconductor device is a semiconductor device including a protected circuit and an electrostatic discharge protection circuit that protects the protected circuit from electrostatic breakdown, and the electrostatic discharge protection circuit is provided on a semiconductor substrate. The first conductivity type first well and the second conductivity type second well formed in contact with each other, the first conductivity type first impurity diffusion layer formed in the first well and separated from each other, and the first well A second conductivity type third impurity diffusion layer, a second conductivity type second impurity diffusion layer and a first conductivity type fourth impurity diffusion layer formed separately from each other in the second well; The two impurity diffusion layers and the third impurity diffusion layer are formed adjacent to each other across an element isolation region provided across the boundary between the first well and the second well. , Connected to the first external connection terminal of the protected circuit, the second impurity diffusion layer and the fourth non-contact Things diffusion layer is characterized by being connected to the second external connection terminal of the protection circuit.

In the illustrated semiconductor device, the second impurity diffusion layer and the third impurity diffusion layer are adjacent to each other with the same conductivity type across the element isolation region provided across the boundary between the first well and the second well. have. For this reason, the base resistance of the parasitic NPN transistor of the thyristor can be reduced without increasing the size of the thyristor. Thereby, since the holding voltage of the thyristor can be increased, an electrostatic discharge protection circuit with excellent latch-up resistance can be realized.

In the exemplary semiconductor device, the first impurity diffusion layer is formed on the opposite side of the boundary between the first well and the second well with the third impurity diffusion layer interposed therebetween, and the fourth impurity diffusion layer is the second impurity diffusion layer. It may be formed on the opposite side of the boundary between the first well and the second well.

In the illustrated semiconductor device, the first impurity diffusion layer has a first protrusion protruding toward the boundary between the first well and the second well, and the second impurity diffusion layer includes the first well and the second well. You may have the 2nd convex part which protruded on the opposite side to the boundary.

In this case, a plurality of third impurity diffusion layers are formed spaced apart from each other in a direction parallel to the boundary between the first well and the second well, and the first protrusion is between the third impurity diffusion layers. A plurality of fourth impurity diffusion layers are formed at intervals in a direction parallel to the boundary between the first well and the second well, and the second protrusions are formed between the fourth impurity diffusion layers. It may be formed in a region between.

In the illustrated semiconductor device, the first conductivity type is N type, the second conductivity type is P type, and the voltage of the first external connection terminal is higher than the voltage of the second external connection terminal. Also good.

In this case, the first external connection terminal may be a power supply terminal or an input / output terminal, and the second external connection terminal may be a ground terminal. Further, the first external connection terminal may be a power supply terminal, and the second external connection terminal may be an input / output terminal.

In the illustrated semiconductor device, the first impurity diffusion layer may be connected to the first external connection terminal.

In this case, the electrostatic discharge protection circuit includes a first trigger circuit and a fifth impurity diffusion layer of the second conductivity type formed in the second well, and the first trigger circuit includes the first trigger circuit A trigger element in which the external connection terminal and the first terminal are connected and the second terminal is connected to the fifth impurity diffusion layer, and a resistance element connected between the second terminal of the trigger element and the second external connection terminal You may have.

Further, the first trigger circuit uses the first well as a collector at a voltage lower than a breakdown voltage of a parasitic transistor having the second well as a collector, the first well as a base, and a third impurity diffusion layer as an emitter. The base of the parasitic transistor having the second well as a base and the fourth impurity diffusion layer as an emitter may be electrically connected to the first external connection terminal.

In the exemplary semiconductor device, the electrostatic discharge protection circuit includes a second trigger circuit, and the second trigger circuit has the first impurity diffusion layer and the first terminal connected, and the second terminal is the second impurity diffusion. A trigger element connected to the layer and the fourth impurity diffusion layer, and a resistance element connected between the first terminal of the trigger element and the first external connection terminal may be included.

In this case, the second trigger circuit uses the second well at a voltage lower than the breakdown voltage of a parasitic transistor having the first well as a collector, the second well as a base, and a fourth impurity diffusion layer as an emitter. The base may be electrically connected between the base of the parasitic transistor having the collector, the first well as the base, and the third impurity diffusion layer as the emitter, and the second external connection terminal.

In the exemplary semiconductor device, the electrostatic discharge protection circuit includes a third trigger circuit, and the third trigger circuit has the first impurity diffusion layer and the first terminal connected, and the second terminal has the second impurity diffusion. The switching element may be connected to the layer and the fourth impurity diffusion layer, and the third terminal may be connected to the power supply terminal.

In this case, when the power supply terminal is in a floating state, the third trigger circuit includes a base of a parasitic transistor having the second well as a collector, the first well as a base, and a third impurity diffusion layer as an emitter. You may conduct | electrically_connect between 2nd external connection terminals.

According to the semiconductor device according to the present disclosure, it is possible to realize a semiconductor device including an electrostatic discharge protection circuit having high latch-up resistance and a small occupied area.

1A and 1B show an electrostatic discharge protection circuit according to the first embodiment, FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line Ib-Ib in FIG. is there. FIG. 2 is an equivalent circuit diagram showing the electrostatic discharge protection circuit according to the first embodiment. FIG. 3 is a graph showing a comparison between the current-voltage characteristics of the electrostatic discharge protection circuit according to the first embodiment and the current-voltage characteristics of a conventional electrostatic discharge protection circuit. FIG. 4 is a graph showing the relationship between the anode-cathode interval and the holding voltage in the electrostatic discharge protection circuit according to the first embodiment in comparison with the conventional electrostatic discharge protection circuit. 5A and 5B show a modification of the electrostatic discharge protection circuit according to the first embodiment, wherein FIG. 5A is a cross-sectional view, and FIG. 5B is an equivalent circuit diagram. FIG. 6 is a circuit diagram illustrating an example of a trigger element used in a modified example of the electrostatic discharge protection circuit according to the first embodiment. 7A and 7B show a modification of the electrostatic discharge protection circuit according to the first embodiment. FIG. 7A is a cross-sectional view, and FIG. 7B is an equivalent circuit diagram. FIG. 8 is a circuit diagram illustrating an example of a trigger element used in a modified example of the electrostatic discharge protection circuit according to the first embodiment. 9A and 9B show a modification of the electrostatic discharge protection circuit according to the first embodiment, wherein FIG. 9A is a cross-sectional view, and FIG. 9B is an equivalent circuit diagram. FIG. 10 is a circuit diagram illustrating an example of a trigger element used in a modification of the electrostatic discharge protection circuit according to the first embodiment. FIG. 11 is a plan view showing an electrostatic discharge protection circuit according to the second embodiment. 12A to 12D show an electrostatic discharge protection circuit according to the second embodiment of the present invention, and FIGS. 12A to 12D show the XIIa-XIIa line and the XIIb-XIIb line in FIG. 11, respectively. , XIIc-XIIc line and XIId-XIId line. FIG. 13 is a cross-sectional view showing an electrostatic discharge protection circuit according to a conventional example.

(First embodiment)
FIGS. 1A and 1B are ESD protection circuits of the semiconductor device according to the first embodiment. FIG. 1A shows a planar configuration, and FIG. 1B is a cross section taken along line Ib-Ib in FIG. The configuration is shown.

As shown in FIG. 1, the ESD protection circuit of the first embodiment is an SCR type ESD protection circuit. An N-type first well 12 and a P-type second well 13 are formed in contact with each other on a semiconductor substrate 11 such as a silicon substrate. In the first well 12, an N-type first impurity diffusion layer 21A and a P-type third impurity diffusion layer 21B are formed. In the second well 13, a P-type second impurity diffusion layer 31A and an N-type fourth impurity diffusion layer 31B are formed.

The first impurity diffusion layer 21A, the third impurity diffusion layer 21B, the second impurity diffusion layer 31A, and the fourth impurity diffusion layer 31B are separated from each other by the element isolation region 15. The third impurity diffusion layer 21B and the second impurity diffusion layer 31A are formed adjacent to each other with an element isolation region 15 provided across the boundary between the first well 12 and the second well 13 interposed therebetween. Yes. The first impurity diffusion layer 21A is formed on the opposite side of the boundary between the first well 12 and the second well 13 with the third impurity diffusion layer 21B interposed therebetween, and the fourth impurity diffusion layer 31B is the second impurity diffusion layer. It is formed on the opposite side of the boundary between the first well 12 and the second well 13 with the layer 31A interposed therebetween.

The first impurity diffusion layer 21A and the third impurity diffusion layer 21B are connected to a first external connection terminal 17 of a protected circuit (not shown) formed in another region of the semiconductor substrate 11. The second impurity diffusion layer 31A and the fourth impurity diffusion layer 31B are connected to the second external connection terminal 18 of the protected circuit. The first external connection terminal 17 is, for example, an input / output terminal, and the second external connection terminal 18 is, for example, a ground terminal.

FIG. 1 shows an example in which the first external connection terminal 17 is an input / output terminal and the second external connection terminal 18 is a ground terminal. However, any terminal may be used as long as the voltage of the first external connection terminal 17 is higher than the voltage of the second external connection terminal 18. For example, the first external connection terminal 17 may be an input terminal or an output terminal that performs only one of input and output. Further, even if the first external connection terminal 17 is a power supply terminal and the second external connection terminal 18 is a ground terminal, the first external connection terminal 17 is a first power supply terminal and the second external connection terminal The connection terminal may be a second power supply terminal whose voltage is lower than that of the first power supply terminal.

With this configuration, as shown in FIG. 2, an ESD protection circuit in which a thyristor (SCR) 41 is connected between the first external connection terminal 17 of the protected circuit and the ground is formed. The thyristor 41 is equivalent to a parasitic PNP transistor 42 and a parasitic NPN transistor 43 whose base and collector are connected to each other. As shown in FIG. 1B, the parasitic PNP transistor 42 has a P-type third impurity diffusion layer 21B as an emitter, an N-type first well 12 as a base, and a P-type second well 13 as a collector. To do. The parasitic NPN transistor 43 has the N-type fourth impurity diffusion layer 31B as an emitter, the P-type second well 13 as a base, and the N-type first well 12 as a collector.

When a surge enters the first external connection terminal 17, the parasitic NPN transistor 43 breaks down, and the collector current of the parasitic NPN transistor 43 flows through the N-type first well 12. By this collector current and the resistance component R1 of the first well 12, the emitter base of the parasitic PNP transistor 42 is forward-biased, and the parasitic PNP transistor 42 becomes conductive. When the parasitic PNP transistor 42 is turned on, the collector current of the parasitic PNP transistor 42 flows through the P-type second well 13. The conduction of the parasitic NPN transistor 43 is promoted by the collector current and the resistance component R2 and the resistance component R3 of the second well. Accordingly, positive feedback is applied to the circuit, and a low-impedance discharge path is formed between the third impurity diffusion layer 21B that is the anode of the thyristor and the fourth impurity diffusion layer 31B that is the cathode of the thyristor. As a result, the surge current is released to the second external connection terminal, which is a ground terminal, so that the protected circuit can be protected.

In order to increase the holding voltage of the thyristor 41, it is effective to reduce the base resistance of the parasitic NPN transistor 43 and make the parasitic NPN transistor 43 less conductive. The base resistance of the parasitic NPN transistor 43 is determined by the values of the resistance component R2 and the resistance component R3 shown in FIG.

The value of the resistance component R2 becomes smaller as the distance between the boundary between the first well 12 and the second well 13 and the second impurity diffusion layer 31A is shorter when the conditions such as the impurity concentration are the same. The value of the resistance component R3 decreases as the area of the second impurity diffusion layer 31A increases.

On the other hand, the current capability of the thyristor 41 becomes higher when the interval between the anode which is the emitter of the parasitic PNP transistor 42 and the cathode which is the emitter of the parasitic NPN transistor 43 is narrowed. That is, from the viewpoint of current capability, it is preferable to narrow the distance between the third impurity diffusion layer 21B and the fourth impurity diffusion layer 31B.

The conventional thyristor places importance on current capability, forms a P-type impurity diffusion layer of an N-type well on the boundary side between the N-type well and the P-type well, and forms an N-type impurity diffusion layer of the P-type well as an N-type well and a P-type well. It is formed on the boundary side with the mold well. That is, the P-type impurity diffusion layer of the N-type well and the N-type impurity diffusion layer of the P-type well are formed adjacent to each other with the boundary between the N-type well and the P-type well interposed therebetween.

In this case, it is conceivable to increase the holding voltage by decreasing the value of the resistance component R3 by increasing the area of the P-type impurity diffusion layer of the P-type well. However, since the size of the thyristor is limited, the effect of reducing the value of the resistance component R3 is limited. Further, since the contribution of the value of the resistance component R2 is large, the value of the base resistance of the parasitic NPN transistor cannot be greatly reduced.

In the ESD protection circuit according to the first embodiment, the P-type second impurity diffusion layer 31A has a P-type sandwiching the element isolation region 15 provided across the boundary between the first well 12 and the second well 13. Adjacent to the third impurity diffusion layer 21B. In other words, of the N-type first impurity diffusion layer 21A and the P-type third impurity diffusion layer 21B formed in the first well 12, the P-type third impurity diffusion layer 21B is closer to the first well 12. Of the P-type second impurity diffusion layer 31A and the N-type fourth impurity diffusion layer 31B formed in the second well 13, the P-type second impurity diffusion layer 31B is formed at a position close to the boundary with the second well 13. The second impurity diffusion layer 31 A is formed at a position closer to the boundary between the first well 12 and the second well 13. Therefore, the value of the resistance component R2 serving as the base resistance of the parasitic NPN transistor 43 is made smaller than that of a conventional thyristor in which the P-type impurity diffusion layer of the N-type well and the N-type impurity diffusion layer of the P-type well are adjacent to each other. be able to. Therefore, as shown in FIG. 3, the holding voltage can be made higher than the normal operating voltage of the semiconductor device to prevent the occurrence of latch-up.

FIG. 4 shows the relationship between the gap between the anode and the cathode and the holding voltage. When the interval between the anode and the cathode is widened, the amplification voltage is lowered, so that the holding voltage can be increased. Even in the conventional thyristor in which the P-type impurity diffusion layer of the N-type well and the N-type impurity diffusion layer of the P-type well are adjacent to each other, the P-type impurity diffusion layer of the N-type well serving as the anode and the N of the P-type well serving as the cathode The holding voltage increases by increasing the distance from the type impurity diffusion layer. However, in this case, the distance from the boundary between the N-type well and the P-type well to the P-type impurity diffusion layer of the P-type well is also increased. For this reason, since the value of the resistance component R2 increases, the effect of increasing the holding voltage is small. In addition, the size of the thyristor is also increased.

On the other hand, in the present embodiment, the second impurity diffusion layer 31A is formed on the boundary side between the first well 12 and the second well 13 rather than the fourth impurity diffusion layer 31B. Therefore, even if the distance between the third impurity diffusion layer 21B serving as the anode and the fourth impurity diffusion layer 31B serving as the cathode is increased, the value of the resistance component R2 hardly increases. In addition, since the contribution of the resistance component R2 to the holding voltage is large, even when the distance between the anode and the cathode is narrow, a holding voltage much higher than that of the conventional thyristor can be realized. That is, the ESD protection circuit of the present embodiment can realize an ESD protection circuit that is small in size and hardly causes latch-up.

The ESD protection circuit of this embodiment may be provided with a trigger circuit that reduces the snapback voltage at which the thyristor is turned on. By providing the trigger circuit, the turn-on voltage can be lowered without lowering the holding voltage of the thyristor.

The trigger circuit may be a circuit that makes the base of the parasitic NPN transistor 43 and the first external connection terminal 17 conductive at a voltage lower than the breakdown voltage of the parasitic PNP transistor 42, for example.

Specific examples are shown in FIGS. 5 (a) and 5 (b). FIG. 5A shows a cross-sectional configuration of an ESD protection circuit to which the first trigger circuit 51 is connected, and FIG. 5B shows a circuit configuration of the ESD protection circuit. The first trigger circuit 51 includes a trigger element 51A and a voltage adjusting resistance element 51B. The first terminal 51a of the trigger element 51A is connected to the first external connection terminal 17, and the second terminal 51b is connected to the P-type fifth impurity diffusion layer 31C formed in the P-type second well 13. At the same time, it is connected to the second external connection terminal 18 with a resistance element 51B interposed therebetween. The fifth impurity diffusion layer 31C is formed on the opposite side of the boundary between the first well 12 and the second well 13 with the second impurity diffusion layer 31A and the fourth impurity diffusion layer 31B interposed therebetween.

That is, the trigger element 51 A is connected between the first external connection terminal 17 and the second well 13 that is the base of the parasitic NPN transistor 43. The trigger element 51A is turned on at a voltage lower than that of the parasitic PNP transistor 42. Therefore, when a surge enters the first external connection terminal 17, the trigger element 51 A is conducted before the thyristor 41. When the trigger element 51A becomes conductive, a current flows through the resistance element 51B, and the base of the parasitic NPN transistor 43 is floated above the ground level due to a current resistance (IR) drop. As a result, the base and emitter of the parasitic NPN transistor 43 are forward biased, and the parasitic NPN transistor 43 becomes conductive. After the parasitic NPN transistor 43 is turned on, the surge current is released to the ground in the same manner as when the first trigger circuit 51 is not provided.

As the trigger element 51A, for example, a MOS (metal-oxide-semiconductor) transistor may be used as shown in FIGS. 6 (a) and 6 (b). When an N-type MOS transistor is used, the gate electrode is connected to the second terminal 51b as shown in FIG. 6A, and when a P-type MOS transistor is used, as shown in FIG. 6B. The gate electrode is connected to the first terminal 51a. The voltage at which the thyristor 41 is turned on by the first trigger circuit 51 can be set by the threshold value of the trigger element 51A, which is a MOS transistor, and the value of the resistance element 51B.

The trigger circuit may be a circuit that conducts between the base of the parasitic PNP transistor 42 and the ground at a voltage lower than the breakdown voltage of the parasitic NPN transistor 43.

Specific examples in this case are shown in FIGS. 7 (a) and 7 (b). FIG. 7A shows a cross-sectional configuration of the ESD protection circuit, and FIG. 7B shows a circuit configuration of the ESD protection circuit. The second trigger circuit 52 includes a trigger element 52A and a voltage adjusting resistance element 52B. The first terminal 52 a of the trigger element 52 A is connected to the N-type first impurity diffusion layer 21 A formed in the N-type first well 12, and the second terminal 52 b is connected to the second external connection terminal 18. . Furthermore, the first terminal 52a of the trigger element 52A is connected to the first external connection terminal 17 with the resistance element 52B interposed.

That is, the trigger element 52A is connected between the first well 12 which is the base of the parasitic PNP transistor 42 and the ground. The trigger element 52A is turned on at a voltage lower than that of the parasitic NPN transistor 43. Therefore, when a surge enters the first external connection terminal 17, the trigger element 52 A becomes conductive before the thyristor 41. When the trigger element 52A is turned on, a current flows through the resistance element 52B, and the base-emitter of the parasitic PNP transistor 42 is forward-biased by a current resistance (IR) drop. Thereby, the parasitic PNP transistor 42 becomes conductive. When the parasitic PNP transistor 42 is turned on, the parasitic NPN transistor 43 is turned on, and the surge current is released to the ground in the same manner as when the second trigger circuit 52 is not provided. Also in this case, the trigger element 52A may be a MOS transistor as shown in FIG. When a P-type MOS transistor is used, the gate electrode is connected to the first terminal 52a as shown in FIG. 8A, and when an N-type MOS transistor is used, as shown in FIG. 8B. The gate electrode is connected to the second terminal 52b.

In addition, when the first external connection terminal 17 is an input / output terminal of a protected circuit, the trigger circuit may be activated by utilizing the fact that the power supply terminal is floating when a surge enters. A specific configuration in this case may be as shown in FIG. FIG. 9A shows a cross-sectional configuration of the ESD protection circuit, and FIG. 9B shows a circuit configuration of the ESD protection circuit. The third trigger circuit 53 has a trigger element 53A. The first terminal 53a of the trigger element 53A is connected to the first impurity diffusion layer 21A, and the second terminal 53b is connected to the second external connection terminal 18 and grounded. The third terminal 53 c is connected to the power supply terminal 19. The trigger element 53A is an element that conducts between the first terminal 53a and the second terminal 53b when the third terminal 53c becomes floating.

Normally, since the power supply voltage is applied to the power supply terminal 19, the trigger element 53A is in an off state. However, in the floating state where the power supply voltage is not applied to the power supply terminal 19, the trigger element 53A is turned on. Therefore, when a surge enters the first external connection terminal 17 when the power supply terminal 19 is in a floating state, the trigger element 53A that is in an on state is turned on, and the base emitter of the parasitic PNP transistor 42 is forward-biased. Transistor 42 conducts. When the parasitic PNP transistor 42 is turned on, the parasitic NPN transistor 43 is turned on, and the surge current is released to the ground in the same manner as when the third trigger circuit 53 is not provided. In this case, the trigger element 53A may be a MOS transistor as shown in FIG. When a P-type MOS transistor is used, the gate electrode and the substrate region are connected to the power supply terminal 19 as shown in FIG.

In the first embodiment, the first impurity diffusion layer 21A and the fourth impurity diffusion layer 31B are N-type, and the second impurity diffusion layer 31A and the third impurity diffusion layer 21B are P-type. However, the first impurity diffusion layer 21A and the fourth impurity diffusion layer 31B may be P-type, and the second impurity diffusion layer 31A and the third impurity diffusion layer 21B may be N-type.

In the first trigger circuit 51 and the second trigger circuit 52, an example in which a MOS transistor and a resistance element are formed is shown, and in the third trigger circuit 53, an example in which a MOS transistor is formed. Any circuit may be used as long as it is a circuit. For example, a diode or the like may be used instead of the MOS transistor.

(Second Embodiment)
Hereinafter, a second embodiment will be described with reference to the drawings. 11 and FIGS. 12A to 12D are ESD protection circuits according to the second embodiment, FIG. 11 shows a plan configuration, and FIGS. 12A to 12D are XIIa in FIG. The cross-sectional structures of the -XIIab line, XIIb-XIIb line, XIIc-XIIc line and XIId-XIId line are shown. 11 and 12, the same components as those in FIG.

As shown in FIGS. 11 and 12, the ESD protection circuit of the second embodiment is an SCR type ESD protection circuit. The first impurity diffusion layer 21 A formed in the N-type first well 12 has a first protrusion 21 a that protrudes to the boundary side between the first well 12 and the second well 13. The second impurity diffusion layer 31 A formed in the P-type second well 13 has a second protrusion 31 a that protrudes on the opposite side of the boundary between the first well 12 and the second well 13. A plurality of the third impurity diffusion layers 21B and the fourth impurity diffusion layers 31B are formed at intervals from each other, and the first protrusions 21a are formed in the regions between the third impurity diffusion layers 21B. A second convex portion 31a is formed in a region between the four impurity diffusion layers 31B.

With this configuration, the effective well resistance between the first well 12 and the second well 13 is reduced. As a result, the base resistances of the parasitic PNP transistor 42 and the parasitic NPN transistor 43 can be further reduced, and the holding voltage can be increased. Therefore, it is possible to realize an ESD protection circuit that is less prone to latch-up.

The area of the third impurity diffusion layer 21B that is the anode of the thyristor 41 and the area of the fourth impurity diffusion layer 31B that is the cathode of the ESD protection circuit of the present embodiment are smaller than those of the ESD protection circuit of the first embodiment. For this reason, the current capability is reduced as compared with the ESD protection circuit of the first embodiment. However, there is usually no problem because the current capability for releasing the surge is sufficient.

In addition, although the example which forms the 1st convex part 21a and the 2nd convex part 31a was shown, you may form only the 1st convex part 21a and the 2nd convex part 31a. In this case, each of the third impurity diffusion layer 21B and the fourth impurity diffusion layer 31B may be one.

As with the ESD protection circuit of the first embodiment, a trigger circuit may be provided in the ESD protection circuit of the second embodiment. As a result, the snapback voltage can be lowered without changing the holding voltage.

In the second embodiment, the first impurity diffusion layer 21A and the fourth impurity diffusion layer 31B are N-type, and the second impurity diffusion layer 31A and the third impurity diffusion layer 21B are P-type. However, the first impurity diffusion layer 21A and the fourth impurity diffusion layer 31B may be P-type, and the second impurity diffusion layer 31A and the third impurity diffusion layer 21B may be N-type. In this case, a third protrusion is formed in the third impurity diffusion layer 21B so as to protrude to the opposite side of the boundary between the first well 12 and the second well 13, and the first well 12 is formed in the fourth impurity diffusion layer 31B. What is necessary is just to form the 4th convex part which protruded in the boundary side of the 2nd well 13 and.

The semiconductor device according to the present disclosure can realize an electrostatic discharge protection circuit that has high latch-up resistance and a small occupation area, and is useful as a semiconductor device including an electrostatic discharge protection circuit that protects a protected circuit from electrostatic breakdown. It is.

DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 12 1st well 13 2nd well 15 Element isolation region 17 1st external connection terminal 18 2nd external connection terminal 19 Power supply terminal 21A 1st impurity diffusion layer 21B 3rd impurity diffusion layer 21a 1st convex part 31A Second impurity diffusion layer 31B Fourth impurity diffusion layer 31C Fifth impurity diffusion layer 31a Second protrusion 41 Thyristor 42 Parasitic PNP transistor 43 Parasitic NPN transistor 51 First trigger circuit

51A Trigger element

51B Resistance element 51a First terminal 51b Second terminal 52 Second trigger circuit

52A Trigger element

52B Resistance element 52a First terminal 52b Second terminal 53 Third trigger circuit 53A Trigger element 53a First terminal 53b Second terminal 53c Third terminal

Claims

Semiconductor devices
A semiconductor device comprising a protected circuit and an electrostatic discharge protection circuit that protects the protected circuit from electrostatic breakdown,
The electrostatic discharge protection circuit is:
A first well of a first conductivity type and a second well of a second conductivity type formed in contact with each other on a semiconductor substrate;
A first impurity diffusion layer of a first conductivity type and a third impurity diffusion layer of a second conductivity type formed separately from each other in the first well;
A second conductivity type second impurity diffusion layer and a first conductivity type fourth impurity diffusion layer formed separately from each other in the second well;
The second impurity diffusion layer and the third impurity diffusion layer are formed adjacent to each other across an element isolation region provided across the boundary between the first well and the second well,
The third impurity diffusion layer is connected to a first external connection terminal of the protected circuit;
The second impurity diffusion layer and the fourth impurity diffusion layer are connected to a second external connection terminal of the protected circuit.
The semiconductor device according to claim 1,
The first impurity diffusion layer is formed on the opposite side of the boundary between the first well and the second well with the third impurity diffusion layer interposed therebetween.
The fourth impurity diffusion layer is formed on the opposite side of the boundary between the first well and the second well with the second impurity diffusion layer interposed therebetween.
The semiconductor device according to claim 1,
The first impurity diffusion layer has a first protrusion protruding to a boundary side between the first well and the second well,
The second impurity diffusion layer has a second convex portion that protrudes on the opposite side of the boundary between the first well and the second well.
The semiconductor device according to claim 3.
A plurality of the third impurity diffusion layers are formed spaced apart from each other in a direction parallel to a boundary between the first well and the second well,
The first protrusion is formed in a region between the third impurity diffusion layers,
A plurality of the fourth impurity diffusion layers are formed at intervals in a direction parallel to the boundary between the first well and the second well,
The second convex portion is formed in a region between the fourth impurity diffusion layers.
The semiconductor device according to claim 1,
The first conductivity type is N-type;
The second conductivity type is P type,
The voltage of the first external connection terminal is higher than the voltage of the second external connection terminal.
The semiconductor device according to claim 5,
The first external connection terminal is a power supply terminal or an input / output terminal,
The second external connection terminal is a ground terminal.
The semiconductor device according to claim 5,
The first external connection terminal is a power supply terminal;
The second external connection terminal is an input / output terminal.
The semiconductor device according to claim 1,
The first impurity diffusion layer is connected to the first external connection terminal.
The semiconductor device according to claim 8,
The electrostatic discharge protection circuit includes a first trigger circuit and a second impurity diffusion layer of a second conductivity type formed in the second well,
The first trigger circuit includes:
A trigger element in which the first external connection terminal and the first terminal are connected, and the second terminal is connected to the fifth impurity diffusion layer;
A resistance element connected between the second terminal of the trigger element and the second external connection terminal;
The semiconductor device according to claim 9.
The first trigger circuit includes the first well at a voltage lower than a breakdown voltage of a parasitic transistor having the second well as a collector, the first well as a base, and the third impurity diffusion layer as an emitter. As a collector, the second well as a base, and the base of a parasitic transistor having the fourth impurity diffusion layer as an emitter, and the first external connection terminal.
The semiconductor device according to claim 1,
The electrostatic discharge protection circuit has a second trigger circuit,
The second trigger circuit includes:
A trigger element having a first terminal connected to the first impurity diffusion layer and a second terminal connected to the second impurity diffusion layer and the fourth impurity diffusion layer;
A resistor element connected between the first terminal of the trigger element and the first external connection terminal;
The semiconductor device according to claim 11,
The second trigger circuit includes the second well at a voltage lower than a breakdown voltage of a parasitic transistor having the first well as a collector, the second well as a base, and the fourth impurity diffusion layer as an emitter. As a collector, the first well as a base, and the base of a parasitic transistor having the third impurity diffusion layer as an emitter, and the second external connection terminal.
The semiconductor device according to claim 1,
The electrostatic discharge protection circuit has a third trigger circuit,
In the third trigger circuit, the first impurity diffusion layer and the first terminal are connected, the second terminal is connected to the second impurity diffusion layer and the fourth impurity diffusion layer, and the third terminal is a power supply terminal. Is a switch element connected to
The semiconductor device according to claim 13,
The third trigger circuit includes a base of a parasitic transistor having the second well as a collector, the first well as a base, and the third impurity diffusion layer as an emitter when the power supply terminal is in a floating state. And the second external connection terminal.