WO2009158679A3 - Shader interfaces - Google Patents

Shader interfaces

Info

Publication number
WO2009158679A3
WO2009158679A3 PCT/US2009/048960 US2009048960W WO2009158679A3 WO 2009158679 A3 WO2009158679 A3 WO 2009158679A3 US 2009048960 W US2009048960 W US 2009048960W WO 2009158679 A3 WO2009158679 A3 WO 2009158679A3
Authority
WO
Grant status
Application
Patent type
Prior art keywords
shader
registers
level
hlsl
complex
Prior art date
Application number
PCT/US2009/048960
Other languages
French (fr)
Other versions
WO2009158679A2 (en )
WO2009158679A8 (en )
Inventor
Michael V. Oneppo
Craig C. Peeper
Andrew L. Bliss
John L. Rapp
Mark M. Lacey
Original Assignee
Microsoft Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/005General purpose rendering architectures
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/44Encoding
    • G06F8/443Optimisation
    • G06F8/4441Reducing the execution time required by the program code
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/448Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4488Object-oriented
    • G06F9/449Object-oriented method invocation or resolution
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/54Interprogram communication
    • G06F9/541Interprogram communication via adapters, e.g. between incompatible applications
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/20Processor architectures; Processor configuration, e.g. pipelining
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/50Lighting effects
    • G06T15/80Shading
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2200/00Indexing scheme for image data processing or generation, in general
    • G06T2200/28Indexing scheme for image data processing or generation, in general involving image processing hardware

Abstract

Allocation of memory registers for shaders by a processor is described herein. For each shader, registers are allocated based on the shader's level of complexity. Simpler shader instances are restricted to a smaller number of memory registers. More complex shader instances are allotted more registers. To do so, developers' high level shading level (HLSL) language includes template classes of shaders that can later be replaced by complex or simple versions of the shader. The HLSL is converted to bytecode that can be used to rasterize pixels on a computing device.
PCT/US2009/048960 2008-06-27 2009-06-26 Shader interfaces WO2009158679A8 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/163,734 2008-06-27
US12163734 US8581912B2 (en) 2008-06-27 2008-06-27 Dynamic subroutine linkage optimizing shader performance

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN 200980124880 CN102077251B (en) 2008-06-27 2009-06-26 Shader interfaces
EP20090771210 EP2289050A4 (en) 2008-06-27 2009-06-26 Shader interfaces

Publications (3)

Publication Number Publication Date
WO2009158679A2 true WO2009158679A2 (en) 2009-12-30
WO2009158679A3 true true WO2009158679A3 (en) 2010-05-06
WO2009158679A8 true WO2009158679A8 (en) 2010-11-18

Family

ID=41445370

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/048960 WO2009158679A8 (en) 2008-06-27 2009-06-26 Shader interfaces

Country Status (4)

Country Link
US (3) US8581912B2 (en)
EP (1) EP2289050A4 (en)
CN (1) CN102077251B (en)
WO (1) WO2009158679A8 (en)

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US9245371B2 (en) * 2009-09-11 2016-01-26 Nvidia Corporation Global stores and atomic operations
US8756590B2 (en) 2010-06-22 2014-06-17 Microsoft Corporation Binding data parallel device source code
US8677186B2 (en) 2010-12-15 2014-03-18 Microsoft Corporation Debugging in data parallel computations
US8997066B2 (en) 2010-12-27 2015-03-31 Microsoft Technology Licensing, Llc Emulating pointers
US8539458B2 (en) 2011-06-10 2013-09-17 Microsoft Corporation Transforming addressing alignment during code generation
US9378560B2 (en) * 2011-06-17 2016-06-28 Advanced Micro Devices, Inc. Real time on-chip texture decompression using shader processors
US9495722B2 (en) * 2013-05-24 2016-11-15 Sony Interactive Entertainment Inc. Developer controlled layout
US9779535B2 (en) 2014-03-19 2017-10-03 Microsoft Technology Licensing, Llc Configuring resources used by a graphics processing unit
US9766954B2 (en) 2014-09-08 2017-09-19 Microsoft Technology Licensing, Llc Configuring resources used by a graphics processing unit
KR20160033479A (en) 2014-09-18 2016-03-28 삼성전자주식회사 Graphic processing unit and method of processing graphic data using the same
US20160225118A1 (en) * 2015-02-02 2016-08-04 Microsoft Technology Licensing, Llc Optimizing compilation of shaders
US9881351B2 (en) 2015-06-15 2018-01-30 Microsoft Technology Licensing, Llc Remote translation, aggregation and distribution of computer program resources in graphics processing unit emulation
US9786026B2 (en) 2015-06-15 2017-10-10 Microsoft Technology Licensing, Llc Asynchronous translation of computer program resources in graphics processing unit emulation
CN105374070A (en) * 2015-12-11 2016-03-02 中国航空工业集团公司西安航空计算技术研究所 3D graphic processing algorithm modeling simulation method

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See also references of EP2289050A4 *

Also Published As

Publication number Publication date Type
US8581912B2 (en) 2013-11-12 grant
US20170039754A1 (en) 2017-02-09 application
US20140063029A1 (en) 2014-03-06 application
CN102077251A (en) 2011-05-25 application
WO2009158679A2 (en) 2009-12-30 application
EP2289050A4 (en) 2012-01-11 application
EP2289050A2 (en) 2011-03-02 application
US9824484B2 (en) 2017-11-21 grant
US9390542B2 (en) 2016-07-12 grant
CN102077251B (en) 2014-01-08 grant
US20090322751A1 (en) 2009-12-31 application
WO2009158679A8 (en) 2010-11-18 application

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