WO2009156952A1 - Electrical device control - Google Patents

Electrical device control Download PDF

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Publication number
WO2009156952A1
WO2009156952A1 PCT/IB2009/052702 IB2009052702W WO2009156952A1 WO 2009156952 A1 WO2009156952 A1 WO 2009156952A1 IB 2009052702 W IB2009052702 W IB 2009052702W WO 2009156952 A1 WO2009156952 A1 WO 2009156952A1
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WO
WIPO (PCT)
Prior art keywords
current
master unit
unit
crossing
slave unit
Prior art date
Application number
PCT/IB2009/052702
Other languages
French (fr)
Other versions
WO2009156952A4 (en
Inventor
Shaul Barak
Original Assignee
B.S.N Pro Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to IL192462A priority Critical patent/IL192462D0/en
Priority to IL192462 priority
Application filed by B.S.N Pro Ltd. filed Critical B.S.N Pro Ltd.
Publication of WO2009156952A1 publication Critical patent/WO2009156952A1/en
Publication of WO2009156952A4 publication Critical patent/WO2009156952A4/en

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Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J13/00Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
    • H02J13/0006Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network for single frequency AC networks
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J13/00Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
    • H02J13/00006Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment
    • H02J13/00007Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment using the power network as support for the transmission
    • H02J13/00009Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment using the power network as support for the transmission using pulsed signals
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR
    • H05B47/00Circuit arrangements for operating light sources in general, i.e. where the type of the light source is not relevant
    • H05B47/10Controlling the light source
    • H05B47/175Controlling the light source by remote control
    • H05B47/185Controlling the light source by remote control via power line carrier transmission
    • Y02B70/3283
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04SSYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S20/00Management or operation of end-user stationary applications or the last stages of power distribution; Controlling, monitoring or operating thereof
    • Y04S20/20End-user application control systems
    • Y04S20/242Home appliances
    • Y04S20/246Home appliances the system involving the remote operation of lamps or lighting equipment

Abstract

A method and apparatus for controlling electrical for communicating over AC mains wires, comprising: providing a master unit and at least one slave unit; connecting the master unit to at least one wire of AC mains; connecting a slave unit to at least two wires of an AC mains; and communicating between the master unit and the at least one slave unit by a plurality of data elements in a half cycle of an AC current about the zero-crossing while substantially maintaining the current waveform.

Description

ELECTRICAL DEVICE CONTROL

FIELD OF THE INVENTION

The present invention relates to method and apparatus for controlling electrical devices. Some embodiments relate to control over electric distribution lines.

BACKGROUND OF THE INVENTION

Controlling electrical devices such as lamps is known in the industry as demonstrated by the lighting and ballast control apparatus using standards interfaces such as 1-lOV, DSI (Digital Signal Interface, trademark of Tridonic Bauelmente GmbH) or DALI (Digital Addressable Lighting Interface, IEC 62386 / NEMA 243- 2004).

As such interfaces typically require dedicated control wiring, employment of standard or regular electricity distribution lines for communication with the light control apparatus have been proposed. For example, US patents 5055746, 5068576, 4523128 and 4408185 relate to control transfer over a pair of AC wires, and, US patents 6225759, 4746809 and 6727662 relate to control transfer over a single phase line. The disclosures of the above citations are incorporated herein by reference.

In many cases, as for instance is typical in Europe and Israel, the contacts for electrical fixtures such as lamps comprise both a phase wire and a neutral wire of the AC distribution, whereas the switch (such as a wall switch) connects or disconnect the phase wire only. Using a single phase line in the switch for providing control to the fixtures may be advantageous since no additional wiring is required.

Typically, the control mechanism over electric distribution lines employ semiconductors switches, such as thyristors, silicon controlled rectifiers (SCR), Triacs or similar devices. Such switches typically have limitations regarding power transmission as they dissipate about 0.7% of the power, which may heat up the control apparatus, especially in the limited space of a wall switch socket. Additionally, the switching time of such switches of about 0.5ms may limit the amount of control data in an AC cycle of 20ms (50Hz) or 16.6ms (60Hz) of the AC current, particularly when the relatively short zero-crossing zone of the AC current is used for control data. Furthermore, thyristors, Triacs and such switches are generally switched off when no voltage is applied at the terminals thereof, potentially further limiting the amount of data that can be transferred during half of an AC cycle. SUMMARY OF THE INVENTION

A general, non-limiting, aspect of the invention relates to controlling an electrical device or appliance by a master unit via a slave unit communicating over wires of an AC mains while substantially maintaining the AC waveform.

An aspect of some embodiments of the invention relates to a method for communicating a plurality of data elements in a half cycle of an AC current between a master unit and at least one slave unit connected by at least one wire of AC mains while substantially maintaining the current waveform. An aspect of some embodiments of the invention relates to a system for communicating a plurality of data elements in a half cycle of an AC current between a master unit and at least one slave unit connected by at least one wire of AC mains while substantially maintaining the current waveform.

An aspect of some embodiments of the invention relates to a method for communicating a plurality of data elements in a half cycle of an AC current between a master unit and at least one slave unit connected by at least one wire of AC mains by uniquely using an electronic switch with faster switching time and/or lower power dissipation than a thyristor or other SCR type switch such as triac.

An aspect of some embodiments of the invention relates to a system for communicating a plurality of data elements in a half cycle of an AC current between a master unit and at least one slave unit connected by at least one wire of AC mains by uniquely using an electronic switch with faster switching time and/or lower power dissipation than a thyristor or other SCR type switch such as triac.

An aspect of other embodiments of the invention relates to a kit comprising a master control unit and at least one slave unit configured to communicate therebetween by a plurality of data elements about the zero-crossing of AC mains current. Optionally, the kit comprises an electrical device that interfaces with a slave unit. In some embodiments, the slave unit is integrated with the device.

In the specification and claims, unless otherwise specified, the term 'substantially maintaining the current waveform' denotes modifying only a minor (low) current for only a minor period at times sufficiently close to the current zero-crossing to still enable handling the current whereby the AC current waveform and/or power are practically maintained or only negligibly affected. In the specification and claims, unless otherwise specified, referring to minor or low current is relative to the AC current RMS and a reference to a minor period is relative to the AC cycle period.

In the specification and claims, unless otherwise specified, the term 'about the zero-crossing' denotes a time sufficiently close to the zero-crossing of the AC current (and/or voltage) to still allow modulating (modifying) the low current.

In the specification and claims, unless otherwise specified, the term 'data elements' denotes data having information equivalent to a plurality of bits, such as a plurality of on-off current pulses.

In the specification and claims, unless otherwise specified, the terms 'master unit' and 'slave units' denote apparatus comprising electrical and/or electronic components configured, inter alia, for communication therebetween.

In the specification and claims, unless otherwise specified, the terms 'wire' and 'line' in electrical context denote an electrical conductor connected to (shared by) a plurality of devices (e.g. phase wire, control line). The communication is carried out by modulating the low current to a plurality of data elements about the zero-crossing of the current.

Typically, without limiting, the low current about the current zero-crossing is in the order of a few percent of the RMS current and is effected (e.g. modified or modulated) within a period of about 0.1ms (or up to 0.5ms or lms) in a half AC cycle wherein a typical AC cycle is in the order of 16ms (60Hz) to 20ms (50Hz).

In some embodiments of the invention, the at least one wire of an AC mains comprises a single wire. In some embodiments, the single wire comprises the phase wire. Optionally, the single wire is a phase wire in a 3-phase power supply. Typically, without limiting, the slave unit is connected to at least both phase and neutral wires, since otherwise no current can flow in the AC electric system.

In some embodiments of the invention, the communication is unidirectional from the master unit to the slave unit. Optionally or alternatively, the communication is bidirectional between the master unit and the slave unit, where the master unit initiates the communication. The communication is synchronized between the master unit and the slave unit according to the zero-crossing of the AC current, and the communication is carried out by modulating the low current about the zero-crossing.

In particular, non limiting, embodiments the electronic switch with faster switching time and/or lower power dissipation than a thyristor or other SCR type switch is or comprises a MOSFET transistor. Optionally, the switch comprises newly developed devices, such as GaN based transistor.

In some embodiments, the lower power dissipation (relative to thyristor or other SCR type switch) allows building a system smaller than a system based on thyristor or other SCR type switches. In some embodiments of the invention, the electronic switch has a sufficiently low impedance or resistance that dissipates sufficiently low heat that allows placing the transmitter and/or the receiver in a closed compartment (e.g. a wall or ceiling socket) under power such as of a typical household power.

In some embodiments of the invention, the master unit (hereinafter also referred to as a 'transmitter') sends control data to the receiver. The slave unit (hereinafter also referred to as a 'receiver') intercepts the control data and regulates and/or controls an electric device or appliance.

Examples of electrical devices or appliances include a gas discharge lamp electronic ballast, an incandescent lamp, an LED, a light or LED array, a motor, a heater or other devices, such as an electric door or a computer. In some embodiments, the device comprises an apparatus or unit or units that control another device or appliance, such as an electronic ballast that controls a fluorescent lamp.

In some embodiments of the invention, the appliance interfaces and/or interacts with the slave unit by receiving and/or providing data to the slave unit. Optionally, the interaction is according to a standard protocol such as DALI or DSI or PWM or 1-lOV or other protocol such as PWM. Optionally or alternatively, the appliance is of a proprietary design and/or manufacturing. Optionally or alternatively, in some embodiments, the protocol is proprietary. Optionally, in some embodiments, the receiver and an appliance are integrated or manufactured such as to comprise an appliance configured to communicate with the master unit by modulating the current into a plurality of data elements about the zero-crossing of the AC current.

The receiver, according to the control data sent by the transmitter, controls the appliance such as by turning it on or off, adjusting or regulating the appliance power or duty cycle or operation pattern or sequence of light or color. Optionally, one receiver controls a plurality of appliances. Optionally or alternatively, the receiver comprises a plurality of receivers, each controlling one or more appliances.

In some embodiments of the invention, the receiver sends data back to the transmitter. For example, the data sent by the receiver comprises acknowledgment of the command (control) to the receiver ('handshake'). Optionally or alternatively, the data comprises, for example, a notification of the status or mode of operation of the appliance, or any other information such as a request for additional data from the transmitter.

In some embodiments, the transmitter is operated under manual control, such as a switch or potentiometer. Optionally or alternatively, the transmitter is operated automatically, such as by a clock or environmental condition (e.g. ambient light or temperature detectors). Optionally or alternatively, the transmitter is operated remotely such as by a wireless or infra-red or ultrasound communication from another device.

In some embodiments, the receiver operates without transmitter control. For example, in the absence of a transmitter (or communication thereof) the receiver turns the appliance on or off, optionally proceeded with a notification such as a LED or light blinking or a sound (e.g. buzzer).

In some embodiments of the invention, the slave unit comprises a plurality of sub-units (optionally referred to herein as slave units) communicating with a single master unit. Optionally, each slave unit interfaces with one or more appliances.

According to an aspect of some embodiments of the present invention there is provided a method for communicating over AC mains wires, comprising: (a) providing a master unit and at least one slave unit; (b) connecting the master unit to at least one wire of AC mains; (c) connecting a slave unit to at least two wires of an AC mains; and (d) communicating between the master unit and the at least one slave unit by a plurality of data elements in a half cycle of an AC current about the zero-crossing while substantially maintaining the current waveform.

In some embodiments, connecting the master unit to at least one wire of AC mains comprises connecting to a single phase wire. In some embodiments, connecting the at least one slave unit to at least two wires of AC mains comprises connecting to phase and neutral wires. In some embodiments, the communicating is unidirectional from the master unit to a slave unit. In some embodiments, the communicating is bidirectional between the master unit and a slave unit. In some embodiments, the communicating between the master unit and a slave unit comprises synchronization by mutually detecting the AC current zero-crossing. In some embodiments, the communicating comprises modulating the current to a plurality of data elements about the AC current zero-crossing. In some embodiments, the at least one slave unit comprises a plurality of slave units. In some embodiments, modulating the current comprises affecting the current within less than lms. In some embodiments, modulating the current comprises affecting the current within less than 0.5ms. In some embodiments, modulating the current comprises affecting the current within about 0.1ms.

According to an aspect of some embodiments of the present invention there is provided a method for communicating over AC mains wires, comprising: (a) providing a master unit and at least one slave unit; (b) connecting the master unit to at least one wire of AC mains; (c) connecting a slave unit to at least two wires of an AC mains; and (d) communicating between the master unit and the at least one slave unit by a plurality of data elements in a half cycle of an AC current about the zero-crossing while substantially maintaining the current waveform by using an electronic switch with at least one of faster switching time or lower power dissipation than a SCR-based switch.

In some embodiments, the SCR-based switch is one of a thyristor or a triac. In some embodiments, the electronic switch with at least one of faster switching time or lower power dissipation than a SCR-based switch comprises at least one MOSFET transistor. In some embodiments, connecting the master unit to at least one wire of AC mains comprises connecting to a single phase wire. In some embodiments, the communicating comprises modulating the current to a plurality of data elements about the AC current zero -crossing.

According to an aspect of some embodiments of the present invention there is provided a system for communicating between a master unit and at least one slave unit, comprising: (a) a master unit, comprising a circuitry configured for communication, connected to at least one wire of AC mains; and (b) at least one slave unit, comprising a circuitry configured for communication, connected to at least two wires of an AC mains, wherein a circuitries comprised in the master unit and the at least one slave units are configured for communications therebetween by a plurality of data elements in a half cycle of an AC current while substantially maintaining the current waveform.

In some embodiments, the master unit is connected to a single phase wire. In some embodiments, the circuitry of the master unit comprises at least one MOSFET transistor. In some embodiments, the circuitry of a slave unit comprises at least one MOSFET transistor. In some embodiments, the circuitry of the master unit and the circuitry of a slave unit are configured for bidirectional communications therebetween. In some embodiments, the circuitry of the master unit and the circuitry of a slave unit are configured to modulate the current to a plurality of data elements about the current zero-crossing. In some embodiments, the circuitry of the master unit and the circuitry of a slave unit are configured to detect modulated current about the current zero-crossing. In some embodiments, the circuitry of the master unit and the circuitry of a slave unit are configured to synchronize the communications by detecting the AC-current zero-crossing. In some embodiments, a slave unit interacts with at least one device. In some embodiments, a slave unit controls at the least one device based on the plurality of data from the master unit. In some embodiments, a slave unit is configured to provide status information to the master unit by a plurality of data elements.

According to an aspect of some embodiments of the present invention there is provided a system for communicating between a master unit and at least one slave unit, comprising: (a) a master unit, comprising circuitry configured for communication, connected to at least one wire of an AC mains; and (b) at least one slave unit, comprising circuitry configured for communication, connected to at least two wires of an AC mains, wherein the circuitry comprised in the master unit and the at least one slave units are configured for communication therebetween by a plurality of data elements in a half cycle of an AC current while substantially maintaining the current waveform by using an electronic switch with at least one of faster switching time or lower power dissipation than a SCR-based switch.

In some embodiments, the master unit is connected to a single phase wire. In some embodiments, the SCR-based switch is one of a thyristor or a triac. In some embodiments, the switch with at least one of faster switching time or lower power dissipation than a SCR-based switch comprises at least one MOSFET transistor.

According to an aspect of some embodiments of the present invention there is provided a kit, comprising: (a) a master unit configured for connection to at least a phase wire of AC mains; and (b) at least one slave unit configured for connection to two wires of AC mains, wherein the master unit and the at least one slave units are configured for communications therebetween by a plurality of data elements about the zero crossing of an AC current while substantially maintaining the current waveform.

In some embodiments, the kit further comprises at least one device configured to interface with the at least one slave unit. In some embodiments, the at least one unit is integrated with at least one device. In some embodiments, the device is at least one of comprises or connected or interacts with an electrical appliance. In some embodiments, connection to at least a phase wire of AC mains comprises connection to single phase wire. In some embodiments, the device comprises an electronic ballast of a gas discharge lamp. In some embodiments, the device comprises an electric motor or a controller thereof.

BRIEF DESCRIPTION OF THE DRAWINGS The invention may be understood upon reading of the following detailed description of non-limiting exemplary embodiments thereof, with reference to the following drawings.

Identical or duplicate or equivalent or similar structures, elements, or parts that appear in more than one drawing are generally labeled with the same reference numeral, optionally with an additional letter or letters for reference to particular objects.

Dimensions of components and features shown in the figures are chosen for convenience or clarity of presentation and are not necessarily shown to scale or true perspective. For clarity, some structures are not shown or shown only partially or without perspective, and duplicate or equivalent or similar parts may not be repeatedly labeled.

Fig. IA schematically illustrates a connection relationship of an appliance controlled by a transmitter via a receiver, in accordance with an embodiment of the invention;

Fig. IB schematically illustrates a connection relationship of a plurality of appliances controlled by a transmitter via a plurality of receivers, in accordance with an embodiment of the invention;

Fig. 2 is a flowchart outlining a sequence of actions for operating a system comprising a transmitter on an AC phase line and a receiver that controls an appliance, in accordance with an embodiment of the invention; Fig. 3 schematically illustrates an AC voltage (and current) waveform indicating regions about the zero-crossing where current is modulated, in accordance with an embodiment of the invention;

Fig. 4 is an electronic circuit schematic drawing of a transmitter, in accordance with an embodiment of the invention; Fig. 5 is an electronic circuit schematic drawing of a receiver, in accordance with an embodiment of the invention;

Fig. 6A is a flowchart for managing the transmitter circuitry of Fig. 4 by the processor thereof, in accordance with an embodiment of the invention; Fig. 6B is a flowchart of complementary actions of the flowchart of Fig. 6A for sending data, in accordance with an embodiment of the invention;

Fig. 6C is a flowchart of complementary actions of the flowchart of Fig. 6A for receiving data, in accordance with an embodiment of the invention; Fig. 6D is a flowchart of complementary actions of the flowchart of Fig. 6A for preparatory routines, in accordance with an embodiment of the invention;

Fig. 7A is a flowchart for managing the receiver circuitry of Fig. 5 by the processor thereof, in accordance with an embodiment of the invention;

Fig. 7B is a flowchart of complementary actions of the flowchart of Fig. 7A for receiving data, in accordance with an embodiment of the invention;

Fig. 7C is a flowchart of complementary actions of the flowchart of Fig. 7A for sending data, in accordance with an embodiment of the invention;

Fig. 7D is a flowchart of complementary actions of the flowchart of Fig. 7A for operational routines, in accordance with an embodiment of the invention; Fig. 8 illustrates time related events about the zero-crossing, in accordance with an embodiment of the invention;

Fig. 9 schematically illustrates a connection relationship of an appliance controlled by a transmitter using both phase and natural wires via a receiver, in accordance with an embodiment of the invention; Fig. 1OA schematically illustrates a kit comprising a transmitter, a receiver and an optional appliance, in accordance with an embodiment of the invention; and

Fig. 1OB schematically illustrates a kit comprising a transmitter and a receiver integrated with an appliance, in accordance with an embodiment of the invention.

DESCRIPTION OF EMBODIMENTS OF THE INVENTION

The following description relates to some non-limiting examples of embodiments of the invention.

The non-limiting section headings used herein are intended for convenience only and are not necessarily limiting the scope of the invention. Connection block diagrams

Fig. IA schematically illustrates a connection relationship 100 of an appliance 112 controlled by a transmitter 102 via a receiver 104. Appliance 112, such as a fluorescent lamp, is regulated by a coupled device 110, such as electronic ballast. Coupled device 110 comprises an electrical and/or electronic interface configured to receive control signals according to which appliance 112 is regulated and/or to provide status information on the state of coupled device 110 and/or appliance 112.

Coupled device 110 (hereinafter 'ballast') receives control signals from receiver 104 wherein the coupled device and receiver are connected to AC mains phase wire 106 and neutral wire 108. Receiver 104 receives control data for ballast 110 from transmitter 102 which is connected on phase wire 106 only that is shared by receiver 104.

In some embodiments of the invention, receiver 104 and ballast 110 are integrated, optionally in a single unit. Fig. IB schematically illustrates a connection relationship 120 of a plurality of appliances 112 regulated by a plurality of ballasts 110 and controlled by a transmitter 102 connected to a phase wire 106 via a plurality of receivers 104. It should be noted that Fig. IB illustrates a combination of two methods for connecting and controlling ballasts 110 by a single transmitter: (i) one receiver controls a plurality of ballasts (typically identical or compatible) as illustrated by a receiver 104a and ballasts 110a and 110b, and (ii) a plurality of receivers controlling a plurality of ballasts as illustrated by an additional receiver 104b and ballast 110c. Further combinations and variations of the methods can be readily appreciated.

Referring still to Figs. 1A-1B, transmitter 104 operates as, or is connected to, a switch 114 on phase wire 106 such that, once connected, transmitter 104 sends control data to receiver 104 on phase wire 106, where receiver 104 consequently sends control signals to ballast 110 to regulate appliance 112. Optionally, receiver 104 sends back to transmitter 102 data (hereinafter 'status data') related to the operation of receiver 104 and/or ballast 110 and/or appliance 112. Preferably, without limiting, transmitter 102 and receiver 104 each comprise at least one processor (not shown) having a program, though alternative electronic apparatus may be used. In the specification and claims, unless otherwise specified, the term 'processor' denotes any apparatus operable according to a predefined and/or alterable plan. The processor, having input and output ports and at least one timer, manages the operation of transmitter 102 and receiver 104. In the specification and claims, unless otherwise specified, the term 'receiver' (or 'slave unit') denotes one or more receivers (such as 104 or 104a and 104b). Basic flowchart

Fig. 2 is a flowchart outlining a sequence of actions for operating a system comprising a transmitter on an AC phase line and a receiver that optionally controls an appliance via a ballast. In discussing the flowchart of Fig. 2 reference is also made to Figs. 1A-1B.

When switch 114 is closed (202) alternating current flows in phase wire 106 and alternating voltage is present between phase wire 106 and neutral wire 108. As the current begins to flow (e.g. switch 114 closes) the processor of transmitter 102 is supplied a voltage (e.g. by dropping the current on an impedance) and initializes (226). Concurrently as voltage is supplied to receiver 104 (between phase wire 106 and neutral wire 108) the processor of receiver 104 is initializes (204).

Once the processor of transmitter 102 operates, transmitter 102 detects when the current diminishes to substantially zero or just when the current begins to increase after the zero current is crossed and the processor marks (stores) the event time, and the next zero-crossing is determined accordingly (228), such that the period of the AC current cycle is determined (or period of a half cycle) (230). Optionally, in order to determine the AC cycle period more accurately, transmitter 102 determines and calculates a plurality of current zero-crossings.

Concurrently and similarly, the processor of receiver 104 determines and marks two or more consecutive voltage zero-crossings (206) and the voltage AC period is determined (208). Thus, transmitter 102 and receiver 104 are synchronized by the zero-crossing event for communication therebetween.

In the next half cycle (reversed current polarity) transmitter 102 senses (by the processor timing and/or by other components) when the current becomes sufficiently low before the current zero-crossing (232) and begins to modulate (see below) the current until the current is too low and too near (time wise) the zero-crossing.

Concurrently with transmitter 102, in the next half cycle receiver 104 intercepts the current modulation and the processor of receiver 104 interprets the message (212), and receiver 104, optionally, provides control signal or signals to ballast 110 (214). According to coordinated timing and/or programs of transmitter 102 and receiver 104, receiver 104 modulates the current in phase wire 106 providing status data to transmitter 102 (216), and transmitter 102 interprets the modulation similarly as receiver 104 interprets the modulation from transmitter 104. After transmitter 102 detects the current zero-crossing, transmitter 102 determines a low current sufficient for modulation (236) and transmitter 102 modulates the current (238) where receiver 104 intercepts the modulation and, optionally, modulates the current as status data for the transmitter, as described above (218-224). The current is modulated according to a setting at transmitter 102. For example, transmitter 102 is installed in a fluorescent light 112 wall switch socket with a dimming knob (or slider, etc.) that is connected to a potentiometer. Changing the knob's position changes the potentiometer resistance, which is sensed by transmitter 102 (e.g. the transmitter's processor measures a voltage drop via an A/D port thereof). Consequently, transmitter 102 sends control data indicating the lighting level by modulating the current.

As another example, transmitter 102 sends, by modulating the current, query messages to receiver 104 in order to check the status of lamp 112 or ballast 110, and receiver 104 notifies transmitter 102 (e.g. by stored data or interface with ballast 110), by modulating the current, about the status of lamp 112, such as light level or working hours.

In some embodiments of the invention, the sequence of events (206-224 and 228-238) described above is repeated as long as the switch 114 is closed. Optionally the communication between transmitter 102 and receiver 104 is performed periodically. Optionally or alternatively, the communication between transmitter 102 and receiver 104 is performed responsive to a changed setting at transmitter 102 (e.g. dimming knob is moved). Optionally, the determination of the AC cycle timing (208, 230) is performed repeatedly (as the AC frequency may somewhat vary), or periodically, or once after switch 114 is connected, relying on the AC period substantial consistency. The current modulation is performed by letting the current flow or blocking the current (on-off pulses modulation) or by modulating the current flow periods (PWM modulation) or by other methods such as by the number of current pulses or by other methods as known in the art.

The modulation, as mapped to (or interpreted as) logical data bits, is according to a communication protocol, either a standard protocol as known in the art or a modified or proprietary protocol. Preferably, without limiting, the protocol comprises error detection and elimination such as parity bit and/or CRC check or redundant bits for error elimination optionally as known in the art. As transmitter 102 may control a plurality of receivers (e.g. 104a and 104b), where each one may interface with a plurality of appliances (e.g. ballasts 110a and 110b connected to corresponding lamps 112), a multi-drop (or other multi-station) protocol may be used where each receiver and/or ballast (or lamp) has a unique ID (address). The control message sent by transmitter 102 comprises the intended appliance address and only the appliance with the same address acts upon the control message. Optionally a broadcast message is sent with a non-specified address, for example, to dim all lights to the same level. Similarly, when receiver 104 sends status data, the message comprises the receiver (or appliance) address such that transmitter 102 can determine the responding device.

It should be noted that the zero-crossing of the current and voltage occurs at each half of AC cycle when the AC polarity changes, so that transmitter 102, and optionally receiver 104, modulate the current and communicate with each other at each 'side' (time-wise) of the zero-crossing. A unique feature of at least some embodiments of the present invention is that modulation at each side of the zero-crossing comprises an equivalent of a plurality of data bits (e.g. a plurality of current pulses). Possibly, in some cases, the modulation at one or more half cycles comprises only a part of a message, and receiver 102 (e.g. the processor thereof) stores the message part for later completion and interpretation and subsequently provides control signal or signals to ballast 110. Similarly transmitter 102 handles part of a message from the receiver 104. Optionally, the order of operation may be varied. For example, operation 216 may precede operation 214.

In order to distinguish between current modulation from transmitter 102 to receiver 104 and vise versa, receiver 104 provides a current sufficiently larger than the current transmitter 102 uses for modulation, so that transmitter 102 can detect the communication from receiver 104. AC waveform

Fig. 3 schematically illustrates an AC voltage (and current) waveform 300 indicating regions 312 about the zero-crossing 310 where current is modulated.

Waveform 300 schematically illustrates a 230V AC voltage with a positive and negative peaks of +235V 302 and 304, respectively. At about voltage (or respective period time) of +15 V 306 and 308, respectively, the current modulation is carried out at either side (time-wise) of the zero-crossing 310, as shown by regions 312. Transmitter and receiver circuitry

Fig. 4 is an electronic circuit schematic drawing 400 of a transmitter operating responsive to a potentiometer position and Fig. 5 is an electronic circuit schematic drawing of a receiver, in accordance with exemplary embodiments of the invention. The principal sections of the drawings are indicated by arrows and the components are labeled as customary in electronic schematics. The circuitry and components are used as a non limiting embodiment of the invention and the circuitry may be varied and other and/or additional components may be used to implement an embodiment according to the invention. The cited values are given as non limiting examples and other values may be used in variant embodiments. For clarity and brevity, the description refers to subsequent notes. In the discussion that follows, reference is made also to Fig. IA as a reference example.

Transmitter circuitry

Apart for some supporting components that are discussed below the circuit is essentially symmetric with respect to the alternating current in the phase wire 106, A processor (PIC 16F688), having several I/O ports and A/D input ports, manages the overall operation of the transmitter. When symmetric operation is involved, the relevant components are generally referred to as a pair.

Voltage A voltage is dropped on resistances (such as Rl or other resistanc as described below) and zener diodes Dl/2 limit the voltage across the phase endpoints (to about +15V). A protection switch SCl (e.g. SCR or Triac) turns on beyond a voltage constraint (-+16V) and shunts the current (e.g. switch-on when the processor is still off or in the case of a circuitry malfunction). The voltage limits are necessary for circuit elements such as MOSFETS Ql/2 and Q3A/B that can operate only within certain voltage levels (e.g. 30V).

In order to provide DC power for the circuit elements, some of the alternating current is rectified by diodes D3/4 and diode of MOSFETS Ql/2 (note 2), and the rectified current charges capacitor Cl (note 3). The voltage of the capacitor is fed into a voltage regulator (Ul) that provides a stabilized DC power supply (5V).

The voltage level is monitored on R2-R3 and sensed by an A/D port of the processor (port AN2). If the voltage is determined to be too low (e.g. below 13V), then the processor takes measures to use the receiver load to draw a current to charge the capacitor (note 1 and note 3).

Current path

The principal current path of phase wire 106 is provided by MOSFETS Ql/2 that are set to either a cutoff state (switch off) or to a short state (switch on). In the switched on state, the low impedance of Ql/2 (5mΩ each) dissipates low power relative to other devices such as Triacs (for example, a 1OA current dissipates only IW while a Triac may dissipate about 10W). Ql/2 are switched on and off by the respective gates that are controlled by the processor (port RC2). Zero-crossing and modulation interval

The transmitter sends control data - such as current on-off modulation periods - in an interval when the AC current is very low but still present (when the voltage is near OV, close to the zero-crossing, such as <12V, which is near zero relative to the mains voltage such as 230V AC). In order to identify the adequate conditions for data transmission - and synchronization with the receiver such as 104 - a sufficiently accurate determination of the current zero-crossing event is necessary.

The zero-crossing is determined by comparators U2A/B in two phases, coarse and fine. Some alternative variations are discussed below (note 6).

Resistors R10-R14 and R15-R19 provide for comparators U2A and U2B, respectively, voltage dividers that apply small positive bias for a better (less ambiguous) determination of the zero-crossing (note 7). The processor sets MOSFETS Q3A/B in a short state (by port RA5) and the voltage (proportional to current) is measured between the end points of phase wire 206 across R8-R9 (2xRx) (note 4 and note 9).

During most of the AC cycle (large current) Ql/2 are shortened (e.g. allowing current flow to ballast 110 and lamp 112) so that current practically (i.e. mostly) flows through the low impedance of Ql/2 (2x5mΩ) in parallel to the relatively high resistance of 2xRx (2xlΩ). Due to the low impedance of Ql/2 the voltage drop is small and the detection sensitivity is low (coarse phase).

For example, with a peak current of 1OA, Ql/2 and Q3A/B are shortened, and the voltage drop on 2xRx is about 9OmV, but when the current diminishes to IA, the voltage drop on 2xRx is about 9mV, which is about the sensitivity of comparators

U2A/B (note 5). That is, with Ql/2 in the on state, comparators U2A/B cannot distinguish a voltage due to a current of about IA or less. As the voltage drops down near zero, either of U2A or U2B detects an approximate zero-crossing, (each for a respective half cycle), and comparators U2A/B trigger the processor (ports ICSPD and RCO, respectively.

Responsive to the triggering, the processor shuts off Ql/2 while Q3A/B are still on, so that the low current drops a voltage only on R8-R9 (2xRx) pair (saving power loss on Ql/2). The resistance of 2xRx is 2 orders of magnitude higher than the impedance of Ql/2 (2Ω vs. lOmΩ), so that comparators U2A/B can detect a zero- crossing more accurately and trigger the processor accordingly. For example, with a marginal current for the coarse phase of IA, the voltage drop now is 2 V, and the detection threshold is about 5mA (note 5) which gives a high accuracy of the zero- crossing detection (in the order of about lOμs). As the measurement is performed near the current (and voltage) zero-crossing, the power dissipation of the current through 2xRx is negligible.

Similarly, with an adequate offset, comparators U2A/B can detect in the AC current conditions of pre-zero-crossing. That is, a current corresponding to a certain voltage (e.g. 12V) which allows a time interval to modulate the current.

Once the zero-crossing timing is obtained, an alternative for the coarse zero detection may be used. Namely, since the frequency of the AC voltage is fairly stable, a practical accurate estimate of a 1/2 cycle period can be determined by the processor. Once the processor decides that a 1/2 cycle is about to reach zero current (and voltage), the processor shuts off Ql/2, so that the now low current drops on R8-R9 (2xRx) pair for precise determination of the modulation interval. Alternatively, the processor can find out the time for the modulation interval and the comparators U2A/B are used only for accurate zero-crossing detections for updating the AC cycle periods. In the alternative method where the processor determines the approach of the zero-crossing, MOSFETS Q3A/B may be switched off during most of a half cycle, until the measurement near the zero-crossing is required.

After the modulation interval is over the processor switches on MOSFETS Ql/2 for the next half cycle. Current modulation

Once the modulation interval starts, the processor switches off MOSFEts Ql/2 and sets MOSFEts Q3A/B to an off state or on state during, or within, a preset period (e.g. 40μs), such that each state represents a certain bit value. For example, an on state (current flows) represents 1 and a period with no current represents the complementary value of 0. The data bits are transmitted (sensed by the receiver) before and/or after the zero-crossing (but not near the zero-crossing where there is no, or negligible, current to modulate). The control bit pattern is set by the processor according to the dimming level obtained from voltage on a potentiometer SPl, which is sensed by the processor A/D port (port AN7). To increase the information of the data, instead of using only on-off modulation, the data may be modulated by particular waveforms. Also, other schemes may be used such as PWM.

After the data transmission, and/or when the current increases, the processor sets MOSFETs Q1/Q2 to an on state to let the power current reach the lamp. The processor may activate Q1/Q2 to an on state responsive to either timing or by voltage level sensing with the comparators. Comparators U3A/B are used to receive status data (e.g. handshake) from the receiver as discussed below.

Receiver circuitry The right (final) stages of circuit 500 are essentially symmetric with respect to the alternating voltage between phase wire 106 and neutral wire 108 and the current in the wires. A processor (PIC 16F688) manages the overall operation of the receiver.

Voltage

The receiver is connected to phase wire 206 from the transmitter and to a neutral wire 208. Diodes D6-D9 rectify the AC voltage. Capacitor C4 smoothes the rectified ripple, and diode D5 ensures that the capacitor is drained so that the voltage of C4 follows the rectified waveform (rather than retains the high voltage).

The rectified voltage is provided to a voltage reducer U5 that supplies 12VDC to (a) the circuit (e.g. bipolar transistors) and (b) to a voltage regulator U6 that supplies a stable 5VDC to the processor and other components (e.g. comparators).

A zener diode DlO, with a break down voltage of 30V, divides the operation of the circuit into two (rectified) voltage regions: (a) above 30V, where most of the mains power is supplied to ballast 110 and lamp 112, and (b) below 30V, which is close to the AC zero-crossing, where the receiver cooperates with the transmitter communications. High voltage (over 30V)

When the voltage between phase wire 106 and neutral wire 108 is above 30V, zener diode DlO conducts and a current flows into the base of transistor Q4 (by the 12V supply). Transistor Q4 begins to conduct whereby the emitter-collector voltage drops to around 0.3V. The low voltage (-0.3V) on Q4 drives MOSFETS Q8/9 to cutoff state.

Low voltage (under 30V)

When the voltage is below 30V, zener diode DlO is in a cutoff, whereby transistor Q4 is also in cutoff, and therefore the collector or transistor Q4 is under a voltage of 12V, which drives the gates of MOSFETS Q8/9 to conduction. The current through MOSFETS Q8/9 drops a voltage on R25/26 (Ry). If the voltage on Ry is above 0.7V, transistors Q6/7 begin to conduct in parallel to Ry to keep the voltage at 0.7V by decreasing the voltage on the gates of MOSFETS Q8/9. If the voltage on Ry is below 0.7V, MOSFETS Q8/9 are cutoff whereby increasing the voltage on the gates of MOSFETS Q8/9, and all the current through MOSFETS Q8/9 passes through Ry (note 10), which raises the voltage to 0.7V where transistors Q6/7 begin to conduct. Thus, the voltage on Ry is a constant 0.7V and the current in the mains wires is a constant 0.7V/Ry (note 8). When no load exists (or a load with a reactive component such as small capacitor or inductor), this constant current is used by the transmitter to detemine the point of the transmitter zero-crossing time, and may be used to charge capacitor Cl of the power supply of the transmitter (note 1). This constant current (0.7V/Ry) is denoted as It.

Detecting zero-crossing and data from the transmitter

When the AC voltage between phase wire 106 and neutral wire 108 reaches zero volts (zero-crossing), there is no current in the wires 106 and 108 (including It which is, after all, driven by the rectified AC voltage). Comparators U7A/B are set by respective voltage dividers R31-R34 and R35-R38 to detect when both inputs are zero, an event which is detected by the processor (ports ICSPC and RCO, respectively). The processor marks (stores) the zero-crossing events, at least initially (e.g. startup) and can determine the period the cycles of the AC voltage.

When in a modulation interval (low voltage) data are expected from the transmitter around the zero-crossing as determined by the processor. If there is no current in the mains wires (the transmitter breaks the phase line), comparators U7A/B trigger the processor which determines the state as a logic value (e.g. 0) and if there is current and comparators U7A/B do not trigger the processor, the processor determines the state as the complementary value (e.g. 1). The receiver as a transmitter

As coordinated with the transmitter (respective processors timing), the transmitter avoids sending data in the modulation interval and awaits data from the receiver (status data). The status data comprises status of the receiver (e.g. transmission acknowledgment or ballast or appliance status).

In order to send data back to the transmitter, the receiver processor (port RA2) sets MOSFETs Q10A/B to conduction. Q10A/B are in series with R27-R28 (Ry/2) and in parallel with Q8/9 and R25-R26 (Ry), so that Q10A/B are under a fixed voltage of 0.7V. Therefore, the current (ignoring the low resistance of MOSFETS QIOA/B) is 0.7/(Ry/3) = 3 x It, (e.g. ~60mA) and is denoted as Ir. A current of Ir denotes a logic value (e.g. 1) and absence of Ir current is the complementary logic value.

The transmitter as a receiver

Reverting to Fig. 4 (transmitter circuit schematics), comparators U3A/B (under an adequate voltage divider) are set to detect a zero-crossing at a current such as 4OmA. Thus, when the transmitter opens a window (determines a time interval) for a status data from the receiver (transmitter not modulating the current, coordinated with the receiver), if current Ir is detected (over 4OmA such as 6OmA) it denotes a logic value (e.g. 1) and when no current is received the transmitter interprets it as the complementary value (e.g. 0). Comparators U2A/B (for zero-crossing detection) are not affected by the relatively high current Ir (relative to It) as comparators U2A/B will not produce an output for zero-crossing (or the processor may ignore them as it is now in a reception window).

The receiver as a controller

Once the receiver has decoded (interpreted) data from the transmitter, the receiver can control a device, e.g. fluorescent electronic ballast 110. For example, if the ballast supports a standard protocol such as DALI or DSI the processor can send commands to the ballast in a digital protocol via output ports. Optionally or alternatively, the processor can use an analog output port to send commands by a 1-lOV protocol or PWM coding. Optionally, proprietary ballast may be used with a proprietary interface.

Optionally, the receiver may notify the transmitter on the status of the lamp. Optionally or alternatively, the processor may turn off or light the lamp in the absence of transmitter commands (e.g. transmitter malfunction). Notes related to transmitter and receiver circuitry described above

(1) Assuming (a) the transmitter's current requirement is 400μA and (b) that the receiver load draws a current of 2OmA, apparently there is enough current (and voltage) for the transmitter operation. However, the receiver connects its load only during 150μs on each side of a zero-crossing. But since the transmitter supply is buffered by a capacitor (see above), an average current may be adequate rather than a continuous current. Therefore, the current may be calculated for 1/2 a cycle of 20ms (e.g. 1/50Hz) to verify that on the average there is enough current for the transmitter operation, as follows: 2OmA x 150μs x 2 / (20ms / 2) = 600μA. Thus, during each 1/2 cycle the receiver load provides more than sufficient current for the operation of the transmitter, even if the current is provided for short periods, and the surplus current (200μA) may be used to charge the capacitor.

(2) A full wave rectifier is constructed with the diodes of MOSFETS Ql/2.

(3) In order to charge capacitor Cl, MOSFETS Ql/2 and Q3A/B must be in a cutoff, otherwise the current will flow through their low resistance rather than charging the capacitor. The condition when both MOSFETS Ql/2 and Q3A/B are cutoff occurs: (a) during initialization (before the processor is powered and active), (b) during data modulation when Q3A/B is in cutoff bit period, and (c) when voltage is low and/whereby the processor switches off the MOSFETS after the data transmission in order to charge the capacitor whether or not the lamp is on (see note 1).

(4) The voltage across 2xRx is close to the voltage between phase-in and phase-out up to the relatively insignificant impedance of the MOSFETS Q3A/B relative to Rx.

(5) The comparators have an uncertainty (threshold) of about 1OmV (offset voltage). That is, a difference between the inputs of about 1OmV is indistinguishable and can be determined as zero or non-zero. For example, to obtain a drop of 1OmV, the current on 2xlΩ is 5mA, which is practically zero and the zero-crossing timing can be obtained with accuracy of a few μs.

(6) Coarse determination is performed by default upon start up to determine the timing of the AC waveform. (7) U2A/B are at offset of 0.7V so the detection is in a proper range of 0-5V + 2OmV bias that will cause an early zero-crossing detection of about 6μS (that is not significant).

(8) It = (0.7V - (-0.7V)V(Ry + Ry + ΔR) ~ 0.7V/Ry ~ 2OmA (up to ΔR, the relatively low resistance of MOSFETS Q8/9 of 2Ω). (9) The resistance of Rx (R8 and R9) is calculated as: Rx ~ 2xVrms / Pmax; where Vrms is the AC voltage root-mean-square value and Pmax is the peak power of AC passing through the transmitter. Some representative, non-limiting, values of Rx are given in Table 1 below.

Figure imgf000022_0001

Table 1

(10) The resistance of Ry (R25 and R26) (or Ry/2, R27 and R28) is calculated as:

Up to 250W: Ry= 36 Ω (constant);

Above 250W: Ry ~ 40xVrms / Pmax

Where Vrms is the AC voltage root-mean-square value and Pmax is the peak power of AC passing through the transmitter and receiver. Some representative, non-limiting, values of Ry are given in Table 2 below.

Figure imgf000022_0002

Table 2 Observations regarding the transmitter and receiver circuitry

It should be noted that by using a fast switch (<lμs) with very low impedance (few mΩ) such as a MOSFET transistor enables to detect accurately the zero-crossing of AC current at the transmitter and voltage at the receiver. The accurate zero-crossing detection allows synchronizing sending and receiving of a plurality of data bits at each side (time wise) of the current zero-crossing, while dissipating a low amount of power. The fast switching and low power dissipation is relative to SCR types of switches or similar elements (switching time ~100μs and power dissipation ~xl00 of the MOSFET). Another unique feature of the invention is an automatic switching (increasing) of impedances near the current zero-crossing, allowing accurate detection of the zero-crossing with very low current (and power) relative to the rest of the AC cycle that pass through the very low impedance Transmitter processor operation

Fig. 6A is a flowchart 600 of actions for managing the transmitter circuitry 400 (Fig. 4) by the processor thereof (U4), The example is provided as a non limiting embodiment and the embodiment may be varied according to the principles of invention. The description refers to the transmitter schematics 400 as a non limiting example. Again, when symmetric operation is involved with respect to current polarity, the relevant components are generally referred to as a pair.

The embodiment is based on an AC cycle of 50Hz and variations for other frequency (e.g. 60Hz) may be readily appreciated. As power is provided (e.g. switch 114 of Fig. IA or Fig. IB closes) the processor is initialized (602). The processor first drives (switches on) Ql/2 and Q3A/B (604) so that the transmitter is practically shortens the AC current (~10mΩ) and voltage is dropped on R8/9.

The output of comparators U2A/B is checked, and if any is high (~5V), a state that indicates that the current is still large (far from zero-crossing, see, for example, above/below 306/308 of Fig. 3) the processor keeps monitoring comparators U2A/B. When the output of both comparators U2A/B is low (coarse zero-crossing detection), the processor promptly switches off Ql/2 (608) so that only Q3A/B are on (higher resistance) and comparators U2A/B can detect the following zero-crossing more accurately by two orders of magnitude, i.e. ~2Ω/10mΩ (fine detection). The fine detection of the zero crossing (310 of Fig. 3) is detected when the output of comparators U2A/B alters, or toggles (e.g. if U2A was high then U2B turns on and if U2B was high then U2A turns on) (610-612). When the zero-crossing is detected, the processor begins to count the duration of the AC half current and sets a timer for 8ms (that expires with an interrupt) (614) and switches on Ql/2 (616) so that the current will flow through a low resistance (~10mΩ).

When the 8ms timer expires (618), indicating that a zero crossing is expected, Ql/2 are switched off (620) and the processor waits for the alteration of the outputs of comparators U2A/B for a fine detection (622) as described above (608-612). When the fine zero-crossing is detected, the processor calculates and marks (stores) the duration of half a cycle of the AC current, and begins to count the period again (624). Having already the period of half a cycle, the processor sets a timer that expires 120μs prior to the next zero-crossing ('Per-120'), and a timer that expires (with interrupt) within 150μs (626). When 150μs have passed (628) the processor checks whether the voltage of capacitor Cl is sufficient. If the voltage is less than 15V (630) the processor switches off Q3A/B (632), letting capacitor Cl to charge until Cl voltage reaches or surpasses 15V (634). If or when the voltage is sufficient of Cl the processor turns on Ql/2 and Q3A/B (236) substantially shortening the circuit (~10mΩ) and the processor performs some routines (described below) during the rest of the AC half cycle until 120μs before the next zero-crossing of the current.

When the Per-120 timer expires (640), the processor switches off Ql/2 (642) and transmits (or sends, by modulating the current) two data bits, 40μs each (644 and 646). Alternatively, instead of transmitting data, the receiver may intercepts status data from the receiver as described below.

After sending the data, the transmitter detects again the zero-crossing responsive to the toggling of comparators U2A/B (648), and marks the time and calculates (updates) the AC half cycle time (650) and sets again the Per-120 timer (652). After 40μs beyond (time wise) the zero-crossing (654), the processor transmits

(or receives) two additional data bits (656 and 658), and after additional delay of 30μs the processor again checks the voltage on Cl and switches off Q3A/B if charging Cl is necessary as described above, and the operations described above (630-660) are repeated as long as the transmitter is switched on (e.g. by switch 114 of Fig. 1). Data bits are sent and/or received by the transmitter and/or receiver in coordinated (synchronized) time frames of 40μs.

Fig. 6B is a flowchart of complementary actions of flowchart 600 for sending data, as indicated by '*' for bits 1-4 (644, 646, 656 and 658). Assuming that bit 'n' is first or third bit, then if the logical value of bit 'n' is "0" (664) the processor switches off Q3A/B (666) so that no current flows (i.e. in phase wire 106 and consequently in neutral wire 108 of Fig. IA). Thus, as coordinated between the transmitter processor and receiver processor, the receiver (see below) would interpret the absence of current as logical vale of "0". Otherwise, the processor switches Q3A/B (668) on so that current flows and the receiver would interpret the current as logical value of "1". After bit 'n' is sent, the processor insets a delay of 40μs (670) providing satisfactory time for the receiver to intercept the data, and bit 'n+1' is sent (672-676 similar to 664-668).

Fig. 6C is a flowchart of complementary actions of flowchart 600 for receiving data. As described above, instead of transmitting data, the receiver may intercept status data from the receiver as indicated by '*' for bits 3 and 4 (646, 656) (though all or other time frames may be used). Since data is transmitted in frames of 40μs, the processor delays for 20μs (678) for targeting the center of the received bit (better detection reliability). If the output of Q3A/B is high (680) then the processor interprets the bit as "1" (682), otherwise the bit is interpreted as "0" (684). According to the described embodiment, Fig. 6D shows a flowchart of complementary actions of flowchart 600 for preparatory routines (638) performed by the processor in the AC half cycles outside the time region within 120μs of the current zero-crossing (which may be referred to as the processor idle time).

The processor measures the voltage on potentiometer SPl such as dimmer (686) and arranges the data for sending the dimming control (688). In case status data bits were received in previous AC half cycle or cycles, the processor processes (e.g. parses and/or interpretes) the bits (890) into a message and operates accordingly, for example, verifies that the dimming level is correct.

Receiver processor operation Fig. 7A is a flowchart 700 for managing the receiver circuitry 500 (Fig. 5) by the processor thereof (U8). The example is provided as a non limiting embodiment and the embodiment may be varied according to the invention. The description refers to the receiver schematics 500 as a non limiting example. Again, when symmetric operation is involved with respect to voltage polarity, the relevant components are generally referred to as a pair. As several operations of the receiver are similar to those of the transmitter

(e.g. zero-crossing and period counting), for clarity and brevity the respective operations are described briefly.

The embodiment is based on an AC cycle of 50Hz and variations for other frequency (e.g. 60Hz) may be readily appreciated. As power is provided (e.g. switch 114 of Fig. IA or Fig. IB closes) the transmitter practically shortens the phase wire, e.g. by switching on Ql/2 of Fig. 4, and the processor is initialized (702).

In order to cooperate in communications with the transmitter, the receiver has to synchronize with the latter. The synchronization is carried out by the receiver detecting the voltage zero-crossing. Namely, when the receiver is near the voltage zero-crossing (e.g. less than I30VI) a current source Q8/9 is turned on as a load, and as the voltage polarity alternates, the output of comparators U7A/B alternate, similar to U2A/B or the transmitter, as described above. Once initialized, the processor switches off transistors Q10A/B (704) and waits (706) till the output of comparators U7A/B alternate (708). As the alternation indicates a voltage zero-crossing, the processor marks the time event for measuring the AC voltage half cycle and sets a timer for 8ms (710). When the 8ms timer expires (712), indicating approach of a voltage zero-crossing, the processor waits till the output of comparators U7A/B alternate (714). Subequently the processor marks the AC half cycle period time and begins to count the next half cycle period (716) and sets a Per- 120 timer (718).

When the Per-120 timer expires, 120μs before zero-crossing (720), the receiver intercepts data bit from the transmitter (722) and after 40μs intercepts another bit (724) (or sends a bit, as described below). Then the processor waits ill the output of comparators U7A/B alternate (726) and marks the AC half cycle period and starts counting the period again (728). After a delay of 40μs the next pair of bits is received (or transmitted) (734-736 similar to 722-724). During the cycle outside the time region of 120μs around the voltage zero-crossing, the processor performs background operations as described below (738) and the operations described above (720-738) are repeated as long power is applied to the receiver.

Fig. 7B is a flowchart of complementary actions of flowchart 700 for receiving data (722, 724, 734 and 736). The receiver waits 20μs for centering at the bit time frame (742) and if the output of the output of comparators U7A/B is high (~5 V, current flows) the receiver interprets the bit as "1" (746), otherwise the receiver interprets the bit as "0" (748).

Fig. 7C is a flowchart of complementary actions of the flowchart of Fig. 7A for sending data. When the receiver's processor determines (as coordinated with the transmitter's processor) that a status data bit is to be sent in a bit time frame, instead of receiving data from the processor, then if the data to be sent is "0" (752) then the processor switches on Q10A/B (e.g. Ir of Figs. 4-5) and shuts down load current Q8/9 (754). Otherwise Q10A/B are switched off and load current (e.g. Ir) is switched on (756). The bit state is kept on for the time frame of 40μs (758). According to the described embodiment Fig. 7D shows a flowchart of complementary actions of flowchart 700 for operational routines in the AC half cycles outside the time region within 120μs of the current zero-crossing (which may be referred to as the processor idle time). The processor processes, e.g. parse the data bits and/or assembles a message from the bits (760). Subsequently the processor applies control signals or sends control data to the appliance (e.g. ballast 110 of Fig. IA) according to the control data from the transmitter (762), for example, by DALI, PWM or other protocols. The processor determines or queries the status of the appliance (764), for example, by DALI, PWM or other protocols, and prepares for sending the status data in modulated current bits in the following data time frame or frames (766).

Optionally, the processor periodically and/or responsive to power failure (detected by low output of U7A/B for a few ms) stores the appliance status (768) in a non- volatile memory (e.g. FLASH memory) so that the status is kept, for example, for later initial state for the appliance

It should be noted that the number of bits sent and/or received by the transmitter and/or receiver may be smaller or larger, for example, by setting different data time frame and/or allowing more time about the zero-crossing, for example, larger or smaller than 120μs.

Time chart

Fig. 8 illustrates a chart 800 of time events about the zero-crossing (~+300μs) related to the description of Figs. 6-7 with respect to circuit diagrams 400-500.

Assuming a half cycle period of 10,000μs (50Hz) of a 230V AC, a curve 804 illustrates an AC voltage (or respective current) about the zero-crossing (802), where

804a is of positive polarity and 804b is of negative polarity (and respective time regions accordingly). The time region is illustrated between crossing of voltage +30V at

9,700μs (820) and crossing the -30V 10,300μs (822).

The region between crossing voltage of +15V at time 9,850μs (806), and crossing the -15V at 10,150μs (808) is intended for data communications wherein the zero-crossing is at 10,000μs (810).

At 30μs after crossing the +15V (812) two periods of 40μs (bit frames) are used for communications of data bit-1 and data bit-2 (831 and 832, respectively) as described, i.e. either for sending control data by the transmitter for the receiver or for sending status data from the receiver to the transmitter. Similarly, 40μs after the zero crossing, at 10,040μs (814), data bit-3 and bit-4 (834 and 834, respectively) are sent.

When the voltage on capacitor Cl of the transmitter is not sufficient, the region between time 9,700μs, crossing the +30V (820), and 10,300μs, crossing the -30V (822), is used for providing the Ir current to charge capacitor Cl, except when "0" bits are sent (from the transmitter or the receiver) since the "0" value is represented by lack of (or negligible) current. Ir may be positive (816) or negative (818), but the transmitter rectifies the current so that capacitor Cl is charged with positive current. It should be noted that the cited values in time or voltage are approximate as the voltage and frequency may vary, and are intended to illustrate how the embodiment described above is related to timing.

Other embodiments

Though unique embodiments of the invention use, without limiting, only a single phase wire (or one of 3 in a 3-phase system), the invention may still be implemented by a dual wire system (phase and neutral).

Fig. 9 schematically illustrates a connection relationship 900, similar to 100 of

Fig. IA, of an appliance controlled by a transmitter using both phase and natural wires via a receiver. The basic difference relative to 100 is that the transmitter 102 is connected also to the neutral wire 108. Connection scheme 900 may be simpler to implement since, for example, no special circuitry is required for generating voltage source (e.g. Cl of Fig. 4).

Optionally, in some embodiments, the invention, with possible variations, may be implemented in a DC system. For example, the circuitry may be implemented for one polarity only, simplifying the embodiment and eliminating components. Or, for example, the DC current or voltage may be 'chopped' or modulated relative to a certain or average as a zero reference thus requiring minor modifications in the circuitry such as

400 and 500 of Figs. 5-6, respectively.

It should be noted that the invention is viable when there is no back current flowing towards the transmitter. However, modern cotemporary ballast and other devices are fitted such that there is no back current and, optionally, substantially exhibit resistive load with no or minor phase change. Optionally, the invention may be modified to tackle back current, such as by using rectifiers (e.g. diodes) or other elements that inhibit or block the back current. In some embodiments, a kit is provided based on embodiments of the invention, comprising a transmitter, at least one receiver and an optional appliance (optionally integrated with a receiver).

Fig. 1OA schematically illustrates a kit 1000 comprising a transmitter 1002

(similar to 102 of Fig. IA), a receiver 1004 (similar to 104 of Fig. IA) and an optional appliance 1006 (such as a ballast). Transmitter 1002 comprises contacts 1008 for connecting to the phase wire (phase in and phase out) and contacts 1010 for connecting to a control apparatus (such as potentiometer SPl of Fig. 4). Receiver 1004 comprises contacts 1012 for connecting to the phase and neutral wires and contacts 1014 for interfacing with appliance 1006. Appliance 1006 comprises contacts 1016 for interfacing with receiver 1004 and contacts 1018 for connecting to the phase and neutral wires.

Fig. 1OB schematically illustrates a kit 1100 comprising a transmitter 1002 and an integrated receiver/appliance 1020, where the connections are substantially similar to those of Fig. 1OA, excluding the interface contacts 1014 and 1016 which are internal to integrated receiver/appliance 1020.

General

All trademarks are the property of their respective owners. In the specifications and claims, unless otherwise specified, the terms 'software', 'program', 'procedure' or 'software module' ('module') or 'software code' ('code') may be used interchangeably and denote one or more instructions executable by a computing or other apparatus, such as one or more computers, processors, or signal Processors (DSP), optionally involving other hardware or software components such as memory, input/output interface or operating system. Without limiting, the software may be stored in a volatile or permanent memory, such as magnetic medium, ROM, RAM, or PROM or as a part of a SOC (System on a Chip), or a combination thereof, or any other apparatus. Software, or equivalent thereof, may optionally be implemented by any apparatus that carries out the function of the software or equivalent thereof.

In the specification and claims, unless otherwise specified, the terms 'about', 'close', 'approximate' and inflections thereof denote, unless otherwise specified or implied in the context, a sufficiently close functional and/or practical respective relation or measure or amount or quantity or degree to the referenced subject matter according to the context in which the terms or their inflections appear.

In the specification and claims, unless otherwise specified, the terms 'substantial', 'considerable', 'significant' and inflections thereof denote, unless otherwise specified or implied in the context, a measure or extent or amount or degree which is large or effective or important relative to the rest of the referenced subject matter. In the specification and claims, unless otherwise specified, the terms 'negligible',

'slight' and 'insignificant' and inflections thereof denote, unless otherwise specified or implied in the context, a sufficiently small functional and/or practical respective relation or measure or amount or quantity or degree according to the context in which the terms or their inflections appear.

In the specification and claims, unless otherwise specified, the terms 'comprises', 'comprising', 'includes', 'including', 'having' and their inflections and conjugates denote 'including but not limited to'.

In the specification and claims, unless otherwise specified, referring to an element, object, method, step, etc. with an indefinite singular article (e.g. "a thing") does not preclude a reference to a plurality thereof (e.g. "things").

The present invention has been described using descriptions of embodiments thereof that are provided by way of example and are not intended to limit the scope of the invention. The described embodiments comprise various features, not all of which are necessarily required in all embodiments of the invention. Some embodiments of the invention utilize only some of the features or possible combinations of the features.

Alternatively and additionally, portions of the invention described/depicted as a single unit may reside in two or more separate physical entities which act in concert to perform the described/depicted function. Alternatively and additionally, portions of the invention described/depicted as two or more separate physical entities may be integrated into a single physical entity to perform the described/depicted function. Variations of embodiments of the present invention that are described and embodiments of the present invention comprising different combinations of features noted in the described embodiments can be combined in all possible combinations including, but not limited to use of features described in the context of one embodiment in the context of any other embodiment.

In the specifications and claims, unless otherwise specified, when a range of values is recited, it is merely for convenience or brevity and includes all the possible sub-ranges as well as individual numerical values within that range. Any numeric value, unless otherwise specified, includes also practical close values enabling an embodiment or a method, and integral values do not exclude fractional values. A sub-range values and practical close values should be considered as specifically disclosed valued.

Terms in the claims that follow should be interpreted, without limiting, as defined and/or denoted and/or described in the specification.

Claims

1. A method for communicating over AC mains wires, comprising:
(a) providing a master unit and at least one slave unit;
(b) connecting the master unit to at least one wire of AC mains; (c) connecting a slave unit to at least two wires of an AC mains; and
(d) communicating between the master unit and the at least one slave unit by a plurality of data elements in a half cycle of an AC current about the zero-crossing while substantially maintaining the current waveform.
2. A method according to claim 1, wherein connecting the master unit to at least one wire of AC mains comprises connecting to a single phase wire.
3. A method according to claim 1, wherein connecting the at least one slave unit to at least two wires of AC mains comprises connecting to phase and neutral wires.
4. A method according to claim 1, wherein the communicating is unidirectional from the master unit to a slave unit.
5. A method according to claim 1, wherein the communicating is bidirectional between the master unit and a slave unit.
6. A method according to claim 1, wherein the communicating between the master unit and a slave unit comprises synchronization by mutually detecting the AC current zero-crossing.
7. A method according to claim 1, wherein the communicating comprises modulating the current to a plurality of data elements about the AC current zero-crossing.
8. A method according to claim 1, wherein the at least one slave unit comprises a plurality of slave units.
9. A method according to claim 1, wherein modulating the current comprises affecting the current within less than lms.
10. A method according to claim 1, wherein modulating the current comprises affecting the current within less than 0.5ms.
11. A method according to claim 1, wherein modulating the current comprises affecting the current within about 0.1ms.
12. A method for communicating over AC mains wires, comprising:
(a) providing a master unit and at least one slave unit;
(b) connecting the master unit to at least one wire of AC mains;
(c) connecting a slave unit to at least two wires of an AC mains; and (d) communicating between the master unit and the at least one slave unit by a plurality of data elements in a half cycle of an AC current about the zero-crossing while substantially maintaining the current waveform by using an electronic switch with at least one of faster switching time or lower power dissipation than a SCR-based switch.
13. A method according to claim 12, wherein the SCR-based switch is one of a thyristor or a triac.
14. A method according to claim 12, wherein the electronic switch with at least one of faster switching time or lower power dissipation than a SCR-based switch comprises at least one MOSFET transistor.
15. A method according to claim 12, wherein connecting the master unit to at least one wire of AC mains comprises connecting to a single phase wire.
16. A method according to claim 12, wherein the communicating comprises modulating the current to a plurality of data elements about the AC current zero-crossing.
17. A system for communicating between a master unit and at least one slave unit, comprising:
(a) a master unit, comprising a circuitry configured for communication, connected to at least one wire of AC mains;
(b) at least one slave unit, comprising a circuitry configured for communication, connected to at least two wires of an AC mains, and wherein a circuitries in the master unit and the at least one slave units are configured for communications therebetween by a plurality of data elements in a half cycle of an AC current while substantially maintaining the current waveform.
18. A system according to claim 17, wherein the master unit is connected to a single phase wire.
19. A system according to claim 17, wherein the circuitry of the master unit comprises at least one MOSFET transistor.
20. A system according to claim 17, wherein the circuitry of a slave unit comprises at least one MOSFET transistor.
21. A system according to claim 17, wherein the circuitry of the master unit and the circuitry of a slave unit are configured for bidirectional communications therebetween.
22. A system according to claim 17, wherein the circuitry of the master unit and the circuitry of a slave unit are configured to modulate the current to a plurality of data elements about the current zero-crossing.
23. A system according to claim 17, wherein the circuitry of the master unit and the circuitry of a slave unit are configured to detect modulated current about the current zero-crossing.
24. A system according to claim 17, wherein the circuitry of the master unit and the circuitry of a slave unit are configured to synchronize the communications by detecting the AC-current zero-crossing.
25. A system according to claim 17, wherein a slave unit interacts with at least one device.
26. A system according to claim 17, wherein a slave unit controls at the least one device based on the plurality of data from the master unit.
27. A system according to claim 17, wherein a slave unit is configured to provide status information to the master unit by a plurality of data elements.
28. A system for communicating between a master unit and at least one slave unit, comprising: (a) a master unit, comprising circuitry configured for communication, connected to at least one wire of an AC mains; and
(b) at least one slave unit, comprising circuitry configured for communication, connected to at least two wires of an AC mains, wherein the circuitry in the master unit and the at least one slave unit are configured for communication therebetween by a plurality of data elements in a half cycle of an AC current while substantially maintaining the current waveform by using an electronic switch with at least one of faster switching time or lower power dissipation than a SCR-based switch.
29. A system according to claim 28, wherein the master unit is connected to a single phase wire.
30. A system according to claim 28, wherein the SCR-based switch is one of a thyristor or a triac.
31. A system according to claim 28, wherein the switch with at least one of faster switching time or lower power dissipation than a SCR-based switch comprises at least one MOSFET transistor.
32. A kit, comprising:
(a) a master unit configured for connection to at least a phase wire of AC mains; and (b) at least one slave unit configured for connection to two wires of AC mains, wherein the master unit and the at least one slave units are configured for communications therebetween by a plurality of data elements about the zero crossing of an AC current while substantially maintaining the current waveform.
33. A kit according to claim 32, further comprising at least one device configured to interface with the at least one slave unit.
34. A kit according to claim 32, wherein the at least one unit is integrated with at least one device.
35. A kit according to claim 32, wherein the device is at least one of comprises or connected or interacts with an electrical appliance.
36. A kit according to claim 32, wherein connection to at least a phase wire of AC mains comprises connection to single phase wire.
37. A kit according to claim 32, wherein the device comprises an electronic ballast of a gas discharge lamp.
38. A kit according to claim 32, wherein the device comprises an electric motor or a controller thereof.
PCT/IB2009/052702 2008-06-26 2009-06-24 Electrical device control WO2009156952A1 (en)

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EP2429265A3 (en) * 2010-07-27 2012-07-11 Abb Ag Method and system for communicating over a load line
WO2012062664A1 (en) * 2010-11-09 2012-05-18 Tridonic Gmbh & Co Kg Interference-free light-emitting means control
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WO2013153097A1 (en) * 2012-04-12 2013-10-17 Zumtobel Lighting Gmbh Lighting system and control unit for same
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WO2014071427A3 (en) * 2012-11-06 2014-07-03 Tridonic Gmbh & Co Kg Method and device for transmitting data via a load line and lighting system
US20150289348A1 (en) * 2012-11-06 2015-10-08 Tridonic Gmbh & Co Kg Control device and method for data transmission via a load line
US20150280782A1 (en) * 2012-11-06 2015-10-01 Tridonic Gmbh & Co Kg Method and device for transmitting data via a load line and lighting system
CN104904318A (en) * 2012-11-06 2015-09-09 赤多尼科两合股份有限公司 Method and device for transmitting data via load line and lighting system
US20160227632A1 (en) * 2014-09-04 2016-08-04 Zhejiang Shenghui Lighting Co., Ltd. Lighting control system and method
US9894737B2 (en) * 2014-09-04 2018-02-13 Zhejiang Shenghui Lighting Co., Ltd Lighting control system and method
TWI709136B (en) 2015-08-13 2020-11-01 英商Arm股份有限公司 Method, system and device for non-volatile memory device operation (1)
WO2018055109A1 (en) * 2016-09-26 2018-03-29 Osram Gmbh Method and sensor apparatus for controlling a lighting device in a lighting system and lighting system for this purpose

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GB2468187A (en) 2010-09-01
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GB201000805D0 (en) 2010-03-03

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