WO2009101824A1 - Mis field effect transistor and method for manufacturing the same, and semiconductor device and method for manufacturing the same - Google Patents
Mis field effect transistor and method for manufacturing the same, and semiconductor device and method for manufacturing the same Download PDFInfo
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- WO2009101824A1 WO2009101824A1 PCT/JP2009/050114 JP2009050114W WO2009101824A1 WO 2009101824 A1 WO2009101824 A1 WO 2009101824A1 JP 2009050114 W JP2009050114 W JP 2009050114W WO 2009101824 A1 WO2009101824 A1 WO 2009101824A1
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- gate electrode
- insulating film
- group
- effect transistor
- transition metal
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Definitions
- the present invention relates to a MIS (Metal Insu1ator Semiconductor) type field effect transistor, a manufacturing method thereof, a semiconductor device, and a manufacturing method thereof.
- the semiconductor device according to the present invention includes the MIS field effect transistor according to the present invention as an n-channel MIS field effect transistor and a p-channel MIS field effect transistor.
- MIS type field effect transistor “n channel MIS type field effect transistor” and “p channel MIS type field effect transistor” are respectively referred to as “MISFET (MIS Field Effect Transistor)”, “nMIS” and “pMIS”. Abbreviated.
- One of them is the thinning of the gate insulating film.
- This method makes it easy to control the depletion layer formed in the Si substrate due to the voltage applied to the gate insulating film by reducing the thickness of the gate insulating film, thereby suppressing the short channel effect. is there.
- the gate electrode of the MISFET is formed of polysilicon doped with impurities, the electric field applied to the gate electrode is relatively strong due to the thinning of the gate insulating film, so that a depletion layer is also formed in the gate electrode. Will be formed. As a result, the gate insulating film becomes substantially thick.
- a metal gate electrode formed of a metal material has an advantage that not only the above-described depletion of the gate electrode can be suppressed, but also the resistance of the gate electrode can be reduced and the penetration of boron can be suppressed. For this reason, in the early stages of development of MISFETs, metal gate electrodes made of metals such as Al, W, WTi, and metal gate electrodes made of nitrides of these metals were used (see, for example, Patent Documents 1 to 3). ).
- the metal gate electrode has the following problems.
- the melting point of Al is as low as about 660 ° C. Therefore, if heat treatment at 400 ° C. or higher for activating the source and drain is performed, the metal gate electrode is disconnected or Al Atoms diffuse into the surrounding area. Further, the characteristics of W change due to oxidation. Furthermore, W and WTi are dissolved when acid cleaning is performed, that is, the cleaning resistance is low.
- group IV transition metal nitrides and silicides are attracting attention as metal gate materials for the following reasons. 1. It is chemically stable and has a high melting point. 2. Good electrical conductivity. 3. High heat resistance on a promising high-k gate insulating film such as HfSiO.
- Non-Patent Document 1 discloses a technique for controlling a work function by forming a TiN film as an nMIS and pMIS gate electrode and then implanting nitrogen only into the nMIS gate electrode.
- the work function control width is as small as about ⁇ 0.1 eV, so that its application is limited to low power consumption CMIS (Complementary MIS).
- CMIS Complementary MIS
- an object of the present invention is to provide a MISFET or the like that can expand the control range of the work function when a nitride or silicide of a group IV transition metal is used as a metal gate material.
- the MISFET according to the present invention is a MISFET having a laminated structure of a gate electrode and a gate insulating film, wherein the gate electrode is made of a conductive film containing a group IV transition metal, and at least a side of the gate insulating film in contact with the gate electrode is the IV It is made of a metal oxide that is not reduced by a group transition metal, and an interface layer between the gate electrode and the gate insulating film contains the group IV transition metal and oxygen.
- a semiconductor device includes the MISFET according to the present invention as an nMIS and a pMIS, wherein an oxygen composition in the interface layer in the nMIS is lower than an oxygen composition in the interface layer in the pMIS. To do.
- a method of manufacturing a MISFET according to the present invention is a method of manufacturing a MISFET having a stacked structure of a gate electrode and a gate insulating film.
- a fourth step of forming an interface layer containing the group IV transition metal and the oxygen by heat treatment between the gate electrode and the gate insulating film is a method of manufacturing a MISFET having a stacked structure of a gate electrode and a gate insulating film.
- a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device using the method for manufacturing a MISFET according to the present invention.
- the gate electrode is formed with a first region for forming an nMIS and a pMIS.
- oxygen is ion-implanted into at least the second region of the first region and the second region, so that the amount of oxygen in the first region is reduced to the second region.
- the amount of oxygen is less than the amount of oxygen.
- the side of the gate insulating film that contacts the gate electrode is a metal oxide that is not reduced by the group IV transition metal, and the interface layer between the gate electrode and the gate insulating film includes the group IV transition metal and oxygen. Therefore, even if a gate electrode made of a conductive film containing a group IV transition metal is used, the work function of the gate electrode can be freely controlled by changing the oxygen composition of the interface layer. Can be expanded.
- FIG. 1A is a cross-sectional view showing a MISFET according to the first embodiment of the present invention
- FIG. 1B is a cross-sectional view showing a MISFET according to the second embodiment of the present invention.
- description will be given based on this drawing.
- the MISFET 10 of the first embodiment has a stacked structure of a gate electrode 11 and a gate insulating film 12.
- the gate electrode 11 is made of a conductive film containing a group IV transition metal. At least the side in contact with the gate electrode 11 of the gate insulating film 12 is made of a metal oxide that is not reduced by a group IV transition metal.
- the interface layer 13 between the gate electrode 11 and the gate insulating film 12 contains a group IV transition metal and oxygen.
- the conductive film containing a group IV transition metal is, for example, a nitride or oxide of a group IV transition metal.
- the group IV transition metals mentioned here are all the same as those contained in the gate electrode 11.
- the group IV transition metal is Ti, Zr, Hf, or the like.
- FIG. 1A only the stacked structure of the gate electrode 11 and the gate insulating film 12 on the semiconductor substrate 14 is shown, and the source, drain, and the like are omitted.
- the gate electrode 11 is TiN. In this TiN, Ti is, for example, 40 to 60 at%, for example, 50 at%, and the rest is N.
- the interface layer 13 is (TiN) 1-x (TiO 2 ) x .
- the gate insulating film 12 is HfO 2 having a thickness of 3.0 nm.
- the semiconductor substrate 14 is Si.
- the manufacturing method of the MISFET 10 includes the following steps. First step: A gate insulating film 12 made of a metal oxide whose upper surface is not reduced by a group IV transition metal is formed on the semiconductor substrate 14. Second step: A gate electrode 11 made of a conductive film containing a group IV transition metal is formed on the gate insulating film 12. Third step: Oxygen ions are implanted into the gate electrode 11. Fourth step: An interface layer 13 containing a group IV transition metal and oxygen is formed between the gate electrode 11 and the gate insulating film 12 by heat treatment.
- the first process corresponds to FIGS. 4 (a) and 4 (b)
- the second process corresponds to FIG. 4 (c)
- the third process corresponds to FIG. 4 (d)
- the fourth process corresponds to FIG. It corresponds to (e).
- the MISFET 20 of the second embodiment has a laminated structure of the gate electrode 11 and the gate insulating film 22.
- the gate electrode 11 is made of a conductive film containing a group IV transition metal. At least the side in contact with the gate electrode 11 of the gate insulating film 22 is made of a metal oxide that is not reduced by a group IV transition metal.
- the interface layer 13 between the gate electrode 11 and the gate insulating film 22 contains a group IV transition metal and oxygen.
- the conductive film containing a group IV transition metal is, for example, a nitride or oxide of a group IV transition metal.
- the group IV transition metals mentioned here are all the same as those contained in the gate electrode 11.
- the group IV transition metal is Ti, Zr, Hf, or the like.
- FIG. 1B only the stacked structure of the gate electrode 11 and the gate insulating film 22 on the semiconductor substrate 14 is shown, and the source, drain, and the like are omitted.
- the gate electrode 11 is TiN. In this TiN, Ti is, for example, 40 to 60 at%, for example, 50 at%, and the rest is N.
- the interface layer 13 is (TiN) 1-x (TiO 2 ) x .
- the gate insulating film 22 is a stacked film of an HfO 2 layer 221 having a thickness of 0.5 nm, an underlying Hf silicate layer 222 having a thickness of 3.0 nm, and an SiO 2 layer 223 having a thickness of 0.5 nm. .
- the HfO 2 layer 221 is on the side in contact with the gate electrode 11.
- the semiconductor substrate 14 is Si.
- the manufacturing method of the MISFET 20 is in accordance with the manufacturing method of the MISFET 10 described above.
- FIG. 2 is a graph showing the relationship between the composition x of the interface layer ((TiN) 1-x (TiO 2 ) x ) and the effective work function of the gate electrode in the first and second embodiments.
- the present inventors have conducted extensive experimental research, and the effective work function of the gate electrode 11 formed of a conductive film containing a group IV transition metal as a main component is the gate electrode 11 and the gate. It was found based on the following experiment that it was determined by the interface layer 13 existing between the insulating film 12. Thus, it was confirmed that the nMIS gate electrode 11 and the pMIS gate electrode 11 can be formed separately.
- a TiN / HfO 2 laminated structure was used as the laminated structure of the gate electrode 11 and the gate insulating film 12 shown in FIG. Then, in order to control the formation of the interface layer 13, oxygen was implanted from above TiN using an ion implantation method. That is, the interface layer 13 was formed at the TiN / HfO 2 interface by ion implantation.
- FIG. 2 shows the relationship between the composition x of the interface layer 13 ((TiN) 1-x (TiO 2 ) x ) as the X axis and the effective work function of the gate electrode 11 as the Y axis.
- the work function of the gate electrode 11 increases as the composition x increases, that is, as the oxygen composition increases.
- nMIS in the interface layer 13 is made lower than that of pMIS, an effective work function suitable for each of nMIS and pMIS can be realized using the gate electrode 11 made of the same material. As a result, a semiconductor device can be manufactured at low cost. Further, since the interface layer 13 has high heat resistance, high heat treatment after the formation of the gate electrode, which was not possible with a general-purpose metal gate transistor, can be performed. Thus, since a self-alignment process can be used when forming the transistor, a fine and high-speed transistor can be realized.
- nMIS can be realized by using a conductive film containing a chemically stable group IV transition metal as a main component.
- the effective work function of the gate electrode 11 is about 4 to 4.2 eV.
- the gate electrode 11 when the composition of the interface layer 13 in the pMIS is expressed as (TiN) 1-x (TiO 2 ) x , when x is 0.84 or more and 0.97 or less, the gate electrode 11 The effective work function of is about 4.7 to 5.1 eV suitable for pMIS. Therefore, pMIS can be realized by using a conductive film containing a chemically stable group IV transition metal as a main component. Further, when x is 0.92 or more and 0.97 or less, the effective work function of the gate electrode 11 is about 4.9 to 5.1 eV. As a result, a pMIS having a low threshold voltage can be realized, so that the speed of the transistor can be increased.
- the gate insulating film 22 shown in FIG. 1B that is, a laminated structure of the silicate layer 222 and the SiO 2 layer 223 whose upper surface is covered with the HfO 2 layer 221 having a thickness of about 0.5 nm. May be used. That is, similar experimental results were obtained with the configuration of the MISFET 20 of FIG. The same effect can be obtained even when another group IV transition metal nitride or oxide is used as the gate electrode 11.
- the gate insulating film 12 contains zirconium or hafnium because a heat treatment at about 1000 ° C. is necessary after forming the gate electrode 11. This is because the gate insulating film 12 containing zirconium or hafnium is excellent in heat resistance. Furthermore, if the gate insulating film 12 is zirconium oxide or hafnium oxide, an increase in oxygen composition in the interface layer 13 in the nMIS can be effectively suppressed. As a result, nMIS with a low threshold voltage can be realized, so that the speed of the transistor can be increased.
- FIG. 3 is a sectional view showing a semiconductor device according to the third embodiment of the present invention. Hereinafter, description will be given based on this drawing.
- the element isolation region 32 is selectively formed in the surface layer portion of the silicon substrate 31.
- An insulating film such as SiO 2 is embedded in the element isolation region 32, and an nMIS formation region 41 and a pMIS formation region 42 are formed between the plurality of element isolation regions 32.
- the depth of the element isolation region 32 is, for example, 100 to 500 nm, and the distance between the plurality of element isolation regions 32 is, for example, 0.05 to 10 ⁇ m.
- a pair of diffusion regions 38 is formed in each of the nMIS formation region 41 and the pMIS formation region 42 in the surface layer portion of the silicon substrate 31.
- the diffusion region 38 is a region formed by implanting impurity ions into the silicon substrate 31 and is formed adjacent to the element isolation region 32.
- An example of the dimensions of the diffusion region 38 is that the width is 0.1 to 10 ⁇ m, for example 0.2 ⁇ m, the depth is 50 to 500 nm, for example 100 nm, and the impurity concentration is 10 19 to 10 21 cm ⁇ 3 .
- An extension region 36 is formed so as to be adjacent to the diffusion region 38 and sandwich the diffusion region 38 together with the element isolation region 32.
- the extension region 36 is also a region formed by ion implantation of impurities into the silicon substrate 31.
- the impurity concentration of the extension region 36 is equal to or lower than that of the diffusion region 38.
- the width is 60 nm
- the depth is 5 to 200 nm
- the impurity concentration is 10 19 to 10 21 cm ⁇ 3 .
- a gate insulating film 33 is formed in the nMIS formation region 41 and the pMIS formation region 42 on the silicon substrate 31.
- the gate insulating film 33 is, for example, HfO 2 .
- gate electrodes 34a and 34b which are metal gate electrodes are formed.
- the thickness of the gate electrodes 34a and 34b is, for example, 20 to 200 nm, for example, 50 to 100 nm.
- the gate electrodes 34a and 34b are, for example, TiN.
- Interfacial layers 39a and 39b containing a group IV transition metal and oxygen are formed between the gate electrode 34a and the gate insulating film 33 and between the gate electrode 34b and the gate insulating film 33, respectively.
- the group IV transition metal in the interface layers 39a and 39b is the same as that contained in the gate electrodes 34a and 34b.
- the amount of oxygen in the interface layer 39a under the gate electrode 34a is lower than the amount of oxygen in the interface layer 39b under the gate electrode 34b.
- the work function of the gate electrode 34a is 4.0 to 4.4 eV suitable for the gate electrode material of nMIS
- the work function of the gate electrode 43b is 4.7 to 5 suitable for the gate electrode material of pMIS. .1 eV.
- the interface layers 39a and 39b are not shown because of their thinness, but their specific structure is the same as that of the interface layer 13 in FIG.
- Side walls 37 are formed around the gate electrodes 34a and 34b.
- the side wall 37 is formed of, for example, a silicon nitride film.
- An interlayer insulating film (not shown) made of SiO 2 , BPSG (Borophosphosilicate Glass), SiN, or a low dielectric constant film is formed so as to fill the periphery of the gate electrodes 34 a and 34 b and the side wall 37.
- the interlayer insulating film that is not shown in order to avoid complication is the same as the interlayer insulating film 59 in FIG.
- the upper surfaces of the gate electrodes 34a and 34b are exposed on the upper surface of the interlayer insulating film.
- the nMIS 43 is formed from the silicon substrate 31, the pair of diffusion regions 38, the pair of extension regions 36, the gate insulating film 33, the interface layer 39a, the gate electrode 34a, and the side wall 37.
- the pair of diffusion regions 38 are a source and a drain, respectively, and a channel region is formed between the source and the drain.
- a pMIS 44 is formed from the silicon substrate 31, the pair of diffusion regions 38, the pair of extension regions 36, the gate insulating film 33, the interface layer 39b, the gate electrode 34b, and the sidewall 37.
- nMIS formation region 41 when a voltage is applied to the gate electrode 34a, an electric field is applied to the channel region via the gate insulating film 33, and the carrier concentration in the channel region changes. As a result, the current flowing between the source and the drain changes. Similarly, when a voltage is applied to the gate electrode 34b in the pMIS formation region 42, the current flowing between the source and the drain changes.
- the semiconductor device 30 has an nMIS 43 and a pMIS 44.
- the gate electrode 34a of the nMIS 43 and the gate electrode 34b of the pMIS 44 are each made of a conductive film containing a group IV transition metal as a main component. At least the surface of the gate insulating film 33 is made of a metal oxide that is not reduced by a group IV transition metal.
- the interface layer 39a under the gate electrode 34a and the interface layer 39b under the gate electrode 34b contain a group IV transition metal and oxygen contained in the gate electrodes 34a and 34b, respectively.
- the oxygen composition in the interface layer 39a is lower than the oxygen composition in the interface layer 39b.
- the work function of a conductive film containing a group IV transition metal as a main component increases as the oxygen composition increases (see FIG. 2). Therefore, due to the presence of the interface layers 39a and 39b, the effective work function of the gate electrodes 34a and 34b is about 4 to 4.4 eV for the nMIS 43 and about 4.7 to 5 eV for the pMIS 44. Further, by making the surface of the gate insulating film 33 a metal oxide that is not reduced by a group IV transition metal, an increase in oxygen composition in the interface layer 39a particularly in the nMIS 44 can be suppressed. As a result, the nMIS 44 having a low threshold voltage can be realized, so that the speed of the transistor can be increased.
- these interface layers 39a and 39b have high heat resistance, high heat treatment can be performed after the formation of the gate electrodes 34a and 34b, which was not possible with a general-purpose metal gate transistor.
- a self-alignment process can be used when forming the transistor, a fine and high-speed transistor can be realized.
- the gate electrodes 34a and 34b of the nMIS 43 and the pMIS 44 are basically made of the same material, the semiconductor device 30 can be manufactured at low cost.
- the group IV transition metal constituting the gate electrodes 34a and 34b is titanium, since it is easy to process, a fine transistor can be realized, thereby reducing the manufacturing cost and improving the yield.
- the composition of the interface layer 39a existing between the gate electrode 34a of the nMIS 42 and the gate insulating film 33 is (TiN) 1.
- ⁇ x (TiO 2 ) x the effective work function of the gate electrode 34a is about 4 to 4.4 eV suitable for the nMIS 43. Therefore, the nMIS 43 can be realized by using a conductive film containing a chemically stable group IV transition metal as a main component.
- the effective work function of the gate electrode 34a is about 4 to 4.2 eV.
- the nMIS 43 having a low threshold voltage can be realized, so that the speed of the transistor can be increased.
- the composition of the interface layer 39b existing between the gate electrode 34b of the pMIS 44 and the gate insulating film 33 is represented as (TiN) 1-x (TiO 2 ) x .
- the effective work function of the gate electrode 34b is about 4.7 to 5.1 eV suitable for the pMIS 44. Therefore, the pMIS 44 can be realized by using a conductive film containing a chemically stable group IV transition metal as a main component.
- the effective work function of the gate electrode 34b is about 4.9 to 5.1 eV. As a result, the pMIS 44 having a low threshold voltage can be realized, and the speed of the transistor can be increased.
- the surface of the gate insulating film 33 preferably contains at least one of zirconium and hafnium.
- the stability of the gate insulating film 33 is increased, so that the yield is improved.
- the surface of the gate insulating film 33 is preferably zirconium oxide or hafnium oxide. This is because an increase in oxygen composition in the interface layer 39a in the nMIS 43 can be suppressed. As a result, since the nMIS 43 having a low threshold voltage can be realized, the speed of the transistor can be increased.
- the semiconductor device 30 has the following effects.
- the gate insulating film 33 that is not reduced by the gate electrodes 34 a and 34 b and the gate electrodes 34 a and 34 b containing a group IV transition metal form interface layers 39 a and 39 b containing a group IV transition metal and oxygen. Is touching through.
- the oxygen composition in the interface layer 39a existing between the gate electrode 34a of the nMIS 43 and the gate insulating film 33 is the oxygen composition in the interface layer 39b existing between the gate electrode 34b of the pMIS 44 and the gate insulating film 33. It is lower than
- nMIS 43 By adopting such a configuration, an increase in oxygen composition in the interface layer 39a in the nMIS 43 can be suppressed, so that a work function of about 4.0 eV can be realized. As a result, the nMIS 43 having a low threshold voltage can be realized, and the speed of the n-channel transistor can be increased.
- the work function of the gate electrode 34b is about 5 eV, so that the pMIS 44 can be operated at high speed. Furthermore, since the effective work function suitable for each MISFET can be realized by using the gate electrodes 34a and 34b made of the same material in the nMIS 43 and the pMIS 44, the semiconductor device 30 can be manufactured at low cost. Since these gate electrodes 34a and 34b, which are metal gate electrodes, do not deplete the gate electrode, they are suitable for increasing the speed of the semiconductor device 30 having a gate length of 0.1 ⁇ m or less.
- FIGS. 4 and 5 are sectional views showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.
- description will be given based on these drawings.
- FIG. 4A to 5G are cross-sectional views showing the method of manufacturing the semiconductor device according to this embodiment in the order of the steps.
- an insulating film is selectively embedded in the surface layer portion of the silicon substrate 31 to form an element isolation region 32.
- the element isolation region 32 is formed by using, for example, a LOCOS (Local Oxidation of Si1icon) method or an STI (Shallow Trench Isolation) method.
- LOCOS Local Oxidation of Si1icon
- STI Shallow Trench Isolation
- a gate insulating film 33 made of an HfO 2 film is formed using a method such as a sputtering method or a CVD (Chemical Vapor Deposition) method.
- the film thickness is, for example, about 3 nm.
- a gate electrode 34 made of a TiN film is formed by using a sputtering method or a CVD method.
- the film thickness is, for example, 20 to 200 nm.
- the surface of the gate electrode 34 in the nMIS formation region 41 is covered with a mask 35 such as a photoresist, and oxygen is injected from the surface of the gate electrode 34 in the pMIS formation region 42 by ion implantation. Added.
- the dose of ion implantation is typically 1 ⁇ 10 15 to 1 ⁇ 10 16 cm ⁇ 2 .
- the composition of the interface layers 39a and 39b (see FIG. 5E) formed in a later step can be controlled.
- the gate electrode 34 is described by distinguishing between the gate electrode 34 a in the nMIS formation region 41 and the gate electrode 34 b in the pMIS formation region 42.
- interface layers 39a and 39b are formed at the interface between the gate insulating film 33 and the gate electrodes 34a and 34b, respectively, using heat treatment.
- the interface layers 39a and 39b contain a group IV transition metal (Ti) and oxygen contained in the gate electrodes 34a and 34b, and do not contain silicon.
- the interface layer 39a is formed.
- the gate insulating film 33 is not reduced by the gate electrode 34a, an increase in the oxygen composition in the interface layer 39a due to the heat treatment can be suppressed.
- the work function of the gate electrode 34a is 4.0 eV suitable for the gate electrode material of nMIS.
- the interface layer 39b contains a group IV transition metal (Ti) and oxygen contained in the gate electrode 34b.
- the amount of oxygen in the interface layer 39b is larger than the amount of oxygen in the interface layer 39a. Therefore, the work function of the gate electrode 34b is about 1 eV higher than the work function of the gate electrode 34a, for example, 5.1 eV, which is suitable for the gate electrode material of pMIS.
- the gate electrodes 34a and 34b are patterned into a predetermined shape.
- the gate electrodes 34 a and 34 b have final shapes in the MIS formation region 41 and the pMIS formation region 42.
- the ion implantation amount is, for example, 1 ⁇ 10 14 to 1 ⁇ 10 15 cm ⁇ 2 , for example, 5 ⁇ 10 14 cm ⁇ 2 .
- the acceleration voltage is 2 kV, for example.
- a part of the implantation region 38 ′ becomes an extension region 36 (see FIG. 5G) in the nMIS formation region 41 by performing a heat treatment described later.
- BF 2 ions are implanted into the pMIS formation region 42 in a self-aligning manner using the gate electrode 34b as a mask.
- an implantation region 38 ′ is formed in the upper layer portion of the silicon substrate 31.
- the ion implantation amount is, for example, 1 ⁇ 10 14 to 1 ⁇ 10 15 cm ⁇ 2 , for example, 5 ⁇ 10 14 cm ⁇ 2 .
- the acceleration voltage is 2.5 kV, for example.
- a part of the implantation region 38 ′ becomes an extension region 36 (see FIG. 5G) in the pMIS formation region 42 by performing a heat treatment described later.
- a silicon nitride film is deposited around the gate electrodes 34a and 34b, and sidewalls 37 of the gate electrodes 34a and 34b are formed by an etch back method.
- the ion implantation amount is, for example, 5 ⁇ 10 14 to 2 ⁇ 10 16 cm ⁇ 2 .
- the ion implantation amount is 4 ⁇ 10 15 cm ⁇ 2 and the acceleration voltage is 8 kV.
- the ion implantation amount is 1 ⁇ 10 15 cm ⁇ 2 and the acceleration voltage is 10 kV.
- B ions are implanted into the pMIS formation region 42 in a self-aligning manner. At this time, the ion implantation amount is, for example, 5 ⁇ 10 14 to 2 ⁇ 10 16 cm ⁇ 2 , for example, 3 ⁇ 10 15 cm ⁇ 2 .
- the acceleration voltage is 2 kV.
- a rapid thermal treatment for impurity activation is performed to form a deep diffusion region 38 that becomes a source and drain region and an extension region 36.
- the temperature of the rapid heat treatment is, for example, 900 to 1100 ° C., and the time of the rapid heat treatment is, for example, 20 seconds or less.
- a layer insulating film (not shown) made of SiO 2 , BPSG, SiN or a low dielectric constant film is deposited so as to fill the periphery of the gate electrodes 34 a and 34 b and the side wall 37.
- the interlayer insulating film that is not shown in order to avoid complication is the same as the interlayer insulating film 59 in FIG. Thereby, the semiconductor device 30 of the present embodiment is completed.
- the semiconductor device 30 has the same configuration as that of FIG.
- the gate insulating film 33 since HfO 2 that is not reduced by the gate electrodes 34a and 34b is used as the gate insulating film 33, it is possible to suppress an increase in the oxygen composition in the interface layer 39a in the nMIS formation region 41 during the heat treatment.
- the work function of the gate electrode 34a is 4.0 eV, which is suitable for the gate electrode material of nMIS, so that an nMIS with a low threshold voltage can be realized, thereby increasing the speed of the transistor.
- the amount of oxygen in the interface layer 39b in the pMIS formation region 42 is larger than the amount of oxygen in the interface layer 39a in the nMIS formation region 41. Therefore, the work function of the gate electrode 34b is about 1 eV higher than the work function of the gate electrode 34a, for example, 5.1 eV, which is suitable for the gate electrode material of pMIS.
- the thickness of the TiN film forming the gate electrodes 34a and 34b is, for example, 5 nm or more, the work functions of the gate electrodes 34a and 34b do not change even if another metal film is stacked on the TiN film. Therefore, the resistance value of the gate electrodes 34a and 34b can be reduced by laminating a gate metal film having a lower resistance than that of the TiN film on the TiN film.
- any material can be used as long as the conductive film includes a group IV transition metal as a main component. May be.
- the manufacturing method of the semiconductor device of this embodiment includes the following steps.
- a gate insulating film 33 made of at least one laminated insulating film made of a metal oxide whose outermost surface is not reduced by a group IV transition metal is formed on the nMIS forming region 41 and the pMIS forming region 42 on the silicon substrate 31 which is a semiconductor substrate. Step of forming (FIGS. 4A and 4B). 2. A step of forming a gate electrode 34 made of a conductive film containing a group IV transition metal as a main component in the nMIS formation region 41 and the pMIS formation region 42 (FIG. 4C). 3. A step of selectively ion-implanting oxygen into the gate electrode 34 of the pMIS formation region 42 (FIG. 4D). 4).
- Steps of forming interface layers 39a and 39b between the gate electrode 34a and the gate insulating film 33 in the nMIS formation region 41 and between the gate electrode 34b and the gate insulating film 33 in the pMIS formation region 42 by heat treatment FIG. 4 (e)). 5.
- a step of forming respective sources and drains by implanting impurities into the surface layer portion of the silicon substrate 31 using the gate electrodes 34a and 34b as masks FIGS. 4F and 4G).
- the manufacturing method of the semiconductor device of this embodiment includes the following steps.
- First step A gate insulating film 33 made of a metal oxide whose upper surface is not reduced by a group IV transition metal is formed on a silicon substrate 31 which is a semiconductor substrate (FIGS. 4A and 4B).
- Second step A gate electrode 34 made of a conductive film containing a group IV transition metal is formed on the gate insulating film 33 (FIG. 4C).
- Third step Oxygen ions are implanted into the gate electrode 34 (FIG. 4D).
- Fourth step Interfacial layers 39a and 39b containing a group IV transition metal and oxygen are formed by heat treatment between the gate electrodes 34a and 34b and the gate insulating film 33 (FIG. 4E).
- the gate electrode 34 is divided into a gate electrode 34a (first region) in the nMIS formation region 41 and a gate electrode 34b (second region) in the pMIS formation region 42. Then, oxygen is ion-implanted into at least the gate electrode 34b of the gate electrodes 34a and 34b, so that the amount of oxygen in the gate electrode 34a is less than the amount of oxygen in the gate electrode 34b.
- the nMIS and pMIS gate electrodes 34a and 34b can be formed by resist mask and ion implantation without peeling off the electrodes, so that the quality of the gate insulating film 33 is deteriorated.
- the outermost surface layer of the gate insulating film 33 is preferably zirconium oxide or hafnium oxide. In this case, an increase in oxygen composition in the interface layer 39a particularly in nMIS can be suppressed. As a result, an nMIS with a low threshold voltage can be realized, so that the speed of the transistor can be increased.
- the other actions and effects are the same as those described in the third embodiment.
- FIG. 6 to 9 are sectional views showing a method for manufacturing a semiconductor device according to the fifth embodiment of the present invention.
- description will be given based on these drawings.
- FIGS. 6A to 9H are cross-sectional views showing the method of manufacturing the semiconductor device according to this embodiment in the order of the steps.
- This embodiment is different from the fourth embodiment described above in that a dummy gate electrode is prepared in advance, and after the activation of impurities implanted into the source and drain is completed, the dummy gate electrode is removed and a metal gate electrode is manufactured. In the point.
- an HfO 2 film having relatively low heat resistance and an HfSiO film containing Hf at a high concentration can be used as the gate insulating film.
- a low melting point metal such as Al.
- the silicate layer / SiO 2 laminated structure covered with HfO 2 having a thickness of about 0.5 nm shown in FIG. 1B is used as the gate insulating film.
- the mobility of the transistor can be kept high.
- it demonstrates in order of a process.
- the element isolation region 32 is selectively formed on the surface layer of the silicon substrate 31 as in the fourth embodiment described above. Subsequently, a silicon oxide film having a thickness of, for example, about 2 to 6 nm is formed as the dummy gate insulating film 53 to be removed in a later process.
- a polysilicon film 56 having a film thickness of, for example, about 150 nm and a silicon nitride film 57 having a film thickness of, for example, about 50 nm are sequentially formed, and a laminated film including the polysilicon film 56 and the silicon nitride film 57 is formed.
- the laminated film is patterned into an electrode shape to form a dummy gate electrode 54 to be removed in a later process.
- extension regions 36 serving as source and drain impurity diffusion layers are formed by ion implantation using the dummy gate electrode 54 as a mask. Then, heat treatment for activating the impurities is performed using the same conditions as in the fourth embodiment described above.
- a side wall 37 is formed on the side of the dummy gate electrode 54 by forming a silicon nitride film using the CVD technique and selectively removing the silicon nitride film using the RIE technique.
- the side wall 37 is made of a silicon nitride film and has a width of about 20 to 40 nm.
- diffusion regions 38 to be high-concentration impurity diffusion layers of source and drain are formed by ion implantation using the dummy gate electrode 54 and the sidewall 37 as a mask, respectively. Then, heat treatment for activating the impurities is performed using the same conditions as in the fourth embodiment described above.
- a silicide film (not shown) having a film thickness of, for example, about 40 nm is formed only in the source and drain regions by the salicide process technique using the dummy gate electrode 54 and the sidewall 37 as a mask.
- a silicon oxide film is deposited by a CVD method to form an interlayer insulating film 59. The steps so far are similar to the steps of FIGS. 4A to 5G.
- the surface of the interlayer insulating film 59 is planarized by a CMP (Chemical Mechanical Polishing) technique to expose the surface of the dummy gate electrode 54, that is, the surface of the silicon nitride film 57. .
- the silicon nitride film 57 on the dummy gate electrode 54 is selectively removed from the interlayer insulating film 59 using, for example, phosphoric acid.
- the polysilicon film 56 is exposed.
- the polysilicon film 56 is selectively removed from the layer insulating film 59 and the side wall 37 by an etching technique using radicals such as fluorine.
- the trench 58 is formed by removing the dummy gate insulating film 53 made of a silicon oxide film using wet etching such as dilute hydrofluoric acid.
- a gate insulating film 63 made of a laminated film is formed.
- the gate insulating film 63 includes a silicate layer 222 and an SiO 2 layer 223 covered with an HfO 2 layer 221 having a thickness of about 0.5 nm shown in FIG.
- the mobility of the transistor can be kept high.
- a gate electrode 64 made of an HfN film is formed on the gate insulating film 63 by using a CVD method or a sputtering method.
- the film thickness is, for example, 20 to 200 nm.
- the surface of the gate electrode 64 in the nMIS formation region 41 is covered with a mask 35, and oxygen is added from the surface of the gate electrode 64 in the pMIS formation region 42 by ion implantation. To do.
- the nMIS formation region 41 becomes a gate electrode 64 with a small amount of oxygen
- the pMIS formation region 42 becomes a gate electrode layer 64 with a large amount of oxygen.
- the interface layers 65a and 65b contain a group IV transition metal (Hf) and oxygen contained in the gate electrodes 64a and 64b, and do not contain silicon.
- Hf group IV transition metal
- the gate electrodes 64a and 64b and the gate insulating film 63 on the layer insulating film 59 are removed by flattening the whole using CMP.
- the inter-layer insulating film 59 is exposed, the final shape gate insulating film 63 and the gate electrode 64a are formed in the nMIS formation region 41, and the final shape gate insulating film 63 and the pMIS formation region 42 are formed.
- a gate electrode 64b is formed.
- HfO 2 that is not reduced by the gate electrodes 64a and 64b is used as the gate insulating film 63, it is possible to suppress an increase in the oxygen composition in the interface layer 65a in the nMIS formation region 41 during the heat treatment.
- the work function of the gate electrode 64a is 4.0 eV suitable for the gate electrode material of nMIS, nMIS with a low threshold voltage can be realized, so that the speed of the transistor can be increased.
- the interface layer 65b contains a group IV transition metal (Hf) and oxygen contained in the gate electrode 64b.
- the amount of oxygen in the interface layer 65b is larger than the amount of oxygen in the interface layer 65a. Therefore, the work function of the gate electrode 64b is about 1 eV higher than the work function of the gate electrode 64a, for example, 5.1 eV. That is, since the gate electrode 64b is suitable for a pMIS gate electrode material, it is possible to realize a pMIS with a low threshold voltage, thereby speeding up the transistor.
- the dummy gate insulating film 53 and the dummy gate electrode 54 are formed, impurities are implanted using these as a mask, heat treatment for activating the impurities is performed, and then the dummy gate insulating film 53 is formed. Then, the dummy gate electrode 54 is removed to form the gate insulating film 63 and the gate electrodes 64a and 64b. This can prevent the gate insulating film 63 and the gate electrodes 64a and 64b from being exposed to the heat treatment. As a result, an HfO 2 film having relatively low heat resistance and an HfSiO film containing Hf at a high concentration can be used as the gate insulating film 63.
- HfN is used as a material for forming the gate electrodes 64a and 64b has been described.
- any conductive film containing a group IV transition metal as a main component may be used. .
- the manufacturing method of the semiconductor device of this embodiment includes the following steps.
- a step of forming a dummy gate electrode 54 in both the nMIS formation region 41 and the pMIS formation region 42 on the silicon substrate 31 which is a semiconductor substrate (FIG. 6A). 2.
- a step of forming a source and a drain by implanting impurities into the surface layer portion of the silicon substrate 31 using the dummy gate electrode 54 as a mask (FIG. 6A).
- a step of performing a heat treatment for activating the impurities (FIG. 6A). 4).
- a step of forming an interlayer insulating film 59 so as to fill the periphery of the dummy gate electrode 54 (FIG. 6A). 5.
- a step of removing the dummy gate electrode 54 and forming a groove 58 in the interlayer insulating film 59 (FIGS. 6B and 7C). 6).
- a step of forming a gate insulating film 63 made of at least one laminated insulating film made of a metal oxide whose outermost surface is not reduced by a group IV transition metal inside the groove 58 (FIG. 7D). 7).
- a step of forming a gate electrode 64 made of a conductive film containing a group IV transition metal as a main component in the nMIS formation region 41 and the pMIS formation region 42 (FIG. 8E). 8).
- a step of selectively ion-implanting oxygen into the gate electrode 64 in the pMIS formation region 42 (FIG. 8F).
- Steps of forming interface layers 65a and 65b by heat treatment between the gate electrode 64a and the gate insulating film 63 in the nMIS formation region 41 and between the gate electrode 64b and the gate insulating film 63 in the pMIS formation region 42 (FIG. 9 (g)).
- a step of processing the gate electrodes 64a and 64b into a predetermined shape by selectively removing the excess film (FIG. 9H).
- the manufacturing method of the semiconductor device of this embodiment includes the following steps.
- First step A gate insulating film 63 made of a metal oxide whose upper surface is not reduced by a group IV transition metal is formed on a silicon substrate 31 as a semiconductor substrate (FIGS. 6A to 7D).
- Second step A gate electrode 64 made of a conductive film containing a group IV transition metal is formed on the gate insulating film 63 (FIG. 8E).
- Third step Oxygen ions are implanted into the gate electrode 64 (FIG. 8F).
- Fourth step Interfacial layers 65a and 65b containing a group IV transition metal and oxygen are formed by heat treatment between the gate electrodes 64a and 64b and the gate insulating film 63 (FIG. 9G).
- the first step includes the following steps.
- a step of forming a dummy gate electrode 54 on the silicon substrate 31 (FIG. 6A).
- a step of forming a source and a drain by implanting impurities into the surface layer portion of the silicon substrate 31 using the dummy gate electrode 54 as a mask (FIG. 6A).
- a step of performing a heat treatment for activating the impurities (FIG. 6A).
- a step of forming an interlayer insulating film 59 so as to fill the periphery of the dummy gate electrode 54 (FIG. 6A).
- a step of forming a trench 58 in the interlayer insulating film 59 by removing the dummy gate electrode 54 (FIGS. 6B and 7C).
- a step of forming a gate insulating film 63 made of a metal oxide in which at least the upper surface is not reduced by the group IV transition metal in the trench 58 (FIG. 7D).
- an HfO 2 film having relatively low heat resistance and an HfSiO film containing Hf at a high concentration can be used as the gate insulating film 63.
- the outermost surface layer of the gate insulating film 63 is zirconium oxide or hafnium oxide. In this case, it is possible to suppress an increase in oxygen composition in the interface layer particularly in nMIS. As a result, an nMIS with a low threshold voltage can be realized, so that the speed of the transistor can be increased.
- Other operations and effects are the same as those described in the third and fourth embodiments.
- the present invention has been described with reference to each of the above embodiments, but the present invention is not limited to each of the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention. Further, the present invention includes a combination of some or all of the configurations of the above-described embodiments as appropriate.
- the work function of the gate electrode can be freely controlled by changing the oxygen composition of the interface layer, thereby controlling the work function. Can contribute to the expansion.
- FIG. 1A is a cross-sectional view showing a MISFET according to the first embodiment of the present invention
- FIG. 1B is a cross-sectional view showing a MISFET according to the second embodiment of the present invention.
- 6 is a graph showing the relationship between the composition x of the interface layer ((TiN) 1-x (TiO 2 ) x ) and the effective work function of the gate electrode in the first and second embodiments. It is sectional drawing which shows the semiconductor device which concerns on 3rd embodiment of this invention.
- FIG. 10 is a cross-sectional view (No. 1) showing the method for manufacturing a semiconductor device according to the fourth embodiment of the invention, in which the steps proceed in the order of FIG. 4A to FIG.
- FIG. 1 is a cross-sectional view showing a MISFET according to the first embodiment of the present invention
- FIG. 1B is a cross-sectional view showing a MISFET according to the second embodiment of the present invention.
- 6 is a graph showing the relationship between the
- FIG. 10 is a cross-sectional view (No. 2) showing the method for manufacturing a semiconductor device according to the fourth embodiment of the invention, in which the steps proceed in the order of FIGS.
- FIG. 10 is a cross-sectional view (No. 1) showing the method for manufacturing a semiconductor device according to the fifth embodiment of the invention, in which the process proceeds in the order of FIG. 6A to FIG. 6B
- FIG. 7D is a cross-sectional view (No. 2) showing the method for manufacturing a semiconductor device according to the fifth embodiment of the invention, in which the process proceeds in the order of FIG. 7C to FIG.
- FIG. 10 is a sectional view (No. 3) showing the method for manufacturing a semiconductor device according to the fifth embodiment of the invention, in which the process proceeds in the order of FIGS. 8E to 8F
- FIG. 9D is a cross-sectional view (No. 4) showing the method for manufacturing a semiconductor device according to the fifth embodiment of the invention, in which the steps proceed in the order of FIG. 9G to FIG.
- MISFET DESCRIPTION OF SYMBOLS 11 Gate electrode 12
- Gate insulating film 13 Interface layer 14
- Semiconductor substrate 20 MISFET 22
- Semiconductor device 31 Silicon substrate 32
- Element isolation region 33 Gate insulating film 34, 34a, 34b Gate electrode 35
- Side wall 38 'Injection region 38 Diffusion region 39a, 39b Interface layer 41
- nMIS formation region 42 pMIS formation region 43
- nMIS 44 pMIS 50 Semiconductor Device 53
- Dummy Gate Insulating Film 54 Dummy Gate Electrode 56
- Silicon Nitride Film 58 Groove 59
- Interlayer Insulating Film 63 Gate Insulating Film 64, 64a, 64b Gate Electrodes 65a, 65b Interface Layer
Abstract
Disclosed is a MISFET or the like wherein the controllable range of the work function can be enlarged when a nitride or silicide of a group IV transition metal is used as a metal gate material. A MISFET (10) has a laminated structure including a gate electrode (11) and a gate insulating film (12). The gate electrode (11) is composed of a conductive film containing a group IV transition metal. At least a side of the gate insulating film (12) which is in contact with the gate electrode (11) is composed of a metal oxide which is not reduced by a group IV transition metal. An interface layer (13) between the gate electrode (11) and the gate insulating film (12) contains a group IV transition metal and oxygen. The conductive film containing a group IV transition metal is, for example, composed of a nitride or oxide of a group IV transition metal. In this connection, all the group IV transition metals are the same as the one contained in the gate electrode (11). Examples of the group IV transition metal may include Ti, Zr and Hf.
Description
本発明は、ＭＩＳ（Metal Insu1ator Semiconductor）型電界効果トランジスタ及びその製造方法並び半導体装置及びその製造方法に関1する。ここで、本発明に係る半導体装置は、本発明に係るＭＩＳ型電界効果トランジスタをｎチャネルＭＩＳ型電界効果トランジスタ及びｐチャネルＭＩＳ型電界効果トランジスタとして備えたものである。以下、「ＭＩＳ型電界効果トランジスタ」、「ｎチャネルＭＩＳ型電界効果トランジスタ」及び「ｐチャネルＭＩＳ型電界効果トランジスタ」を、それぞれ「ＭＩＳＦＥＴ（MIS Field Effect Transistor）」、「ｎＭＩＳ」及び「ｐＭＩＳ」と略称する。
The present invention relates to a MIS (Metal Insu1ator Semiconductor) type field effect transistor, a manufacturing method thereof, a semiconductor device, and a manufacturing method thereof. Here, the semiconductor device according to the present invention includes the MIS field effect transistor according to the present invention as an n-channel MIS field effect transistor and a p-channel MIS field effect transistor. Hereinafter, “MIS type field effect transistor”, “n channel MIS type field effect transistor” and “p channel MIS type field effect transistor” are respectively referred to as “MISFET (MIS Field Effect Transistor)”, “nMIS” and “pMIS”. Abbreviated.
半導体装置の集積密度を向上させて半導体装置の性能を向上させるために、半導体装置の構成要素であるＭＩＳＦＥＴの微細化が進んでいる。しかし、ＭＩＳＦＥＴを微細化すると、短チャネル効果の影響が大きくなるため、その抑制が重要な課題となっている。短チャネル効果を抑制する方法として、いわゆるスケーリング則に従った方法がいくつか提案されている。
In order to improve the integration density of semiconductor devices and improve the performance of semiconductor devices, miniaturization of MISFETs which are constituent elements of semiconductor devices is progressing. However, when the MISFET is miniaturized, the influence of the short channel effect is increased, so that suppression thereof is an important issue. As a method for suppressing the short channel effect, several methods according to a so-called scaling rule have been proposed.
その一つにゲート絶縁膜の薄膜化がある。この方法は、ゲート絶縁膜を薄くすることにより、ゲート絶縁膜への印加電圧に起因してＳｉ基板中に形成される空乏層の制御を容易にし、その結果、短チャネル効果を抑制するものである。しかし、不純物をドーピングしたポリシリコンでＭＩＳＦＥＴのゲート電極を形成する場合は、ゲート絶縁膜の薄膜化に起因して相対的にゲート電極にかかる電場が強くなるので、ゲート電極中にも空乏層が形成されることになる。この結果、ゲート絶縁膜が実質的に厚くなってしまう。
One of them is the thinning of the gate insulating film. This method makes it easy to control the depletion layer formed in the Si substrate due to the voltage applied to the gate insulating film by reducing the thickness of the gate insulating film, thereby suppressing the short channel effect. is there. However, when the gate electrode of the MISFET is formed of polysilicon doped with impurities, the electric field applied to the gate electrode is relatively strong due to the thinning of the gate insulating film, so that a depletion layer is also formed in the gate electrode. Will be formed. As a result, the gate insulating film becomes substantially thick.
このゲート電極の空乏化の問題を解決するために、ゲート電極を金属材料で形成することが提案されている。金属材料で形成されたメタルゲート電極には、前述のゲート電極の空乏化を抑制できるばかりか、ゲート電極の抵抗を低減できるとともにボロンの突き抜けを抑制できるという利点がある。このため、ＭＩＳＦＥＴの開発初期には、Ａｌ、Ｗ、ＷＴｉなどの金属からなるメタルゲート電極や、これらの金属の窒化物等からなるメタルゲート電極が使用されていた（例えば特許文献１～３参照）。
In order to solve the problem of depletion of the gate electrode, it has been proposed to form the gate electrode with a metal material. A metal gate electrode formed of a metal material has an advantage that not only the above-described depletion of the gate electrode can be suppressed, but also the resistance of the gate electrode can be reduced and the penetration of boron can be suppressed. For this reason, in the early stages of development of MISFETs, metal gate electrodes made of metals such as Al, W, WTi, and metal gate electrodes made of nitrides of these metals were used (see, for example, Patent Documents 1 to 3). ).
一方、メタルゲート電極には次のような問題点がある。例えば、Ａｌをメタルゲート電極に用いた場合は、Ａｌの融点が約６６０℃と低いため、ソース及びドレインを活性化するための４００℃以上の熱処理を行うと、メタルゲート電極が断線したりＡｌ原子が周辺領域へ拡散したりする。また、Ｗは酸化によりその特性が変化してしまう。更に、Ｗ及びＷＴｉは、酸洗浄を行うと溶解してしまう、すなわち耐洗浄性が低い。
On the other hand, the metal gate electrode has the following problems. For example, when Al is used for the metal gate electrode, the melting point of Al is as low as about 660 ° C. Therefore, if heat treatment at 400 ° C. or higher for activating the source and drain is performed, the metal gate electrode is disconnected or Al Atoms diffuse into the surrounding area. Further, the characteristics of W change due to oxidation. Furthermore, W and WTi are dissolved when acid cleaning is performed, that is, the cleaning resistance is low.
そこで、IV族遷移金属の窒化物や珪化物が、次の理由によりメタルゲート材料として注目されている。１．化学的に安定かつ高い融点を有する。２．電気伝導性が良好である。３．ＨｆＳｉＯなどの有望なｈｉｇｈ－ｋゲート絶縁膜上で、高い耐熱性を持つ。
Therefore, group IV transition metal nitrides and silicides are attracting attention as metal gate materials for the following reasons. 1. It is chemically stable and has a high melting point. 2. Good electrical conductivity. 3. High heat resistance on a promising high-k gate insulating film such as HfSiO.
しかし、IV族遷移金属の窒化物や珪化物の仕事関数はＳｉミッドギャップ付近であることにより、低しきい電圧のｎＭＩＳ及びｐＭＩＳを得るためにその仕事関数を制御する必要がある。例えば、非特許文献１では、ＴｉＮ膜をｎＭＩＳ及びｐＭＩＳのゲート電極として成膜した後に、ｎＭＩＳのゲート電極にのみに窒素をイオン注入することにより仕事関数を制御する技術が、開示されている。
However, since the work function of the nitride or silicide of the group IV transition metal is in the vicinity of the Si mid gap, it is necessary to control the work function in order to obtain nMIS and pMIS with low threshold voltages. For example, Non-Patent Document 1 discloses a technique for controlling a work function by forming a TiN film as an nMIS and pMIS gate electrode and then implanting nitrogen only into the nMIS gate electrode.
しかしながら、非特許文献１に記載の技術では、仕事関数の制御幅が±０．１ｅＶ程度と小さいため、その用途が低消費電力ＣＭＩＳ（Complementary MIS）に限られる。これに加え、絶縁膜中への窒素混入による信頼性劣化も懸念される。
However, in the technique described in Non-Patent Document 1, the work function control width is as small as about ± 0.1 eV, so that its application is limited to low power consumption CMIS (Complementary MIS). In addition to this, there is a concern about reliability deterioration due to nitrogen mixing in the insulating film.
そこで、本発明の目的は、IV族遷移金属の窒化物や珪化物をメタルゲート材料に用いた場合に、その仕事関数の制御幅を拡大できるＭＩＳＦＥＴ等を提供することを目的とする。
Therefore, an object of the present invention is to provide a MISFET or the like that can expand the control range of the work function when a nitride or silicide of a group IV transition metal is used as a metal gate material.
本発明に係るＭＩＳＦＥＴは、ゲート電極及びゲート絶縁膜の積層構造を有するＭＩＳＦＥＴにおいて、前記ゲート電極がIV族遷移金属を含む導電膜からなり、前記ゲート絶縁膜の少なくとも前記ゲート電極に接する側が前記IV族遷移金属によって還元されない金属酸化物からなり、前記ゲート電極と前記ゲート絶縁膜との間の界面層が前記IV族遷移金属及び酸素を含む、ことを特徴とする。
The MISFET according to the present invention is a MISFET having a laminated structure of a gate electrode and a gate insulating film, wherein the gate electrode is made of a conductive film containing a group IV transition metal, and at least a side of the gate insulating film in contact with the gate electrode is the IV It is made of a metal oxide that is not reduced by a group transition metal, and an interface layer between the gate electrode and the gate insulating film contains the group IV transition metal and oxygen.
本発明に係る半導体装置は、本発明に係るＭＩＳＦＥＴをｎＭＩＳ及びｐＭＩＳとして備え、前記ｎＭＩＳにおける前記界面層中の酸素組成が前記ｐＭＩＳにおける前記界面層中の酸素組成に比べて低い、ことを特徴とする。
A semiconductor device according to the present invention includes the MISFET according to the present invention as an nMIS and a pMIS, wherein an oxygen composition in the interface layer in the nMIS is lower than an oxygen composition in the interface layer in the pMIS. To do.
本発明に係るＭＩＳＦＥＴの製造方法は、ゲート電極及びゲート絶縁膜の積層構造を有するＭＩＳＦＥＴを製造する方法において、半導体基板上に少なくとも上面がIV族遷移金属によって還元されない金属酸化物からなるゲート絶縁膜を形成する第一工程と、前記ゲート絶縁膜上に前記IV族遷移金属を含む導電膜からなるゲート電極を形成する第二工程と、前記ゲート電極に対して酸素をイオン注入する第三工程と、前記ゲート電極と前記ゲート絶縁膜との間に前記IV族遷移金属及び前記酸素を含む界面層を熱処理によって形成する第四工程と、を含むことを特徴とする。
A method of manufacturing a MISFET according to the present invention is a method of manufacturing a MISFET having a stacked structure of a gate electrode and a gate insulating film. A second step of forming a gate electrode made of a conductive film containing the group IV transition metal on the gate insulating film, and a third step of ion-implanting oxygen into the gate electrode And a fourth step of forming an interface layer containing the group IV transition metal and the oxygen by heat treatment between the gate electrode and the gate insulating film.
本発明に係る半導体装置の製造方法は、本発明に係るＭＩＳＦＥＴの製造方法を用いた半導体装置の製造方法であって、前記第三工程において、前記ゲート電極をｎＭＩＳを形成する第一領域とｐＭＩＳを形成する第二領域とに分け、前記第一領域及び前記第二領域のうち少なくとも前記第二領域に対して酸素をイオン注入することにより、前記第一領域中の酸素量を前記第二領域の酸素量よりも少なくする、ことを特徴とする。
A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device using the method for manufacturing a MISFET according to the present invention. In the third step, the gate electrode is formed with a first region for forming an nMIS and a pMIS. And oxygen is ion-implanted into at least the second region of the first region and the second region, so that the amount of oxygen in the first region is reduced to the second region. The amount of oxygen is less than the amount of oxygen.
本発明によれば、ゲート絶縁膜のゲート電極に接する側をIV族遷移金属によって還元されない金属酸化物とし、ゲート電極とゲート絶縁膜との間の界面層をIV族遷移金属及び酸素を含む構成としたことにより、IV族遷移金属を含む導電膜からなるゲート電極を用いても、界面層の酸素組成を変えることによりゲート電極の仕事関数を自在に制御できるので、当該仕事関数の制御幅を拡大できる。
According to the present invention, the side of the gate insulating film that contacts the gate electrode is a metal oxide that is not reduced by the group IV transition metal, and the interface layer between the gate electrode and the gate insulating film includes the group IV transition metal and oxygen. Therefore, even if a gate electrode made of a conductive film containing a group IV transition metal is used, the work function of the gate electrode can be freely controlled by changing the oxygen composition of the interface layer. Can be expanded.
以下、本発明の実施形態を図に基づいて詳細に説明する。
図１（ａ）は本発明の第一実施形態に係るＭＩＳＦＥＴを示す断面図であり、図１（ｂ）は本発明の第二実施形態に係るＭＩＳＦＥＴを示す断面図である。以下、この図面に基づき説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1A is a cross-sectional view showing a MISFET according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view showing a MISFET according to the second embodiment of the present invention. Hereinafter, description will be given based on this drawing.
図１（ａ）は本発明の第一実施形態に係るＭＩＳＦＥＴを示す断面図であり、図１（ｂ）は本発明の第二実施形態に係るＭＩＳＦＥＴを示す断面図である。以下、この図面に基づき説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1A is a cross-sectional view showing a MISFET according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view showing a MISFET according to the second embodiment of the present invention. Hereinafter, description will be given based on this drawing.
第一実施形態のＭＩＳＦＥＴ１０は、ゲート電極１１及びゲート絶縁膜１２の積層構造を有する。ゲート電極１１は、IV族遷移金属を含む導電膜からなる。ゲート絶縁膜１２の少なくともゲート電極１１に接する側は、IV族遷移金属によって還元されない金属酸化物からなる。ゲート電極１１とゲート絶縁膜１２との間の界面層１３は、IV族遷移金属及び酸素を含む。IV族遷移金属を含む導電膜とは、例えばIV族遷移金属の窒化物や酸化物である。ここで言うIV族遷移金属は、全てゲート電極１１に含まれるものと同じである。また、IV族遷移金属は、Ｔｉ、Ｚｒ、Ｈｆなどである。なお、図１（ａ）では、半導体基板１４上のゲート電極１１及びゲート絶縁膜１２の積層構造のみを示し、ソース、ドレイン等は省略している。
The MISFET 10 of the first embodiment has a stacked structure of a gate electrode 11 and a gate insulating film 12. The gate electrode 11 is made of a conductive film containing a group IV transition metal. At least the side in contact with the gate electrode 11 of the gate insulating film 12 is made of a metal oxide that is not reduced by a group IV transition metal. The interface layer 13 between the gate electrode 11 and the gate insulating film 12 contains a group IV transition metal and oxygen. The conductive film containing a group IV transition metal is, for example, a nitride or oxide of a group IV transition metal. The group IV transition metals mentioned here are all the same as those contained in the gate electrode 11. The group IV transition metal is Ti, Zr, Hf, or the like. In FIG. 1A, only the stacked structure of the gate electrode 11 and the gate insulating film 12 on the semiconductor substrate 14 is shown, and the source, drain, and the like are omitted.
ＭＩＳＦＥＴ１０の具体例を述べる。ゲート電極１１はＴｉＮである。このＴｉＮは、Ｔｉが例えば４０～６０ａｔ％例えば５０ａｔ％であり、残りがＮである。界面層１３は（ＴｉＮ）１－ｘ（ＴｉＯ２）ｘである。ゲート絶縁膜１２は膜厚が３．０ｎｍのＨｆＯ２である。半導体基板１４はＳｉである。
A specific example of the MISFET 10 will be described. The gate electrode 11 is TiN. In this TiN, Ti is, for example, 40 to 60 at%, for example, 50 at%, and the rest is N. The interface layer 13 is (TiN) 1-x (TiO 2 ) x . The gate insulating film 12 is HfO 2 having a thickness of 3.0 nm. The semiconductor substrate 14 is Si.
ＭＩＳＦＥＴ１０の製造方法は、次の工程を含む。第一工程：半導体基板１４上に、少なくとも上面がIV族遷移金属によって還元されない金属酸化物からなるゲート絶縁膜１２を形成する。第二工程：ゲート絶縁膜１２上に、IV族遷移金属を含む導電膜からなるゲート電極１１を形成する。第三工程：ゲート電極１１に対して酸素をイオン注入する。第四工程：ゲート電極１１とゲート絶縁膜１２との間に、IV族遷移金属及び酸素を含む界面層１３を熱処理によって形成する。例えば、第一工程は図４（ａ）（ｂ）に相当し、第二工程は図４（ｃ）に相当し、第三工程は図４（ｄ）に相当し、第四工程は図４（ｅ）に相当する。
The manufacturing method of the MISFET 10 includes the following steps. First step: A gate insulating film 12 made of a metal oxide whose upper surface is not reduced by a group IV transition metal is formed on the semiconductor substrate 14. Second step: A gate electrode 11 made of a conductive film containing a group IV transition metal is formed on the gate insulating film 12. Third step: Oxygen ions are implanted into the gate electrode 11. Fourth step: An interface layer 13 containing a group IV transition metal and oxygen is formed between the gate electrode 11 and the gate insulating film 12 by heat treatment. For example, the first process corresponds to FIGS. 4 (a) and 4 (b), the second process corresponds to FIG. 4 (c), the third process corresponds to FIG. 4 (d), and the fourth process corresponds to FIG. It corresponds to (e).
第二実施形態のＭＩＳＦＥＴ２０は、ゲート電極１１及びゲート絶縁膜２２の積層構造を有する。ゲート電極１１は、IV族遷移金属を含む導電膜からなる。ゲート絶縁膜２２の少なくともゲート電極１１に接する側は、IV族遷移金属によって還元されない金属酸化物からなる。ゲート電極１１とゲート絶縁膜２２との間の界面層１３は、IV族遷移金属及び酸素を含む。IV族遷移金属を含む導電膜とは、例えばIV族遷移金属の窒化物や酸化物である。ここで言うIV族遷移金属は、全てゲート電極１１に含まれるものと同じである。また、IV族遷移金属は、Ｔｉ、Ｚｒ、Ｈｆなどである。なお、図１（ｂ）では、半導体基板１４上のゲート電極１１及びゲート絶縁膜２２の積層構造のみを示し、ソース、ドレイン等は省略している。
The MISFET 20 of the second embodiment has a laminated structure of the gate electrode 11 and the gate insulating film 22. The gate electrode 11 is made of a conductive film containing a group IV transition metal. At least the side in contact with the gate electrode 11 of the gate insulating film 22 is made of a metal oxide that is not reduced by a group IV transition metal. The interface layer 13 between the gate electrode 11 and the gate insulating film 22 contains a group IV transition metal and oxygen. The conductive film containing a group IV transition metal is, for example, a nitride or oxide of a group IV transition metal. The group IV transition metals mentioned here are all the same as those contained in the gate electrode 11. The group IV transition metal is Ti, Zr, Hf, or the like. In FIG. 1B, only the stacked structure of the gate electrode 11 and the gate insulating film 22 on the semiconductor substrate 14 is shown, and the source, drain, and the like are omitted.
ＭＩＳＦＥＴ２０の具体例を述べる。ゲート電極１１はＴｉＮである。このＴｉＮは、Ｔｉが例えば４０～６０ａｔ％例えば５０ａｔ％であり、残りがＮである。界面層１３は（ＴｉＮ）１－ｘ（ＴｉＯ２）ｘである。ゲート絶縁膜２２は、膜厚が０．５ｎｍのＨｆＯ２層２２１と、膜厚が３．０ｎｍの下地Ｈｆシリケート層２２２と、膜厚が０．５ｎｍのＳｉＯ２層２２３との積層膜である。ＨｆＯ２層２２１がゲート電極１１に接する側である。半導体基板１４はＳｉである。ＭＩＳＦＥＴ２０の製造方法は、前述したＭＩＳＦＥＴ１０の製造方法に準ずる。
A specific example of the MISFET 20 will be described. The gate electrode 11 is TiN. In this TiN, Ti is, for example, 40 to 60 at%, for example, 50 at%, and the rest is N. The interface layer 13 is (TiN) 1-x (TiO 2 ) x . The gate insulating film 22 is a stacked film of an HfO 2 layer 221 having a thickness of 0.5 nm, an underlying Hf silicate layer 222 having a thickness of 3.0 nm, and an SiO 2 layer 223 having a thickness of 0.5 nm. . The HfO 2 layer 221 is on the side in contact with the gate electrode 11. The semiconductor substrate 14 is Si. The manufacturing method of the MISFET 20 is in accordance with the manufacturing method of the MISFET 10 described above.
図２は、第一及び第二実施形態における界面層（（ＴｉＮ）１－ｘ（ＴｉＯ２）ｘ）の組成ｘとゲート電極の実効仕事関数との関係を示すグラフである。以下、図１及び図２に基づき説明する。
FIG. 2 is a graph showing the relationship between the composition x of the interface layer ((TiN) 1-x (TiO 2 ) x ) and the effective work function of the gate electrode in the first and second embodiments. Hereinafter, a description will be given based on FIG. 1 and FIG.
本発明者等は、前述の課題を解決するために鋭意実験研究を重ね、IV族遷移金属を主成分として含む導電膜により形成されるゲート電極１１の実効的な仕事関数がゲート電極１１とゲート絶縁膜１２との間に存在する界面層１３によって決定されていることを、以下のような実験に基づいて見出した。これにより、ｎＭＩＳのゲート電極１１とｐＭＩＳのゲート電極１１とを、作り分けることができることを確認した。
In order to solve the above-mentioned problems, the present inventors have conducted extensive experimental research, and the effective work function of the gate electrode 11 formed of a conductive film containing a group IV transition metal as a main component is the gate electrode 11 and the gate. It was found based on the following experiment that it was determined by the interface layer 13 existing between the insulating film 12. Thus, it was confirmed that the nMIS gate electrode 11 and the pMIS gate electrode 11 can be formed separately.
本実験では、図１（ａ）に示すゲート電極１１及びゲート絶縁膜１２の積層構造として、ＴｉＮ／ＨｆＯ２積層構造を用いた。そして、界面層１３の形成を制御するために、ＴｉＮの上からイオン注入法を用いて酸素を注入した。すなわち、界面層１３は、イオン注入法によってＴｉＮ／ＨｆＯ２界面に形成された。
In this experiment, a TiN / HfO 2 laminated structure was used as the laminated structure of the gate electrode 11 and the gate insulating film 12 shown in FIG. Then, in order to control the formation of the interface layer 13, oxygen was implanted from above TiN using an ion implantation method. That is, the interface layer 13 was formed at the TiN / HfO 2 interface by ion implantation.
図２は、界面層１３（（ＴｉＮ）１－ｘ（ＴｉＯ２）ｘ）の組成ｘをＸ軸とし、ゲート電極１１の実効仕事関数をＹ軸として、これらの関係を表している。図２に明らかなように、ゲート電極１１の仕事関数は、組成ｘの増大に伴いすなわちその酸素組成の増加に伴い増大する。
FIG. 2 shows the relationship between the composition x of the interface layer 13 ((TiN) 1-x (TiO 2 ) x ) as the X axis and the effective work function of the gate electrode 11 as the Y axis. As apparent from FIG. 2, the work function of the gate electrode 11 increases as the composition x increases, that is, as the oxygen composition increases.
このため、界面層１３においてｎＭＩＳの酸素組成をｐＭＩＳの酸素組成に比べて低くすれば、基本的に同じ材質のゲート電極１１を用いてｎＭＩＳ及びｐＭＩＳのそれぞれに適した実効仕事関数を実現できる。その結果、低コストに半導体装置を製造できる。また、界面層１３は高い耐熱性を持つため、汎用のメタルゲートトランジスタではできなかったゲート電極形成後の高熱処理が可能となる。このことにより、トランジスタ形成の際セルフアラインプロセスを用いることができるため、微細かつ高速なトランジスタが実現できる。
For this reason, if the oxygen composition of nMIS in the interface layer 13 is made lower than that of pMIS, an effective work function suitable for each of nMIS and pMIS can be realized using the gate electrode 11 made of the same material. As a result, a semiconductor device can be manufactured at low cost. Further, since the interface layer 13 has high heat resistance, high heat treatment after the formation of the gate electrode, which was not possible with a general-purpose metal gate transistor, can be performed. Thus, since a self-alignment process can be used when forming the transistor, a fine and high-speed transistor can be realized.
また、図２に示すように、ｎＭＩＳにおける界面層１３の組成を（ＴｉＮ）１－ｘ（ＴｉＯ２）ｘと表した場合、ｘを０．５以上かつ０．６８以下とすると、ゲート電極１１の実効的な仕事関数はｎＭＩＳに適した４～４．４ｅＶ程度になる。よって、化学的に安定なIV族遷移金属を主成分として含む導電膜を用いて、ｎＭＩＳを実現できる。更に、ｘを０．５以上かつ０．５８以下とすると、ゲート電極１１の実効的な仕事関数は４～４．２ｅＶ程度になる。その結果、低いしきい値電圧を持つｎＭＩＳを実現できるので、トランジスタをより高速化できる。
As shown in FIG. 2, when the composition of the interface layer 13 in nMIS is expressed as (TiN) 1-x (TiO 2 ) x , when x is 0.5 or more and 0.68 or less, the gate electrode 11 The effective work function is about 4 to 4.4 eV suitable for nMIS. Therefore, nMIS can be realized by using a conductive film containing a chemically stable group IV transition metal as a main component. Further, when x is 0.5 or more and 0.58 or less, the effective work function of the gate electrode 11 is about 4 to 4.2 eV. As a result, an nMIS having a low threshold voltage can be realized, so that the speed of the transistor can be increased.
一方、図２に示すように、ｐＭＩＳにおける界面層１３の組成を（ＴｉＮ）１－ｘ（ＴｉＯ２）ｘと表した場合、ｘを０．８４以上かつ０．９７以下にすると、ゲート電極１１の実効的な仕事関数はｐＭＩＳに適した４．７～５．１ｅＶ程度になる。よって、化学的に安定なIV族遷移金属を主成分として含む導電膜を用いて、ｐＭＩＳを実現できる。更に、ｘを０．９２以上かつ０．９７以下にすると、ゲート電極１１の実効的な仕事関数は４．９～５．１ｅＶ程度になる。その結果、低いしきい値電圧を持つｐＭＩＳを実現できるので、トランジスタをより高速化できる。
On the other hand, as shown in FIG. 2, when the composition of the interface layer 13 in the pMIS is expressed as (TiN) 1-x (TiO 2 ) x , when x is 0.84 or more and 0.97 or less, the gate electrode 11 The effective work function of is about 4.7 to 5.1 eV suitable for pMIS. Therefore, pMIS can be realized by using a conductive film containing a chemically stable group IV transition metal as a main component. Further, when x is 0.92 or more and 0.97 or less, the effective work function of the gate electrode 11 is about 4.9 to 5.1 eV. As a result, a pMIS having a low threshold voltage can be realized, so that the speed of the transistor can be increased.
以上の結果は、ゲート絶縁膜１２の表面がゲート電極１１によって還元されないことに起因する。そのため、ゲート絶縁膜１２の代わりに図１（ｂ）に示すゲート絶縁膜２２、すなわち上面が膜厚０．５ｎｍ程度のＨｆＯ２層２２１に覆われたシリケート層２２２及びＳｉＯ２層２２３の積層構造を用いてもよい。すなわち、図１（ｂ）のＭＩＳＦＥＴ２０の構成でも、同様の実験結果が得られた。また、ゲート電極１１として他のIV族遷移金属の窒化物や酸化物を用いた場合でも、同様な効果が得られる。
The above results are due to the fact that the surface of the gate insulating film 12 is not reduced by the gate electrode 11. Therefore, instead of the gate insulating film 12, the gate insulating film 22 shown in FIG. 1B, that is, a laminated structure of the silicate layer 222 and the SiO 2 layer 223 whose upper surface is covered with the HfO 2 layer 221 having a thickness of about 0.5 nm. May be used. That is, similar experimental results were obtained with the configuration of the MISFET 20 of FIG. The same effect can be obtained even when another group IV transition metal nitride or oxide is used as the gate electrode 11.
また、セルフアラインプロセスで微細ＣＭＩＳを作製する場合、ゲート電極１１を形成後に１０００℃程度の熱処理が必要になることから、ゲート絶縁膜１２がジルコニウム又はハフニウムを含むことが好ましい。その理由は、ジルコニウム又はハフニウムを含むゲート絶縁膜１２が耐熱性に優れるからである。更に、ゲート絶縁膜１２が酸化ジルコニウム又は酸化ハフニウムであれば、特にｎＭＩＳにおける界面層１３中の酸素組成の増加を効果的に抑制できる。その結果、低いしきい値電圧のｎＭＩＳを実現できるので、トランジスタをより高速化できる。
Further, when a fine CMIS is produced by a self-alignment process, it is preferable that the gate insulating film 12 contains zirconium or hafnium because a heat treatment at about 1000 ° C. is necessary after forming the gate electrode 11. This is because the gate insulating film 12 containing zirconium or hafnium is excellent in heat resistance. Furthermore, if the gate insulating film 12 is zirconium oxide or hafnium oxide, an increase in oxygen composition in the interface layer 13 in the nMIS can be effectively suppressed. As a result, nMIS with a low threshold voltage can be realized, so that the speed of the transistor can be increased.
図３は、本発明の第三実施形態に係る半導体装置を示す断面図である。以下、この図面に基づき説明する。
FIG. 3 is a sectional view showing a semiconductor device according to the third embodiment of the present invention. Hereinafter, description will be given based on this drawing.
本実施形態の半導体装置３０においては、シリコン基板３１の表層部に素子分離領域３２が選択的に形成されている。素子分離領域３２にはＳｉＯ２等の絶縁膜が埋め込まれており、複数の素子分離領域３２の相互間がｎＭＩＳ形成領域４１及びｐＭＩＳ形成領域４２となっている。素子分離領域３２の深さは例えば１００～５００ｎｍであり、複数の素子分離領域３２相互の距離は例えば０．０５～１０μｍである。
In the semiconductor device 30 of this embodiment, the element isolation region 32 is selectively formed in the surface layer portion of the silicon substrate 31. An insulating film such as SiO 2 is embedded in the element isolation region 32, and an nMIS formation region 41 and a pMIS formation region 42 are formed between the plurality of element isolation regions 32. The depth of the element isolation region 32 is, for example, 100 to 500 nm, and the distance between the plurality of element isolation regions 32 is, for example, 0.05 to 10 μm.
シリコン基板３１の表層部におけるｎＭＩＳ形成領域４１及びｐＭＩＳ形成領域４２には、それぞれ一対の拡散領域３８が形成されている。拡散領域３８は、シリコン基板３１に不純物イオンを注入することにより形成された領域であり、素子分離領域３２に隣接するように形成されている。拡散領域３８の寸法の一例を述べれば、幅が０．１～１０μｍ例えば０．２μｍであり、深さが５０～５００ｎｍ例えば１００ｎｍであり、不純物濃度が１０１９～１０２１ｃｍ－３である。
A pair of diffusion regions 38 is formed in each of the nMIS formation region 41 and the pMIS formation region 42 in the surface layer portion of the silicon substrate 31. The diffusion region 38 is a region formed by implanting impurity ions into the silicon substrate 31 and is formed adjacent to the element isolation region 32. An example of the dimensions of the diffusion region 38 is that the width is 0.1 to 10 μm, for example 0.2 μm, the depth is 50 to 500 nm, for example 100 nm, and the impurity concentration is 10 19 to 10 21 cm −3 .
拡散領域３８に隣接し素子分離領域３２とともに拡散領域３８を挟むように、エクステンション領域３６が形成されている。エクステンション領域３６も、シリコン基板３１に不純物をイオン注入することにより形成された領域である。エクステンション領域３６の不純物濃度は、拡散領域３８と同等か又は拡散領域３８よりも低くなっている。エクステンション領域３６の寸法の一例を述べれば、幅が６０ｎｍであり、深さが５～２００ｎｍであり、不純物濃度が１０１９～１０２１ｃｍ－３である。
An extension region 36 is formed so as to be adjacent to the diffusion region 38 and sandwich the diffusion region 38 together with the element isolation region 32. The extension region 36 is also a region formed by ion implantation of impurities into the silicon substrate 31. The impurity concentration of the extension region 36 is equal to or lower than that of the diffusion region 38. To describe an example of the dimensions of the extension region 36, the width is 60 nm, the depth is 5 to 200 nm, and the impurity concentration is 10 19 to 10 21 cm −3 .
シリコン基板３１上のｎＭＩＳ形成領域４１及びｐＭＩＳ形成領域４２には、ゲート絶縁膜３３が形成されている。ゲート絶縁膜３３は、例えばＨｆＯ２である。
A gate insulating film 33 is formed in the nMIS formation region 41 and the pMIS formation region 42 on the silicon substrate 31. The gate insulating film 33 is, for example, HfO 2 .
ゲート絶縁膜３３上には、メタルゲート電極であるゲート電極３４ａ，３４ｂが形成されている。ゲート電極３４ａ，３４ｂの厚さは、例えば２０～２００ｎｍであり、例えば５０～１００ｎｍである。ゲート電極３４ａ，３４ｂは、例えばＴｉＮである。
On the gate insulating film 33, gate electrodes 34a and 34b which are metal gate electrodes are formed. The thickness of the gate electrodes 34a and 34b is, for example, 20 to 200 nm, for example, 50 to 100 nm. The gate electrodes 34a and 34b are, for example, TiN.
ゲート電極３４ａとゲート絶縁膜３３との間、及びゲート電極３４ｂとゲート絶縁膜３３との間には、それぞれIV族遷移金属及び酸素を含む界面層３９ａ，３９ｂが形成されている。界面層３９ａ，３９ｂ中のIV族遷移金属は、ゲート電極３４ａ，３４ｂに含まれるものと同じである。ゲート電極３４ａ下の界面層３９ａ中における酸素量は、ゲート電極３４ｂ下の界面層３９ｂ中における酸素量に比べて低い。その結果、ゲート電極３４ａの仕事関数はｎＭＩＳのゲート電極材料に適した４．０～４．４ｅＶとなっており、ゲート電極４３ｂの仕事関数はｐＭＩＳのゲート電極材料に適した４．７～５．１ｅＶとなっている。なお、界面層３９ａ，３９ｂについては、薄いためにその厚みの図示を省略しているが、その具体的な構造は図１における界面層１３と同様である。
Interfacial layers 39a and 39b containing a group IV transition metal and oxygen are formed between the gate electrode 34a and the gate insulating film 33 and between the gate electrode 34b and the gate insulating film 33, respectively. The group IV transition metal in the interface layers 39a and 39b is the same as that contained in the gate electrodes 34a and 34b. The amount of oxygen in the interface layer 39a under the gate electrode 34a is lower than the amount of oxygen in the interface layer 39b under the gate electrode 34b. As a result, the work function of the gate electrode 34a is 4.0 to 4.4 eV suitable for the gate electrode material of nMIS, and the work function of the gate electrode 43b is 4.7 to 5 suitable for the gate electrode material of pMIS. .1 eV. The interface layers 39a and 39b are not shown because of their thinness, but their specific structure is the same as that of the interface layer 13 in FIG.
ゲート電極３４ａ，３４ｂの周囲には、それぞれ側壁３７が形成されている。側壁３７は、例えばシリコン窒化膜によって形成されている。ゲート電極３４ａ，３４ｂ及び側壁３７の周囲を埋めるように、ＳｉＯ２、ＢＰＳＧ（Borophosphosilicate Glass）、ＳｉＮ又は低誘電率膜からなる層間絶縁膜（図示せず）形成されている。煩雑化を避けるために図示しなかった層間絶縁膜は、図６（ａ）における層間絶縁膜５９と同様のものである。ゲート電極３４ａ，３４ｂの上面は、層間絶縁膜の上面において露出している。
Side walls 37 are formed around the gate electrodes 34a and 34b. The side wall 37 is formed of, for example, a silicon nitride film. An interlayer insulating film (not shown) made of SiO 2 , BPSG (Borophosphosilicate Glass), SiN, or a low dielectric constant film is formed so as to fill the periphery of the gate electrodes 34 a and 34 b and the side wall 37. The interlayer insulating film that is not shown in order to avoid complication is the same as the interlayer insulating film 59 in FIG. The upper surfaces of the gate electrodes 34a and 34b are exposed on the upper surface of the interlayer insulating film.
このような構成により、ｎＭＩＳ形成領域４１では、シリコン基板３１、一対の拡散領域３８、一対のエクステンション領域３６、ゲート絶縁膜３３、界面層３９ａ、ゲート電極３４ａ及び側壁３７から、ｎＭＩＳ４３が形成されている。一対の拡散領域３８はそれぞれソース及びドレインとなっており、ソース及びドレインの間がチャネル領域となっている。同様に、ｐＭＩＳ形成領域４２では、シリコン基板３１、一対の拡散領域３８、一対のエクステンション領域３６、ゲート絶縁膜３３、界面層３９ｂ、ゲート電極３４ｂ及び側壁３７から、ｐＭＩＳ４４が形成されている。
With this configuration, in the nMIS formation region 41, the nMIS 43 is formed from the silicon substrate 31, the pair of diffusion regions 38, the pair of extension regions 36, the gate insulating film 33, the interface layer 39a, the gate electrode 34a, and the side wall 37. Yes. The pair of diffusion regions 38 are a source and a drain, respectively, and a channel region is formed between the source and the drain. Similarly, in the pMIS formation region 42, a pMIS 44 is formed from the silicon substrate 31, the pair of diffusion regions 38, the pair of extension regions 36, the gate insulating film 33, the interface layer 39b, the gate electrode 34b, and the sidewall 37.
ｎＭＩＳ形成領域４１において、ゲート電極３４ａに電圧が印加されると、ゲート絶縁膜３３を介してチャネル領域に電界が印加され、チャネル領域のキャリア濃度が変化する。これにより、ソース・ドレイン間を流れる電流が変化する。同様に、ｐＭＩＳ形成領域４２において、ゲート電極３４ｂに電圧が印加されると、ソース・ドレイン間を流れる電流が変化する。
In the nMIS formation region 41, when a voltage is applied to the gate electrode 34a, an electric field is applied to the channel region via the gate insulating film 33, and the carrier concentration in the channel region changes. As a result, the current flowing between the source and the drain changes. Similarly, when a voltage is applied to the gate electrode 34b in the pMIS formation region 42, the current flowing between the source and the drain changes.
次に、本実施形態の半導体装置３０について、更に詳しく説明する。
Next, the semiconductor device 30 of this embodiment will be described in more detail.
半導体装置３０は、ｎＭＩＳ４３及びｐＭＩＳ４４を有する。ｎＭＩＳ４３のゲート電極３４ａ及びｐＭＩＳ４４のゲート電極３４ｂは、それぞれIV族遷移金属を主成分として含む導電膜からなる。ゲート絶縁膜３３の少なくとも表面は、IV族遷移金属によって還元されない金属酸化物からなる。ゲート電極３４ａ下の界面層３９ａ及びゲート電極３４ｂ下の界面層３９ｂは、それぞれゲート電極３４ａ，３４ｂに含まれるIV族遷移金属及び酸素を含む。界面層３９ａ中の酸素組成は、界面層３９ｂ中の酸素組成に比べて低い。
The semiconductor device 30 has an nMIS 43 and a pMIS 44. The gate electrode 34a of the nMIS 43 and the gate electrode 34b of the pMIS 44 are each made of a conductive film containing a group IV transition metal as a main component. At least the surface of the gate insulating film 33 is made of a metal oxide that is not reduced by a group IV transition metal. The interface layer 39a under the gate electrode 34a and the interface layer 39b under the gate electrode 34b contain a group IV transition metal and oxygen contained in the gate electrodes 34a and 34b, respectively. The oxygen composition in the interface layer 39a is lower than the oxygen composition in the interface layer 39b.
IV族遷移金属を主成分として含む導電膜の仕事関数は、その酸素組成の増加に伴い増大する（図２参照）。そのため、界面層３９ａ，３９ｂの存在により、ゲート電極３４ａ，３４ｂの実効的な仕事関数は、ｎＭＩＳ４３で４～４．４ｅＶ程度になり、ｐＭＩＳ４４で４．７～５ｅＶ程度になる。また、ゲート絶縁膜３３の表面を、IV族遷移金属によって還元されない金属酸化物とすることによって、特にｎＭＩＳ４４における界面層３９ａ中の酸素組成の増加を抑制できる。その結果、低いしきい値電圧のｎＭＩＳ４４を実現できるので、トランジスタを高速化できる。
The work function of a conductive film containing a group IV transition metal as a main component increases as the oxygen composition increases (see FIG. 2). Therefore, due to the presence of the interface layers 39a and 39b, the effective work function of the gate electrodes 34a and 34b is about 4 to 4.4 eV for the nMIS 43 and about 4.7 to 5 eV for the pMIS 44. Further, by making the surface of the gate insulating film 33 a metal oxide that is not reduced by a group IV transition metal, an increase in oxygen composition in the interface layer 39a particularly in the nMIS 44 can be suppressed. As a result, the nMIS 44 having a low threshold voltage can be realized, so that the speed of the transistor can be increased.
また、これらの界面層３９ａ，３９ｂは高い耐熱性を持つため、汎用のメタルゲートトランジスタでは行えなかったゲート電極３４ａ，３４ｂ形成後の高熱処理を行える。このことにより、トランジスタ形成の際にセルフアラインプロセスを用いることができるため、微細かつ高速なトランジスタが実現できる。更に、ｎＭＩＳ４３及びｐＭＩＳ４４のゲート電極３４ａ，３４ｂが基本的に同じ材質であるので、低コストで半導体装置３０を製造できる。
In addition, since these interface layers 39a and 39b have high heat resistance, high heat treatment can be performed after the formation of the gate electrodes 34a and 34b, which was not possible with a general-purpose metal gate transistor. Thus, since a self-alignment process can be used when forming the transistor, a fine and high-speed transistor can be realized. Furthermore, since the gate electrodes 34a and 34b of the nMIS 43 and the pMIS 44 are basically made of the same material, the semiconductor device 30 can be manufactured at low cost.
特に、ゲート電極３４ａ，３４ｂを構成するIV族遷移金属がチタンである場合、加工が容易なため微細なトランジスタが実現でき、これにより製造コストの低減や歩留まりの向上が実現できる。
In particular, when the group IV transition metal constituting the gate electrodes 34a and 34b is titanium, since it is easy to process, a fine transistor can be realized, thereby reducing the manufacturing cost and improving the yield.
また、ゲート電極３４ａ，３４ｂを構成するIV族遷移金属が窒化チタン（ＴｉＮ）である場合、ｎＭＩＳ４２のゲート電極３４ａとゲート絶縁膜３３との間に存在する界面層３９ａの組成を（ＴｉＮ）１－ｘ（ＴｉＯ２）ｘと表す。このとき、ｘが０．５以上かつ０．６８以下であれば、ゲート電極３４ａの実効的な仕事関数がｎＭＩＳ４３に適した４～４．４ｅＶ程度になる。よって、化学的に安定なIV族遷移金属を主成分として含む導電膜を用いて、ｎＭＩＳ４３を実現できる。更に、ｘが０．５以上かつ０．５８以下であれば、ゲート電極３４ａの実効的な仕事関数が４～４．２ｅＶ程度になる。その結果、低いしきい値電圧を持つｎＭＩＳ４３を実現できるので、トランジスタを高速化できる。
Further, when the group IV transition metal constituting the gate electrodes 34a and 34b is titanium nitride (TiN), the composition of the interface layer 39a existing between the gate electrode 34a of the nMIS 42 and the gate insulating film 33 is (TiN) 1. −x (TiO 2 ) x . At this time, if x is 0.5 or more and 0.68 or less, the effective work function of the gate electrode 34a is about 4 to 4.4 eV suitable for the nMIS 43. Therefore, the nMIS 43 can be realized by using a conductive film containing a chemically stable group IV transition metal as a main component. Further, when x is 0.5 or more and 0.58 or less, the effective work function of the gate electrode 34a is about 4 to 4.2 eV. As a result, the nMIS 43 having a low threshold voltage can be realized, so that the speed of the transistor can be increased.
一方、ｐＭＩＳ４４のゲート電極３４ｂとゲート絶縁膜３３との間に存在する界面層３９ｂの組成を（ＴｉＮ）１－ｘ（ＴｉＯ２）ｘと表す。このとき、ｘが０．８４以上かつ０．９７以下であれば、ゲート電極３４ｂの実効的な仕事関数がｐＭＩＳ４４に適した４．７～５．１ｅＶ程度になる。よって、化学的に安定なIV族遷移金属を主成分として含む導電膜を用いて、ｐＭＩＳ４４を実現できる。更に、ｘが０．９２以上かつ０．９７以下であれば、ゲート電極３４ｂの実効的な仕事関数が４．９～５．１ｅＶ程度になる。その結果、低いしきい値電圧を持つｐＭＩＳ４４を実現できるので、トランジスタを高速化できる。
On the other hand, the composition of the interface layer 39b existing between the gate electrode 34b of the pMIS 44 and the gate insulating film 33 is represented as (TiN) 1-x (TiO 2 ) x . At this time, if x is 0.84 or more and 0.97 or less, the effective work function of the gate electrode 34b is about 4.7 to 5.1 eV suitable for the pMIS 44. Therefore, the pMIS 44 can be realized by using a conductive film containing a chemically stable group IV transition metal as a main component. Further, when x is 0.92 or more and 0.97 or less, the effective work function of the gate electrode 34b is about 4.9 to 5.1 eV. As a result, the pMIS 44 having a low threshold voltage can be realized, and the speed of the transistor can be increased.
また、ゲート絶縁膜３３の表面は、はジルコニウム又はハフニウムの少なくとも一方を含むことが好ましい。ゲート絶縁膜３３がジルコニウム又はハフニウムを含むことによって、ゲート絶縁膜３３の安定性が高まるため歩留まりが向上する。特に、ゲート絶縁膜３３の表面は酸化ジルコニウム又は酸化ハフニウムであることが好ましい。その理由は、ｎＭＩＳ４３における界面層３９ａ中の酸素組成の増加を抑制できるからである。その結果、低いしきい値電圧のｎＭＩＳ４３を実現できるので、トランジスタを高速化できる。
Further, the surface of the gate insulating film 33 preferably contains at least one of zirconium and hafnium. When the gate insulating film 33 contains zirconium or hafnium, the stability of the gate insulating film 33 is increased, so that the yield is improved. In particular, the surface of the gate insulating film 33 is preferably zirconium oxide or hafnium oxide. This is because an increase in oxygen composition in the interface layer 39a in the nMIS 43 can be suppressed. As a result, since the nMIS 43 having a low threshold voltage can be realized, the speed of the transistor can be increased.
以上詳述したように、半導体装置３０によれば次の効果を奏する。
As described in detail above, the semiconductor device 30 has the following effects.
半導体装置３０では、ゲート電極３４ａ，３４ｂによって還元されることのないゲート絶縁膜３３とIV族遷移金属を含むゲート電極３４ａ，３４ｂとが、IV族遷移金属及び酸素を含む界面層３９ａ，３９ｂを介して接している。そして、ｎＭＩＳ４３のゲート電極３４ａとゲート絶縁膜３３との間に存在する界面層３９ａ中の酸素組成は、ｐＭＩＳ４４のゲート電極３４ｂとゲート絶縁膜３３との間に存在する界面層３９ｂ中の酸素組成に比べ低くなっている。
In the semiconductor device 30, the gate insulating film 33 that is not reduced by the gate electrodes 34 a and 34 b and the gate electrodes 34 a and 34 b containing a group IV transition metal form interface layers 39 a and 39 b containing a group IV transition metal and oxygen. Is touching through. The oxygen composition in the interface layer 39a existing between the gate electrode 34a of the nMIS 43 and the gate insulating film 33 is the oxygen composition in the interface layer 39b existing between the gate electrode 34b of the pMIS 44 and the gate insulating film 33. It is lower than
このような構成をとることにより、ｎＭＩＳ４３における界面層３９ａ中の酸素組成の増加を抑制できるので、４．０ｅＶ程度の仕事関数を実現できる。その結果、低いしきい値電圧のｎＭＩＳ４３を実現できるので、ｎチャネル型トランジスタを高速化できる。
By adopting such a configuration, an increase in oxygen composition in the interface layer 39a in the nMIS 43 can be suppressed, so that a work function of about 4.0 eV can be realized. As a result, the nMIS 43 having a low threshold voltage can be realized, and the speed of the n-channel transistor can be increased.
また、ｐＭＩＳ４４の界面層３９ｂはｎＭＩＳ４３中の界面層３９ａに比べ酸素を多く含むため、ゲート電極３４ｂの仕事関数が５ｅＶ程度となるので、ｐＭＩＳ４４の高速動作を実現できる。更に、ｎＭＩＳ４３とｐＭＩＳ４４とで基本的に同じ材質のゲート電極３４ａ，３４ｂを用いて各ＭＩＳＦＥＴに適した実効仕事関数を実現できるので、低コストに半導体装置３０を製造できる。これらのメタルゲート電極であるゲート電極３４ａ，３４ｂは、ゲート電極空乏化が起こらないため、ゲート長が０．１μｍ以下の半導体装置３０の高速化に適している。
Further, since the interface layer 39b of the pMIS 44 contains more oxygen than the interface layer 39a in the nMIS 43, the work function of the gate electrode 34b is about 5 eV, so that the pMIS 44 can be operated at high speed. Furthermore, since the effective work function suitable for each MISFET can be realized by using the gate electrodes 34a and 34b made of the same material in the nMIS 43 and the pMIS 44, the semiconductor device 30 can be manufactured at low cost. Since these gate electrodes 34a and 34b, which are metal gate electrodes, do not deplete the gate electrode, they are suitable for increasing the speed of the semiconductor device 30 having a gate length of 0.1 μm or less.
図４及び図５は、本発明の第四実施形態に係る半導体装置の製造方法を示す断面図である。以下、これらの図面に基づき説明する。
4 and 5 are sectional views showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. Hereinafter, description will be given based on these drawings.
図４（ａ）乃至図５（ｇ）は、本実施形態に係る半導体装置の製造方法をその工程順に示す断面図である。まず、図４（ａ）に示すように、シリコン基板３１の表層部に絶縁膜を選択的に埋め込み、素子分離領域３２を形成する。素子分離領域３２は、例えばＬＯＣＯＳ（Local Oxidation of Si1icon）法又はＳＴＩ（Shallow Trench Isolation）法を用いて形成する。
4A to 5G are cross-sectional views showing the method of manufacturing the semiconductor device according to this embodiment in the order of the steps. First, as shown in FIG. 4A, an insulating film is selectively embedded in the surface layer portion of the silicon substrate 31 to form an element isolation region 32. The element isolation region 32 is formed by using, for example, a LOCOS (Local Oxidation of Si1icon) method or an STI (Shallow Trench Isolation) method.
続いて、図４（ｂ）に示すように、スパッタリング法又はＣＶＤ（Chemical Vapor Deposition）法等の方法を用いて、ＨｆＯ２膜からなるゲート絶縁膜３３を成膜する。その膜厚は例えば３ｎｍ程度である。続いて、図４（ｃ）に示すように、スパッタリング法又はＣＶＤ法等の方法を用いて、ＴｉＮ膜からなるゲート電極３４を成膜する。その膜厚は例えば２０～２００ｎｍである。
Subsequently, as shown in FIG. 4B, a gate insulating film 33 made of an HfO 2 film is formed using a method such as a sputtering method or a CVD (Chemical Vapor Deposition) method. The film thickness is, for example, about 3 nm. Subsequently, as shown in FIG. 4C, a gate electrode 34 made of a TiN film is formed by using a sputtering method or a CVD method. The film thickness is, for example, 20 to 200 nm.
続いて、図４（ｄ）に示すように、ｎＭＩＳ形成領域４１のゲート電極３４の表面をフォトレジストなどのマスク３５で覆い、ｐＭＩＳ形成領域４２のゲート電極３４の表面からイオン注入法により酸素を添加する。イオン注入のドーズ量は、典型的には１×１０１５～１×１０１６ｃｍ－２である。このとき、ドーズ量を制御することによって、後の工程で形成される界面層３９ａ，３９ｂ（図５（ｅ）参照）の組成を制御できる。
Subsequently, as shown in FIG. 4D, the surface of the gate electrode 34 in the nMIS formation region 41 is covered with a mask 35 such as a photoresist, and oxygen is injected from the surface of the gate electrode 34 in the pMIS formation region 42 by ion implantation. Added. The dose of ion implantation is typically 1 × 10 15 to 1 × 10 16 cm −2 . At this time, by controlling the dose amount, the composition of the interface layers 39a and 39b (see FIG. 5E) formed in a later step can be controlled.
一般に、ゲート絶縁膜３３の表面には、製造工程中に自然に形成された僅かな酸化膜が残存している。そのため、ｎＭＩＳ形成領域４１のゲート電極３４とゲート絶縁膜３３との界面にも僅かな酸素が存在する。したがって、その酸素を利用することにより、ｎＭＩＳ形成領域４１のゲート電極３４に対する酸素のイオン注入を省略することができる。もちろん、ｎＭＩＳ形成領域４１のゲート電極３４に酸素をイオン注入する工程を加えてもよい。ただし、ｎＭＩＳ形成領域４１のゲート電極３４に添加される酸素量は、ｐＭＩＳ形成領域４２のゲート電極３４に添加される酸素量よりも少なくする。以下、ゲート電極３４は、ｎＭＩＳ形成領域４１のゲート電極３４ａとｐＭＩＳ形成領域４２のゲート電極３４ｂとで区別して表記する。
Generally, a slight oxide film naturally formed during the manufacturing process remains on the surface of the gate insulating film 33. Therefore, slight oxygen is also present at the interface between the gate electrode 34 and the gate insulating film 33 in the nMIS formation region 41. Therefore, by using the oxygen, oxygen ion implantation into the gate electrode 34 in the nMIS formation region 41 can be omitted. Of course, a step of ion-implanting oxygen into the gate electrode 34 in the nMIS formation region 41 may be added. However, the amount of oxygen added to the gate electrode 34 in the nMIS formation region 41 is smaller than the amount of oxygen added to the gate electrode 34 in the pMIS formation region 42. Hereinafter, the gate electrode 34 is described by distinguishing between the gate electrode 34 a in the nMIS formation region 41 and the gate electrode 34 b in the pMIS formation region 42.
続いて、図５（ｅ）に示すように、ゲート絶縁膜３３とゲート電極３４ａ，３４ｂとの界面に、熱処理を用いてそれぞれ界面層３９ａ，３９ｂを形成する。界面層３９ａ，３９ｂは、ゲート電極３４ａ，３４ｂに含まれるIV族遷移金属（Ｔｉ）及び酸素を含み、シリコンを含まない
Subsequently, as shown in FIG. 5E, interface layers 39a and 39b are formed at the interface between the gate insulating film 33 and the gate electrodes 34a and 34b, respectively, using heat treatment. The interface layers 39a and 39b contain a group IV transition metal (Ti) and oxygen contained in the gate electrodes 34a and 34b, and do not contain silicon.
これにより、ｎＭＩＳ形成領域４１においては、界面層３９ａが形成される。このとき、ゲート絶縁膜３３はゲート電極３４ａによって還元されないため、界面層３９ａ中の酸素組成が熱処理によって増加することを抑制できる。その結果、ゲート電極３４ａの仕事関数は、ｎＭＩＳのゲート電極材料に適した４．０ｅＶとなる。
Thereby, in the nMIS formation region 41, the interface layer 39a is formed. At this time, since the gate insulating film 33 is not reduced by the gate electrode 34a, an increase in the oxygen composition in the interface layer 39a due to the heat treatment can be suppressed. As a result, the work function of the gate electrode 34a is 4.0 eV suitable for the gate electrode material of nMIS.
一方、ｐＭＩＳ形成領域４２においては、ゲート電極３４ｂ中に添加された酸素がゲート電極３４ｂとゲート絶縁膜３３との界面に拡散することにより、界面層３９ｂが形成される。界面層３９ｂは、ゲート電極３４ｂに含まれるIV族遷移金属（Ｔｉ）及び酸素を含む。界面層３９ｂ中の酸素量は、界面層３９ａの酸素量に比べて多い。そのため、ゲート電極３４ｂの仕事関数は、ゲート電極３４ａの仕事関数よりも１ｅＶ程度高くなっており、例えば５．１ｅＶであるので、ｐＭＩＳのゲート電極材料に適している。
On the other hand, in the pMIS formation region 42, oxygen added to the gate electrode 34b diffuses to the interface between the gate electrode 34b and the gate insulating film 33, thereby forming the interface layer 39b. The interface layer 39b contains a group IV transition metal (Ti) and oxygen contained in the gate electrode 34b. The amount of oxygen in the interface layer 39b is larger than the amount of oxygen in the interface layer 39a. Therefore, the work function of the gate electrode 34b is about 1 eV higher than the work function of the gate electrode 34a, for example, 5.1 eV, which is suitable for the gate electrode material of pMIS.
続いて、図５（ｆ）に示すように、ゲート電極３４ａ，３４ｂを所定の形状にパターニングする。これにより、ゲート電極３４ａ，３４ｂは、ＭＩＳ形成領域４１及びｐＭＩＳ形成領域４２において最終的な形状になる。
Subsequently, as shown in FIG. 5F, the gate electrodes 34a and 34b are patterned into a predetermined shape. As a result, the gate electrodes 34 a and 34 b have final shapes in the MIS formation region 41 and the pMIS formation region 42.
続いて、ｎＭＩＳ形成領域４１に対して、ゲート電極３４ａをマスクとして、セルフアライン的にＡｓのイオン注入を行う。これにより、シリコン基板３１の上層部に、注入領域３８’が形成される。このとき、イオン注入量は、例えば１×１０１４～１×１０１５ｃｍ－２であり、例えば５×１０１４ｃｍ－２である。加速電圧は例えば２ｋＶである。なお、注入領域３８’の一部は、後述する熱処理を施すことによって、ｎＭＩＳ形成領域４１におけるエクステンション領域３６（図５（ｇ）参照）になる。
Subsequently, As ions are implanted into the nMIS formation region 41 in a self-aligning manner using the gate electrode 34a as a mask. As a result, an implantation region 38 ′ is formed in the upper layer portion of the silicon substrate 31. At this time, the ion implantation amount is, for example, 1 × 10 14 to 1 × 10 15 cm −2 , for example, 5 × 10 14 cm −2 . The acceleration voltage is 2 kV, for example. A part of the implantation region 38 ′ becomes an extension region 36 (see FIG. 5G) in the nMIS formation region 41 by performing a heat treatment described later.
続いて、ｐＭＩＳ形成領域４２に対して、ゲート電極３４ｂをマスクとして、セルフアライン的にＢＦ２のイオン注入を行う。これにより、シリコン基板３１の上層部に、注入領域３８’が形成される。このとき、イオン注入量は、例えば１×１０１４～１×１０１５ｃｍ－２であり、例えば５×１０１４ｃｍ－２である。加速電圧は例えば２．５ｋＶである。なお、注入領域３８’の一部は、後述する熱処理を施すことによって、ｐＭＩＳ形成領域４２におけるエクステンション領域３６（図５（ｇ）参照）になる。
Subsequently, BF 2 ions are implanted into the pMIS formation region 42 in a self-aligning manner using the gate electrode 34b as a mask. As a result, an implantation region 38 ′ is formed in the upper layer portion of the silicon substrate 31. At this time, the ion implantation amount is, for example, 1 × 10 14 to 1 × 10 15 cm −2 , for example, 5 × 10 14 cm −2 . The acceleration voltage is 2.5 kV, for example. A part of the implantation region 38 ′ becomes an extension region 36 (see FIG. 5G) in the pMIS formation region 42 by performing a heat treatment described later.
続いて、図５（ｇ）に示すように、ゲート電極３４ａ，３４ｂの周囲にシリコン窒化膜を堆積し、エッチバック法によってゲート電極３４ａ，３４ｂの側壁３７を形成する。
Subsequently, as shown in FIG. 5G, a silicon nitride film is deposited around the gate electrodes 34a and 34b, and sidewalls 37 of the gate electrodes 34a and 34b are formed by an etch back method.
続いて、ｎＭＩＳ形成領域４１に対して、セルフアライン的にＡｓ又はＰのイオン注入を行う。イオン注入量は例えば５×１０１４～２×１０１６ｃｍ－２である。例えば、Ａｓをイオン注入する場合は、イオン注入量が４×１０１５ｃｍ－２であり、加速電圧が８ｋＶである。Ｐをイオン注入する場合は、イオン注入量が１×１０１５ｃｍ－２であり、加速電圧が１０ｋＶである。また、ｐＭＩＳ形成領域４２に対して、セルフアライン的にＢのイオン注入を行う。このとき、イオン注入量は、例えば５×１０１４～２×１０１６ｃｍ－２であり、例えば３×１０１５ｃｍ－２である。加速電圧は２ｋＶである。
Subsequently, As or P ions are implanted into the nMIS formation region 41 in a self-aligning manner. The ion implantation amount is, for example, 5 × 10 14 to 2 × 10 16 cm −2 . For example, when As is ion-implanted, the ion implantation amount is 4 × 10 15 cm −2 and the acceleration voltage is 8 kV. In the case of ion implantation of P, the ion implantation amount is 1 × 10 15 cm −2 and the acceleration voltage is 10 kV. Further, B ions are implanted into the pMIS formation region 42 in a self-aligning manner. At this time, the ion implantation amount is, for example, 5 × 10 14 to 2 × 10 16 cm −2 , for example, 3 × 10 15 cm −2 . The acceleration voltage is 2 kV.
続いて、不純物活性化のための急速加熱処理（ＲＴＡ：Rapid Thermal Annealing）を施すことにより、ソース及びドレイン領域となる深い拡散領域３８を形成するとともに、エクステンション領域３６を形成する。急速加熱処理の温度は例えば９００～１１００℃であり、急速加熱処理の時問は例えば２０秒以下である。
Subsequently, a rapid thermal treatment (RTA: Rapid Thermal Annealing) for impurity activation is performed to form a deep diffusion region 38 that becomes a source and drain region and an extension region 36. The temperature of the rapid heat treatment is, for example, 900 to 1100 ° C., and the time of the rapid heat treatment is, for example, 20 seconds or less.
最後に、ゲート電極３４ａ，３４ｂ及び側壁３７の周囲を埋めるように、ＳｉＯ２，ＢＰＳＧ、ＳｉＮ又は低誘電率膜からなる層問絶縁膜（図示せず）を堆積する。煩雑化を避けるために図示しなかった層間絶縁膜は、図６（ａ）における層間絶縁膜５９と同様のものである。これにより、本実施形態の半導体装置３０が完成する。半導体装置３０は図３の構成と同じである。
Finally, a layer insulating film (not shown) made of SiO 2 , BPSG, SiN or a low dielectric constant film is deposited so as to fill the periphery of the gate electrodes 34 a and 34 b and the side wall 37. The interlayer insulating film that is not shown in order to avoid complication is the same as the interlayer insulating film 59 in FIG. Thereby, the semiconductor device 30 of the present embodiment is completed. The semiconductor device 30 has the same configuration as that of FIG.
本実施形態では、ゲート電極３４ａ，３４ｂによって還元されないＨｆＯ２をゲート絶縁膜３３として用いているため、ｎＭＩＳ形成領域４１における界面層３９ａ中の酸素組成が熱処理中に増加することを抑制できる。その結果、ゲート電極３４ａの仕事関数がｎＭＩＳのゲート電極材料に適した４．０ｅＶとなるため、低いしきい値電圧のｎＭＩＳを実現でき、これによりトランジスタを高速化できる。また、ｐＭＩＳ形成領域４２の界面層３９ｂ中の酸素量は、ｎＭＩＳ形成領域４１の界面層３９ａの酸素量に比べて多い。そのため、ゲート電極３４ｂの仕事関数は、ゲート電極３４ａの仕事関数よりも１ｅＶ程度高く、例えば５．１ｅＶであるので、ｐＭＩＳのゲート電極材料に適している。
In this embodiment, since HfO 2 that is not reduced by the gate electrodes 34a and 34b is used as the gate insulating film 33, it is possible to suppress an increase in the oxygen composition in the interface layer 39a in the nMIS formation region 41 during the heat treatment. As a result, the work function of the gate electrode 34a is 4.0 eV, which is suitable for the gate electrode material of nMIS, so that an nMIS with a low threshold voltage can be realized, thereby increasing the speed of the transistor. Further, the amount of oxygen in the interface layer 39b in the pMIS formation region 42 is larger than the amount of oxygen in the interface layer 39a in the nMIS formation region 41. Therefore, the work function of the gate electrode 34b is about 1 eV higher than the work function of the gate electrode 34a, for example, 5.1 eV, which is suitable for the gate electrode material of pMIS.
なお、ゲート電極３４ａ，３４ｂを形成するＴｉＮ膜の膜厚が例えば５ｎｍ以上であれば、ＴｉＮ膜上に他の金属膜を積層しても、ゲート電極３４ａ，３４ｂの仕事関数は変化しない。したがって、ＴｉＮ膜よりも低抵抗のゲート金属膜を、ＴｉＮ膜上に積層することにより、ゲート電極３４ａ，３４ｂの抵抗値を低減することができる。
If the thickness of the TiN film forming the gate electrodes 34a and 34b is, for example, 5 nm or more, the work functions of the gate electrodes 34a and 34b do not change even if another metal film is stacked on the TiN film. Therefore, the resistance value of the gate electrodes 34a and 34b can be reduced by laminating a gate metal film having a lower resistance than that of the TiN film on the TiN film.
また、ゲート電極３４ａ，３４ｂを形成する材料として、本実施形態ではＴｉＮを使用する例を示したが、IV族遷移金属を主成分として含む導電膜になるならば、どのような材料を使用してもよい。
Further, although TiN is used as an example of the material for forming the gate electrodes 34a and 34b in this embodiment, any material can be used as long as the conductive film includes a group IV transition metal as a main component. May be.
次に、本実施形態の半導体装置の製造方法について総括する。本実施形態の半導体装置の製造方法は、次の工程を含む。
Next, the semiconductor device manufacturing method of this embodiment will be summarized. The manufacturing method of the semiconductor device of this embodiment includes the following steps.
１．半導体基板であるシリコン基板３１上におけるｎＭＩＳ形成領域４１及びｐＭＩＳ形成領域４２に、最表面がIV族遷移金属によっては還元されない金属酸化物からなる少なくとも一層以上の積層絶縁膜からなるゲート絶縁膜３３を形成する工程（図４（ａ）（ｂ））。２．ｎＭＩＳ形成領域４１及びｐＭＩＳ形成領域４２に、IV族遷移金属を主成分として含む導電膜からなるゲート電極３４を形成する工程（図４（ｃ））。３．ｐＭＩＳ形成領域４２のゲート電極３４に対して、選択的に酸素をイオン注入する工程（図４（ｄ））。４．熱処理によって、ｎＭＩＳ形成領域４１のゲート電極３４ａとゲート絶縁膜３３との間、及びｐＭＩＳ形成領域４２のゲート電極３４ｂとゲート絶縁膜３３との間に、それぞれ界面層３９ａ，３９ｂを形成する工程（図４（ｅ））。５．ゲート電極３４ａ及びゲート電極３４ｂをマスクとし、シリコン基板３１の表層部に不純物を注入することにより、それぞれのソース及びドレインを形成する工程（図４（ｆ）（ｇ））。
1. A gate insulating film 33 made of at least one laminated insulating film made of a metal oxide whose outermost surface is not reduced by a group IV transition metal is formed on the nMIS forming region 41 and the pMIS forming region 42 on the silicon substrate 31 which is a semiconductor substrate. Step of forming (FIGS. 4A and 4B). 2. A step of forming a gate electrode 34 made of a conductive film containing a group IV transition metal as a main component in the nMIS formation region 41 and the pMIS formation region 42 (FIG. 4C). 3. A step of selectively ion-implanting oxygen into the gate electrode 34 of the pMIS formation region 42 (FIG. 4D). 4). Steps of forming interface layers 39a and 39b between the gate electrode 34a and the gate insulating film 33 in the nMIS formation region 41 and between the gate electrode 34b and the gate insulating film 33 in the pMIS formation region 42 by heat treatment ( FIG. 4 (e)). 5. A step of forming respective sources and drains by implanting impurities into the surface layer portion of the silicon substrate 31 using the gate electrodes 34a and 34b as masks (FIGS. 4F and 4G).
換言すると、本実施形態の半導体装置の製造方法は、次の工程を含むことを特徴とする。第一工程：半導体基板であるシリコン基板３１上に、少なくとも上面がIV族遷移金属によって還元されない金属酸化物からなるゲート絶縁膜３３を形成する（図４（ａ）（ｂ））。第二工程：ゲート絶縁膜３３上に、IV族遷移金属を含む導電膜からなるゲート電極３４を形成する（図４（ｃ））。第三工程：ゲート電極３４に対して酸素をイオン注入する（図４（ｄ））。第四工程：ゲート電極３４ａ，３４ｂとゲート絶縁膜３３との間に、IV族遷移金属及び酸素を含む界面層３９ａ，３９ｂを熱処理によって形成する（図４（ｅ））。
In other words, the manufacturing method of the semiconductor device of this embodiment includes the following steps. First step: A gate insulating film 33 made of a metal oxide whose upper surface is not reduced by a group IV transition metal is formed on a silicon substrate 31 which is a semiconductor substrate (FIGS. 4A and 4B). Second step: A gate electrode 34 made of a conductive film containing a group IV transition metal is formed on the gate insulating film 33 (FIG. 4C). Third step: Oxygen ions are implanted into the gate electrode 34 (FIG. 4D). Fourth step: Interfacial layers 39a and 39b containing a group IV transition metal and oxygen are formed by heat treatment between the gate electrodes 34a and 34b and the gate insulating film 33 (FIG. 4E).
これに加え、第三工程において、ゲート電極３４を、ｎＭＩＳ形成領域４１のゲート電極３４ａ（第一領域）と、ｐＭＩＳ形成領域４２のゲート電極３４ｂ（第二領域）とに分ける。そして、ゲート電極３４ａ，３４ｂのうち少なくともゲート電極３４ｂに対して、酸素をイオン注入することにより、ゲート電極３４ａ中の酸素量をゲート電極３４ｂ中の酸素量よりも少なくする。
In addition, in the third step, the gate electrode 34 is divided into a gate electrode 34a (first region) in the nMIS formation region 41 and a gate electrode 34b (second region) in the pMIS formation region 42. Then, oxygen is ion-implanted into at least the gate electrode 34b of the gate electrodes 34a and 34b, so that the amount of oxygen in the gate electrode 34a is less than the amount of oxygen in the gate electrode 34b.
本実施形態の製造方法では、デュアルメタルプロセスと異なり電極の剥離を行うことなく、ｎＭＩＳ及びｐＭＩＳのゲート電極３４ａ，３４ｂをレジストマスクとイオン注入で形成できるため、ゲート絶縁膜３３の品質が劣化することがない。また、ゲート絶縁膜３３の最表面層は、酸化ジルコニウム又は酸化ハフニウムであることが好ましい。この場合は、特にｎＭＩＳにおける界面層３９ａ中の酸素組成の増加を抑制できる。その結果、低いしきい値電圧のｎＭＩＳを実現できるので、トランジスタを高速化できる。なお、その他の作用及び効果は、第三実施形態で述べた内容と同じである。
In the manufacturing method of the present embodiment, unlike the dual metal process, the nMIS and pMIS gate electrodes 34a and 34b can be formed by resist mask and ion implantation without peeling off the electrodes, so that the quality of the gate insulating film 33 is deteriorated. There is nothing. The outermost surface layer of the gate insulating film 33 is preferably zirconium oxide or hafnium oxide. In this case, an increase in oxygen composition in the interface layer 39a particularly in nMIS can be suppressed. As a result, an nMIS with a low threshold voltage can be realized, so that the speed of the transistor can be increased. The other actions and effects are the same as those described in the third embodiment.
図６乃至図９は、本発明の第五実施形態に係る半導体装置の製造方法を示す断面図である。以下、これらの図面に基づき説明する。
6 to 9 are sectional views showing a method for manufacturing a semiconductor device according to the fifth embodiment of the present invention. Hereinafter, description will be given based on these drawings.
図６（ａ）乃至図９（ｈ）は、本実施形態に係る半導体装置の製造方法をその工程順に示す断面図である。本実施形態が前述の第四実施形態と異なる点は、あらかじめダミーゲート電極を作製し、ソース及びドレインに注入した不純物の活性化が終了した後に、ダミーゲート電極を取り除き、メタルゲート電極を作製する点にある。この方法によれば、比較的低い耐熱性を有するＨｆＯ２膜や、Ｈｆを高濃度で含むＨｆＳｉＯ膜を、ゲート絶縁膜として使用することができる。また、ゲート電極の抵抗を低減するために、Ａｌ等の低融点金属を使用することも可能となる。また、ゲート絶縁膜として図１（ｂ）に示した膜厚０．５ｎｍ程度のＨｆＯ２で覆われたシリケート層／ＳｉＯ２積層構造を用いている。この積層構造を用いると、トランジスタの移動度を高く保つことができる。以下、工程順に説明する。
6A to 9H are cross-sectional views showing the method of manufacturing the semiconductor device according to this embodiment in the order of the steps. This embodiment is different from the fourth embodiment described above in that a dummy gate electrode is prepared in advance, and after the activation of impurities implanted into the source and drain is completed, the dummy gate electrode is removed and a metal gate electrode is manufactured. In the point. According to this method, an HfO 2 film having relatively low heat resistance and an HfSiO film containing Hf at a high concentration can be used as the gate insulating film. In addition, in order to reduce the resistance of the gate electrode, it is possible to use a low melting point metal such as Al. Further, as the gate insulating film, the silicate layer / SiO 2 laminated structure covered with HfO 2 having a thickness of about 0.5 nm shown in FIG. 1B is used. When this stacked structure is used, the mobility of the transistor can be kept high. Hereinafter, it demonstrates in order of a process.
まず、図６（ａ）に示すように、前述の第四実施形態と同様に、シリコン基板３１の表層に素子分離領域３２を選択的に形成する。続いて、後の工程において除去されるダミーゲート絶縁膜５３として、膜厚が例えば２～６ｎｍ程度のシリコン酸化膜を形成する。
First, as shown in FIG. 6A, the element isolation region 32 is selectively formed on the surface layer of the silicon substrate 31 as in the fourth embodiment described above. Subsequently, a silicon oxide film having a thickness of, for example, about 2 to 6 nm is formed as the dummy gate insulating film 53 to be removed in a later process.
続いて、膜厚が例えば約１５０ｎｍであるポリシリコン膜５６及び膜厚が例えば約５０ｎｍであるシリコン窒化膜５７を順次形成し、ポリシリコン膜５６及びシリコン窒化膜５７からなる積層膜を形成する。続いて、この積層膜を電極形状にパターニングすることにより、後の工程において除去されるダミーゲート電極５４を形成する。
Subsequently, a polysilicon film 56 having a film thickness of, for example, about 150 nm and a silicon nitride film 57 having a film thickness of, for example, about 50 nm are sequentially formed, and a laminated film including the polysilicon film 56 and the silicon nitride film 57 is formed. Subsequently, the laminated film is patterned into an electrode shape to form a dummy gate electrode 54 to be removed in a later process.
続いて、ｎＭＩＳ形成領域４１及びｐＭＩＳ形成領域４２において、それぞれダミーゲート電極５４をマスクとして、イオン注入技術によりソース及びドレインの不純物拡散層となるエクステンション領域３６を形成する。そして、前述の第四実施形態と同様な条件を用いて、不純物を活性化させるための熱処理を行う。
Subsequently, in the nMIS formation region 41 and the pMIS formation region 42, extension regions 36 serving as source and drain impurity diffusion layers are formed by ion implantation using the dummy gate electrode 54 as a mask. Then, heat treatment for activating the impurities is performed using the same conditions as in the fourth embodiment described above.
続いて、シリコン窒化膜をＣＶＤ技術を用いて成膜し、このシリコン窒化膜をＲＩＥ技術を用いて選択的に除去することにより、ダミーゲート電極５４の側方に側壁３７を形成する。側壁３７は、シリコン窒化膜からなり、幅が２０～４０ｎｍ程度である。
Subsequently, a side wall 37 is formed on the side of the dummy gate electrode 54 by forming a silicon nitride film using the CVD technique and selectively removing the silicon nitride film using the RIE technique. The side wall 37 is made of a silicon nitride film and has a width of about 20 to 40 nm.
続いて、ｎＭＩＳ形成領域４１及びｐＭＩＳ形成領域４２において、それぞれダミーゲート電極５４及び側壁３７をマスクとして、イオン注入技術によりソース及びドレインの高濃度不純物拡散層となる拡散領域３８を形成する。そして、前述の第四実施形態と同様な条件を用いて、不純物を活性化させるための熱処理を行う。
Subsequently, in the nMIS formation region 41 and the pMIS formation region 42, diffusion regions 38 to be high-concentration impurity diffusion layers of source and drain are formed by ion implantation using the dummy gate electrode 54 and the sidewall 37 as a mask, respectively. Then, heat treatment for activating the impurities is performed using the same conditions as in the fourth embodiment described above.
続いて、サリサイドプロセス技術により、ダミーゲート電極５４及び側壁３７をマスクとして、ソース及びドレイン領域のみに膜厚が例えば約４０ｎｍのシリサイド膜（図示せず）を形成する。続いて、例えばシリコン酸化膜をＣＶＤ法により堆積し、層間絶縁膜５９を形成する。ここまでの工程は、図４（ａ）乃至図５（ｇ）の工程に類似する。
Subsequently, a silicide film (not shown) having a film thickness of, for example, about 40 nm is formed only in the source and drain regions by the salicide process technique using the dummy gate electrode 54 and the sidewall 37 as a mask. Subsequently, for example, a silicon oxide film is deposited by a CVD method to form an interlayer insulating film 59. The steps so far are similar to the steps of FIGS. 4A to 5G.
続いて、図６（ｂ）に示すように、層間絶縁膜５９の表面をＣＭＰ（Chemical Mechanical Polishing）技術により平坦化することにより、ダミーゲート電極５４の表面すなわちシリコン窒化膜５７の表面を露出させる。続いて、例えば燐酸を使用して、ダミーゲート電極５４上部のシリコン窒化膜５７を層間絶縁膜５９に対して選択的に除去する。これにより、ポリシリコン膜５６が露出する。続いて、フッ素等のラジカルを使用するエッチング技術により、ポリシリコン膜５６を層問絶縁膜５９及び側壁３７に対して選択的に除去する。
Subsequently, as shown in FIG. 6B, the surface of the interlayer insulating film 59 is planarized by a CMP (Chemical Mechanical Polishing) technique to expose the surface of the dummy gate electrode 54, that is, the surface of the silicon nitride film 57. . Subsequently, the silicon nitride film 57 on the dummy gate electrode 54 is selectively removed from the interlayer insulating film 59 using, for example, phosphoric acid. As a result, the polysilicon film 56 is exposed. Subsequently, the polysilicon film 56 is selectively removed from the layer insulating film 59 and the side wall 37 by an etching technique using radicals such as fluorine.
続いて、図７（ｃ）に示すように、希フッ酸等のウェットエッチングを用いて、シリコン酸化膜からなるダミーゲート絶縁膜５３を除去することにより、溝５８を形成する。
Subsequently, as shown in FIG. 7C, the trench 58 is formed by removing the dummy gate insulating film 53 made of a silicon oxide film using wet etching such as dilute hydrofluoric acid.
続いて、図７（ｄ）に示すように、積層膜からなるゲート絶縁膜６３を形成する。ゲート絶縁膜６３は、図１（ｂ）に示す膜厚０．５ｎｍ程度のＨｆＯ２層２２１で覆われたシリケート層２２２及びＳｉＯ２層２２３からなる。ゲート絶縁膜６３を用いると、トランジスタの移動度を高く保つことができる。
Subsequently, as shown in FIG. 7D, a gate insulating film 63 made of a laminated film is formed. The gate insulating film 63 includes a silicate layer 222 and an SiO 2 layer 223 covered with an HfO 2 layer 221 having a thickness of about 0.5 nm shown in FIG. When the gate insulating film 63 is used, the mobility of the transistor can be kept high.
続いて、図８（ｅ）に示すように、ゲート絶縁膜６３上に、ＣＶＤ法又はスパッタリング法を用いて、ＨｆＮ膜からなるゲート電極６４を成膜する。その膜厚は例えば２０～２００ｎｍである。
Subsequently, as shown in FIG. 8E, a gate electrode 64 made of an HfN film is formed on the gate insulating film 63 by using a CVD method or a sputtering method. The film thickness is, for example, 20 to 200 nm.
続いて、図８（ｆ）に示すように、ｎＭＩＳ形成領域４１のゲート電極６４の表面をマスク３５で覆い、イオン注入法を用いて、ｐＭＩＳ形成領域４２のゲート電極６４の表面から酸素を添加する。これにより、ｎＭＩＳ形成領域４１では酸素量の少ないゲート電極６４となり、ｐＭＩＳ形成領域４２では酸素量の多いゲート電極層６４となる。
Subsequently, as shown in FIG. 8F, the surface of the gate electrode 64 in the nMIS formation region 41 is covered with a mask 35, and oxygen is added from the surface of the gate electrode 64 in the pMIS formation region 42 by ion implantation. To do. As a result, the nMIS formation region 41 becomes a gate electrode 64 with a small amount of oxygen, and the pMIS formation region 42 becomes a gate electrode layer 64 with a large amount of oxygen.
一般に、ゲート絶縁膜６３の表面には、製造工程中に自然に形成された僅かな酸化膜が残存している。そのため、ｎＭＩＳ形成領域４１のゲート電極６４とゲート絶縁膜３３との界面にも僅かな酸素が存在する。したがって、その酸素を利用することにより、ｎＭＩＳ形成領域４１のゲート電極６４に対する酸素のイオン注入を省略することができる。もちろん、ｎＭＩＳ形成領域４１のゲート電極６４に酸素をイオン注入する工程を加えてもよい。ただし、ｎＭＩＳ形成領域４１のゲート電極６４に添加される酸素量は、ｐＭＩＳ形成領域４２のゲート電極６４に添加される酸素量よりも少なくする。以下、ゲート電極６４は、ｎＭＩＳ形成領域４１のゲート電極６４ａとｐＭＩＳ形成領域４２のゲート電極６４ｂとで区別して表記する。
In general, a slight oxide film naturally formed during the manufacturing process remains on the surface of the gate insulating film 63. Therefore, slight oxygen is also present at the interface between the gate electrode 64 and the gate insulating film 33 in the nMIS formation region 41. Therefore, by using the oxygen, oxygen ion implantation into the gate electrode 64 in the nMIS formation region 41 can be omitted. Of course, a step of ion-implanting oxygen into the gate electrode 64 of the nMIS formation region 41 may be added. However, the amount of oxygen added to the gate electrode 64 in the nMIS formation region 41 is made smaller than the amount of oxygen added to the gate electrode 64 in the pMIS formation region 42. Hereinafter, the gate electrode 64 is described by distinguishing between the gate electrode 64 a in the nMIS formation region 41 and the gate electrode 64 b in the pMIS formation region 42.
続いて、図９（ｇ）に示すように、ｎＭＩＳ形成領域４１及びｐＭＩＳ形成領域４２において、熱処理を施して、ゲート電極６４ａ，６４ｂとゲート絶縁膜６３との界面に界面層６５ａ，６５ｂを形成する。界面層６５ａ，６５ｂは、ゲート電極６４ａ，６４ｂに含まれるIV族遷移金属（Ｈｆ）及び酸素を含み、シリコンを含まない。
Subsequently, as shown in FIG. 9G, heat treatment is performed in the nMIS formation region 41 and the pMIS formation region 42 to form interface layers 65a and 65b at the interfaces between the gate electrodes 64a and 64b and the gate insulating film 63. To do. The interface layers 65a and 65b contain a group IV transition metal (Hf) and oxygen contained in the gate electrodes 64a and 64b, and do not contain silicon.
最後に、図９（ｈ）に示すように、ＣＭＰを用いて全体を平坦化することにより、層問絶縁膜５９上のゲート電極６４ａ，６４ｂとゲート絶縁膜６３を除去する。これにより、層問絶縁膜５９が露出するとともに、ｎＭＩＳ形成領域４１に最終的な形状のゲート絶縁膜６３及びゲート電極６４ａが形成され、ｐＭＩＳ形成領域４２に最終的な形状のゲート絶縁膜６３及びゲート電極６４ｂが形成される。これで、半導体装置５０が完成する。
Finally, as shown in FIG. 9 (h), the gate electrodes 64a and 64b and the gate insulating film 63 on the layer insulating film 59 are removed by flattening the whole using CMP. As a result, the inter-layer insulating film 59 is exposed, the final shape gate insulating film 63 and the gate electrode 64a are formed in the nMIS formation region 41, and the final shape gate insulating film 63 and the pMIS formation region 42 are formed. A gate electrode 64b is formed. Thus, the semiconductor device 50 is completed.
本実施形態では、ゲート絶縁膜６３としてゲート電極６４ａ，６４ｂによって還元されないＨｆＯ２を用いているため、ｎＭＩＳ形成領域４１における界面層６５ａ中の酸素組成が熱処理中に増加することを抑制できる。その結果、ゲート電極６４ａの仕事関数がｎＭＩＳのゲート電極材料に適した４．０ｅＶとなることにより、低いしきい値電圧のｎＭＩＳを実現できるので、トランジスタを高速化できる。
In this embodiment, since HfO 2 that is not reduced by the gate electrodes 64a and 64b is used as the gate insulating film 63, it is possible to suppress an increase in the oxygen composition in the interface layer 65a in the nMIS formation region 41 during the heat treatment. As a result, since the work function of the gate electrode 64a is 4.0 eV suitable for the gate electrode material of nMIS, nMIS with a low threshold voltage can be realized, so that the speed of the transistor can be increased.
一方、熱処理中において、ｐＭＩＳ形成領域４２のゲート電極６４ｂ中に添加された酸素がゲート電極６４ｂとゲート絶縁膜６３との界面に拡散することにより、界面層６５ｂが形成される。界面層６５ｂは、ゲート電極６４ｂに含まれるIV族遷移金属（Ｈｆ）及び酸素を含む。界面層６５ｂ中の酸素量は、界面層６５ａの酸素量に比べて多い。そのため、ゲート電極６４ｂの仕事関数は、ゲート電極６４ａの仕事関数よりも１ｅＶ程度高くなっており、例えば５．１ｅＶである。すなわち、ゲート電極６４ｂは、ｐＭＩＳのゲート電極材料に適しているため、低いしきい値電圧のｐＭＩＳを実現でき、これによりトランジスタを高速化できる。
On the other hand, during the heat treatment, oxygen added into the gate electrode 64b of the pMIS formation region 42 diffuses to the interface between the gate electrode 64b and the gate insulating film 63, thereby forming the interface layer 65b. The interface layer 65b contains a group IV transition metal (Hf) and oxygen contained in the gate electrode 64b. The amount of oxygen in the interface layer 65b is larger than the amount of oxygen in the interface layer 65a. Therefore, the work function of the gate electrode 64b is about 1 eV higher than the work function of the gate electrode 64a, for example, 5.1 eV. That is, since the gate electrode 64b is suitable for a pMIS gate electrode material, it is possible to realize a pMIS with a low threshold voltage, thereby speeding up the transistor.
また、本実施形態では、ダミーゲート絶縁膜５３及びダミーゲート電極５４を形成し、これらをマスクとして不純物の注入を行い、この不純物を活性化させるための熱処理を行い、その後、ダミーゲート絶縁膜５３及びダミーゲート電極５４を除去して、ゲート絶縁膜６３及びゲート電極６４ａ，６４ｂを形成している。これにより、ゲート絶縁膜６３及びゲート電極６４ａ，６４ｂが熱処理に曝されることを防止できる。この結果、比較的低い耐熱性を有するＨｆＯ２膜や、Ｈｆを高濃度で含むＨｆＳｉＯ膜を、ゲート絶縁膜６３として使用できる。なお、本実施形態では、ゲート電極６４ａ，６４ｂを形成する材料として、ＨｆＮを使用する例を示したが、IV族遷移金属を主成分として含む導電膜であれば、どれを使用してもよい。
In this embodiment, the dummy gate insulating film 53 and the dummy gate electrode 54 are formed, impurities are implanted using these as a mask, heat treatment for activating the impurities is performed, and then the dummy gate insulating film 53 is formed. Then, the dummy gate electrode 54 is removed to form the gate insulating film 63 and the gate electrodes 64a and 64b. This can prevent the gate insulating film 63 and the gate electrodes 64a and 64b from being exposed to the heat treatment. As a result, an HfO 2 film having relatively low heat resistance and an HfSiO film containing Hf at a high concentration can be used as the gate insulating film 63. In the present embodiment, an example in which HfN is used as a material for forming the gate electrodes 64a and 64b has been described. However, any conductive film containing a group IV transition metal as a main component may be used. .
次に、本実施形態の半導体装置の製造方法について総括する。本実施形態の半導体装置の製造方法は、次の工程を含む。
Next, the semiconductor device manufacturing method of this embodiment will be summarized. The manufacturing method of the semiconductor device of this embodiment includes the following steps.
１．半導体基板であるシリコン基板３１上におけるｎＭＩＳ形成領域４１及びｐＭＩＳ形成領域４２の双方に、ダミーゲート電極５４を形成する工程（図６（ａ））。２．ダミーゲート電極５４をマスクとしてシリコン基板３１の表層部に不純物を注入して、ソース及びドレインを形成する工程（図６（ａ））。３．不純物を活性化させる熱処理を行う工程（図６（ａ））。４．ダミーゲート電極５４の周囲を埋めるように層間絶縁膜５９を形成する工程（図６（ａ））。５．ダミーゲート電極５４を除去して層間絶縁膜５９に溝５８を形成する工程（図６（ｂ）及び図７（ｃ））。６．ｎＭＩＳ形成領域４１及びｐＭＩＳ形成領域４２において、溝５８の内部に、最表面がIV族遷移金属によっては還元されない金属酸化物からなる少なくとも一層以上の積層絶縁膜からなるゲート絶縁膜６３を形成する工程（図７（ｄ））。７．ｎＭＩＳ形成領域４１及びｐＭＩＳ形成領域４２に、IV族遷移金属を主成分として含む導電膜からなるゲート電極６４を形成する工程（図８（ｅ））。８．ｐＭＩＳ形成領域４２のゲート電極６４に対して選択的に酸素をイオン注入する工程（図８（ｆ））。９．ｎＭＩＳ形成領域４１においてゲート電極６４ａとゲート絶縁膜６３との間、及びｐＭＩＳ形成領域４２においてゲート電極６４ｂとゲート絶縁膜６３との間に、それぞれ熱処理によって界面層６５ａ，６５ｂを形成する工程（図９（ｇ））。１０．余分な膜を選択的に除去することにより、ゲート電極６４ａ，６４ｂを所定形状に加工する工程（図９（ｈ））。
1. A step of forming a dummy gate electrode 54 in both the nMIS formation region 41 and the pMIS formation region 42 on the silicon substrate 31 which is a semiconductor substrate (FIG. 6A). 2. A step of forming a source and a drain by implanting impurities into the surface layer portion of the silicon substrate 31 using the dummy gate electrode 54 as a mask (FIG. 6A). 3. A step of performing a heat treatment for activating the impurities (FIG. 6A). 4). A step of forming an interlayer insulating film 59 so as to fill the periphery of the dummy gate electrode 54 (FIG. 6A). 5. A step of removing the dummy gate electrode 54 and forming a groove 58 in the interlayer insulating film 59 (FIGS. 6B and 7C). 6). In the nMIS formation region 41 and the pMIS formation region 42, a step of forming a gate insulating film 63 made of at least one laminated insulating film made of a metal oxide whose outermost surface is not reduced by a group IV transition metal inside the groove 58 (FIG. 7D). 7). A step of forming a gate electrode 64 made of a conductive film containing a group IV transition metal as a main component in the nMIS formation region 41 and the pMIS formation region 42 (FIG. 8E). 8). A step of selectively ion-implanting oxygen into the gate electrode 64 in the pMIS formation region 42 (FIG. 8F). 9. Steps of forming interface layers 65a and 65b by heat treatment between the gate electrode 64a and the gate insulating film 63 in the nMIS formation region 41 and between the gate electrode 64b and the gate insulating film 63 in the pMIS formation region 42 (FIG. 9 (g)). 10. A step of processing the gate electrodes 64a and 64b into a predetermined shape by selectively removing the excess film (FIG. 9H).
換言すると、本実施形態の半導体装置の製造方法は、次の工程を含むことを特徴とする。第一工程：半導体基板であるシリコン基板３１上に、少なくとも上面がIV族遷移金属によって還元されない金属酸化物からなるゲート絶縁膜６３を形成する（図６（ａ）～図７（ｄ））。第二工程：ゲート絶縁膜６３上に、IV族遷移金属を含む導電膜からなるゲート電極６４を形成する（図８（ｅ））。第三工程：ゲート電極６４に対して酸素をイオン注入する（図８（ｆ））。第四工程：ゲート電極６４ａ，６４ｂとゲート絶縁膜６３との間に、IV族遷移金属及び酸素を含む界面層６５ａ，６５ｂを熱処理によって形成する（図９（ｇ））。
In other words, the manufacturing method of the semiconductor device of this embodiment includes the following steps. First step: A gate insulating film 63 made of a metal oxide whose upper surface is not reduced by a group IV transition metal is formed on a silicon substrate 31 as a semiconductor substrate (FIGS. 6A to 7D). Second step: A gate electrode 64 made of a conductive film containing a group IV transition metal is formed on the gate insulating film 63 (FIG. 8E). Third step: Oxygen ions are implanted into the gate electrode 64 (FIG. 8F). Fourth step: Interfacial layers 65a and 65b containing a group IV transition metal and oxygen are formed by heat treatment between the gate electrodes 64a and 64b and the gate insulating film 63 (FIG. 9G).
これに加え、第一工程は、次の工程を含む。シリコン基板３１上にダミーゲート電極５４を形成する工程（図６（ａ））。ダミーゲート電極５４をマスクとしてシリコン基板３１の表層部に不純物を注入することにより、ソース及びドレインを形成する工程（図６（ａ））。不純物を活性化させる熱処理を行う工程（図６（ａ））。ダミーゲート電極５４の周囲を埋めるように層間絶縁膜５９を形成する工程（図６（ａ））。ダミーゲート電極５４を除去することにより、層間絶縁膜５９に溝５８を形成する工程（図６（ｂ）及び図７（ｃ））。溝５８内に、少なくとも上面がIV族遷移金属によって還元されない金属酸化物からなるゲート絶縁膜６３を形成する工程（図７（ｄ））。
In addition to this, the first step includes the following steps. A step of forming a dummy gate electrode 54 on the silicon substrate 31 (FIG. 6A). A step of forming a source and a drain by implanting impurities into the surface layer portion of the silicon substrate 31 using the dummy gate electrode 54 as a mask (FIG. 6A). A step of performing a heat treatment for activating the impurities (FIG. 6A). A step of forming an interlayer insulating film 59 so as to fill the periphery of the dummy gate electrode 54 (FIG. 6A). A step of forming a trench 58 in the interlayer insulating film 59 by removing the dummy gate electrode 54 (FIGS. 6B and 7C). A step of forming a gate insulating film 63 made of a metal oxide in which at least the upper surface is not reduced by the group IV transition metal in the trench 58 (FIG. 7D).
この結果、比較的低い耐熱性を有するＨｆＯ２膜や、Ｈｆを高濃度で含むＨｆＳｉＯ膜を、ゲート絶縁膜６３として使用することができる。また、ゲート絶縁膜６３の最表面層は、酸化ジルコニウム又は酸化ハフニウムであることが好ましい。この場合は、特にｎＭＩＳにおける界面層中の酸素組成の増加を抑制できる。その結果、低いしきい値電圧のｎＭＩＳを実現できるので、トランジスタを高速化できる。なお、その他の作用及び効果は、第三及び第四実施形態で述べた内容と同じである。
As a result, an HfO 2 film having relatively low heat resistance and an HfSiO film containing Hf at a high concentration can be used as the gate insulating film 63. Moreover, it is preferable that the outermost surface layer of the gate insulating film 63 is zirconium oxide or hafnium oxide. In this case, it is possible to suppress an increase in oxygen composition in the interface layer particularly in nMIS. As a result, an nMIS with a low threshold voltage can be realized, so that the speed of the transistor can be increased. Other operations and effects are the same as those described in the third and fourth embodiments.
以上、上記各実施形態を参照して本発明を説明したが、本発明は上記各実施形態に限定されるものではない。本発明の構成や詳細については、当業者が理解し得るさまざまな変更を加えることができる。また、本発明には、上記各実施形態の構成の一部又は全部を相互に適宜組み合わせたものも含まれる。
As described above, the present invention has been described with reference to each of the above embodiments, but the present invention is not limited to each of the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention. Further, the present invention includes a combination of some or all of the configurations of the above-described embodiments as appropriate.
この出願は２００８年２月１３日に出願された日本出願特願２００８－０３１６８９を基礎とする優先権を主張し、その開示の全てをここに取り込む。
This application claims priority based on Japanese Patent Application No. 2008-031689 filed on Feb. 13, 2008, the entire disclosure of which is incorporated herein.
本発明によれば、IV族遷移金属を含む導電膜からなるゲート電極を用いても、界面層の酸素組成を変えることにより、ゲート電極の仕事関数を自在に制御して前記仕事関数の制御幅を拡大することに貢献できる。
According to the present invention, even when a gate electrode made of a conductive film containing a group IV transition metal is used, the work function of the gate electrode can be freely controlled by changing the oxygen composition of the interface layer, thereby controlling the work function. Can contribute to the expansion.
１０ ＭＩＳＦＥＴ
１１ ゲート電極
１２ ゲート絶縁膜
１３ 界面層
１４ 半導体基板
２０ ＭＩＳＦＥＴ
２２ ゲート絶縁膜
２２１ ＨｆＯ２層
２２２ 下地Ｈｆシリケート層
２２３ ＳｉＯ２層
３０ 半導体装置
３１ シリコン基板
３２ 素子分離領域
３３ ゲート絶縁膜
３４，３４ａ，３４ｂ ゲート電極
３５ マスク
３６ エクステンション領域
３７ 側壁
３８’ 注入領域
３８ 拡散領域
３９ａ，３９ｂ 界面層
４１ ｎＭＩＳ形成領域
４２ ｐＭＩＳ形成領域
４３ ｎＭＩＳ
４４ ｐＭＩＳ
５０ 半導体装置
５３ ダミーゲート絶縁膜
５４ ダミーゲート電極
５６ ポリシリコン膜
５７ シリコン窒化膜
５８ 溝
５９ 層間絶縁膜
６３ ゲート絶縁膜
６４，６４ａ，６４ｂ ゲート電極
６５ａ，６５ｂ 界面層 10 MISFET
DESCRIPTION OFSYMBOLS 11 Gate electrode 12 Gate insulating film 13 Interface layer 14 Semiconductor substrate 20 MISFET
22Gate insulating film 221 HfO 2 layer 222 Base Hf silicate layer 223 SiO 2 layer 30 Semiconductor device 31 Silicon substrate 32 Element isolation region 33 Gate insulating film 34, 34a, 34b Gate electrode 35 Mask 36 Extension region 37 Side wall 38 'Injection region 38 Diffusion region 39a, 39b Interface layer 41 nMIS formation region 42 pMIS formation region 43 nMIS
44 pMIS
50Semiconductor Device 53 Dummy Gate Insulating Film 54 Dummy Gate Electrode 56 Polysilicon Film 57 Silicon Nitride Film 58 Groove 59 Interlayer Insulating Film 63 Gate Insulating Film 64, 64a, 64b Gate Electrodes 65a, 65b Interface Layer
１１ ゲート電極
１２ ゲート絶縁膜
１３ 界面層
１４ 半導体基板
２０ ＭＩＳＦＥＴ
２２ ゲート絶縁膜
２２１ ＨｆＯ２層
２２２ 下地Ｈｆシリケート層
２２３ ＳｉＯ２層
３０ 半導体装置
３１ シリコン基板
３２ 素子分離領域
３３ ゲート絶縁膜
３４，３４ａ，３４ｂ ゲート電極
３５ マスク
３６ エクステンション領域
３７ 側壁
３８’ 注入領域
３８ 拡散領域
３９ａ，３９ｂ 界面層
４１ ｎＭＩＳ形成領域
４２ ｐＭＩＳ形成領域
４３ ｎＭＩＳ
４４ ｐＭＩＳ
５０ 半導体装置
５３ ダミーゲート絶縁膜
５４ ダミーゲート電極
５６ ポリシリコン膜
５７ シリコン窒化膜
５８ 溝
５９ 層間絶縁膜
６３ ゲート絶縁膜
６４，６４ａ，６４ｂ ゲート電極
６５ａ，６５ｂ 界面層 10 MISFET
DESCRIPTION OF
22
44 pMIS
50
Claims (10)
- ゲート電極及びゲート絶縁膜の積層構造を有するＭＩＳ型電界効果トランジスタにおいて、
前記ゲート電極がIV族遷移金属を含む導電膜からなり、前記ゲート絶縁膜の少なくとも前記ゲート電極に接する側が前記IV族遷移金属によって還元されない金属酸化物からなり、前記ゲート電極と前記ゲート絶縁膜との間の界面層が前記IV族遷移金属及び酸素を含む、
ことを特徴とするＭＩＳ型電界効果トランジスタ。 In a MIS field effect transistor having a laminated structure of a gate electrode and a gate insulating film,
The gate electrode is made of a conductive film containing a group IV transition metal, and at least the side of the gate insulating film in contact with the gate electrode is made of a metal oxide that is not reduced by the group IV transition metal, and the gate electrode, the gate insulating film, The interfacial layer between comprises the Group IV transition metal and oxygen,
MIS type field effect transistor. - 前記IV族遷移金属がチタンである、
ことを特徴とする請求項１記載のＭＩＳ型電界効果トランジスタ。 The group IV transition metal is titanium;
The MIS field effect transistor according to claim 1. - 請求項２記載のＭＩＳ型電界効果トランジスタをｎチャネルＭＩＳ型電界効果トランジスタ及びｐチャネルＭＩＳ型電界効果トランジスタとして備え、
前記ｎチャネルＭＩＳ型電界効果トランジスタにおける前記界面層中の酸素組成が前記ｐチャネルＭＩＳ型電界効果トランジスタにおける前記界面層中の酸素組成に比べて低い、
ことを特徴とする半導体装置。 The MIS field effect transistor according to claim 2 is provided as an n-channel MIS field effect transistor and a p-channel MIS field effect transistor,
The oxygen composition in the interface layer in the n-channel MIS field effect transistor is lower than the oxygen composition in the interface layer in the p-channel MIS field effect transistor;
A semiconductor device. - 前記界面層の組成が（ＴｉＮ）１－ｘ（ＴｉＯ２）ｘであり、前記ｎチャネルＭＩＳ型電界効果トランジスタにおける前記ｘが０．５以上かつ０．６８以下であり、前記ｐチャネルＭＩＳ型電界効果トランジスタにおける前記ｘが０．８４以上かつ０．９７以下である、
ことを特徴とする請求項３記載の半導体装置。 The composition of the interface layer is (TiN) 1-x (TiO 2 ) x , and in the n-channel MIS field effect transistor, x is 0.5 or more and 0.68 or less, and the p-channel MIS type electric field is X in the effect transistor is 0.84 or more and 0.97 or less,
The semiconductor device according to claim 3. - 前記ｎチャネルＭＩＳ型電界効果トランジスタにおける前記ｘが０．５以上かつ０．５８以下であり、前記ｐチャネルＭＩＳ型電界効果トランジスタにおける前記ｘが０．９２以上かつ０．９７以下である、
ことを特徴とする請求項４記載の半導体装置。 The x in the n-channel MIS field effect transistor is 0.5 or more and 0.58 or less, and the x in the p-channel MIS field effect transistor is 0.92 or more and 0.97 or less.
The semiconductor device according to claim 4. - 前記ゲート電極に接する側がジルコニウム及びハフニウムの少なくとも一方を含む、
ことを特徴とする請求項５記載の半導体装置。 The side in contact with the gate electrode contains at least one of zirconium and hafnium;
The semiconductor device according to claim 5. - 前記ゲート電極に接する側が酸化ジルコニウム又は酸化ハフニウムである、
ことを特徴とする請求項６記載の半導体装置。 The side in contact with the gate electrode is zirconium oxide or hafnium oxide,
The semiconductor device according to claim 6. - ゲート電極及びゲート絶縁膜の積層構造を有するＭＩＳ型電界効果トランジスタを製造する方法において、
半導体基板上に、少なくとも上面がIV族遷移金属によって還元されない金属酸化物からなるゲート絶縁膜を形成する第一工程と、
前記ゲート絶縁膜上に、前記IV族遷移金属を含む導電膜からなるゲート電極を形成する第二工程と、
前記ゲート電極に対して酸素をイオン注入する第三工程と、
前記ゲート電極と前記ゲート絶縁膜との間に、前記IV族遷移金属及び前記酸素を含む界面層を熱処理によって形成する第四工程と、
を含むことを特徴とするＭＩＳ型電界効果トランジスタの製造方法。 In a method of manufacturing a MIS field effect transistor having a stacked structure of a gate electrode and a gate insulating film,
Forming a gate insulating film made of a metal oxide on at least an upper surface of which is not reduced by a group IV transition metal on a semiconductor substrate;
Forming a gate electrode made of a conductive film containing the group IV transition metal on the gate insulating film;
A third step of ion-implanting oxygen into the gate electrode;
A fourth step of forming an interface layer containing the Group IV transition metal and the oxygen by heat treatment between the gate electrode and the gate insulating film;
A method of manufacturing a MIS field effect transistor comprising: - 請求項８記載のＭＩＳ型電界効果トランジスタの製造方法を用いた半導体装置の製造方法であって、
前記第三工程において、前記ゲート電極をｎチャネルＭＩＳ型電界効果トランジスタを形成する第一領域とｐチャネルＭＩＳ型電界効果トランジスタを形成する第二領域とに分け、前記第一領域及び前記第二領域のうち少なくとも前記第二領域に対して酸素をイオン注入することにより、前記第一領域中の酸素量を前記第二領域の酸素量よりも少なくする、
ことを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device using the method of manufacturing a MIS field effect transistor according to claim 8,
In the third step, the gate electrode is divided into a first region for forming an n-channel MIS field effect transistor and a second region for forming a p-channel MIS field effect transistor, and the first region and the second region The oxygen amount in the first region is less than the oxygen amount in the second region by ion-implanting oxygen into at least the second region of
A method for manufacturing a semiconductor device. - 前記第一工程は、半導体基板上にダミーゲート電極を形成する工程と、前記ダミーゲート電極をマスクとして前記半導体基板の表層部に不純物を注入することによりソース及びドレインを形成する工程と、前記不純物を活性化させる熱処理を行う工程と、前記ダミーゲート電極の周囲を埋めるように層間絶縁膜を形成する工程と、前記ダミーゲート電極を除去することにより前記層間絶縁膜に溝を形成する工程と、前記溝内に少なくとも上面がIV族遷移金属によって還元されない金属酸化物からなるゲート絶縁膜を形成する工程とを含む、
ことを特徴とする請求項９記載の半導体装置の製造方法。 The first step includes a step of forming a dummy gate electrode on a semiconductor substrate, a step of forming a source and a drain by implanting impurities into a surface layer portion of the semiconductor substrate using the dummy gate electrode as a mask, and the impurity A step of performing a heat treatment to activate, a step of forming an interlayer insulating film so as to fill the periphery of the dummy gate electrode, a step of forming a groove in the interlayer insulating film by removing the dummy gate electrode, Forming a gate insulating film made of a metal oxide whose at least upper surface is not reduced by a group IV transition metal in the trench,
10. A method for manufacturing a semiconductor device according to claim 9, wherein:
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015046623A (en) * | 2014-11-04 | 2015-03-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． | Semiconductor device manufacturing method and semiconductor device |
| JP2019079907A (en) * | 2017-10-24 | 2019-05-23 | 東京エレクトロン株式会社 | Semiconductor device and CMOS transistor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003273350A (en) * | 2002-03-15 | 2003-09-26 | Nec Corp | Semiconductor device and method for manufacturing the same |
| JP2004186693A (en) * | 2002-12-03 | 2004-07-02 | Asm Internatl Nv | Method of forming electrode with adjusted work function |
| JP2007012783A (en) * | 2005-06-29 | 2007-01-18 | Toshiba Corp | Semiconductor device and its manufacturing method |
| JP2007073660A (en) * | 2005-09-06 | 2007-03-22 | Renesas Technology Corp | Semiconductor device and method of manufacturing same |
| JP2007165872A (en) * | 2005-12-16 | 2007-06-28 | Internatl Business Mach Corp <Ibm> | Semiconductor structure containing double metal gate and method for manufacturing same (self-alignment integration of double metal gate) |
Family Cites Families (1)
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| JP4764030B2 (en) * | 2005-03-03 | 2011-08-31 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003273350A (en) * | 2002-03-15 | 2003-09-26 | Nec Corp | Semiconductor device and method for manufacturing the same |
| JP2004186693A (en) * | 2002-12-03 | 2004-07-02 | Asm Internatl Nv | Method of forming electrode with adjusted work function |
| JP2007012783A (en) * | 2005-06-29 | 2007-01-18 | Toshiba Corp | Semiconductor device and its manufacturing method |
| JP2007073660A (en) * | 2005-09-06 | 2007-03-22 | Renesas Technology Corp | Semiconductor device and method of manufacturing same |
| JP2007165872A (en) * | 2005-12-16 | 2007-06-28 | Internatl Business Mach Corp <Ibm> | Semiconductor structure containing double metal gate and method for manufacturing same (self-alignment integration of double metal gate) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015046623A (en) * | 2014-11-04 | 2015-03-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． | Semiconductor device manufacturing method and semiconductor device |
| JP2019079907A (en) * | 2017-10-24 | 2019-05-23 | 東京エレクトロン株式会社 | Semiconductor device and CMOS transistor |
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