WO2009084026A2

WO2009084026A2 - System and method for high speed modulo operations

Info

Publication number: WO2009084026A2
Application number: PCT/IN2008/000800
Authority: WO
Inventors: Chandra Mohan Umapathy
Original assignee: Chandra Mohan Umapathy
Priority date: 2007-11-30
Filing date: 2008-12-01
Publication date: 2009-07-09
Also published as: WO2009084026A3

Abstract

The present invention proposes a system and method for high-speed modulo operation. The system comprises means (10) to accept two inputs P, Q on which the modulus operation is to be performed. A transformation of said inputs is carried out based on a choice enabled by a first multiplexer (11). Simultaneously, a second multiplexer (12) acts in conjunction with the first multiplexer (11) to decide on the numerical base in which this transformation is to be performed. The transformed inputs are then put though the means (13, 14) to perform the modulus operation. In case the outputs need to be biased (15, 16) this is also carried out before the final result (17) is presented. Two alternative embodimens, a parallel modulus method and a recursive modulus method, are also utilized.

Description

A SYSTEM, METHOD AND APPARATUS FOR HIGH-SPEED MODULO

OPERATIONS

FIELD OF THE INVENTION

This invention relates to a method of modulo in digital systems

DISCUSSION OF PRIOR ART

The modulo operation finds the remainder of division of one number by another. Given two numbers, a (the dividend) and n (the divisor), a modulo n (abbreviated as a mod n) is the remainder, on division of a by n. For example, "7 mod 3" would evaluate to 1, while "9 mod 3" would evaluate to 0. Typically a and n are integers however, several alternate computing systems allow other types of numeric operands. Modulo operations might be implemented such that division with remainder is calculated each time. For special cases, there are faster alternatives on some hardware. For example, the modulus of powers of 2 can alternatively be expressed as a bitwise AND operation: x % 2ⁿ =_ x & (2ⁿ - l)

Examples: x % 2 = x & 1 x % 4 == x & 3 x % 8 = x & 7

In devices and software that implement bit wise operations more efficiently than modulo, these alternative forms can result in faster calculations.

Several proposals have been put forth for efficient modulo operations, which find their use in several real-world applications including convolutional interleaving in telecommunication systems, cryptographic communication, turbo (de-)interleaving algorithms used with mobile radio standards, in particular UMTS, etc. The solutions present themselves at varying levels of abstraction including design-level solutions [1] which proposes an alternative modulo reduction theorem to decompose the base of the modulo operation. One of the end-applications envisioned is the reduction of the modulo size of the modified Chinese remainder theorem (CRT). Additionally, an FPGA implementation shows that the proposed modulo part of the residue-to-binary converter is nearly twice as fast, requiring only half the hardware of modulo converters proposed in prior art. US Patent 20050004967A1 proposes a Method and device for calculating modulo operations wherein the operation on positive numbers a mod p is calculated by using a look-up table containing the values n*p for n=l ,2,3..... a, where a mod p = a-n*p. US Patent 20030065697A1 proposes a Fast, iterative system and method for evaluating a modulo operation without using division wherein M mod J is calculated by decomposing M into two integers A, B such that B=M-A. The steps of evaluating A mod J and M'=(AmodJ)+B are then carried out. M' is then checked to determine if that is the final answer or whether another iteration needs to be carried out. US Patent 6536001 proposes a Circuit and method for convolutional interleaving using a single modulo operation wherein a pointer for interleaving/deinterleaving is used, which employs a single modulo operation. The single modulo pointer of this US Patent may be used to increase data throughput and a memory address pointer, for use with this patent, can be implemented by means of a multiplexer, an adder, a counter and a modulo operator.

Most inventions of the prior art tie the modulo operation's application to a particular area of technology such as communications or cryptography. The specific area of technology to which the modulo operation is applied determines the parameters of the inventions of the prior art.

SUMMARY OF THE INVENTION

It is an object of this invention to provide a method, system and apparatus for performing modulo operations, by transforming either one or both input & base of operation, depending on the inputs and constraints. This invention proposes a generic method, system and apparatus for performing modulo operations, irrespective of the ultimate application, which is power-efficient. It is another object of this invention to provide design space compression by processing (n/x) width compressed inputs. By performing simpler computations, the present invention proposes an apparatus that is optimally harnessed for locality and regularity. The system of the present invention comprises means to transform the inputs to the modulus operation, into a smaller design space, means to compute the mod of the compressed inputs and means to compute the Inverse Transform of the result obtained in the previous step in order to bring the result into required design space.

It is another object of this invention to provide a system and method for computing the modulus wherein the design constraints of power dissipation, verification complexity and area utilized are optimized by compressing the design space of the data path. It is another object of this invention to provide optimizations to enable high-speed modulus calculations, irrespective of the application that is using that operation, by employing transformations at both the architectural and algorithmic levels of abstraction. The system and method of the present invention leverage the reduction of the design space to effectively reduce the complexity of the modulus operation. It is another object of this invention to provide an apparatus for performing the mod operation that has regularity and locality characteristics that address the issues of power consumption and ease of design.

BRIEF DESCRIPTION OF DRAWINGS

Fig. 1 shows the architecture for the system of the present invention at the top-level, using a generalized base.

Fig. 2a shows the Top-Level architecture for the Parallel Mod operation with four level partitioning.

Figure 2b shows the Top-Level architecture for the Parallel Mod operation with two level partitioning corresponding to example 5.

Fig. 3 shows the architecture of the system for recursive modulus computation. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention proposes different methods to perform the modulus operation including the steps of transforming the inputs (dividend and/or divisor) to achieve design space compression, performing the modulus operation in the reduced design space, inverse transforming the outputs of the operation thus performed to yield the final result.

EMBODIMENT I - MODULO OPERATIONS IN VARIOUS NUMBER SYSTEMS

EXAMPLE 1: Decimal Number System, Single Base Single Transformation

Consider an arbitrary two digit number 99 as dividend & a single digit arbitrary number 6 as divisor.

The goal is to compute | 99 | β = | a |_c

Since it is two digit number, consider the arbitrary base Bl = 100. The method of the present invention would follow the steps outlined below:

Cl = Bl - a = 1. TTRBANSFORM

C2 = I Bl M I OD

I O = 4. C3 = I Cl I α = 1.

INVERSE

C4 = C2 - C3 = 3 = | a i o TRANSFORM

EXAMPLE 2: Decimal Number System (DNS), Multiple Base(s) Multiple Transformation (Two Bases Two Level Transformation)

Consider an arbitrary two digit number 69 as dividend & a single digit arbitrary number 6 as divisor. The goal is to compute | 69 | ₆ = | a |_c

Since it is two digit number, consider two arbitrary bases Bl = 100 and B2 = 25, with B2 being chosen after the first transformation is performed. The method of the present invention would follow the steps outlined below:

Cl = Bl - a = 31. TRANSFORM

C2 = B2 + C.

= 25 + 6 = 31.

C3 = I c I C = 0 •

MOD

C4 = I B2 I C = 1.

C5 = I Bl I c= 4 .

INVERSE

Cl = C5 - C6 = 3 = I a I c TRANSFORM

EXAMPLE 3: Decimal Number System (DNS): Multiple Base(s) Multiple Transformation (Three Bases Three Level Transformation)

Consider an arbitrary two digit number 69 as dividend & a single digit arbitrary number 6 as divisor. The goal is to compute | 69 | β = | a |_c

Since it is two digit number, consider three bases Bl = 100, B2 = 50, B3 - 25

Cl = Bl - a = 31.

C2 = B2 + Cl = 19. TRANSFORM

C3 = B3 - C2 = 6.

C3 = I c I O = 0.

C4 = I B3 MOD

I c = L

C5 = I B2 I _c = 2.

C6 = I Bl I _c = 4. C7 = C4-C3 .= 1 = I C2 I C INVERSE TRANSFORM

C8 = C5-C4 = 1 = I Cl I c

C9 = C6-C5 I a I C

EXAMPLE 4 : Binary Number System (BNS): (Two Bases Two Level Transformation)

Consider an arbitrary four bit number 1001 as dividend and a two bit arbitrary number 11 as divisor where the goal is to compute 1 1001 | π = | a |_c

Since it is four bit number, consider Bl = 10000, B2 = 1000

Cl = Bl - a = 111. C2 = B2 - Cl = 01. TRANSFORM

C3 = I C2 Ic= 01.

C4 = I B2 I c = 10. MOD

C5 = I Bl I „ = 01.

C6 = C4 - C3= 01.

INVERSE C7 = C5 - C4 = 00. TRANSFORM

Biasing: At the final stage if the remainder is negative, we need to bias it by adding the divided once to the final remainder to get the correct result.

EMBODIMENT II - MODULO OPERATIONS IN VARIOUS NUMBER SYSTEMS WITH BIASING EXAMPLE 5: Binary Number System (BNS): Single Base(s) Single Transformation

Consider an arbitrary four bit number 1110 as dividend & a two bit arbitrary number 11 as divisor where the goal is to compute | 1110 | π = | a |_c

Cl = Bl - a = 10. TRANSFORM

C2 = I Cl I o = 10.

MOD C3 = I Bl I o = 01.

C4 = C3 - C2= -01.

INVERSE C5 = C+C4 = 10. TRANSFORM WITH BIASING

Fig. 1 shows the architecture for the system of the present invention at the top-level, using a generalized base. The means to accept inputs 10 accepts two inputs P, Q on which the modulus operation is to be performed. The transformation is carried out based on a choice, which is enabled by the multiplexer 11. Simultaneously, a second multiplexer 12 acts in conjunction with 11 to decide on the numerical base in which this transformation is to be performed. The transformed inputs are then put through the means to perform the modulus operation 13,14. hi case the outputs need to be biased 15,16 this is also carried out before the final result 17 is presented.

EMBODIMENT in - PARALLEL MODULO OPERATION EXAMPLE 6 : Decimal Number System

Consider an arbitrary two digit number 69 as dividend & a single digit arbitrary number 6 as divisor. The goal is to compute | 69 1 ₆ = | a |_c hi this case multiple bases & multiple levels is the only possibility.

In this case, the computation can be performed in parallel by choosing the base to suit the size of the operands, in the decimal number system the bases are chosen as powers of 10, starting with exponent 0, from right to left, such that:

69 mod 6 = (6 mod 6) * (10 mod 6) + (9 mod 6) = 0*4 + 3. Hence, 69 mod 6 = 3. Where Bl = 1O¹^I=IO⁰.

Fig. 2a shows the Top-Level architecture for the Parallel Mod operation with four level partitioning, hi this example, the means to accept input 1 takes in two inputs PQRS and T upon which the modulus operation is to be performed. The means to transform the inputs 2 partitions the inputs, using four-level partitioning, so that the modulus operation can be performed in parallel on each of the four partitions P, Q, R, S. The means to perform the modulus operation 3,4,5,6 uses a multiplicity of bases B3, B2, Bl, BO thereby demonstrating that multiple numeric formats can be supported in this system. The outputs of the modulus operation are then reverse transformed 7 in order to yield the final result 8.

Figure 2b shows the Top-Level architecture for the Parallel Mod operation with two level partitioning corresponding to example 5. Consider an arbitrary two digit number 69 (PQ) as dividend & a single digit arbitrary number 6 (T) as divisor. The goal is to compute | 69

Since it is two digit number, consider the partitioning input into two parts. The method of the present invention would follow the steps outlined below:

Cl = 6, C2 = 9

PARTITION / TRANSFORM

C3 = I Cl I _c = = 0.

C4 = I C2 I _c ^• = 3. MOD

C5 = I B⁰ I c . = 1.

C6 = I B¹ I c = 4.

C7 = C3 * C5 + C4 * C6 = 3

INVERSE TRANSFORM wrra BIASING Hence 69 mod 6 = 3. As shown in Fig. 2b, the means to accept input 20 takes in two inputs PQ and T upon which the modulus operation is to be performed. The means to transform the inputs 21 partitions the inputs, using four-level partitioning, so that the modulus operation can be performed in parallel on each of the four partitions P₅Q₅R₅S. The means to perform the modulus operation 22,23 uses a multiplicity of bases Bl₅BO thereby demonstrating that multiple numeric formats can be supported in this system. The outputs of the modulus operation are then reverse transformed 25 in order to yield the final result 26.

EMBODIMENT IV - RECURSIVE MODULO OPERATION

Fig. 3 shows the system diagram for the recursive modulo operation wherein the means to accept inputs, accepts two inputs a and c. There exists a decision block 30 which represents the means to transform the inputs if the need arises using the transformation means 31, 32, 33, 34. The means to compute the modulus and reverse transform the intermediate outputs to present the final output 35 are also shown.

EXAMPLE 7: Recursive Mod Operation, Binary Number System

Here we will transform (shift the base) the base to nearest power of 2 value, compute mod & then inverse transform. Figure 3 depicts the top-level architecture for the recursive mod operation.

I 10101 u = I 10101 100

= 10.

= 10 + 10 * ( 1 100I ₁₁)

= 10 + 10 * 1

= I 1001 11

I 10101 u ₌ 2 EXAMPLE 8 : Recursive Mod Operation, Binary Number System

I 10101 11 = I 10101 ₁₀₀₀

= 010.

= 010 + 1 * ( I 10001 ii)

= 10 + 1 * 10

= I 1001 n

I 10101 11 = 1

Consider an arbitrary four bit number 1010 as dividend & a two bit arbitrary number 11 as divisor where the goal is to compute 1 1010 | n = | a |_c.

1. Choosing 1000 as the base.

C = 11, Cl = 1000, C2 = a / Cl = TRANSFORM 1

C3 = I a I ci = 010.

MOD C4 = I Cl 1 _Q = 10.

C5 = C3 + C2 * C4= 1. INVERSE

TRANSFORM C6 = I C5 I c = 1 = I a |_o WITH BIASING

2.Choosing 100 as the base.

C = 11 , Cl = 100, C2 = a / Cl TRANSFORM

= 1 n

INVERSE

TRANSFORM

WITH BIASING

BIBLIOGRAPHY

1. Modulo deflation in (2/sup n/+l, 2/sup n/, 2/sup n/-l) converters haoqiang Bi; Wei Wang; Al-Khalili, A.

Claims

CLAIMS:

1. A method of computing the modulus for two inputs p and q, comprising the steps of: a. Accepting the Inputs; b. Deciding on whether the inputs need transformation; i. If the inputs need transformation, performing the same; c. Performing the modulus operation; d. Deciding on whether the inputs need inverse transformation; i. If the inputs need inverse transformation, performing the same; e. Generating the output.

2. A method of claim 1, wherein the inputs can be in any base and represented in any numerical format including decimal, binary or hexadecimal formats.

3. A method of claim 1, wherein the step of deciding on whether the inputs need transformation, is carried out depending on the parameter, which the design is trying to optimize, such as area, performance or power.

4. A method of claim 1 , wherein the transformation can be carried out such that: a. One or more transformations are performed on inputs, using one or more bases; b. Recursive transformations are performed using a one or more bases; and c. One or more transformations are performed using different bases.

5. A method of claim 1, wherein the transformation can utilize the subtraction operation.

6. A method of claim 1, wherein the transformation can utilize taking two's complement.

7. A method of claim 1 , wherein if the result of performing the modulus operation is negative, biasing is applied to the final result, to get the correct output.

8. A method of claim 1 , wherein the modulus operation can be computed in parallel, with the appropriate choice of transformation.

9. A method of claim 1, wherein the step of transformation, if applied multiple times, is referred to as a multi-level transformation wherein the transformations are performed until such time as the design parameter optimization objective is met.

10. A method of claim 1, wherein when using multi-level transformation, a different numerical base might be used at each transformation step.

11. A method of claim 1 , wherein when the inputs may each be in a different numeric base.

12. A method of claim 8, wherein the parallel modulus operation can be carried out in a multiplicity of numerical bases, using a multiplicity of transformation levels.

13. A method of claim 8, wherein the parallel modulus operation can be carried out by utilizing a numeric base, which is chosen based on the size of the operands.

14. A method of claim 1, wherein the modulus operation can be performed recursively including the use of biasing.

15. A system for performing the modulus operation on two inputs p and q, comprising: a. Means to accept inputs or operands, upon which the modulus operation is to be performed; b. Means to transform these operands into the required representation, iteratively; c. Means to perform the modulus operation on the transformed operands, to obtain the correct, numeric result; and d. Means to reverse the transformation of the result generated, in order to obtain the result in a numeric format similar to the input format.

16. A system of claim 9, wherein the means to transform operands and the means to reverse the transformation are capable of supporting such transformations as resulting from subtraction.

17. A system of claim 9, wherein the means to transform operands and the means to reverse the transformation are capable of supporting such transformations as resulting from taking two's complement.

18. A system of claim 9, wherein the inputs can be in any base and represented in any numerical format including decimal, binary or hexadecimal formats.

19. A system of claim 9, wherein the means to transform operands into the required representation is capable of making decisions based on the parameter, which the design is trying to optimize, such as area, performance or power.

20. A system of claim 9, wherein the means to perform transformation further comprises: a. Means to perform one or more transformations on inputs, using one or more bases; b. Means to perform recursive transformations using a one or more bases; and c. Means to perform one or more transformations using different numerical bases.

21. A system of claim 9, wherein if the result of performing the modulus operation is negative, biasing is applied to the final result, to get the correct output.

22. A system of claim 9, wherein the modulus operation can be computed in parallel, with the appropriate choice of transformation.

23. A system of claim 9, wherein the transformation, if performed multiple times, is referred to as a multi-level transformation wherein the transformations are performed until such time as the design parameter optimization objective is met.

24. A system of claim 9, wherein using multi-level transformation, a different numerical base might be used at each transformation step.

25. A system of claim 9, wherein using multi-level transformation, the inputs may each be in a different numeric base.

26. A system of claim 22, wherein the parallel modulus operation can be carried out in a multiplicity of numerical bases, using a multiplicity of transformation levels.

27. A system of claim 22, wherein the parallel modulus operation can be carried out by utilizing a numeric base, which is chosen based on the size of the operands.

28. A system of claim 22, wherein the parallel modulus operation can be carried out by transforming the inputs, also referred to as partitioning, in order to compute the modulus in parallel on various parts of the input.

29. A system of claim 22, wherein the parallel modulus operation can be carried out by partitioning the inputs into multiple partitions obtained by the transformation.

30. A system of claim 9, wherein the modulus operation can be performed recursively including the use of biasing.