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WO2009040670A3 - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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Publication number
WO2009040670A3
WO2009040670A3 PCT/IB2008/003119 IB2008003119W WO2009040670A3 WO 2009040670 A3 WO2009040670 A3 WO 2009040670A3 IB 2008003119 W IB2008003119 W IB 2008003119W WO 2009040670 A3 WO2009040670 A3 WO 2009040670A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
manufacturing method
method therefor
plasma
barrier layer
Prior art date
Application number
PCT/IB2008/003119
Other languages
French (fr)
Other versions
WO2009040670A2 (en
Inventor
Kotaro Miyatani
Original Assignee
Tokyo Electron Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US99543207P priority Critical
Priority to US60/995,432 priority
Application filed by Tokyo Electron Limited filed Critical Tokyo Electron Limited
Publication of WO2009040670A2 publication Critical patent/WO2009040670A2/en
Publication of WO2009040670A3 publication Critical patent/WO2009040670A3/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • H01L23/53295Stacked insulating layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention is a method of forming a barrier layer, which includes an insulator, on a fluorocarbon film formed on a substrate, the method including the steps of producing a plasma from a gas, forming the barrier layer on the fluorocarbon film by using the plasma and exposing the surface of the substrate to the plasma including a nitrogen to dope the nitrogen to the surface of the barrier layer.
PCT/IB2008/003119 2007-09-26 2008-09-25 Semiconductor device and manufacturing method therefor WO2009040670A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US99543207P true 2007-09-26 2007-09-26
US60/995,432 2007-09-26

Publications (2)

Publication Number Publication Date
WO2009040670A2 WO2009040670A2 (en) 2009-04-02
WO2009040670A3 true WO2009040670A3 (en) 2009-10-15

Family

ID=40511956

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2008/003119 WO2009040670A2 (en) 2007-09-26 2008-09-25 Semiconductor device and manufacturing method therefor

Country Status (1)

Country Link
WO (1) WO2009040670A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104752400A (en) * 2013-12-31 2015-07-01 中芯国际集成电路制造(上海)有限公司 Interconnection dielectric layer, manufacturing method thereof and semiconductor device thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1187342A (en) * 1996-11-28 1999-03-30 Sony Corp Method of forming inter-layer dielectric
JP2003218109A (en) * 2002-01-17 2003-07-31 Internatl Business Mach Corp <Ibm> Method for forming metallic pattern using sacrifice hard mask
JP2003531493A (en) * 2000-04-03 2003-10-21 シャープ株式会社 Method for increasing the adhesion of the silicon nitride to low-k fluorine-containing amorphous carbon with silicon carbide adhesion promoter layer
JP2005217142A (en) * 2004-01-29 2005-08-11 Semiconductor Leading Edge Technologies Inc Process for fabricating semiconductor device
WO2006137384A1 (en) * 2005-06-20 2006-12-28 Tohoku University Interlayer insulating film and wiring structure, and process for producing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1187342A (en) * 1996-11-28 1999-03-30 Sony Corp Method of forming inter-layer dielectric
JP2003531493A (en) * 2000-04-03 2003-10-21 シャープ株式会社 Method for increasing the adhesion of the silicon nitride to low-k fluorine-containing amorphous carbon with silicon carbide adhesion promoter layer
JP2003218109A (en) * 2002-01-17 2003-07-31 Internatl Business Mach Corp <Ibm> Method for forming metallic pattern using sacrifice hard mask
JP2005217142A (en) * 2004-01-29 2005-08-11 Semiconductor Leading Edge Technologies Inc Process for fabricating semiconductor device
WO2006137384A1 (en) * 2005-06-20 2006-12-28 Tohoku University Interlayer insulating film and wiring structure, and process for producing the same

Also Published As

Publication number Publication date
WO2009040670A2 (en) 2009-04-02

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