WO2008155801A1 - 情報処理装置及びレジスタ制御方法 - Google Patents

情報処理装置及びレジスタ制御方法 Download PDF

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Publication number
WO2008155801A1
WO2008155801A1 PCT/JP2007/000659 JP2007000659W WO2008155801A1 WO 2008155801 A1 WO2008155801 A1 WO 2008155801A1 JP 2007000659 W JP2007000659 W JP 2007000659W WO 2008155801 A1 WO2008155801 A1 WO 2008155801A1
Authority
WO
WIPO (PCT)
Prior art keywords
register
processing unit
information processing
threads
work registers
Prior art date
Application number
PCT/JP2007/000659
Other languages
English (en)
French (fr)
Inventor
Takashi Suzuki
Toshio Yoshida
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to EP07790185A priority Critical patent/EP2159690A4/en
Priority to PCT/JP2007/000659 priority patent/WO2008155801A1/ja
Priority to JP2009520142A priority patent/JP5316407B2/ja
Publication of WO2008155801A1 publication Critical patent/WO2008155801A1/ja
Priority to US12/638,764 priority patent/US8019973B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G06F9/30127—Register windows
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

　同時マルチスレッディング方式であり、各スレッドに設けられたレジスタウィンドウ方式を採用したマスタレジスタとワークレジスタとを接続するためのデータ転送バスを、スレッド間で共有することにより、回路面積を縮小するとともに、スレッド間でのレジスタへのアクセスの競合に伴う他スレッドへの命令実行の干渉を防止するレジスタウィンドウ方式の情報処理装置及びその制御方法を提供する。 　レジスタ読み出しにレジスタウィンドウ方式をとる装置において、同時マルチスレッディングを実現するため、マスタレジスタとワークレジスタをそれぞれスレッドごとに保有し、マスタレジスタからワークレジスタへのデータ転送バスをスレッド間で共有するレジスタセットを保有するレジスタウィンドウ方式の情報処理装置及びその制御方法。
PCT/JP2007/000659 2007-06-20 2007-06-20 情報処理装置及びレジスタ制御方法 WO2008155801A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP07790185A EP2159690A4 (en) 2007-06-20 2007-06-20 INFORMATION PROCESSING UNIT AND METHOD FOR CONTROLLING A REGISTER
PCT/JP2007/000659 WO2008155801A1 (ja) 2007-06-20 2007-06-20 情報処理装置及びレジスタ制御方法
JP2009520142A JP5316407B2 (ja) 2007-06-20 2007-06-20 演算処理装置および演算処理装置の制御方法
US12/638,764 US8019973B2 (en) 2007-06-20 2009-12-15 Information processing apparatus and method of controlling register

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000659 WO2008155801A1 (ja) 2007-06-20 2007-06-20 情報処理装置及びレジスタ制御方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/638,764 Continuation US8019973B2 (en) 2007-06-20 2009-12-15 Information processing apparatus and method of controlling register

Publications (1)

Publication Number Publication Date
WO2008155801A1 true WO2008155801A1 (ja) 2008-12-24

Family

ID=40155966

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000659 WO2008155801A1 (ja) 2007-06-20 2007-06-20 情報処理装置及びレジスタ制御方法

Country Status (4)

Country Link
US (1) US8019973B2 (ja)
EP (1) EP2159690A4 (ja)
JP (1) JP5316407B2 (ja)
WO (1) WO2008155801A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5115555B2 (ja) * 2007-06-20 2013-01-09 富士通株式会社 演算処理装置
JP2015014891A (ja) * 2013-07-04 2015-01-22 富士通株式会社 演算処理装置及び演算処理装置の制御方法
JP2016042268A (ja) * 2014-08-18 2016-03-31 ルネサスエレクトロニクス株式会社 マイクロコンピュータ

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8519008B2 (en) 2003-01-22 2013-08-27 Purina Animal Nutrition Llc Method and composition for improving the health of young monogastric mammals
CN117132450B (zh) * 2023-10-24 2024-02-20 芯动微电子科技(武汉)有限公司 一种可实现数据共享的计算装置和图形处理器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3646127B2 (ja) * 2000-10-13 2005-05-11 今井澄子デザイン事務所株式会社 広告媒体を備えた自動車
JP2006039815A (ja) * 2004-07-26 2006-02-09 Fujitsu Ltd マルチスレッドプロセッサおよびレジスタ制御方法
JP2006039874A (ja) * 2004-07-26 2006-02-09 Fujitsu Ltd 情報処理装置
JP2006099719A (ja) * 2004-08-30 2006-04-13 Sanyo Electric Co Ltd 処理装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06110688A (ja) * 1991-06-13 1994-04-22 Internatl Business Mach Corp <Ibm> 複数の順序外れ命令を並行処理するためのコンピュータ・システム
US6507862B1 (en) * 1999-05-11 2003-01-14 Sun Microsystems, Inc. Switching method in a multi-threaded processor
US6553487B1 (en) * 2000-01-07 2003-04-22 Motorola, Inc. Device and method for performing high-speed low overhead context switch
JP3737755B2 (ja) 2001-12-28 2006-01-25 富士通株式会社 レジスタウィンドウ方式によるレジスタファイル及びその制御方法
US7143412B2 (en) * 2002-07-25 2006-11-28 Hewlett-Packard Development Company, L.P. Method and apparatus for optimizing performance in a multi-processing system
JP3646137B2 (ja) * 2003-03-25 2005-05-11 独立行政法人科学技術振興機構 命令発行方法及び装置、中央演算装置、命令発行プログラム及びそれを記憶したコンピュータ読み取り可能な記憶媒体
US7426630B1 (en) * 2004-06-30 2008-09-16 Sun Microsystems, Inc. Arbitration of window swap operations
JP2006139496A (ja) * 2004-11-11 2006-06-01 Seiko Epson Corp 演算処理装置
WO2008155838A1 (ja) * 2007-06-20 2008-12-24 Fujitsu Limited 命令処理装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3646127B2 (ja) * 2000-10-13 2005-05-11 今井澄子デザイン事務所株式会社 広告媒体を備えた自動車
JP2006039815A (ja) * 2004-07-26 2006-02-09 Fujitsu Ltd マルチスレッドプロセッサおよびレジスタ制御方法
JP2006039874A (ja) * 2004-07-26 2006-02-09 Fujitsu Ltd 情報処理装置
JP2006099719A (ja) * 2004-08-30 2006-04-13 Sanyo Electric Co Ltd 処理装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2159690A4 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5115555B2 (ja) * 2007-06-20 2013-01-09 富士通株式会社 演算処理装置
JP2015014891A (ja) * 2013-07-04 2015-01-22 富士通株式会社 演算処理装置及び演算処理装置の制御方法
JP2016042268A (ja) * 2014-08-18 2016-03-31 ルネサスエレクトロニクス株式会社 マイクロコンピュータ

Also Published As

Publication number Publication date
JP5316407B2 (ja) 2013-10-16
US20100095093A1 (en) 2010-04-15
JPWO2008155801A1 (ja) 2010-08-26
US8019973B2 (en) 2011-09-13
EP2159690A1 (en) 2010-03-03
EP2159690A4 (en) 2010-09-01

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