WO2008130195A1

WO2008130195A1 - Display and method of driving the same

Info

Publication number: WO2008130195A1
Application number: PCT/KR2008/002310
Authority: WO
Inventors: Jea Gun Park; Gon Sub Lee; Su Hwan Lee; Dal Ho Kim; Sung Ho Seo; Woo Sik Nam; Hyun Min Seung; Jong Dae Lee; Dong Won Shin
Original assignee: Iucf-Hyu
Priority date: 2007-04-24
Filing date: 2008-04-23
Publication date: 2008-10-30

Abstract

Provided are a display and a method of driving the same. The display includes a plurality of scanning lines, a plurality of signal lines crossing the plurality of scanning lines, and a plurality of pixels provided in regions where the scanning lines and the signal lines cross each other. Herein, each of the pixels includes a charge trapping layer having bistable conductance and negative differential resistance (NDR) characteristics, and an organic luminescent layer electrically connected to the charge trapping 1 ayer.

Description

[DESCRIPTION] [Invention Title]

DISPLAY AND METHOD OF DRIVING THE SAME [Technical Field] The present disclosure relates to a display, and more particularly, to a display using a luminescent device where a charge trapping layer and an organic luminescent layer are stacked, and a method of driving the display. [BACKGROUND ART]

An organic electroluminescent device (OLED), which is considered as a promising next-generation flat panel display to replace a liquid crystal display (LCD) and a plasma display panel (PDP). Generally, the OLED includes multi-layered organic compounds of illuminants, and emits light as current flows when a voltage is applied thereto. Such an OLED is also called an organic electroluminescent display or an organic light emitting diode. While an LCD displays an image by selectively transmitting light and a PDP displays an image through plasma discharge, an OLED displays an image through electroluminescent mechanism. That is, an OLED includes two electrodes, i.e., cathode and anode, and an organic luminescent material interposed therebetween, and emits light in such a way that holes and electrons are injected into an organic luminescent layer from the anode and cathode, respectively, and then recombined with each other to create a recombination energy stimulating organic molecules. Such an OLED is being popularly applied to small-sized displays because it is self-luminescent and also has several advantageous merits such as wide viewing angle, high- definition, high-quality image and high response time. In particular, the OLED is in the limelight as next-generation displays for televisions and flexible displays.

Recently, an active matrix organic light emitting diode (AMOLED) is being predominantly used among various OLEDs because it adopts an active driving method capable of individually controlling pixels that are minimum units forming a screen. In the AMOLED, a scanning line is formed in one direction, and a signal line and a power supply line are formed in another direction crossing the one direction, thereby defining one pixel area. A switching thin film transistor (TFT) is formed in a region of the pixel area where the scanning line and the signal line cross each other. The switching TFT and the power supply line are connected to form a storage capacitor, and the storage capacitor and the power supply line are connected to form a driving TFT configured to supply current. Therefore, the OLED connected to the driving TFT is achieved.

In the AMOLED that supplies current through a TFT, carrier mobility becomes poor if an active layer used as a channel of the TFT is formed of amorphous silicon. Accordingly, polysilicon is used for the active layer because it has a high carrier mobility of 10 cπf/Vsec or more. However, a fabrication process of a polysilicon TFT is performed at a very high temperature, which makes it difficult to fabricate a flexible display. Since a glass substrate used to fabricate the TFT is deformed at a high temperature of 600 ^°C or more, a low temperature polysilicon (LTPS), which is obtained by crystallizing amorphous silicon at a low temperature, has been proposed to form polysilicon. To crystallize the amorphous silicon, an excimer laser annealing (ELA) process has been suggested. According to the ELA process, however, an overlap region onto which laser is duplicately irradiated may appear so that the overlap region differs in crystallization degree from other regions where laser is not duplicately irradiated. This leads to a decrease in stability, for example, a difference in current amount of a TFT due to device characteristics caused by crystallization degree, e.g., particularly, threshold voltage difference. Further, each TFT has a different grain boundary, and thus has nonuniform electrical properties.

Amorphous silicon or polysilicon should be formed in a typical display because the typical display employs TFTs. Further, a TFT configured to compensate for a current should be formed because an OLED is driven by a current. Hence, four or six TFTs should be used at present, thus causing a fabrication process to be too complicated and fabrication cost to be increased. Moreover, the TFT leads to a decrease in an aperture ratio in a bottom emission type device so that the aperture ratio is considerably reduced to 30-50%.

A related art display has only one current level, and thus a voltage should be divided into 64 levels for realizing 64 gray scale levels using only one current level. However, the related art display has a limitation in that it is difficult to realize a desired gray scale if a divisible voltage level is too small . [Disclosure]

[Technical Problem]

The present disclosure provides a display and a method of driving the same, which can improve an operating speed as well as an aperture ratio without using a thin film transistor (TFT). The present disclosure also provides a display and a method of driving the same, which can improve an aperture ratio and operating speed and easily control a gray scale by forming an organic layer and an organic luminescent layer between conductive layers. [Technical Solution]

In accordance with an exemplary embodiment, a display includes: a plurality of scanning lines; a plurality of signal lines crossing the plurality of scanning lines; and a plurality of pixels provided in regions where the scanning lines and the signal lines cross each other. Herein, each of the pixels includes: a charge trapping layer having bistable conductance and negative differential resistance (NDR) characteristics; and an organic luminescent layer electrically connected to the charge trapping layer.

The pixel may further includes an upper conductive layer and a lower conductive layer disposed over and under the charge trapping layer and the organic luminescent layer, respectively. The upper conductive layer may be connected to the signal line, and the lower conductive layer may be connected to the scanning line. The pixel may further include an intermediate conductive layer disposed between the charge trapping layer and the organic luminescent layer. The charge trapping layer may include an organic layer. The charge trapping layer may further include a nanocrystal layer disposed in the organic layer. The nanocrystal layer may include a plurality of nanocrystals and a barrier layer surrounding the nanocrystals. The nanocrystal may include at least one of aluminum (Al), titanium (Ti), zinc (Zn), iron (Fe), nickel (Ni), copper (Cu), gold (Au), silver (Ag), and an alloy thereof. The luminescent device may perform a program operation, an erase operation or a read operation depending on a level of a voltage applied between the scanning line and the signal line. Light is emitted during the read operation. An absolute value of an erase voltage may be greater than an absolute value of a program voltage, and an absolute value of a read voltage may be smaller than the absolute value of the program voltage.

The program voltage, the erase voltage and the read voltage are positive voltages or negative voltages. The program voltage may include a plurality of voltages with different levels, and the program voltage may be selected from a range of a threshold voltage of the pixel or higher and not greater than an NDR region. Here, a current with a plurality of levels may be output during the read operation depending on levels of the program voltages. The read voltage may include a plurality of voltages with different levels. Here, a current with a plurality of levels may be output during the read operation depending on levels of the read voltages.

In accordance with another exemplary embodiment, a method of driving a display includes: applying a program voltage to one pixel of the display including a plurality of pixels each of which includes a charge trapping layer having bistable conductance and NDR characteristic, and an organic luminescent layer emitting light using charges supplied from the organic layer; and applying a read voltage to the one pixel to allow the one pixel to emit light. The method may further include applying an erase voltage to the one pixel .

The program voltage may be applied to another pixel connected to another scanning line while the one pixel emits light. The erase voltage may be applied to another pixel connected to another scanning line while the one pixel emits light.

An absolute value of the erase voltage may be greater than an absolute value of the program voltage, and an absolute value of the read voltage may be smaller than the absolute value of the program voltage. In one frame, the erase voltage may be applied to the one pixel, after the program voltage is applied and then the read voltage is applied to the one pixel.

[Advantageous Effects]

As described above, in accordance with the exemplary embodiments, it is possible to manufacture a luminescent device with a simple structure, thus improving process efficiency and reliability of the device. Furthermore, since a TFT is not required in a display if the display is implemented by the use of the luminescent device of the exemplary embodiments, an entire device can be utilized as a display. This allows an aperture ratio to be increased to nearly 100%.

Also, in accordance with the exemplary embodiments, programming, erasing and reading speeds of a luminescent device are in the range of several nanoseconds to several tens of nanoseconds, and thus an operating speed of the device can be improved significantly.

Further, in accordance with the exemplary embodiments, the luminescent device has a variety of current levels depending on a program voltage and a read voltage. Accordingly, it is possible to realize 256 gray scale levels using such a variety of current levels.

Moreover, in accordance with the exemplary embodiments, since the luminescent device has low power consumption and a temperature increase is very small accordingly, a flexible display can be implemented. Also, it is possible to realize a wearable display that can be worn on the human body because the luminescent device is formed of almost organic materials.

Additionally, in accordance with the exemplary embodiments, it is possible to implement a display having ultra-high resolution of 1,000 ppi or more and low voltage performance, thus making it possible to realize a system on panel (SOP). [Description of Drawings]

Exemplary embodiments can be understood in more detail from the following description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a cross-sectional view of a luminescent device in accordance with an exemplary embodiment;

FIG. 2 is a cross-sectional view of a luminescent device in accordance with another exemplary embodiment;

FIG. 3 is a graph illustrating an operating speed of a luminescent device;

FIGS. 4 and 5 are graphs illustrating current versus voltage characteristics of a luminescent device employing AIDCN depending on a positive voltage and a negative voltage, respectively;

FIG. 6 is a graph illustrating retention characteristics of the luminescent device employing AIDCN;

FIGS. 7(a) and 7(b) are micrographic views of the luminescent device employing AIDCN;

FIGS. 8(a) and 8(b) are a graph and an optical image illustrating luminescent states of a luminescent device employing α-NPD; FIG. 9 is a schematic view of a display in accordance with an exemplary embodiment ;

FIG. 10 is a schematic constitutional view and a waveform diagram illustrating a method of driving the display in accordance with an exemplary embodiment ; FIG. 11 is a schematic constitutional view and a waveform diagram illustrating a method of driving the display in accordance with another exemplary embodiment; and

FIG. 12 is a graph illustrating relations between pixel width, resolution and aperture ratio of a display device in accordance with an exemplary embodiment . [Best Mode]

Hereinafter, specific embodiments will be described in detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

FIG. 1 is a cross-sectional view of a luminescent device in accordance with an exemplary embodiment. Specifically, FIG. 1 illustrates a bottom emission type luminescent device.

Referring to FIG. 1, an organic luminescent layer 120 is disposed between a first conductive layer 110 and a second conductive layer 130, and a charge trapping layer is disposed between the second conductive layer 130 and a third conductive layer 170. The luminescent device in accordance with this embodiment includes the first conductive layer 110, the organic luminescent layer 120, the second conductive layer 130, a first organic layer 140, a nanocrystal layer 150, a second organic layer 160, and the third conductive layer 170, which are sequentially stacked over a substrate 100. Therefore, the first organic layer 140, the nanocrystal layer 150 and the second organic layer 160 form the charge trapping layer. At least one of a hole injection layer and a hole transport layer may be further provided between the first conductive layer 110 and the organic luminescent layer 120. Likewise, an electron injection layer may be further provided between the organic luminescent layer 120 and the second conductive layer 130. The substrate 100 includes a light-transmitting substrate. For example, the substrate 100 may include an insulation substrate, a semiconductor substrate, or a conductive substrate. More specifically, the substrate 100 may include at least one of a plastic substrate (PE, PES, PET, PEN, etc.), a glass substrate, an aluminum oxide (A1203) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, a gallium phosphide (GaP) substrate, a lithium aluminum oxide (L1A1203) substrate, a boron nitride (BN) substrate, an aluminum nitride (AlN) substrate, a si licon-on-insulator (SOI) substrate, and a gallium nitride (GaN) substrate. When a semiconductor substrate or a conductive substrate is used as the substrate 100, an insulator should be provided between the first conductive layer 110 and the substrate 100 to insulate them from each other. In addition, a flexible substrate may be used as the substrate 100, which makes it possible to realize a flexible display or a wearable display.

The first conductive layer 110, which serves as an electrode for supplying holes, is formed of a transparent metal oxide having a high work function and allowing light to be emitted outside the device. For instance, the first conductive layer 110 is formed of indium tin oxide (ITO) to approximately 150 nm thick. In addition to the ITO, the first conductive layer 110 may be formed of chemically-doped conjugated polymer including polythiopene with excellent stability. Alternatively, the first conductive layer 110 may be formed of a metallic material with a high work function. In this case, it is possible to prevent the reduction in efficiency through non- radiative recombination at the first conductive layer 110. The organic luminescent layer 120, which functions to generate light through the recombination of holes and electrons, is formed to approximately 60 nm thick using a high- or low-molecular material. The low-molecular material used as the organic luminescent layer 120 may include hydroxyquinoline aluminum (Alq3) or the like, and the high-molecular material used as the organic luminescent layer 120 may include poly(p- phenylenevinylene) (PPV), ρoly(thiophene)s ((PTh)s), Cyano-PPV, poly(p- phenylene) (PPP) and polyCfluorene)s). As described above, the hole injection layer and the hole transport layer may be further provided between the first conductive layer 110 and the organic luminescent layer 120. The hole injection layer may be formed to approximately 20 nm thick using copper phthaloyanine (CuPc), and the hole transport layer may be formed to approximately 40 nm thick using a low-molecular material such as α-NPD or a high-molecular material such as poly(n-vinylcarbazole) (PVK). Likewise, the electron transport layer and the electron injection layer may be further provided between the organic luminescent layer 120 and the second conductive layer 140. The electron transport layer may be formed of Alq3, and the electron injection layer may be formed of lithium fluorine (LiF). Herein, the electron transport layer and the electron injection layer may be formed to approximately 0.5 nm thick, respectively. The second conductive layer 130, which serves as an electrode for injecting electrons into the organic luminescent layer 120, may be formed of a material with electrical conductivity to a thickness ranging from approximately 20 nm to approximately 150 nm. The second conductive layer 130 may be formed of a metal having low electrical resistance and excellent interfacial properties with a conductive organic material. For instance, the second conductive layer 130 may be formed of aluminum (Al), silver (Ag), gold (Au), platinum (Pt) or copper (Cu). Particularly, the second conductive layer 130 may be formed of a metal with a low work function so as to achieve high current density in electron injection by lowering a barrier between the organic luminescent layer 120 and the second conductive layer 130. Hence, the second conductive layer 130 may be formed of Al, which is relatively more stable in air.

The first organic layer 140 may be formed in a thickness range of approximately 5 nm to approximately 50 nm using a high- or low-molecular material. The high-molecular material may include PVK or polystyrene (Ps), and the low-molecular material may include at least one of AIDCN, α~NPD and Alq3. The first organic layer 140 may have bistable conductance, that is, two conductance states at the same voltage. The nanocrystal layer 150 maintains program or erase state of the luminescent device through charging or discharging. The nanocrystal layer 150 includes nanocrystals 151 and a barrier layer 152. The nanocrystals 151 may be formed of at least one of aluminum (Al), magnesium (Mg), zinc (Zn), nickel (Ni), iron (Fe), copper (Cu), gold (Au) and silver (Ag), or an alloy thereof. The barrier layer 152 surrounds the nanocrystals 151, and is formed of an oxide. For example, the nanocrystal 151 may be formed of Al, and the barrier layer 152 may be formed of AIxOy. The nanocrystal layer 150 may be formed by depositing metal in an evaporation deposition chamber and oxidizing it. The nanocrystal layer 150 may have a monolayered structure, or a multi- layered structure. When the nanocrystal layer 150 has the monolayered structure, it may be formed to a thickness ranging from approximately 1 nm to approximately 40 nm. When the nanocrystal layer 150 has the multi-layered structure, one to ten monolayered crystal layers may be stacked in sequence. Similarly to the first organic layer 140, the second organic layer 160 may be formed in a thickness range of approximately 5 nm to approximately 50 nm using at least one of a high-molecular material such as PVK and Ps, and a low-molecular material such as AIDCN, α-NPD and Alq3.

The third conductive layer 170 serves as an electrode for accumulating charges in the nanocrystal layer 150. Similarly to the second conductive layer 130, the third conductive layer 170 may be formed in a thickness range of approximately 2 nm to approximately 80 nm using all the materials with electrical conductivity. In particular, the third conductive layer 170 may be formed of Al . A thickness of each of the layers in the luminescent device in accordance with this embodiment is merely illustrated for convenience in description, and thus it is not limited thereto.

In the luminescent device in accordance with this exemplary embodiment of FIG. 1, the organic luminescent layer and the organic layer may be formed through the combination of a high-molecular material and a low-molecular material. That is, it is possible to manufacture the luminescent device by respectively forming the organic luminescent layer and the organic layer of a high-molecular material and a high-molecular material, a high-molecular material and a low-molecular material, a low-molecular material and a high molecular material, or a low-molecular material and a low-molecular material. Here, the high-molecular material of the organic luminescent layer may include PPV, (PTh)s, Cyano-PPV, PPP, polyCfluorene)s, or the like, and the low-molecular material may include Alq3 or the like. The high-molecular material of the organic layer may include PVR or Ps, and the low-molecular material may include AIDC, α-NPD or Alq3.

In the luminescent device in accordance with the exemplary embodiment, the nanocrystal layer 150 is shaped such that the barrier layer 152 surrounds the nanocrystals 151. That is, the nanocrystal layer 150 is formed through oxidation of metal elements. However, the present invention is not limited thereto, and thus the nanocrystal layer 150 may be formed in various ways. For example, a first barrier layer, a metal layer and a second barrier layer are formed between the first and second organic layers 140 and 160, and then cured to thereby form the nanocrystal layer 150 where the nanocrystals are surrounded by the barrier layer. Alternatively, the nanocrystal layer 150 and an organic layer may be formed by forming an organic material where nanocrystals surrounded by the barrier layer are dispersed. Various methods of forming the nanocrystal layer 150 will be described later.

Although the exemplary embodiment of FIG. 1 illustrates the bottom emission type luminescent device, the luminescent device where the organic luminescent layer and the organic layer are stacked may have a top emission type structure. Referring to FIG. 2, the top emission type luminescent device may be manufactured by forming a first organic layer 140, a nanocrystal layer 150 and a second organic layer 160 between a first conductive layer 110 and a second conductive layer 130, and forming an organic luminescent layer 120 between the second conductive layer 130 and a third conductive layer 170. Here, the first and second conductive layers 110 and 130 may be formed of a material with electrical conductivity, for example, Al. The third conductive layer 170 may be formed of a transparent conductive material, for example, a transparent conductive oxide (TCO) such as indium tin oxide (ITO) and indium zinc oxide (IZO). The second conductive layer 130 serves as an electrode for supplying electrons, and the third conductive layer 170 serves as an electrode for supplying holes. Alternatively, the top emission type luminescent device may be implemented such that the second conductive layer 130 serves as the electrode for supplying holes, and the third conductive layer 170 serves as an electrode for supplying electrons. In this case, the second conductive layer 130 may be formed of a metal with a high work function, for example, gold (Au). Alternatively, the second conductive layer 130 may be formed of a reflective metal and a transparent conductive material with a high work function. The reflective metal may include Al, Al:Nd, Ag or an alloy thereof. The transparent conductive material may include a transparent conductive oxide such as ITO and IZO. A light-transmitting electrode containing a metal having a lower work function than the second conductive layer 130 may be used for the third conductive layer 170. For example, the third conductive layer 170 may be formed of at least one selected from the group consisting of Mg, Mg".Ag, Ca, Ca:Ag, Ag, AlXa, Al:Ag, Li:Mg and Li. The luminescent device having the above-described structure performs a program or erase operation by charging or discharging the nanocrystal layer 150 when a program voltage or an erase voltage is applied to induce a predetermined voltage difference between the first and third conductive layers 110 and 170. When a read voltage is applied after the program operation, charges, i.e., electrons accumulated in the nanocrystal layer 150 are injected into the organic luminescent layer 120, thus allowing light to be emitted from the organic luminescent layer 120. The luminescent device of the exemplary embodiments can rapidly operate at a speed of several tens of nanoseconds, and has bistable conductance and negative differential resistance (NDR) characteristics. The luminescent device of the exemplary embodiments has a variety of current levels depending on the program voltage and the read voltage, which makes it possible to realize a desired gray scale. Hereinafter, characteristics of the luminescent device of the exemplary embodiments will be described in detail. FIG. 3 is a graph illustrating an operating speed of a luminescent device in accordance with the exemplary embodiments. Specifically, FIG. 3 is a graph of a current flow time measured after a voltage is applied to the luminescent device.

Referring to FIG. 3, it takes several tens of nanoseconds for a current (B) to starts flowing after a voltage (A) is applied to the luminescent device. Therefore, the program, erase, and read operations can be performed at ultra-high speed of several tens of nanoseconds. Accordingly, the luminescent device can remarkably improve its operating speed in comparison with a related art active matrix organic light emitting diode (AMOLED) of which pixel selection rate is 1/60 second. Further, there is no image sticking so that the display quality can be also enhanced.

FIG. 4 is a graph of current versus voltage (I-V) characteristics when a voltage is applied to a luminescent device in a forward direction using AIDCN for the first and second organic layers 140 and 160, and FIG. 5 is a graph of current versus voltage (I-V) characteristics when a voltage is applied to the luminescent device in a reverse direction. FIG. 6 is a graph illustrating retention characteristics of the luminescent device. FIGS. 7(a) and (b) are micrographic views of the luminescent device. The luminescent device to be illustrated in FIGS. 4 through 7 has a multi-layered structure including a first conductive layer of a 150 nm-thick ITO layer, a hole injection layer of a 20 nm-thick CuPc layer, a hole transport layer of a 40 nm-thick α-NPD layer, an organic luminescent layer of a 60 nm-thick Alq3 layer, an electron injection layer of a 0.5 nm-thick LiF layer, a second conducive layer of a 80 nm-thick Al layer, a first organic layer of a 30 nm- thick AIDCN layer, a metal layer of a 20 nm-thick Al layer, a second organic layer of a 30 nm-thick AIDCN layer, and a third conductive layer of a 80 nm- thick Al layer.

An oxygen plasma treatment is performed on ITO of the first conductive layer 110 and Al of the nanocrystal layer 150. The oxygen plasma treatment for the first conductive layer 110 is performed for approximately 30 seconds to clean the first conductive layer 110 and reduce a work function, and the oxygen plasma treatment for Al is performed for approximately 300 seconds to form the nanocrystal layer 150.

Referring to FIG. 4, when a predetermined voltage is applied to the first and third conductive layers 110 and 170 of the bottom emission type luminescent device where AIDCN is used for the first and second organic layers 140 and 160 and AL is used in the nanocrystal layer 150, the luminescent device has various current levels within a predetermined voltage range. That is, when an anode is connected to the first conductive layer 110 and a cathode is connected to the third conductive layer 170, and then a voltage is applied to the first and third conductive layers 110 and 170 in a forward direction while increase its voltage level continually, a current increases according to an increase in a voltage until the voltage reaches up to a predetermined level but the current decreases in spite of a voltage increase after the predetermined level. Such a region where the current decreases in spite of a voltage increase is called a negative differential resistance (NDR) region. Beyond the NDR region, the current increases again according as the voltage increases. For example, when the first and third conductive layers 110 and 170 are respectively connected to an anode and a cathode, and a voltage is applied in a forward direction while continually increasing its voltage level up to 10 V (see the plot 11 of FIG. 4), the amount of current flowing through the luminescent device increases from a threshold voltage (Vth) of approximately 3 V. As the applied voltage increases, the current reaches the maximum level at a voltage (Vimax) of approximately 4.5 V. Thereafter, the NDR region appears in a range between approximately 4.5 V to approximately 6 V, during which the current decreases as the voltage increases. When the voltage exceeds the NDR region, the current increases again from approximately 6 V as the voltage increases. Therefore, a voltage at which the current increases again beyond the NDR region, for example, 8 V, is an erase voltage (Ve).

Accordingly, by the use of the current versus voltage characteristics described above, it is possible to set respective voltages required for program, erase and read operations of the luminescent device in accordance with the exemplary embodiment. That is, the program voltage may be selected from a voltage range of the threshold voltage (approximately 3 V) or higher and not greater than the NDR region (approximately 6 V), the erase voltage may be selected from a voltage range beyond the NDR region (approximately 6 V), and the read voltage may be selected from a voltage range below the threshold voltage (approximately 3 V).

Further, in accordance with the exemplary embodiment, a current with different levels flow through the luminescent device during read operation depending on a voltage level of the program voltage.

Referring to the plot 12 of FIG. 14, when the luminescent device is programmed by a program voltage (Vp) of 4.5 V and a voltage increased to 4.5 V is then applied again, a current increases than before. Referring to the plots 13 and 14 of FIG. 4, when 5.3 V and 6 V of the NDR region are respectively applied to program the luminescent device and thereafter 5.3 V and 6 V are applied again, the current has an intermediate level higher than the current level of the plot 11 but lower than the current level of the plot 12. That is, it can be appreciated that a current having a level higher than the current level of the plot 11 flows when a read operation is performed after the program operation. The current level of the plot 11 may be equal to a current level when a read operation is performed after the luminescent device is erased.

Why such a phenomenon occurs will be described below. In the luminescent device of the exemplary embodiment, the first and second organic layers 140 and 160 serve as a Schottky barrier, and the barrier layer 152 serves as a tunneling barrier. Therefore, below the threshold voltage, charges are not accumulated in the nanocrystal layer 150 due to a difference in energy level between the nanocrystal layer 150 and the first and second organic layers 140 and 160, so that the amount of current increases minutely. When, however, a voltage applied between the first and third conductive layers 110 and 170 is higher than the threshold voltage (Vth) of the luminescent device of the exemplary embodiment, charges are accumulated in the nanocrystal layer 150 so that the amount of current increases sharply. Thereafter, the amount of current in the case where the charges are accumulated in the nanocrystal layer 150 is several tens to several hundreds of times the amount of current in the case where the charges are not accumulated. When the voltage applied between the first and third conductive layers 110 and 170 has a voltage level in the NDR region, the amount of current is lower than that of the case where charges are partially charged or discharged in the nanocrystal layer 150 (i.e., the case of applying Vimax voltage) but higher than that of the case where charges are not accumulated (i.e. the case of applying the erase voltage). When a voltage higher exceeding the NDR region, i.e., erase voltage, is applied, the charges accumulated in the nanocrystal layer 150 are discharged so that the luminescent device changes to an uncharged state.

In other words, when the voltage applied to the first and third conductive layers 110 and 170 is higher than the threshold voltage, charges are accumulated in the nanocrystal layer 150. This is because the charges are tunneled through the barrier layer and trapped in the nanocrystal layer 150. Beyond the threshold voltage, therefore, a current increases sharply. Afterwards, when the voltage continually increases to enter the NDR region, the charges are partially charged/discharged in the nanocrystal 150. NDR phenomenon occurs due to the electric field effect and partial charging/discharging of the charges trapped in the nanocrystal layer 150 so that the amount of current decreases although the applied voltage increases. When the voltage further increases continually, the erase phenomenon occurs so that the charges are not trapped in the nanocrystal layer 150 and further the charges trapped in the nanocrystal layer 150 are tunneled through the barrier layer to move into the organic layer. Accordingly, the charges trapped in the nanocrystal layer are removed at near the erase voltage, and the current increase as the voltage increases.

When a high program voltage selected from the NDR region of FIG. 4 is applied, the nanocrystal layer has a high resistance. This is because a current of the nanocrystal layer is reduced compared to the case where a relatively low program voltage selected from the NDR region is applied. That is, from Ohm' s law, i.e., R=V/I, a current has a low level with respect to a high voltage in the NDR region. Therefore, the application of high program voltage causes the resistance of the nanocrystal layer to be decreased.

When a read voltage is applied after the high program voltage is applied, the nanocrystal layer has a low current level at the read voltage due to its high resistance. On the contrary, when the read voltage is applied after the low program voltage is applied, the nanocrystal layer has a high current level at the read voltage due to a relatively low resistance.

As described above, a current flowing through the luminescent device is set differently depending on a level of the program voltage. Accordingly, a driving current required for light-emitting operation may be differently set depending on the applied program voltage.

As such, since the NDR region exists in the luminescent device of the exemplary embodiment, it is possible to apply a voltage (i.e., program voltage) with a plurality of levels used to accumulate charges in the nanocrystal layer 150. As the program voltages with the plurality of levels are applied, it is possible to realize a plurality of current levels, e.g., four current levels. Furthermore, a current with different levels may flow depending on the read voltage in the luminescent device of the exemplary embodiment. Consequently, compared to the related art luminescent device where 256 gray scale levels are realized using only one current level, the luminescent device of the exemplary embodiment realizes 256 gray scale levels using four current levels because 64 gray scale levels can be realized through one current level, making it possible to achieve a gray scale effectively. Here, the applied program voltage may be selected from a range of the threshold voltage or higher and not greater than a voltage of the NDR region. Since a slope of a current-voltage curve is steep in a range between the threshold voltage and the voltage Vimax, however, gentle in the NDR region, the program voltage may be selected from the NDR region to express accurate gradation. Referring again to FIG. 4, it can be observed that there are four current levels at 2 V. That is, an on-current (Ion) with a high current level (i.e., low resistance) appears at the read voltage (Vr) after the program voltage of 4.5 V is applied; intermediate currents (Iintl and Iint2) with intermediate current levels (i.e., intermediate resistance) appear at the read voltage (Vr) after the program voltages of 5.3 V and 6 V in the NDR region are applied; and an off-current (Ioff) with a low current level (i.e., high resistance) appears at the read voltage (Vr) after an erase voltage (Ve) is applied. A ratio (Ion/Ioff) of the on-current (Ion) with high level to the off-current (Ioff) with low level (hereinafter, referred to as on/off current ratio in brief) is approximately 1.2X102, and a current difference between the on-current (Ion) and the off-current (Ioff) is approximately 102 at the read voltage of 2 V. Hence, if AIDCN is used for the first and second organic layers 140 and 160, operation of the luminescent device can be variously controlled using the program voltage (Vp) in the range of 3 V to 6 V, the erase voltage (Ve) of 8 V, and the read voltage (Vr) of 2 V. The NDR region exists between the threshold voltage and the erase voltage, a program voltage with a plurality of levels can be applied, which makes it possible to obtain a plurality of current levels in a read operation. Therefore, a multi-state gray scale can be easily realized using the plurality of current levels. For example, since a four-state gray scale can be realized when the on/off current ratio (Ion/Ioff) is approximately 1.2X1028, 16 or 256 gray scale levels can be achieved by adjusting the on/off current ratio (Ion/Ioff). In the related art luminescent device, however, there is only one current level, and thus a voltage should be divided into 64 levels in order to achieve 64 gray scale levels using the one current level. Furthermore, if a divisible voltage level is small in the related art luminescent device, there is a limitation in realizing a gray scale. In contrast, the luminescent device of the exemplary embodiment has a variety of current levels depending on a program voltage and a read voltage, and thus 256 gray scale levels can be easily realized using the variety of current levels.

FIG. 5 is a graph of current versus voltage (I-V) characteristics when a voltage is applied to a luminescent device in a reverse direction. Referring to FIG. 5, if a voltage is successively increased in a reverse direction, a current increases up to a voltage with a predetermined level, then an NDR region appears in which a current decreases as a voltage increases, and subsequently a current increases again as a voltage increases. This is attributed to a symmetrical structure of a device, and therefore, the aforesaid mechanism of the case where the voltage is applied in the forward direction is also applicable to the case where the voltage is applied in the reverse direction.

By the use of this principle, the luminescent device of the exemplary embodiment performs program and erase operations by charging and discharging the nanocrystal layer 150 through application of a program voltage and an erase voltage, and also emits light using charges accumulated in the nanocrystal layer 150 through application of a read voltage. Accordingly, it is possible to perform main operations of a typical nonvolatile memory device, for example, program operation, read operation and erase operation. That is, when a program voltage is applied to the luminescent device, charges are accumulated in the nanocrystal layer 150 so that data '1' of logic HIGH is stored. On the contrary, when an erase voltage is applied to the luminescent device, charges are discharged from the nanocrystal layer 150 so that data is erased to '0' , i.e., logic LOW. When an intermediate program voltage, i.e., a voltage of the NDR region, is applied to the luminescent device, charges are partially accumulated in the nanocrystal layer 150 so that data having an intermediate logic level between logic HIGH and logic LOW is programmed to the luminescent device. When a read voltage is applied to the luminescent device, the amount of current flowing through the nanocrystal layer 150 is greatly varied according to whether the charges are accumulated in the nanocrystal layer 150. Resultingly, this current allows the organic luminescent layer 120 to emit light. Herein, the above-described logic levels may be changed depending on a measured current direction.

FIG. 6 is a graph illustrating current versus program/erase cycle when AIDCN is used for the first and second organic layers 140 and 160. Referring to FIG. 6, in the case (see the plot 11) where a read voltage of 2 V is applied after an erase voltage of 10 V is applied, in the case (see the plot 12) where the read voltage of 2 V is applied after a first program voltage of 4.5 V is applied, in the case (see the plot 13) where a read voltage of 2 V is applied after a second program voltage of 5.3 V is applied, and in the case (see the plot 14) where the read voltage of 2 V is applied after a third program voltage of 6 V is applied, constant current levels and four current states are maintained even if the program/erase cycle is increased. Thus, it is possible to realize four gray scales.

Referring to FIG. 7(a), it can be observed that a first conductive layer, an organic luminescent layer, a second conductive layer, a first organic layer, a nanocrystal layer, a second organic layer and a third conductive layer are distinctly formed. Referring to FIG. 7(b), it can be observed that a nanocrystal layer including Al nanocrystals and a barrier layer of an amorphous AIxOy surrounding the Al nanocrystals is formed between first and second organic layers. Herein, it can be also observed that the plurality of Al nanocrystals are surrounded by the barrier layer so that they are sufficiently isolated from each other. Although the description for characteristics of the luminescent device has been made in the case where AIDCN is used for the first and second organic layers 140 and 160, the luminescent device exhibits the same characteristics even if it employs a low-molecular material such as α-NPD and Alq3 or a high-molecular material such as PVK and Ps. For example, FIGS. 8(a) and 8(b) are optical images illustrating luminescent states of the case where a read voltage is applied after a program voltage is applied, and the case where a read voltage is applied after an erase voltage is applied. As illustrated in FIGS. 8(a) and 8(b) , light is not emitted when the read voltage is applied after the erase voltage is applied, whereas light is emitted when the read voltage is applied after the program voltage is applied. Herebelow, a display using the aforesaid luminescent device and a method of driving the same will be described.

FIG. 9 is a schematic view of a display in accordance with an exemplary embodiment. The display in accordance with this exemplary embodiment is implemented such that pixels are arranged in a matrix form. Here, each of the pixels includes an organic luminescent layer electrically connected to a charge trapping layer having bistable conductance and NDR characteristics.

Referring to FIG. 9, the display in accordance with this exemplary embodiment includes a plurality of scanning lines SLl to SLm extending in one direction, e.g., horizontal direction, a plurality of signal lines DLl to DLn extending in another direction, e.g., vertical direction and crossing the scanning lines SLl to SLm, and a plurality of pixels Mil to Mmn disposed in regions where the scanning lines SLl to SLm and the signal lines DLl to DLn cross each other. Here, each of the pixels Mil to Mmn includes a first conductive layer 110 and a third conductive layer 170, as illustrated in FIG. 1. The first conductive layer 110 is connected to the scanning line SLl to SLm, and the third conductive layer 170 is connected to the signal line DLl to DLn. Alternatively, the pixels Mil to Mmn may be implemented such that the first conductive layer 110 may be connected to the signal line DLl to DLn, and the third conductive layer 170 may be connected to the scanning line SLl to SLm. A program voltage (Vp), an erase voltage (Ve) and a read voltage (Vr) are applied to the luminescent device so as to program, erase and emit light through the scanning lines SLl to SLm or the signal lines DLl to DLn.

FIG. 10 is a schematic constitutional view and a waveform diagram illustrating a method of driving the display in accordance with an exemplary embodiment. In particular, FIG. 10 illustrates a method of driving the display using a bottom emission type luminescent device when a positive voltage is applied.

In the following exemplary embodiment, description for the method of driving pixels Mil to M54 will be made assuming that a program voltage (Vp) is 5 V, a read voltage (Vr) is 2 V, and an erase voltage (Ve) is 9 V. Herein, the program voltage (Vp) is a voltage used to program a pixel by accumulating charges in a charge trapping layer, a read voltage (Vr) is a voltage used to emit light by discharging the charges accumulated in the charge trapping layer, and the erase voltage (Ve) is a voltage used to discharge the charges accumulated in the charge trapping layer. The meaning the program voltage (Vp) is 5 V is that a voltage difference between the scanning line SLl to SL5 and the signal line DLl to DL4 is 5 V. Also, the meaning the read voltage (Vr) is 2 V is that a voltage difference between the scanning line SLl to SL5 and the signal line DLl to DL4 is 2 V. Likewise, the meaning that the erase voltage (Ve) is 9 V is that a voltage difference between the scanning line SLl to SL5 and the signal line DLl to DL4 is 9 V. Accordingly, it is possible to obtain the same result regardless of a negative or positive voltage only if an applied voltage induces a predetermined voltage difference between the scanning line SLl to SL5 and the signal line DLl to DL4. The case of applying a negative voltage will be described later. The program voltage (Vp), the erase voltage (Ve) and the read voltage (Vr) may be applied in a pulse type having a pulse width of several tens of nanoseconds. Herebelow, the driving method will be described for each operation at a timing when a pulse is applied. It is assumed that a driving mechanism of this exemplary embodiment starts from a state that charges are not accumulated in all the pixels, that is, an erased state.

In operation SIlO, 5 V is applied to the first scanning line SLl, 2 V is applied to the first and third signal lines DLl and DL3, and 0 V is applied to the second and fourth signal lines D2 and D4. At this time, 2 V is applied to the second to fifth scanning lines SL2 to SL5. Therefore, the pixels Mil and M13 connected between the first scanning line SLl and the first and third signal lines DLl and DL3 have a voltage difference of 3 V, and thus they are not programmed. In contrast, the pixels M12 and M14 connected between the first scanning line SLl and the second and fourth signal lines DL2 and DL4 have a voltage difference of 5 V, and thus they are programmed. The pixels M21 to M54 connected between the second to fifth scanning lines SLl to SL5 and the first to fourth signal lines DLl to DL4 have a voltage difference of 2 V or 0 V, and thus they are not programmed either.

In operation S120, the pixels M12 and M14 programmed in the operation SIlO emit light when 2 V is applied to the first scanning line SLl, 2 V is applied to the first and third signal lines DLl and DL3, and 0 V is applied to the second and fourth signal lines DL2 and DL4. At the same time, when 5 V is applied to the second scanning line SL2 and 2 V is applied to the third to fifth scanning lines SL3 to SL5, the pixels M12 and M14 maintain their luminescent states, and the pixels M22 and M24 connected between the second scanning lines SL2 and the second and fourth signal lines DL2 and DL4 are programmed because a voltage difference therebetween is 5 V.

In operation S130, the pixels M22 and M24 programmed in the operation S130 emit light when 2 V is applied to the first signal line DLl and 0 V is applied to the second to fourth signal lines DL2, DL3 and DL4 while 2 V is applied to the first and second scanning lines SLl and SL2. Resultingly, the pixels M22 and M24 emit light while the pixels M12 and M14 emit light. At the same time, when 5 V is applied to the third scanning line SL3 and 2 V is applied to the fourth and fifth scanning lines SL4 and SL5, the pixels M32, M33 and M34 connected between the third scanning line SL3 and the second to fourth signal lines DL2 to DL4 are programmed because a voltage difference therebetween is 5 V.

In operation S140, the pixels M32, M33 and M34 programmed in the operation S130 emit light when 2 V is applied to the third scanning line SL3, 2 V is applied to the first and third signal lines DLl and DL3, and 0 V is applied to the second and fourth signal lines DL2 and DL4 while 2 V is applied to the first and second scanning lines SLl and SL2. As a result, the pixels M32, M33 and M34 emit light while the pixels M12, M22, M14 and M24 emit light. At the same time, when 5 V is applied to the fourth scanning line SL4 and 2 V is applied to the fifth scanning line SL5, the pixels M42 and M44 connected between the fourth scanning line SL4 and the second and fourth signal lines DL2 and DL4 are programmed because a voltage difference therebetween is 5 V.

In operation S150, likewise, the pixels M42 and M44 programmed in the operation S140 emit light when 2 V is applied to the fourth scanning line SL4, 2 V is applied to the first and third signal lines DLl and DL3, and 0 V is applied to the second and fourth signal lines DL2 and DL4. At the same time, when 5 V is applied to the fifth scanning line SL5, the pixels M52 and M54 connected between the fifth scanning line SL5 and the second and fourth signal lines DL2 and DL4 are programmed.

In operation S160, the pixels M52 and M54 programmed in the operation

S150 emit light when 2 V is applied to the fifth scanning line SL5, 2 V is applied to the first and third signal lines DLl and DL3, and 0 V is applied to the second and fourth signal lines DL2 and DL4. Consequently, the pixels

M12, M14, M22, M24, M32, M33, M34, M42, M44, M52 and M54 emit light so that

"H" is displayed on a screen.

Thereafter, the luminescent device may be erased when 9 V is applied to the first to fifth scanning lines SLl to SL5 and 0 V is applied to the first to fourth signal lines DLl to DL4.

Although this exemplary embodiment illustrates the driving method where a read operation is carried out after each pixel is programmed, and then an erase operation is performed again, the present invention is not limited thereto. That is, the luminescent device may be driven in such a manner that a read operation is performed after each pixel is selectively programmed or erased.

Meanwhile, in the above exemplary embodiment, the pixels emit light by applying the program voltage of 5 V, the erase voltage of 9 V and the read voltage of 2 V to the scanning lines SLl to SL5. However, the luminescent device may emit light by applying a negative voltage of ^~2 V as the read voltage. In this case, the third conductive layer 170 is connected to the scanning lines SLl to SL5 so that the pixels Mil to M54 receive the program voltage of 5 V, the erase voltage of 9 V, and the read voltage of -2 V, and the first conductive layer 110 is connected to the signal lines DLl to DL4 so that the pixels Mil to M54 receive 0 V or 2 V. In this case, even if the pixels Mil to M54 are selectively programmed or erased by applying the program voltage or the erase voltage, light is not emitted because a reverse voltage is applied. When the read voltage of -2 V is applied, a current flows between the pixels Mil to Mmn. Accordingly, the selected pixels Mil to Mmn, which are programmed, emit light.

Further, the pixel may emit light in such a manner that the pixel is selectively programmed by applying a negative voltage as the program voltage and the erase voltage, and thereafter a positive voltage is applied as the read voltage. A method of driving the display using the negative program and erase voltages will be described below with reference to FIG. 11.

FIG. 11 is a schematic constitutional view and a waveform diagram illustrating a method of driving the display in accordance with another exemplary embodiment. In particular, FIG. 11 illustrates a method of driving the display using a bottom emission type luminescent device when a negative voltage is applied.

Referring to FIG. 11, the pixels Mil to M54 are implemented such that the first conductive layer 110 is connected to the scanning line SLl to SL5, and the third conductive layer 170 is connected to the signal line DLl to DL4. In this exemplary embodiment, the pixels Mil to M54 are driven by applying a program voltage (Vp) of -5 V, a read voltage (Vr) of 2 V, and an erase voltage (Ve) of -10 V. The method of driving the pixels Mil to M54 in accordance with this exemplary embodiment of FIG. 11 is the same as the method of driving the pixels Mil to M54 in accordance with the previous exemplary embodiment of FIG. 10 except that a negative voltage is used as the program voltage and the erase voltage. Thus, description for the driving method will be made briefly and concisely. The program voltage of -5 V is sequentially applied to the first to fifth scanning lines SLl to SL5. For example, 0 V is applied to the second signal line DL2 and the fourth signal line DL4 connected to pixels for displaying "H" , and 0 V is also applied to the third signal line DL3 only when -5 V is applied to the third scanning line SL3. When 0 V is applied to the second, third and fourth signal lines DL2, DL3 and DL4 while -5 V is applied to the first to fifth scanning lines SLl to SL5, the pixels connected to the scanning lines and the signal lines are programmed because a voltage difference therebetween is 5 V. At this time, -2 V is applied to the signal lines connected to unprogrammed pixels, that is, -2 V is applied to the first and third signal lines DLl and DL3. Hence, a voltage difference between the scanning lines SLl to SL5 and the signal lines DLl and DL3 becomes 3 V so that the pixels disposed therebetween are not programmed.

The read voltage of 2 V is applied to the previous scanning line while the program voltage of -5 V is applied to a next scanning line. For example, the read voltage of 2 V is applied to the first scanning line SLl while the program voltage of -5 V is applied to the second scanning line SL2. At this time, 0 V is applied to the second and fourth signal lines DL2 and DL4. Consequently, the pixels receiving the read voltage of 2 V emit light. Of course, although -2 V is applied to the first and third signal lines DLl and DL3 connected to the unprogrammed pixels, 0 V is also applied to the third signal line DL3 when the program voltage is applied to the third scanning line SL3.

Thus light-emitting operation continues until the erase voltage of -10 V is applied to the first to fifth scanning lines SLl to SL5.

FIG. 12 is a graph illustrating relations between pixel width, resolution and aperture ratio of a display device in accordance with an exemplary embodiment. The resolution (D) and the aperture ratio (E) were simulated under conditions that widths of the scanning line and the signal line are set to 100 nm and the pixel width is varied from 0.1 μm to 1,000 μm. As illustrated in FIG. 12, it is possible to achieve the resolution of 1,000 ppi and the aperture ratio of 97.6% if the pixel width is 10 μm. Therefore, a display with ultra-high resolution and ultra-high aperture ratio can be realized.

Claims

[CLAIMS] [Claims Il

A display comprising^". a plurality of scanning lines; a plurality of signal lines crossing the plurality of scanning lines; and a plurality of pixels provided in regions where the scanning lines and the signal lines cross each other, wherein each of the pixels comprises a charge trapping layer having bistable conductance and negative differential resistance (NDR) characteristics, and an organic luminescent layer electrically connected to the charge trapping layer.

[Claims 2]

The display of claim 1, wherein the pixel further comprises an upper conductive layer and a lower conductive layer disposed over and under the charge trapping layer and the organic luminescent layer, respectively.

[Claims 3]

The display of claim 2, wherein the upper conductive layer is connected to the signal line, and the lower conductive layer is connected to the scanning line.

[Claims 4]

The display of claim 2, wherein the pixel further comprises an intermediate conductive layer disposed between the charge trapping layer and the organic luminescent layer.

[Claims 5] The display of claim 1, wherein the charge trapping layer comprises an organic layer.

[Claims 6]

The display of claim 5, wherein the charge trapping layer further comprises a nanocrystal layer disposed in the organic layer.

[Claims 7]

The display of claim 6, wherein the nanocrystal layer comprises a plurality of nanocrystals and a barrier layer surrounding the nanocrystals.

[Claims 8]

The display of claim 6, wherein the nanocrystal comprises at least one of aluminum (Al), titanium (Ti), zinc (Zn), iron (Fe), nickel (Ni), copper (Cu), gold (Au), silver (Ag), and an alloy thereof.

[Claims 9]

The display of claim 1, wherein the luminescent device performs a program operation, an erase operation or a read operation depending on a level of a voltage applied between the scanning line and the signal line that are connected to the pixel, and emits light during the read operation.

[Claims 10]

The display of claim 9, wherein an absolute value of a voltage for the erase operation is greater than an absolute value of a voltage for the program operation; and an absolute value of a voltage for the read operation is smaller than the absolute value of the voltage for the program operation.

[Claims 11] The display of claim 10, wherein the program voltage, the erase voltage and the read voltage are positive voltages.

[Claims 12] The display of claim 10, wherein the program voltage, the erase voltage and the read voltage are negative voltages.

[Claims 13]

The display of claim 9, wherein the program voltage includes a plurality of voltages having different levels, and the program voltage is selected in the range from a threshold voltage of the pixel to an NDR region, and currents having a plurality of levels are output during the read operation depending on levels of the program voltages.

[Claims 14]

The display of claim 13, wherein the read voltage includes a plurality of voltages having different levels, and currents having a plurality of levels are output during the read operation depending on levels of the read voltages.

[Claims 15]

The display of claim 9, wherein the read voltage comprises a plurality of voltages having different levels, and currents having a plurality of levels are output during the read operation depending on levels of the read voltages.

[Claims 16]

A method of driving a display, the method comprising: applying a program voltage to one pixel of the display which comprises a plurality of pixels each of which comprises a charge trapping layer having bistable conductance and NDR characteristic, and an organic luminescent layer emitting light using charges supplied from the organic layer; and applying a read voltage to the one pixel to allow the one pixel to emit light.

[Claims 17]

The method of claim 16, further comprising applying an erase voltage to the one pixel .

[Claims 18]

The method of claim 17, wherein the program voltage is applied to another pixel connected to another scanning line while the one pixel emits light.

[Claims 19]

The method of claim 17, wherein the erase voltage is applied to another pixel connected to another scanning line while the one pixel emits light.

[Claims 20]

The method of claim 17, wherein an absolute value of the erase voltage is greater than an absolute value of the program voltage; and an absolute value of the read voltage is smaller than the absolute value of the program voltage.

[Claims 21]

The method of claim 17, wherein the program voltage is applied to the one pixel, and then the read voltage is applied to the one pixel, and thereafter the erase voltage is applied to the one pixel, in one frame.