WO2008114201A2

WO2008114201A2 - Method for operating a data processing device, a data processing device and a data processing system

Info

Publication number: WO2008114201A2
Application number: PCT/IB2008/050996
Authority: WO
Inventors: Ivon Franciscus Helwegen; Henricus Renatus Martinus Verberne; Edwin Gerardus Johannus Maria Bongers
Original assignee: Koninklijke Philips Electronics N. V.
Priority date: 2007-03-21
Filing date: 2008-03-17
Publication date: 2008-09-25
Also published as: WO2008114201A3

Abstract

In order to reduce a power consumption of a data processing device (10) for use in a networked data processing system, the crystal oscillator device (16) and corresponding clock signal generator circuit (14) are switched off, when the data processing device is idle. However, restart of the crystal oscillator device results in a relatively long start-up period, during which relatively much energy is consumed. In accordance with the present invention, during the idle state, the crystal oscillator device is alternatingly switched on and off at a predetermined frequency and with a predetermined duty cycle. Thus, it is possible to substantially shorten the start-up period and substantially reduce the average power consumption in the idle state.

Description

Method for operating a data processing device, a data processing device and a data processing system

FIELD OF THE INVENTION

The present invention relates to a data processing device, a data processing system comprising such a data processing device and a method for operating the data processing device.

BACKGROUND OF THE INVENTION

In a data processing system such as a sensor network a relatively large number of sensor devices are coupled to each other and / or to a main data processing device. Such a data processing system may be a home control system, or any other environmental control system, comprising sensor devices for determining a condition in response to which the control system may control an appliance. Other applications include health care systems, such as a body area sensor network, and security systems, for example.

The devices of the data processing system may be coupled through cabling or wirelessly. Using integrated circuitry and wireless communication technology a data processing device such as a sensor device may be relatively small. Preferably, sensor devices are low-cost, multifunctional and small. Such a sensor device needs to be supplied with power without the need to be connected to an external power supply. Therefore, such a sensor device, i.e. a data processing device, may be provided with a (small) battery. To provide a reasonable operating period using a single battery, the power consumption needs to be as low as possible. Using integrated circuitry, which decreases in size and in power consumption over the years, it is possible to provide low-power consumption processing devices, but the remaining power consumption is still to high. Therefore, in known wireless apparatus such as PDA's, mobile phones and the like, a burst mode is employed. In a burst mode, the main circuitry of the apparatus is switched off preventing e.g. leakage currents to flow, thereby increasing battery life. However, other circuitry parts, such as the system clock, are left running. This may be acceptable in such apparatus, since the power consumption of these circuitry parts is relatively low compared to the power consumption of the apparatus as a whole. For example, a 32 kHz system clock may consume an amount of power in the order of 1 μW and a 20 MHz, or more, system clock may consume an amount of power in the order of 1 mW, or more. Small sensor devices, however, have not sufficient battery power for supplying such an amount of energy during a relatively long period. In a known method, the system clock signal generator circuit may be switched off as well. However, start-up of the crystal oscillator takes time, while the generated signal is not suitable to be used as a clock signal, and during start-up the power consumption is relatively high. Hence, a relatively large amount of energy is wasted during start-up.

OBJECT OF THE INVENTION

It is an object of the present invention to provide an operating method and a device, wherein an amount of energy consumed during start-up is decreased.

SUMMARY OF THE INVENTION

The above object is achieved in a method according to claim 1 and a data processing device according to claim 3. The present invention further provides a data processing system according to claim 8. In the method according to the present invention, when the data processor is in a standby mode and, thus, is not requiring a clock signal, the clock signal generator circuit and the crystal oscillator device are also put in a standby mode. In the standby mode, the crystal oscillator is alternatingly activated at a predetermined frequency and with a predetermined duty cycle. If the crystal oscillator is switched off and is switched on again within a certain period of time, the start-up period is shorter and the crystal does not have excessive power consumption. It is considered that the reduced start-up time and power consumption will only function well if the crystal has reached a certain oscillation state before being switched off. Thus, the above-mentioned period of time determines a frequency and the time for reaching the above-mentioned oscillation state determines the duty cycle, i.e. the period during which the crystal oscillator is switched on. Preferably, the duty cycle is selected such that the crystal oscillator oscillates stably, when the crystal oscillator is switched off again.

It is noted that in the method of the present invention, energy is required during the standby mode for driving the crystal oscillator in a pulsed way. However, the energy thus required is less than the energy required for start-up from a complete idle state. Hence, when using a suitable frequency and duty cycle, the overall power consumption is decreased. Moreover, also the start-up time (may also be referred to as recovery time) from the standby mode is decreased. The data processing device according to the present invention comprises a crystal oscillator device for supplying an oscillator signal; a clock signal generator circuit coupled to the crystal oscillator device for generating a clock signal based on the oscillator signal; and a data processor coupled to the clock signal generator circuit for receiving the clock signal. Further, the data processing device comprises an oscillator control circuit for switching the crystal oscillator device alternatingly on and off at a predetermined frequency and with a predetermined duty cycle, when the data processor is in a standby mode. Thus, the data processing device according to the present invention is configured for performing the method according to the present invention.

In an embodiment, the oscillator control circuit comprises a NAND-operator for switching the crystal oscillator device on and off. A first input of the NAND-operator is coupled to a low-frequency oscillator, the low- frequency oscillator being configured to output a switch signal oscillating at the predetermined frequency and with the predetermined duty cycle. A second input and the output of the NAND operator are coupled to the crystal oscillator device and are configured to function as an inverter circuit, when the switch signal has a low level. Thus, the oscillator control circuit controls the crystal oscillator device to be on or off corresponding to the switch signal provided by the low- frequency oscillator. It is noted that the low- frequency oscillator consumes little power such that the overall power consumption remains low.

In an embodiment the data processing device further comprises a network interface circuit for communicating in a networked data processing system. In particular, the network interface circuit is configured for wireless network communication.

In an embodiment, the data processing device is a sensor device. In such an embodiment the data processing device comprises a sensor circuit for sensing an external condition, the sensor circuit being coupled to the data processor for supplying a sensor signal to the data processor.

The present invention further provides a data processing system comprising at least one data processing device according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

Hereinafter, the present invention is elucidated with reference to the appended drawing, in which non-limiting embodiments are illustrated, and wherein

Fig. IA illustrates a data processing system comprising a number of data processing devices;

Fig. IB shows a block diagram of a prior art data processing device for use in the data processing system of Fig. IA;

Fig. 2 shows a block diagram of a data processing device in accordance with the present invention; Fig. 3 A shows a circuit diagram of a prior-art crystal oscillator device and a corresponding clock signal generator circuit;

Fig. 3B shows a graph illustrating an output signal of the clock signal generator circuit of Fig. 3 A during a stabilization phase after start-up;

Fig. 3C shows a graph illustrating an output signal of the clock signal generator circuit of Fig. 3 A during a stable steady- state operation phase;

Fig. 3D shows a graph illustrating the frequency content of the output signal of the clock signal generator circuit of Fig. 3A as a function of the time after start-up;

Fig. 4A shows a circuit diagram of a crystal oscillator device and a corresponding clock signal generator circuit in accordance with the present invention; Fig. 4B shows a graph illustrating a control signal, an energy consumption signal and an oscillating output signal;

Fig. 5A shows a graph illustrating a minimum power consumption as a function of the frequency of the on/off switching of the crystal oscillator;

Fig. 5B shows a graph of a duty cycle as a function of the frequency at minimum power consumption as shown in Fig. 5A; and

Fig. 6 shows a graph illustrating a control signal, an energy consumption signal and an oscillating output signal at minimum energy consumption of a crystal oscillator device operated in accordance with the present invention.

DETAILED DESCRIPTION OF EXAMPLES

In the drawings, similar reference numerals refer to similar elements. Fig. IA illustrates an embodiment of a data processing system 1. The data processing system 1 may be a sensor system, for example. The data processing system 1 comprises a main processing device 2 for receiving data from other devices and processing said data. The main processing device 2 may be coupled to said other devices through a data network 4, like the Internet, for example. A number of data processing devices 10, e.g. sensor devices, generate data and provide said data to the main processing device 2. Thereto, the data processing devices 10 may be networked allowing communication among each other and with a network connection device 6, such as an Internet gateway device, for example. In an embodiment, the data processing devices 10 may be directly linked to the data network 4 and/or configured to directly communicate with the main processing device 2.

In operation, each data processing device 10 generates data, for example by sensing an external condition. In an embodiment, the data processing system 1 is configured for monitoring a condition of a human body for use in health care. In such embodiment, the external condition may be a body condition such as a body temperature, a blood pressure, a heart beat rate, and the like. In another embodiment, the data processing system 1 may be configured for use in an ambient intelligence system. In such an embodiment, the external condition may be a room temperature, a detector for detecting the presence of a person, a lighting condition sensor, and the like. The present invention is however not limited to any kind of application of the data processing system 1.

The data generated by the data processing devices 10 is transferred to the main processing device 2 through a suitable connection as mentioned above. A suitable connection may be a direct communication link between each data processing device 10 and the main processing device 2 or may be, as shown, a network communication link through one or more other data processing devices 10, the network connection device 6, using a the data network 4. The main processing device 2 may evaluate the received data and/or control any device in response to the received, and possibly evaluated, data. Fig. IB illustrates an embodiment of a prior art data processing device 10 for example for use in a networked data processing system as shown in Fig. IA. The data processing device 10 comprises a data processor 12. The data processor 12 is coupled to a clock signal generator circuit 14 and a crystal oscillator device 16 for receiving a clock signal generated by the crystal oscillator device 16 and the clock signal generator circuit 14. A sensor device 18 is coupled to the data processor 12 for supplying a data signal comprising data representing an external condition 28 sensed by the sensor device 18. Received data may be stored in a suitable memory device 20 and/or may be transmitted by a suitable transmitter circuit 22. The transmitter circuit 22 may also be a transceiver circuit, of course. The transmission may be performed by means of wires or wireless. A suitable controller circuit 24, such as an interrupt handler for example, is coupled to the sensor device 18, the data processor 12 and a clock signal switch 26. The controller circuit 24 is configured to control the clock signal switch 26 in response to a sleep signal or an activation signal. For example, the data processor 12 may supply a sleep signal to the controller circuit 24 as soon as the data processing and/or data transmission and/or data storage operation is completed in order to reduce power consumption during an idle time of the data processor 12. In response to the sleep signal, the controller circuit 24 switches the clock signal switch 26 non conducting, thereby disconnecting the data processor 12 and the clock signal generator circuit 14. Since no clock signal is provided to the data processor 12, the data processor 12 is put in a low power-consumption sleep mode, thus using less power during the idle time. The crystal oscillator device 16 and the clock signal generator circuit 14 are still operative and consuming power. As soon as the sensor device 18 supplies an activation signal to the controller circuit 24, the controller circuit 24 may switch the clock signal switch 26 conductive, resulting in the data processor 12 receiving the clock signal again and therefore becoming operative again.

Fig. 2 illustrates an embodiment of a data processing device 10 in accordance with the present invention for example for use in a networked data processing system as shown in Fig. IA. Compared to the prior art data processing device as presented in Fig. IB, the data processing device 10 according to the present invention lacks a clock signal switch 26. In order to put the data processor 12 in a sleep mode, a suitable sleep mode signal is supplied by the controller circuit 24 to the data processor 12. Further, the sleep mode signal is supplied to the crystal oscillator device 16 and the clock signal generator circuit 14, which in response enter a sleep mode as well, thereby consuming less power, compared to the prior art embodiment of Fig. IB, when the data processor 12 is in the sleep mode. Fig. 3 A illustrates in more detail a crystal oscillator device 16 and a corresponding clock signal generator circuit. The illustrated circuit is a well-known prior art circuit. The clock signal generator circuit comprises a first capacitance C 1 , a second capacitance C2, a first resistance Rl, a second resistance R2 and an inverting operator OPl having an output terminal Sout for supplying the clock signal. In an embodiment, the crystal oscillator device is a GSX-333 crystal oscillating at 16 MHz. In such embodiment, the first and the second capacitances Cl, C2 may have a capacitance of 27 pF; the first and the second resistances Rl, R2 may have a resistance of 100 kΩ, 10 MΩ, respectively.

During a start-up phase of the crystal oscillator device 16, i.e. a period of time after activating the crystal oscillator device 16 to oscillate, the crystal oscillator device 16 does not oscillate. The start-up phase may take about 50 μs, for example. In a stabilization phase, occurring after the start-up phase, the crystal oscillator device 16 oscillates, but generates a signal comprising frequencies in a large range. The stabilization phase may take about 7 ms, for example. Thereafter, the crystal oscillator device 16 oscillates stably at a predetermined frequency in a relatively small frequency band.

The stabilization phase and the stable oscillation phase are illustrated in Fig. 3B - 3D. In Fig. 3D, an oscillation frequency as a function of the time is plotted. As is clearly visible, during the first 7 ms, the oscillation frequency varies considerably in a range between about 3 MHz and about 58 MHz. In Fig. 3B, the signal output by the clock signal generator circuit at the output terminal Sout is illustrated as a function of the time at about 2 ms after start of the oscillation of the crystal oscillator device 16. Referring to Fig. 3D again, after about 7 ms, the oscillation is stable at about 16 MHz, or at least in a small frequency range around 16 MHz. The clock signal at the output terminal Sout as a function of the time at about 10 ms after start-up is shown in Fig. 3C. During start-up and stabilization phase of the crystal oscillator device 16, a relatively high power consumption occurs. The power consumption is such that switching off the crystal oscillator device 16 during a relatively short period may not result in a reduction of power consumption compared to leaving the crystal oscillator device 16 in an operative state. Moreover, as apparent from Fig. 3B and 3D, the resulting signal in the stabilization phase is not suitable to be used as a clock signal. Consequently, in the prior art, the power consumed during the stabilization phase and the start-up phase is wasted.

In accordance with the present invention, the crystal oscillator device is alternatingly switched on and off at a predetermined frequency and with a predetermined duty cycle. Thereby, it is possible to prevent that the crystal oscillator device needs to go through the start-up phase and the stabilization phase as illustrated in Fig. 3B and 3D. Referring to Fig. 4A, an embodiment of a crystal oscillator device 16 and a clock signal generator circuit in accordance with the present invention is shown. Compared to the prior art circuit as shown in Fig. 3A, the clock signal generator circuit now comprises a NAND- operator NANDl instead of the inverting operator OPl. The NAND operator NANDl has two inputs, one of which is coupled to the other components of the clock signal generator circuit and the other input is coupled to an input terminal Sin for receiving a low- frequency input signal. When the input signal is has a low signal value, the crystal oscillator device 16 is switched on and when the input signal is has a high signal value, the crystal oscillator device 16 is switched off. Fig. 4B shows three signals Sl, S2, S3 as a function of time. The first signal Sl is an activation signal provided at the input terminal Sin. As mentioned above, if the activation signal is low, the crystal oscillator device 16 is switched on, otherwise the crystal oscillator device 16 is switched off. The second signal S2 represents power consumed by the crystal oscillator device 16. The third signal S3 represents the (clock) signal provided at the output terminal Sout.

As shown in Fig. 4B, at t = 0 ms, the activation signal Sl changes from a high signal value to a low signal value, thereby switching the crystal oscillator device 16 on. As illustrated by the third signal S3, after a short start-up phase the crystal oscillator device 16 starts to generate a wave signal, while consuming relatively high power as shown by the second signal S2. At about t = 1.8 ms, the power consumption (referring to the second signal S2) is reduced and as seen from the third signal S3, the oscillation becomes (more) stable. The stabilization phase has taken less than 2 ms instead of 7 ms as shown in Fig. 3D. The stabilization phase may be shorter, if the crystal oscillator device 16 has not been switched off during a relatively long period of time before it is switched on again.

Moreover, the duration of the stabilization phase may be dependent on the period of time that the crystal oscillator device 16 has been switched off and may be dependent on the phase in which the crystal oscillator device 16 was at the time that the crystal oscillator device was switched off. Referring to Fig. 5A, the frequency with which the crystal oscillator device is switched on and off determines the time period during which the crystal oscillator device is switched off. As mentioned above, the length of this time period at least partly determines the length of stabilization phase and thus the corresponding power consumption. In Fig. 5 A, a power consumption of the crystal oscillator device is shown as a function of the on/off frequency. At about 10 Hz, i.e. being switched on and off about 10 times per second, almost 12 mW is consumed by the crystal oscillator device. The indicated power is determined as an average over the on/off period and multiplied by the number of on/off periods per second resulting in an average power consumption in Watts. At about 300 Hz, the power consumption is relatively low: about 4 mW. So, selecting a suitable frequency may reduce the power consumption by almost a factor of 3.

Above, it was also mentioned that the oscillation phase of the crystal oscillator device (start-up phase / stabilization phase / stable oscillation phase) at the time of switching off is relevant with respect to the duration of the stabilization phase and the corresponding power consumption. The oscillation phase is directly linked to the duration of the time period during which the crystal oscillator device is switched on. Defining the duty cycle as the percentage of the on/off period (T_on+off) during which the crystal oscillator is switched on (T_0n), so duty cycle D = (T_0n / T_on+Off) %, Fig. 5 B shows the duty cycle as a function of the frequency. The indicated graph shows the duty cycle at which the power consumption is lowest for the corresponding frequency. So, referring to Fig. 5A and 5B, for each frequency, there is a duty cycle at which the power consumption is at a minimum. Fig. 5A shows the minimum power consumption and Fig. 5B shows the duty cycle at which said minimum power consumption occurs.

Referring to Fig. 5B, it is noted that at about 10 Hz, the minimum power consumption occurs at a duty cycle of about 95%, meaning that the crystal oscillator device is best switched on almost continuously. Apparently, more power is consumed by switching off and restarting again then keeping the crystal oscillator device in an operative state. At about 300 Hz, however, the minimum-power duty cycle is about 5%, meaning that the crystal oscillator device is switched on for a relatively short period of time (T_0n = about 0.17 ms) once every about 3.3 ms (T_on+Off = about 3.3 ms) in order to arrive at the minimum average power consumption. This is illustrated in more detail in Fig. 6.

Fig. 6 shows three signals S4, S5 and S6. S4 is an activation signal; S5 is a power consumption signal and S6 is an oscillation signal (corresponding to Sl - S3 of Fig. 4B, respectively). The signals S4 - S6 are shown as a function of time. At to, i.e. t = 0, the activation signal S 1 is set at its low signal value, thereby switching the crystal oscillator device on. Correspondingly, the crystal oscillator device goes through a start-up phase and a stabilization phase as shown by the power consumption signal S5 and the oscillation signal S6. After a short period of time of about 0.17 ms, at t = t_{l s} the activation signal S4 is switched to a high signal value, thereby switching the crystal oscillator device off. At t₂, i.e. t = about 3.3 ms, the activation signal S4 is switched low again and the previous described steps are repeated. In the time period between ti and t₂ substantially no power is consumed and no oscillation signal is provided. However, due to repeatedly switching the crystal oscillator device on, the stabilization phase is short, as is best seen from the rapid fall off the power consumption signal S5 after switching on. Moreover, at t_ls it appears that the crystal oscillator device has already reached the stable oscillation phase.

Due to the operation method according to the present invention, the power consumption, in particular during an idle period, of a data processing device is substantially lowered. As a further advantage, the time required for recovering from the sleep mode is substantially lowered. As mentioned above, after about 0.17 ms, the crystal oscillator device reaches the stable oscillation phase and so the data processor of the data processing device may start performing operations and thus the data processing device has recovered in about 0.17 ms.

Although detailed embodiments of the present invention are disclosed herein, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which can be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed structure. More in particular, the present invention has been illustrated with reference to a particular crystal oscillator device (GSX- 333 @ 16 MHz). The length of the different phases during start-up may differ for other crystal oscillator devices and consequently, the frequency and duty cycle for arriving at a minimum power consumption may be different. Further, the illustrated examples and measurements are based on circuits comprising discrete electronic elements. If an integrated circuit is used, the power consumption may be further lowered.

Further, the terms and phrases used herein are not intended to be limiting; but rather, to provide an understandable description of the invention. The terms "a" or "an", as used herein, are defined as one or more than one. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily by means of wires.

Claims

CLAIMS:

1. Method for operating a data processing device (10), the data processing device comprising a crystal oscillator device (16) for supplying an oscillator signal, a clock signal generator circuit (14) coupled to the crystal oscillator device for receiving the oscillator signal and for generating a clock signal and a data processor (12) coupled to the clock signal generator circuit for receiving the clock signal, the method comprising:

- switching the crystal oscillator device alternatingly on and off at a predetermined frequency and with a predetermined duty cycle, when the data processor is in a standby mode.

2. Method according to claim 1, wherein the duty cycle is selected such that the oscillator is switched off, when the crystal oscillator device oscillates stably.

3. Data processing device (10) comprising:

- a crystal oscillator device (16) for supplying an oscillator signal; - a clock signal generator circuit (14) coupled to the crystal oscillator device for generating a clock signal based on the oscillator signal;

- a data processor (12) coupled to the clock signal generator circuit for receiving the clock signal;

- an oscillator control circuit for switching the crystal oscillator device alternatingly on and off at a predetermined frequency and with a predetermined duty cycle, when the data processor is in a standby mode.

4. Data processing device according to claim 3, wherein the oscillator control circuit comprises a NAND-operator (NANDl) for switching the crystal oscillator device on and off, a first input of the NAND-operator being coupled to a low- frequency oscillator, the low- frequency oscillator being configured to output an activation signal oscillating at the predetermined frequency and with the predetermined duty cycle, a second input and the output being coupled to the crystal oscillator device and functioning as an inverter circuit, when the activation signal has a low level.

5. Data processing device according to claim 3, wherein the data processing device further comprises a network interface circuit (22) for communicating in a networked data processing system (1).

6. Data processing device according to claim 5, wherein the network interface circuit is configured for wireless network communication.

7. Data processing device according to claim 3, wherein the data processing device further comprises a sensor circuit (18) for sensing an external condition (28), the sensor circuit being coupled to the data processor for supplying a sensor signal to the data processor.

8. Data processing system (1) comprising at least one data processing device according to any one of the claims 3 - 7.