WO2008114107A3 - Method of fabricating a hybrid substrate - Google Patents

Method of fabricating a hybrid substrate Download PDF

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Publication number
WO2008114107A3
WO2008114107A3 PCT/IB2008/000567 IB2008000567W WO2008114107A3 WO 2008114107 A3 WO2008114107 A3 WO 2008114107A3 IB 2008000567 W IB2008000567 W IB 2008000567W WO 2008114107 A3 WO2008114107 A3 WO 2008114107A3
Authority
WO
WIPO (PCT)
Prior art keywords
donor substrate
substrate
remainder
species
fabricating
Prior art date
Application number
PCT/IB2008/000567
Other languages
French (fr)
Other versions
WO2008114107A2 (en
Inventor
Konstantin Bourdelle
Original Assignee
Soitec Silicon On Insulator
Konstantin Bourdelle
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator, Konstantin Bourdelle filed Critical Soitec Silicon On Insulator
Priority to KR1020097011274A priority Critical patent/KR101428614B1/en
Priority to CN2008800012478A priority patent/CN101568992B/en
Priority to JP2009554093A priority patent/JP2010522426A/en
Priority to EP08719275A priority patent/EP2137755A2/en
Publication of WO2008114107A2 publication Critical patent/WO2008114107A2/en
Publication of WO2008114107A3 publication Critical patent/WO2008114107A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Abstract

The invention relates to a method of fabricating a hybrid substrate comprising at least two layers of crystalline material that are bonded directly to each other. This method is noteworthy in that it comprises steps consisting in: implanting at least one category of atomic and/or ionic species into a donor substrate so as to form therein a weakened zone forming the boundary between an active layer and a remainder; subjecting the front faces of the donor substrate and of a receiver substrate, to a heat treatment between 900°C and 1200°C, under hydrogen and/or argon for a time of at least 30 seconds; bonding said front faces to each other; detaching said remainder; the nature, implantation dose and implantation energy of said species being chosen so that the defects induced by these species within the donor substrate allow the remainder of the donor substrate to be subsequently detached but do not develop sufficiently during said heat treatment to prevent the subsequent bonding or to deform the front face of the donor substrate.
PCT/IB2008/000567 2007-03-20 2008-02-26 Method of fabricating a hybrid substrate WO2008114107A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020097011274A KR101428614B1 (en) 2007-03-20 2008-02-26 Method of fabricating a hybrid substrate
CN2008800012478A CN101568992B (en) 2007-03-20 2008-02-26 Method of fabricating a hybrid substrate
JP2009554093A JP2010522426A (en) 2007-03-20 2008-02-26 Method for manufacturing hybrid substrate
EP08719275A EP2137755A2 (en) 2007-03-20 2008-02-26 Method of fabricating a hybrid substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0702004A FR2914110B1 (en) 2007-03-20 2007-03-20 PROCESS FOR PRODUCING A HYBRID SUBSTRATE
FR0702004 2007-03-20

Publications (2)

Publication Number Publication Date
WO2008114107A2 WO2008114107A2 (en) 2008-09-25
WO2008114107A3 true WO2008114107A3 (en) 2008-12-11

Family

ID=38529493

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2008/000567 WO2008114107A2 (en) 2007-03-20 2008-02-26 Method of fabricating a hybrid substrate

Country Status (6)

Country Link
EP (1) EP2137755A2 (en)
JP (1) JP2010522426A (en)
KR (1) KR101428614B1 (en)
CN (1) CN101568992B (en)
FR (1) FR2914110B1 (en)
WO (1) WO2008114107A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2938117B1 (en) * 2008-10-31 2011-04-15 Commissariat Energie Atomique METHOD FOR PRODUCING A HYBRID SUBSTRATE HAVING AN ELECTRICALLY INSULATING CONTINUOUS LAYER BURIED
US20130154049A1 (en) * 2011-06-22 2013-06-20 George IMTHURN Integrated Circuits on Ceramic Wafers Using Layer Transfer Technology
US9281233B2 (en) * 2012-12-28 2016-03-08 Sunedison Semiconductor Limited Method for low temperature layer transfer in the preparation of multilayer semiconductor devices
CN108701589A (en) * 2016-02-16 2018-10-23 G射线瑞士公司 Structure, system and method for transmitting charge across bonded interface

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5421953A (en) * 1993-02-16 1995-06-06 Nippondenso Co., Ltd. Method and apparatus for direct bonding two bodies
EP1324385A2 (en) * 2001-12-21 2003-07-02 S.O.I. Tec Silicon on Insulator Technologies Process for transfering semiconductor thin layers and process for forming a donor wafer for such a transfer process
US20060208341A1 (en) * 2001-04-17 2006-09-21 California Institute Of Technology Bonded substrate and method of making same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2748851B1 (en) 1996-05-15 1998-08-07 Commissariat Energie Atomique PROCESS FOR PRODUCING A THIN FILM OF SEMICONDUCTOR MATERIAL
CN1260907A (en) * 1997-06-19 2000-07-19 旭化成工业株式会社 SOI substrate and process for preparing same, semi-conductor device and process for preparing same
FR2835097B1 (en) * 2002-01-23 2005-10-14 OPTIMIZED METHOD FOR DEFERRING A THIN LAYER OF SILICON CARBIDE ON A RECEPTACLE SUBSTRATE
KR100504163B1 (en) 2002-09-12 2005-07-27 주성엔지니어링(주) SOI substrate and method of manufacturing the same
US20040262686A1 (en) * 2003-06-26 2004-12-30 Mohamad Shaheen Layer transfer technique
FR2868599B1 (en) 2004-03-30 2006-07-07 Soitec Silicon On Insulator OPTIMIZED SC1 CHEMICAL TREATMENT FOR CLEANING PLATELETS OF SEMICONDUCTOR MATERIAL
WO2006037783A1 (en) * 2004-10-04 2006-04-13 S.O.I.Tec Silicon On Insulator Technologies Method for transferring a thin film comprising a controlled disturbance of a crystal structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5421953A (en) * 1993-02-16 1995-06-06 Nippondenso Co., Ltd. Method and apparatus for direct bonding two bodies
US20060208341A1 (en) * 2001-04-17 2006-09-21 California Institute Of Technology Bonded substrate and method of making same
EP1324385A2 (en) * 2001-12-21 2003-07-02 S.O.I. Tec Silicon on Insulator Technologies Process for transfering semiconductor thin layers and process for forming a donor wafer for such a transfer process

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CHUNG TAEKRYONG ET AL.: "InGaAsP lasers on GaAs fabricated by the surface activated wafer direct bonding method at room temperature", JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 37, no. 3B, March 1998 (1998-03-01), pages 1405 - 1407, XP002453643 *
TONG QIN-YI ET AL.: "Low temperature wafer direct bonding", JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, vol. 3, no. 1, 1 March 1994 (1994-03-01), pages 29 - 35, XP002453642 *

Also Published As

Publication number Publication date
FR2914110A1 (en) 2008-09-26
JP2010522426A (en) 2010-07-01
CN101568992B (en) 2011-03-30
FR2914110B1 (en) 2009-06-05
CN101568992A (en) 2009-10-28
WO2008114107A2 (en) 2008-09-25
EP2137755A2 (en) 2009-12-30
KR20090122176A (en) 2009-11-26
KR101428614B1 (en) 2014-08-11

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