Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/01—Manufacture or treatment
  • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
  • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/63—Vias, e.g. via plugs
  • H10W70/635—Through-vias
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/01—Manufacture or treatment
  • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
  • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers

Definitions

• the present invention relates to electrical connections and, more particularly, to a process of forming a package for such electrical connections.
• One aspect of our approach involves plating pillars of electrically conductive material up from a seed layer located on a substrate, surrounding the pillars with a fill material so that the pillars and fill material collectively define a first package, and removing the substrate from the first package.
• Another aspect of our approach involves a process for forming a package.
• the process involves applying a photoresist onto a seed layer-bearing substrate, defining openings in the photoresist at locations where interconnects are to be located, the openings extending down to and exposing the seed layer at the locations, plating the exposed seed layer until a desired height of plating metal has been built up, removing the photoresist while leaving the built up plating metal in place, applying a fill material into a volume created by the removal of the photoresist, and removing the substrate.
• FIG. 1 illustrates, in simplified form, a portion of a substrate 100 that will serve as the base for the process described herein;
• FIG. 2 illustrates, in simplified form, the portion of the substrate 100 after a seed layer has been deposited by metalizing
• FIG. 3 illustrates, in simplified form, the portion of the substrate of FIG. 2 in which a photoresist has been applied and patterned to create openings down to the seed layer;
• FIG. 4 illustrates, in simplified form, the portion of the substrate after plating is complete
• FIG. 5 illustrates, in simplified form, the portion of the substrate after removal of the photoresist
• FIG. 6 illustrates, in simplified form, the portion of the substrate after the package material is fully hardened
• FIG. 7 illustrates, in simplified form, the package after removal of the substrate and seed layer
• FIG 8 illustrates, in simplified form, the underside of a portion of the package containing the cross section of FIG. 7;
• FIG. 9 through FIG. 16 collectively illustrate, in simplified form, a more sophisticated variant of the instant approach to formation of a plated pillar package
• FIG. 17 illustrates, in simplified form, a package variant created by using the variant of FIG. 10 through FIG. 15 as a substrate for the basic approach of FIG. 2 through FIG. 7; and [0018] FIG. 18 illustrates, in simplified form, a package variant created by using the variant of FIG. 10 through FIG. 15, to create a first package and then using that package as the substrate in the same variant approach.
• FIG. 1 through FIG. 8 collectively illustrate, in simplified form, a basic version of the instant approach to formation of a plated pillar package.
• FIG. 1 illustrates, in simplified form, a portion of a substrate 100 that will serve as the base for the process described herein.
• the substrate 100 can be a semiconductor wafer, a wafer of ceramic, or some other material of having the characteristics that it can withstand the operations involved in the process and, ultimately, can be removed without damaging the formed package.
• the substrate 100 will be very flat (e.g. if a standard 8" wafer, it should have an overall bow or dish of no more than, and preferably much less than, lO ⁇ m).
• the process begins by metalizing the substrate 100 to apply a thin layer of metal onto the substrate 100 and thereby form a seed layer for a subsequent plating operation (electroless or electro-plating).
• the metalization can be done through, for example, a vapor deposition process (chemical or physical) or any other suitable process.
• the substrate itself could be a metal or metal alloy. In such cases, if the substrate itself can serve as the seed layer, the metalizing step would be optional or unnecessary.
• the metalizing operation can be performed across the entire substrate, limited to particular areas (for example, an area suitably sized relative to the area of a chip to which the package will ultimately be attached), or even more limited to the vicinity of defined connection points.
• FIG. 2 illustrates, in simplified form, the portion of the substrate 100 after a seed layer 200 has been deposited by metalizing.
• FIG. 3 illustrates, in simplified form, the portion of the substrate 100 of FIG. 2 in which a photoresist 300 has been applied and patterned to create openings 302, 304, 306, 308 extending down to, and exposing, parts of the seed layer 200.
• the photoresist 300 can be flowable or solid.
• Conventional flowable photoresists used in semiconductor processing are suitable for use with the process.
• Suitable solid photoresist include those from the Riston® dry film photoresist line, specifically, the Riston® PlateMaster, EtchMaster and TentMaster lines of photoresist, all commercially available from E. I. du Pont de Nemours & Co.
• the openings all fall within about a
• the openings can be any desired size, but the approach will be most advantageous for high density interconnects where the openings are 50 ⁇ m wide or less, in some cases, less than lO ⁇ m wide, and the openings are on a pitch of 50 ⁇ m or less, in some cases again, less than lO ⁇ m.
• the substrate is inserted into a plating bath so that a plating metal 400 will build up on the parts of the seed layer 200 that were exposed through the patterned photoresist 300.
• a plating metal 400 can be allowed to build up to any height within the openings as desired.
• FIG. 4 illustrates, in simplified form, the portion of the substrate 100 after plating is complete.
• the photoresist 300 is removed as required for the particular photoresist 300 used.
• FIG. 5 illustrates, in simplified form, the portion of the substrate 100 after removal of the photoresist 300.
• the plating metal 400 left behind after removal of the photoresist 300 results in a series of upstanding "pillars" of the plating metal 400 that have essentially coplanar upper surfaces 402 and are anchored at their bottoms to the seed layer 200. These pillars will form the interconnects of the ultimate package.
• a package material 600 is applied to the substrate 100 to fill in the volume previously occupied by the photoresist 300 up to about the level of the upper surfaces 402.
• the package material 600 when solidified, should be electrically non-conducting and relatively stable and/or inert.
• the package material 600 is then allowed to solidify by hardening or curing as appropriate.
• this package material 600 can be a self hardening, curable or other material.
• Suitable examples of the package material 600 include moldable and flowable resins and plastics, such as for example, epoxies or liquid crystal polymers.
• FIG. 6 illustrates, in simplified form, the portion of the substrate 100 after the package material 600 is fully hardened.
• the substrate 100 and seed layer 200 are removed using a mechanical, chemical or chemical-mechanical process appropriate for the particular materials involved, leaving behind the fully formed package 700.
• FIG. 7 illustrates, in simplified form, the package 700 after removal of the substrate 100 and seed layer 200 from the underside 702 of the package 700.
• FIG. 8 illustrates, in simplified form, the underside 702 of a portion of the package 700 containing the cross section of FIG. 7, the cross section having been taken through the location indicated by the dashed line.
• this approach allows for formation of densely packed interconnects. For example, in the left side of FIG. 8, there are eight interconnects 400 located within a square area that is about 50 ⁇ m on a side.
• FIG. 9 through FIG. 16 collectively illustrate, in simplified form, a more sophisticated variant of the instant approach to formation of a plated pillar package.
• the approach is similar to that of FIG. 1 through FIG. 8, except for the metalization details.
• this variant will be described in abbreviated form with the understanding that, except as specifically noted, the details are the same as described in connection with FIG. 1 through FIG. 8.
• the process begins with a substrate 100.
• the process of metalizing the substrate 100 to form a seed layer 1000 for the subsequent plating operation occurs.
• the seed layer 1000 is applied after an intermediate patterning and lift-off has been performed to ensure that the seed layer 1000 is only located in areas where traces or contact points in the final package will be located.
• the seed layer 1000 is applied to be of sufficient thickness to allow the connection to ultimately carry the necessary current.
• FIG. 10 illustrates, in simplified form, the substrate 100 after the localized seed layer 1000 has been applied.
• Other metal or conductive material can connect the seed layers to allow current to flow to them if electroplating is subsequently used, however, the thickness of these connection regions need not be thick enough to carry the operating current of the final chips that are attached to the package.
• FIG. 11 through FIG. 14 the approach is the same as described above. Specifically, a photoresist 300 is applied and patterned to expose the relevant portion of the seed layer 1000 (FIG. 11). Then, the plating occurs to build up the plating metal 400 (FIG. 12). Next, the photoresist 300 is removed, leaving behind the pillars of plating metal 400. (FIG. 13).
• the substrate can undergo a preliminary plating operation.
• the purpose of this plating operation is to build up the seed to a thickness appropriate for handling the current that could be carried by the contact or trace in the ultimate package.
• the approach would otherwise be the same, except that the seed layer of FIG. 10 would already have a layer of plating metal over its extent and thus be thicker.
• the package material 600 is applied and solidified (FIG. 14), followed by removal of the substrate 100 (FIG. 15) from the underside 1402, and any connections between the seed portions (if a metal or other conductor were used as described above) leaving behind the fully formed package 1500.
• FIG. 16 illustrates, in simplified form, the underside 1402 of a portion of the package 1500 containing the cross section of FIG. 15, the cross section having been taken through the location indicated by the dashed line.
• this approach further allows for the package to contain connections 1602, 1604 between the interconnects or routing traces 1606, that can be connected to from external to the package 1500, for example, from another chip or another package.
• packages 700, 1500 can be treated as chips and thus, in addition to acting as a package for one or more chips, they can be stacked on and joined to each other or sandwiched between chips to allow for the formation of complex interconnects rivaling those created when back-end processing of a wafer to interconnect devices occurs.
• more complex interconnect arrangements can be created by simply using the final basic package in place of the substrate 100 and using the localized seed placement variant to apply a localized seed layer to a surface of the completed package. Then, the process described herein can be performed as described up to the point where the package material 600 is applied and solidified, at which point, the more complex package will be complete (i.e. there is no substrate to remove.
• FIG. 17 illustrates, in simplified form, a package 1700 variant created by using the variant of FIG. 10 through FIG. 15, and then using it as a substrate for the basic approach of FIG. 2 through FIG. 7.
• FIG. 18 illustrates, in simplified form, a package 1800 variant created by using the variant of FIG. 10 through FIG. 15, to create a first package and then using that package as the substrate in the same variant approach.
• plated packages created as described herein can, in some cases, be ideally suited for use with the different intelligent chip packages, or as the back end wafers, described in the above-incorporated applications.

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• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Electroplating Methods And Accessories (AREA)
• Manufacturing Of Printed Wiring (AREA)

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Family Applications (1)

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Citations (3)

Family Cites Families (254)

• 2007
  • 2007-02-16 US US11/675,731 patent/US7670874B2/en not_active Expired - Fee Related
• 2008
  • 2008-02-14 WO PCT/US2008/053994 patent/WO2008101102A1/en not_active Ceased
  • 2008-02-14 KR KR1020127003235A patent/KR101225921B1/ko not_active Expired - Fee Related
  • 2008-02-14 CN CN2012105183353A patent/CN103050437A/zh active Pending
  • 2008-02-14 EP EP08729889A patent/EP2118924A1/en not_active Withdrawn
  • 2008-02-14 KR KR1020097018959A patent/KR20090119901A/ko not_active Ceased
  • 2008-02-14 CN CN200880005012A patent/CN101715606A/zh active Pending
  • 2008-02-14 JP JP2009549725A patent/JP5204789B2/ja not_active Expired - Fee Related
• 2009
  • 2009-03-16 US US12/404,872 patent/US20090174079A1/en not_active Abandoned

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