WO2008069567A1  Apparatus and method for updating check node of lowdensity parity check codes  Google Patents
Apparatus and method for updating check node of lowdensity parity check codes Download PDFInfo
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 WO2008069567A1 WO2008069567A1 PCT/KR2007/006277 KR2007006277W WO2008069567A1 WO 2008069567 A1 WO2008069567 A1 WO 2008069567A1 KR 2007006277 W KR2007006277 W KR 2007006277W WO 2008069567 A1 WO2008069567 A1 WO 2008069567A1
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 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
 H03M13/1102—Codes on graphs and decoding on graphs, e.g. lowdensity parity check [LDPC] codes
 H03M13/1105—Decoding
 H03M13/1111—Softdecision decoding, e.g. by means of message passing or belief propagation algorithms
 H03M13/1117—Softdecision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the minsum rule
 H03M13/1122—Softdecision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the minsum rule storing only the first and second minimum values per check node

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
 H03M13/1102—Codes on graphs and decoding on graphs, e.g. lowdensity parity check [LDPC] codes
 H03M13/1105—Decoding
 H03M13/1111—Softdecision decoding, e.g. by means of message passing or belief propagation algorithms
 H03M13/1117—Softdecision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the minsum rule

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
 H03M13/1102—Codes on graphs and decoding on graphs, e.g. lowdensity parity check [LDPC] codes
 H03M13/1105—Decoding
 H03M13/1111—Softdecision decoding, e.g. by means of message passing or belief propagation algorithms
 H03M13/1117—Softdecision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the minsum rule
 H03M13/112—Softdecision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the minsum rule with correction functions for the minsum rule, e.g. using an offset or a scaling factor

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/65—Purpose and implementation aspects
 H03M13/6577—Representation or format of variables, register sizes or wordlengths and quantization
 H03M13/6583—Normalization other than scaling, e.g. by subtraction
Abstract
Description
Description APPARATUS AND METHOD FOR UPDATING CHECK NODE
OF LOWDENSITY PARITY CHECK CODES
Technical Field
[1] The present invention relates to error correction codes for use in a wired/wireless communications system, and more particularly, to an apparatus and method for updating check nodes of lowdensity parity check (LDPC) codes .
[2] This work was supported by the IT R&D program of MIC/IITA [2007S00101,
IMT Advanced Radio Transmission Technology with Low Mobility]. Background Art
[3] Signals transmitted by a wired/wireless communications system may not be demodulated in a receiver due to noise, interference, or fading according to the state of a channel.
[4] Several methods are used to reduce an error generation rate that increases with highspeed communications. These methods include a method of using error correction codes.
[5] Most recent wireless communications systems use error correction codes. In particular, lowdensity parity check (LDPC) codes are receiving much attention as error correction codes for nextgeneration highcapacity wireless communications systems, because variable nodes and check nodes of a decoder can be implemented to have low complexity and a decoder can achieve fast decoding by employing a parallel processing technique.
[6] LDPC codes have been proposed by Gallager, and are defined by a sparse parity check matrix. Most of the elements of the sparse parity check matrix are 0 and a very small number of elements are 1.
[7] There are two basic classes of the LDPC codes proposed by Gallager. Regular LDPC codes have a constant number of ones in every column or row of a parity check matrix. With irregular LDPC codes, the number of ones varies from row to row and column to column.
[8] It is generally known that irregular LDPC codes provide better performance than regular LDPC codes.
[9] Conventional techniques for updating check nodes will now be described.
[10] Equation 1 below is a variable node updating equation of a Sum Product algorithm for use in decoding LDPC codes: [11] [Math.l]
LLR channel i=O,i≠j (Equation 1)
[12] where LLR denotes an input log likelihood ratio (LLR) obtained by a de channel modulator, d denotes the degree of a variable node, u denotes an ith input LLR of the v i variable node, and v denotes a jth output LLR of the variable node. j
[13] The update of a variable node is represented as a sum of input values and thus hardware can be implemented by simply subtracting a specific value of the check node from a sum of d v inputs. Equation 2 below is a check node updating equation of a Sum
Product algorithm:
[14] [Math.2]
... (Equation 2)
[15] wherein d denotes the degree of a check node, v denotes a jth input LLR of the c J check node, and u denotes an ith output LLR of the check node. i [16] The update of a check node is represented as a sum of hyperbolic tangent values of input values and thus is difficult to be implemented by hardware. [17] Accordingly, several methods of lowering the complexity of variable nodes and check nodes of a decoder have been proposed. One of these methods can be represented as Equation 3, which is the logarithm of Equation 2:
[18] [Math.3]
... (Equation 3)
[19] According to Equation 3, multiplication is not needed when updating a check node, but Equation 3 should be calculated using a lookup table or the like as in Equation 2. Instead of such a complex process, a check node updating method has been proposed, which slightly degrades the performance and is represented as Equation 4:
[20] [Math.4]
... (Equation 4)
[21] wherein sgn denotes a function of outputting +1 when an input is positive and outputting  1 when an input is negative, and min denotes a function of outputting a minimum input value among various input values. Equation 4 represents a MinSum algorithm.
[22] Equation 5, representing a normalized MinSum algorithm, is as follows: [23] [Math.5]
... (Equation 5)
[24] wherein α denotes a normalization value. [25] Equation 6, representing an offset MinSum algorithm, is as follows: [26] [Math.6]
W, =
... (Equation 6)
[27] wherein β denotes an offset. [28] Although Equations 4, 5, and 6 have slight differences therebetween, they can be processed by performing an XOR operation on the sign of an output and obtaining a first minimum value and a second minimum value from d absolute input values.
Therefore, Equations 4, 5, and 6 can provide easier hardware implementations than the other equations. Disclosure of Invention Technical Problem
[29] The present invention provides an apparatus and method for obtaining a first minimum value and a second minimum value among several input values while linearly increasing only the complexity of calculation with an increase in the degree of a check node and not increasing the speed of parallel processing when parallel processing is used.
[30] The present invention also provides an apparatus and method for obtaining a first minimum input value and a second minimum input value among several input values while linearly increasing only the complexity of calculation with an increase in the degree of a check node and not increasing the processing speed when a check node of a low density parity check (LDPC) code is implemented. This method is applicable to a technique of using a MinSum algorithm, an Offset MinSum algorithm, or a Normalized MinSum algorithm during the update of a check node of a LDPC decoder in environments that require a fast processing decoder.
[31] Generally, even in an irregular LDPC code, at most about 12 d values (i.e., at least about two d values and about 3 to 4 d values on the average), and thus the complexity v v of implementation of a variable node is not high.
[32] However, the number of degrees of a check node increases with an increase in the code rate, and thus in IEEE 802.16e or 802.1 In, a check node of a LDPC code having an error rate of 5/6 has an average of about 20 degrees.
[33] Additionally, when a very high code rate, such as a code rate of 8/9, is used, the average number of degrees of a check node may be about 30. When a check node has a very large number of degrees as described above, a method of obtaining a minimum value by repeating a method of comparing two input values with each other and leaving a smaller input value may be inefficient.
[34] In a method of updating a check node while preventing an inefficient search for a minimum value according to the present invention, a first minimum input value is found by obtaining a most significant bit (MSB) of the minimum value from MSBs of respective input values and a least significant bit (LSB) of the minimum value from LSBs of the respective input values.
[35] The present invention also provides the use of a single apparatus both when a first minimum input value and a second minimum input value for each of a part and another part of a check node are obtained using a row split process and when a first minimum input value and a second minimum input value for the entire check node are obtained using a row split process. Technical Solution
[36] According to an aspect of the present invention, there is provided a method of updating a check node of an LDPC code in order to decode the LDPC code, the method comprising: (a) obtaining a first bit of a first minimum value among input values, the number of input values being equal to the number of degrees of the check node, by performing an AND operation on first bits of the input values, the first bits being most significant bits of the input values; (b) obtaining result values by switching and sequentially performing an XOR operation and an OR operation on the first bit of the first minimum value and each of the first bits of the input values; and (c) performing operations (a) and (b) on the result values set as input values and performing operations (a) and (b) a number of times corresponding to the number of bits of each input value, that is, repeating until last bits are set as input values, to thereby obtain the first minimum value, the last bits being least significant bits of the input values.
[37] According to another aspect of the present invention, there is provided an apparatus for updating a check node of an LDPC code in order to decode the LDPC code, the apparatus comprising a first bit processor, a second bit processor, a third bit processor, a fourth bit processor, and a bit minimum value calculator. The first bit processor obtains a first bit of a first minimum input value among 4bit input values, the number of which is equal to the number of degrees of the check node, by performing an AND operation on first bits of the 4bit input values, the first bits being MSBs of the 4bit input values, obtains first result values by sequentially performing an XOR operation and an OR operation on the first bit of the first minimum value and each of the first bits of 4bit input values, and obtains second result values by switching the 4bit input values to the first result values. The second bit processor obtains a second bit of the first minimum value among the 4bit input values by performing an AND operation on second bits of the second result values, obtains third result values by sequentially performing an XOR operation and an OR operation on the second bit of the first minimum value and the second bit of each of second result values, and obtains fourth results by switching the second result values to the third result values. The third bit processor obtains a third bit of the first minimum value among the 4bit input values by performing an AND operation on third bits of the fourth result values, obtains fifth result values by sequentially performing an XOR operation and an OR operation on the third bit of the first minimum value and the third bit of each of the fourth result values, and obtains sixth result values by switching the fourth result values to the fifth result values. The fourth bit processor obtains a fourth bit of the first minimum input value among the 4bit input values by performing an AND operation on fourth bits of the sixth result values, obtains seventh result values by sequentially performing an XOR operation and an OR operation on the fourth bit of the first minimum value and the fourth bit of each of the sixth result values, and obtains eighth result values by switching the sixth result values to the seventh result values. The bit minimum value calculator obtains the first minimum value by performing an AND operation on the first, third, fifth, and seventh result values. Advantageous Effects
[38] As described above, the present invention provides an apparatus and method for obtaining a first minimum input value and a second minimum input value among several input values while linearly increasing only the complexity with an increase in the degree of a check node and not increasing the processing speed when a check node of a LDPC decoder is updated using a MinSum algorithm, an Offset MinSum algorithm, or a Normalized MinSum algorithm. Accordingly, as compared with the conventional art, the check node update according to the present invention reduces the complexity of hardware and provides super highspeed processing.
[39] Moreover, the check node update according to the present invention is applicable to not only the field of LDPC code decoding but also all fields that require a function of searching a minimum input value. Description of Drawings
[40] The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
[41] FIG. 1 illustrates a factor structure of a lowdensity parity check (LDPC) code designed so that a check node with a degree of 24 can be rowsplit into two check nodes Rl and R2 each having a degree of 12;
[42] FIG. 2 illustrates an arithmetic operational block for obtaining sign bits in the LDPC code illustrated in FIG. 1 ;
[43] FIG. 3 illustrates an arithmetic operational block for obtaining a first minimal value and a second minimal value in the LDPC code illustrated in FIG. 1 ;
[44] FIG. 4 illustrates an arithmetic operational block for obtaining a first minimal value and a second minimal value in a LDPC code designed so that a check node with a degree of 24 can be rowsplit into two check nodes Rl and R2 each having a degree of 12, according to an embodiment of the present invention;
[45] FIG. 5 is a flowchart illustrating a method of updating a check node for a LDPC code, according to an embodiment of the present invention; and
[46] FIG. 6 is a flowchart illustrating a method of updating a
[47] check node for a LDPC code when a number of input values equal to the number of degrees of the check node are 4bit input values, according to an embodiment of the present invention. Best Mode
[48] According to an aspect of the present invention, there is provided a method of updating a check node of an LDPC code in order to decode the LDPC code, the method comprising: (a) obtaining a first bit of a first minimum value among input values, the number of input values being equal to the number of degrees of the check node, by performing an AND operation on first bits of the input values, the first bits being most significant bits of the input values; (b) obtaining result values by switching and sequentially performing an XOR operation and an OR operation on the first bit of the first minimum value and each of the first bits of the input values; and (c) performing operations (a) and (b) on the result values set as input values and performing operations (a) and (b) a number of times corresponding to the number of bits of each input value, that is, repeating until last bits are set as input values, to thereby obtain the first minimum value, the last bits being least significant bits of the input values.
[49] The first minimum value is set as a maximum input value, and a second minimum value is obtained by repeating operations (a), (b), and (c).
[50] The operations (a), (b), and (c) are repeated until a number of minimum values corresponding to the number of degrees of the check node are obtained.
[51] When the check node is a check node for a rowsplit parity check matrix, operations
(a), (b), and (c) are repeated until a number of minimum values corresponding to the number of degrees of each of the check node and another check node for a row split parity check matrix are obtained.
[52] When the input values are 4bit input values, operation (a) comprises obtaining the first bit of the first minimum input value among the 4bit input values by performing an AND operation on the first bits of the 4bit input values, the first bits being most significant bits of the 4bit input values, and operation (b) comprises obtaining first result values by sequentially performing an XOR operation and an OR operation on the first bit of the first minimum value, and each of the first bits of the 4bit input values and obtaining second result values by switching the 4bit input values to the first result values.
[53] The operation (c) comprises: (cl) obtaining a second bit of the first minimum value among the 4bit input values by performing an AND operation on second bits of the second result values; and (c2) obtaining third result values by sequentially performing an XOR operation and an OR operation on the second bit of the first minimum input value and the second bit of each of the second result values, and obtaining fourth result values by switching the second result values to the third result values.
[54] The operation (c) further comprises: (c3) obtaining a third bit of the first minimum value among the 4bit input values by performing an AND operation on third bits of the fourth result values; and (c4) obtaining fifth result values by sequentially performing an XOR operation and an OR operation on the third bit of the first minimum value and the third bit of each of the fourth result values, and obtaining sixth result values by switching the fourth result values to the fifth result values .
[55] The operation (c) further comprises: (c5) obtaining a fourth bit of the first minimum value among the 4bit input values by performing an AND operation on fourth bits of the sixth result values; and (c6) obtaining seventh result values by sequentially performing an XOR operation and an OR operation on the fourth bit of the first minimum value and the fourth bit of each of the sixth result values, and obtaining eighth result values by switching the sixth result values to the seventh result values.
[56] The operation (c) further comprises (c7) obtaining the first minimum value by performing an AND operation on the first, third, fifth, and seventh result values.
[57] The method further comprises (d) obtaining a second minimum value by setting as
4bit input values, the number of 4bit input values being equal to the number of degrees of the check node in operation (a), values obtained by switching the 4bit input values to results of NOT operations performed on the first minimum value and by re performing operations (a), (b), and (c).
[58] When the check node is a check node for a rowsplit parity check matrix, the method further comprises: obtaining a first minimum value and a second minimum value among 4bit input values for another rowsplit check node, the number of 4bit input values equal to the number of degrees of the another rowsplit check node, by performing operations (a), (b), and (c) on the 4bit input values; and obtaining a minimum value for each of the two check nodes from the first and second minimum values among the 4bit input values for each of the two check nodes.
[59] According to another aspect of the present invention, there is provided an apparatus for updating a check node of an LDPC code in order to decode the LDPC code, the apparatus comprising a first bit processor, a second bit processor, a third bit processor, a fourth bit processor, and a bit minimum value calculator. The first bit processor obtains a first bit of a first minimum input value among 4bit input values, the number of which is equal to the number of degrees of the check node, by performing an AND operation on first bits of the 4bit input values, the first bits being MSBs of the 4bit input values, obtains first result values by sequentially performing an XOR operation and an OR operation on the first bit of the first minimum value and each of the first bits of 4bit input values, and obtains second result values by switching the 4bit input values to the first result values. The second bit processor obtains a second bit of the first minimum value among the 4bit input values by performing an AND operation on second bits of the second result values, obtains third result values by sequentially performing an XOR operation and an OR operation on the second bit of the first minimum value and the second bit of each of second result values, and obtains fourth results by switching the second result values to the third result values. The third bit processor obtains a third bit of the first minimum value among the 4bit input values by performing an AND operation on third bits of the fourth result values, obtains fifth result values by sequentially performing an XOR operation and an OR operation on the third bit of the first minimum value and the third bit of each of the fourth result values, and obtains sixth result values by switching the fourth result values to the fifth result values. The fourth bit processor obtains a fourth bit of the first minimum input value among the 4bit input values by performing an AND operation on fourth bits of the sixth result values, obtains seventh result values by sequentially performing an XOR operation and an OR operation on the fourth bit of the first minimum value and the fourth bit of each of the sixth result values, and obtains eighth result values by switching the sixth result values to the seventh result values. The bit minimum value calculator obtains the first minimum value by performing an AND operation on the first, third, fifth, and seventh result values.
[60] A second minimum value is obtained by setting, as the 4bit input values in the first bit processor, values obtained by switching the 4bit input values to results of NOT operations performed on the first minimum value obtained in the bit minimum value calculator.
[61] The apparatus further comprises a node minimum value calculator which, when the check node is a check node for a rowsplit parity check matrix, calculates a minimum value for each of the check node and another rowsplit check node by using first and second minimum values of 4bit input values for each of the two check nodes, wherein the first and second minimum values of the 4bit input values for the another check node, the number of which is equal to the number of degrees of the another rowsplit check node, are obtained by setting the 4bit input values as the input values of the first bit processor. Mode for Invention
[62] The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown.
[63] In order to implement a decoder for lowdensity parity check (LDPC) codes, log likelihood ratio (LLR) values which are transmitted through edges need to be quantized and represented with x bits. [64] A quantization technique and the number of bits used affect the performance and complexity of the decoder for LDPC codes. When a normalization MinSum method is used, the value of a normalization factor α also affects the performance of the decoder for LDPC codes. When an offset MinSum method is used, the value of an offset β also affects the performance of the decoder for LDPC codes.
[65] A method of decoding LDPC codes according to the present invention is applicable to a MinSum method, a normalization MinSum method, and an offset MinSum method regardless of quantization techniques and parameter values. However, an application of the method of the present invention to an offset MinSum method will be illustrated. A similar extensive application of the present invention to the other methods can be easily performed, and a change to a block for performing a function similar to the update of a check node in a LDPC decoder can also be easily made.
[66] The present invention will be described in terms of two cases, namely, when a check node has a degree of 24 and when the check node with a degree of 24 is row split into two check nodes each having a degree of 12. Here, the number of parity bits of a parity check matrix when a row split has occurred is double the number of parity bits of a parity check matrix when a row split has not occurred.
[67] A case where 5 bits are used as quantization bits of a message will be considered. In this case, in order to update check nodes, one bit is used as a sign bit and four bits are used as magnitude bits.
[68] FIG. 1 illustrates a factor structure of a conventional LDPC code designed so that a check node with a degree of 24 can be row split into two check nodes Rl and R2 each having a degree of 12.
[69] In FIG. 1, when a row split is applied, two check nodes are formed. When a row split is not applied, a single check node remains.
[70] FIG. 2 illustrates an arithmetic operational block for obtaining sign bits in the conventional LDPC code illustrated in FIG. 1.
[71] It is assumed that an input value m[i] input to the arithmetic operational block uses 5 bits and a most significant bit (MSB) m[i][4] is used as a sign bit.
[72] When a row split is not applied, parity bits of Rl and R2, sgn_Rl and sgn_R2, have the same value. An output sign bit can be obtained by performing an XOR operation on the sgn_Rl and each of MSBs m[0][4] through m[l 1][4] of 5bit input values, and an output sign bit can be obtained by performing an XOR operation on the sgn_R2 and each of MSBs m[12][4] through m[23][4].
[73] The abovedescribed sign bit obtainment performed in the arithmetic operational block is widely used due to its simplicity. Accordingly, the present invention uses this sign bit obtainment.
[74] FIG. 3 illustrates an arithmetic operational block for obtaining a first minimal value and a second minimal value among input values in the conventional LDPC code illustrated in FIG. 1.
[75] Referring to FIG. 3, an input value m[i] input to the arithmetic operational block represents 4 magnitude bits excluding a MSB representing a sign among 5 bits.
[76] In FIG. 3, a quantization step 1 is used as an offset value β of the offset MinSum algorithm, and the arithmetic operational block is designed so as to repeat a function of obtaining the first and second minimal values among four input values.
[77] When a row split is not applied, first minimal values of Rl and R2, minl_Rl and minl_R2, have the same value, and second minimal values of Rl and R2, min2_Rl and min2_R2, have the same value.
[78] When minl_Rl is equal to each of input values m[0] through m[l 1], min2_Rl is determined as an output magnitude. On the other hand, when minl_Rl is different from each of the input values m[0] through m[l 1], minl_Rl is determined as an output magnitude. When minl_R2 is equal to each of input values m[12] through m[23], min2_R2 is determined as an output magnitude. On the other hand, when minl_R2 is different from each of the input values m[12] through m[23], minl_R2 is determined as an output magnitude.
[79] In the arithmetic operational block illustrated in FIG. 3, the number of comparison operations increases with an increase in the number of inputs. According to FIG. 3, 16 4bit comparators are needed for 12 inputs during 17 stages.
[80] In particular, the row degree of a LDPC code increases with an increase in a code rate, and thus a method of more efficiently processing the method of obtaining the first and second minimal values is needed.
[81] FIG. 4 illustrates an arithmetic operational block for obtaining a first minimal input value and a second minimal input value in a LDPC code designed so that a check node with a degree of 24 can be rowsplit into two check nodes Rl and R2 each having a degree of 12, according to an embodiment of the present invention. Referring to FIG. 4, the arithmetic operational block according to the current embodiment of the present invention includes a first bit processor, a second bit processor, a third bit processor, a fourth bit processor, a bit minimum value calculator, and a node minimum value calculator.
[82] Each of the first through fourth bit processors, the bit minimum value calculator, and the node minimum value calculator includes logic operators and processes a digital signal representing each input value.
[83] The first bit processor obtains a first bit of a first minimum input value among 4bit input values, the number of which is equal to the number of degrees of the check node, by performing an AND operation on first bits of the 4bit input values, the first bits being MSBs of the 4bit input values, obtains first result values by sequentially performing an XOR operation and an OR operation on the first bit of the first minimum value and each of the first bits of 4bit input values, and obtains second result values by switching the 4bit input values to the first result values.
[84] The second bit processor obtains a second bit of the first minimum value among the
4bit input values by performing an AND operation on second bits of the second result values, obtains third result values by sequentially performing an XOR operation and an OR operation on the second bit of the first minimum value and the second bit of each of second result values, and obtains fourth results by switching the second result values to the third result values.
[85] The third bit processor obtains a third bit of the first minimum value among the 4bit input values by performing an AND operation on third bits of the fourth result values, obtaining fifth result values by sequentially performing an XOR operation and an OR operation on the third bit of the first minimum value and the third bit of each of the fourth result values, and obtaining sixth result values by switching the fourth result values to the fifth result values.
[86] The fourth bit processor obtains a fourth bit of the first minimum input value among the 4bit input values by performing an AND operation on fourth bits of the sixth result values, obtains seventh result values by sequentially performing an XOR operation and an OR operation on the fourth bit of the first minimum value and the fourth bit of each of the sixth result values, and obtains eighth result values by switching the sixth result values to the seventh result values.
[87] The bit minimum value calculator obtains the first minimum value by performing an
AND operation on the first, third, fifth, and seventh result values.
[88] When the check node is for a rowsplit parity check matrix, the node minimum value calculator calculates a minimum value for each of the check node and another row split check node by using first and second minimum input values of 4bit input values for each of the two check nodes. The first and second minimum input values of the 4bit input values for the latter check node, the number of 4bit input values being equal to the number of degrees of the latter rowsplit check node, are obtained by setting the 4bit input values as the input values of the first bit processor and performing the operations of the first through fourth bit processors and the bit minimal value calculator on the 4bit input values.
[89] Referring to FIG. 4, an input value m[i] represents four magnitude bits excluding a
MSB representing a sign among five bits. A method of obtaining a first bit minl_Ql[3 ] of a first minimum input value among 12 input values for the check node Rl by using a quantization step 1 as an offset β of the offset MinSum algorithm and by using first bits m[0][3] through m[l 1][3] is performed on a second bit to a least significant bit (LSB), thereby obtaining a first bit of the first minimum value, minl_Ql. the input value m[i] corresponding to the minl_Ql is set to be a maximum input value, and the abovedescribed method of obtaining the minimum value is performed again, thereby obtaining a second bit of the first minimum value, min2_Ql.
[90] Although only a method of obtaining the minimum input value for the check node Rl has been explained with reference to FIG. 4, minl_Q2 and min2_Q2 for the check node R2 can also be obtained by applying the abovedescribed method of obtaining the minimum value to input values m[12] through m[23] for the check node R2. As illustrated in FIG. 3, a rowsplit check node is input, and output values for 24 input values of the check node can be obtained.
[91] When row split is not applied, minl_ Rl and minl_R2 have an identical value, and min2_Rl and min2_R2 have an identical value. When minl_Rl is equal to each of input values m[0] through m[l 1], min2_Rl is determined as an output magnitude. On the other hand, when minl_Rl is different from each of the input values m[0] through m[l 1], minl_Rl is determined as an output magnitude. When minl_R2 is equal to each of input values m[12] through m[23], min2_R2 is determined as an output magnitude. On the other hand, when minl_R2 is different from each of the input values m[12] through m[23], minl_R2 is determined as an output magnitude.
[92] When describing the method explained with reference to FIG. 4 in greater detail, an
AND operation is performed on first bits (i.e., MSBs) m[0][3], m[l][3], ..., and m[l l] [3] of 12 4bit input values m[0], m[l], ..., and m[l 1] in order to obtain a first bit minl_Ql[3] of a first minimum input value among the 12 4bit input values. Results values xl[i] are obtained by sequentially performing an XOR operation and an OR operation on minl_Ql[3] and m[i][3], and values a[i] are obtained by switching minl_Ql[3] to xl[i].
[93] Next, similar to the abovedescribed process, an AND operation is performed on second bits a[0][2], a[l][2], ..., and a[l l][2] of 12 4bit input values a[0], a[l ], ..., and a[l 1] in order to obtain a second bit minl_Ql[2] of the first minimum input value. Results values x2[i] are obtained by sequentially performing an XOR operation and an OR operation on minl_Ql[2] and a[i][2], and values b[i] are obtained by switching minl_Ql[2] to x2[i].
[94] Next, similar to the abovedescribed process, an AND operation is performed on third bits b[0][l], b[l][l], ..., and b[l I][I] of 12 4bit input values b[0], b[l], ..., and b[l 1] to obtain a third bit minl_Ql[l] of the first minimum input value. Results values x3[i] are obtained by sequentially performing an XOR operation and an OR operation on minl_Ql[l] and b[i][l], and values c[i] are obtained by switching minl_Ql[l] to x3[i].
[95] Next, similar to the abovedescribed process, an AND operation is performed on fourth bits c[0][0], c[l][0], ..., and C[I l][O] of 12 4bit input values c[0], c[l], ..., and c[l 1] in order to obtain a fourth bit minl_Ql[0] of the first minimum input value, and results values x4[i] are obtained by sequentially performing an XOR operation and an OR operation on minl_Ql[0] and c[i][l].
[96] An AND operation is performed on results xl[i], x2[i], x3[i], and x4[i] to thereby obtain each bit s[i] of the first minimum value.
[97] The above description is about a first minimum search block shown on the top of
FIG. 4.
[98] A e[i]value is calculated using the thuscalculated values s[i] and m[i], and is input to a second minimum search block below the first minimum search block shown on the top of FIG. 4, thereby obtaining first through fourth bits min2_Ql[3], min2_Ql[2], min2_Ql[l], and min2_Ql[0] of a second minimum input value among the 12 4bit input values m[0], m[l], ..., and m[l I]. The first and second minimum search blocks perform the same minimum search operations.
[99] A node minimal value calculation block below the second minimum search block performs its operation on minl_Q2 and min2_Q2, which are obtained according to the same method as the method of obtaining the values minl_Ql, min2_Ql.
[100] As compared with FIG. 3, the method described with reference to FIG. 4 is characterized in that no comparators are used during the search for the first and second minimum input values from the 12 input values. Therefore, the minimum value search according to the present invention can be performed fast. In particular, when the number of input bits is small, the speed of the minimum value search is increased.
[101] Even when about 4 bits are used as magnitude bits when regular quantization is used, and about 3 bits are used as magnitude bits when irregular quantization is used, LDPC codes provide good performance. Therefore, the method according to the present invention may be more effective for LDPC codes.
[102] FIG. 5 is a flowchart illustrating a method of updating a check node for a LDPC code, according to an embodiment of the present invention.
[103] In operation S500, a first bit of a first minimum value among input values, the number input values being equal to the number of degrees of the check node, is obtained by performing an AND operation on first bits (i.e., MSBs) of the input values.
[104] In operation S510, result values are obtained by switching and sequentially performing an XOR operation and an OR operation on the first bit of the first minimum value and each of the first bits of the input values. In operation S520, operations S500 and S510 are performed again on the result values set as input values, and operations S500 and S510 are performed a number of times corresponding to the number of bits of each input value, that is, operations S500 and S510 are performed until last bits (i.e., LSBs) are set as input values, thereby obtaining the first minimum value. [105] FIG. 6 is a flowchart illustrating a method of updating a check node for a LDPC code when a number of input values equal to the number of degrees of the check node are 4bit input values, according to an embodiment of the present invention .
[106] In operation S600, when a number of input values equal to the number of degrees of the check node are 4bit input values, a first bit of a first minimum value among the 4bit input values is obtained by performing an AND operation on first bits (i.e., MSBs) of the 4bit input values.
[107] In operation S610, an XOR operation and an OR operation are sequentially performed on the first bit of the first minimum value and each of the first bits of the 4bit input values in order to obtain first result values, and second result values are obtained by switching the 4bit input values to the first result values.
[108] In operation S620, a second bit of the first minimum value is obtained by performing an AND operation on second bits of the second result values, an XOR operation and an OR operation are sequentially performed on the second bit of the first minimum value and the second bit of each of the second result values in order to obtain third result values, and fourth result values are obtained by switching the second result values to the third result values.
[109] In operation S630, a third bit of the first minimum value is obtained by performing an AND operation on third bits of the fourth result values, an XOR operation and an OR operation are sequentially performed on the third bit of the first minimum value and the third bit of each of the fourth result values in order to obtain fifth result values, and sixth result values are obtained by switching the fourth result values to the fifth result values.
[110] In operation S640, a fourth bit of the first minimum value is obtained by performing an AND operation on fourth bits of the sixth result values, an XOR operation and an OR operation are sequentially performed on the fourth bit of the first minimum value and the fourth bit of each of the sixth result values in order to obtain seventh result values, and eighth result values are obtained by switching the sixth result values to the seventh result values.
[I l l] In operation S650, the first minimum value is obtained by performing an AND operation on the first, third, fifth, and seventh result values.
[112] The invention can also be embodied as computer readable codes on a computer readable recording medium. The computer readable recording medium is any data storage device that can store data which can be thereafter read by a computer system. Examples of the computer readable recording medium include readonly memory (ROM), randomaccess memory (RAM), CDROMs, magnetic tapes, floppy disks, optical data storage devices, and carrier waves (such as data transmission through the Internet). The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
Claims
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US20050028071A1 (en) *  20030729  20050203  BaZhong Shen  LDPC (Low Density Parity Check) coded modulation hybrid decoding 
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US20050028071A1 (en) *  20030729  20050203  BaZhong Shen  LDPC (Low Density Parity Check) coded modulation hybrid decoding 
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CAVUS E. ET AL.: "A computationally efficient selective node updating scheme for decoding of LDPC codes", MILITARY COMMUNICATIONS CONFERENCE, 2005. MILCOM 2005 IEEE, vol. 3, 17 October 2005 (20051017)  20 October 2005 (20051020), pages 1375  1379, XP010901367, DOI: doi:10.1109/MILCOM.2005.1605869 * 
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