WO2008064348A2

WO2008064348A2 - Power over ethernet with isolation

Info

Publication number: WO2008064348A2
Application number: PCT/US2007/085454
Authority: WO
Inventors: Sajol Ghoshal; Philip John Crawley; Timothy A. Dhuyvetter; John R. Camagna
Original assignee: Akros Silicon, Inc.
Priority date: 2006-11-22
Filing date: 2007-11-21
Publication date: 2008-05-29
Also published as: WO2008064348A3

Abstract

A powered device on a network is isolated by communicating operating power and data to a powered device from a network line, referencing the network line to a line reference, and referencing the powered device to a device reference that can be different from the line reference. The powered device is isolated from the network line with an isolation boundary positioned between distributed power and the powered device at a digital port coupled to the powered device.

Description

POWER OVER ETHERNET WITH ISOLATION

Sajol Ghoshal Philip John Crawley Timothy A. Dhuyvetter John R. Camagna

BACKGROUND

[0001] Various communications, medical, computing, industrial, and other systems implement isolation barriers to electrically isolate sections of electronic circuitry. An isolator is a device that can transfer a signal between sections of electronic circuitry while maintaining electrical isolation between the sections.

[0002] A typical conventional design attains isolation, for example, by connecting to a communication channel through a transformer. The transformer provides isolation both for surge and galvanic isolation. Power can be transmitted on the line through the transformer.

SUMMARY [0003] According to an embodiment of a network system, a powered device on a network is isolated by communicating operating power and data to a powered device from a network line, referencing the network line to a line reference, and referencing the powered device to a device reference that can be different from the line reference. The powered device is isolated from the network line with an isolation boundary positioned between distributed power and the powered device at a digital port coupled to the powered device.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Embodiments of the invention relating to both structure and method of operation may best be understood by referring to the following description and accompanying drawings:

FIGURES IA and IB are schematic block diagrams that respectively illustrate a high level example embodiments of client devices in which power is supplied separately to network attached client devices, and a switch that is a power supply equipment (PSE)- capable power-over Ethernet (PoE) enabled LAN switch that supplies both data and power signals to the client devices;

FIGURE 2 is a functional block diagram illustrating a network interface including a network powered device (PD) interface and a network power supply equipment (PSE) interface, each implementing a non-magnetic transformer and choke circuitry; FIGURES 3A, 3C, 3D, and 3E are schematic block diagrams respectively illustrating embodiments of circuits adapted for connectivity to a network that include isolation of multiple ground domains;

FIGURE 3B is a schematic block diagram showing a connectivity circuit without isolation;

FIGURES 4A and 4B are schematic block diagrams that depict embodiments of isolators that can be used in the connectivity circuits that include isolation of ground domains;

FIGURE 5 is a schematic block diagram illustrating an embodiment of a system that connects to and can be powered from a network that includes isolation of ground domains;

FIGURES 6A and 6B are schematic flow diagrams depicting a method for isolating a powered device in a network configuration that forms multiple ground domains;

FIGURES 7A and 7B are schematic block and circuit diagrams illustrating embodiments of transformer-based Power-over-Ethernet circuits that supply power to a network device in an isolated arrangement;

FIGURE 8 is a schematic block diagram illustrating an embodiment of a signal isolator that enables a general analog transmission isolation method over an isolation barrier;

FIGURE 9 is a schematic block and circuit diagram showing an embodiment of an isolator circuit that uses capacitors to couple a feedback signal across an isolation barrier; FIGURE 10 is a schematic combined block and circuit diagram that illustrates an embodiment of a signal isolator;

FIGURES HA, HB, and HC illustrate a block diagram and circuit diagrams showing an example of an embodiment of a pulse width modulator that can be used in the illustrative signal isolators; FIGURES 12A, 12B, 12C, and 12D is a set of combined block and circuit diagrams depicting several circuits and associated methods for transmitting an analog signal across an isolation boundary;

FIGURE 13A is a combined block and circuit diagram illustrating an embodiment of a signal isolator configured as a dual-channel bidirectional isolator coupling a primary domain and a secondary domain;

FIGURE 13B is a block and circuit diagram showing an embodiment of a digital isolator that can be implemented in the isolator; FIGURE 13C is a block and circuit diagram showing an embodiment of an analog isolator that can be implemented in the isolator;

FIGURE 14 is a schematic block and circuit diagram illustrates an embodiment of a power controller including a signal isolator that uses capacitors to couple a feedback signal across an isolation barrier;

FIGURE 15 is a schematic block diagram illustrating an embodiment of an isolated power converter that includes a DC -DC converter and optical coupler isolation;

FIGURES 16A and 16B are a group of flow charts depicting aspects of methods that can be implemented individually or in combination in one or more embodiments for transmitting an information signal across an isolation barrier;

FIGURES 17A through 17E are a group of flow charts depicting aspects of methods that can be implemented individually or in combination in one or more embodiments for controlling power in an electrical system;

FIGURE 18A is a schematic circuit diagram depicting an embodiment of a signal isolator that is configured as a digital isolator with capacitors arranged to create magnetic and electrical differentiality;

FIGURE 18B is a schematic circuit diagram illustrating another embodiment of a signal isolator that is configured as a digital isolator with an isolation capacitor on one die;

FIGURE 18C is a schematic block diagram showing an embodiment of a signal isolator configured as a digital isolator with multiple differentiators;

FIGURES 19A and 19B respectively show a schematic circuit diagram and associated system which respectively illustrate an embodiment of a current-mode differentiator that can be implemented in various implementations of a signal isolator;

FIGURE 19C is a block diagram illustrating another embodiment of a current-mode technique using a current conveyor that can be used in a differentiator;

FIGURE 20 is a schematic circuit diagram depicting an embodiment of a current-mode differentiator that can be implemented in a digital signal isolator;

FIGURE 21 is a schematic circuit diagram showing an embodiment of a comparator that can be implemented in a digital signal isolator; FIGURES 22A, 22B, and 22C are a set of time waveform algorithms illustrating aspects of operation of a first differentiator output signal; FIGURES 23A, 23B, and 23C are several cross-sectional views depicting an embodiment of a semiconductor device including a metal stack that can be used for implementing the illustrative signal isolators including integration of capacitors;

FIGURES 23D and 23E are schematic pictorial views showing arrangement of metal plates in embodiments of isolation capacitors;

FIGURE 24 is a schematic block diagram illustrating an embodiment of an interface that can be implemented to operate a high speeds, for example in the gigabit per second range;

FIGURE 25A is a schematic circuit diagram showing an embodiment of a capacitive calibration circuit used to calibrate a capacitor such that the differentiator bandwidth tracks process;

FIGURE 25B is a circuit diagram depicting an embodiment of a positive feedback recovery circuit that can be used to reclaim a digital signal from a sliced pulse signal;

FIGURES 26A, 26B, and 26C respectively depict a schematic graph, a circuit diagram of a typical implementation, and a block diagram illustrating a system using a differentiator and associated technique for amplifying the pulse to reduce capacitor size in the isolation barrier;

FIGURE 27 is a schematic block and circuit diagram depicting an embodiment of a converter that can be used in the interface;

FIGURES 28A and 28B are a schematic circuit and block diagram and a symbolic representation showing an embodiment of a differentiator that can be used in the signal interface;

FIGURE 29 is a schematic block and circuit diagram illustrating an embodiment of a signal interface;

FIGURE 3OA through 3OC are multiple flow charts showing one or more embodiments or aspects of a method for transmitting a signal through an isolation barrier;

FIGURES 31A through 31D are a set of flow charts depicting embodiments and aspects of various embodiments of a method for constructing a signal isolator;

FIGURES 32A through 32E are multiple flow charts showing one or more embodiments or aspects of a method for constructing a semiconductor device; FIGURE 33 is a schematic circuit diagram showing an embodiment of a signal isolator that implements process tracking enabling high-speed performance for the differentiator; FIGURE 34A is a schematic block diagram showing an embodiment of a signal isolator that implements channel management;

FIGURES 34B and 34C are schematic block and circuit diagrams illustrating an embodiment of an isolator interface that implements a management channel configured to operate continuously to set amplitude;

FIGURE 34D is a set of time waveforms depicting digital signals at several locations in the digital isolator;

FIGURE 34E is a state diagram illustrating an embodiment of operation of the state machine and failsafe logic for managing channels in the signal isolator; FIGURE 34F is a set of time waveforms depicting digital signals at several locations in the digital isolator;

FIGURES 35A and 35B are flow charts illustrating embodiments of a method for constructing a signal isolator;

FIGURE 36 is a flow chart showing an embodiment of a method for operating a signal isolator;

FIGURES 37A through 37C are a set of flow charts showing embodiments and aspects of various embodiments of a method for communicating an information signal across an isolation barrier;

FIGURE 38 is a schematic circuit diagram illustrates an embodiment of a high-speed differentiator that can be implemented in a digital signal isolator;

FIGURES 39A and 39B are schematic block and circuit diagrams respectively showing implementations of blocking on an isolated interface in a low voltage differential signaling (LVDS) system and a serial gigabit media independent interface (SGMII) system; and FIGURES 4OA, 4OB, and 4OC are a set of time waveforms illustrating aspects of operation of a first differentiator output signal.

DETAILED DESCRIPTION

[0005] Referring to FIGURE 3 A, a schematic block diagram illustrates an embodiment of a circuit 300A adapted for connectivity to a network. The circuit 300A comprises an application device 302 with a port 304 for interfacing to a powered device 306 and an interface 308 configured for coupling a network line 310 to the powered device 306 via the application device 302 and communicating operating power and data to the powered device 306 from the network line 310. The circuit 300A further comprises an isolator 312 coupled between the application device 302 and the powered device 306 that isolates the application device 302 and the interface 308 which are referenced to a line reference 314 from the powered device 306 that is referenced to a device reference 316. [0006] In an illustrative embodiment, the application device 302 and the interface 308 can be configured in compliance to an Institute of Electrical and Electronics Engineers (IEEE) 802.3 Power over Ethernet (PoE) standard for PoE applications. The interface 308 can connect directly to the line and forms a seamless interface to IEEE 802.3 compliant 10/100/1000 PHY.

[0007] In a particular example embodiment, the interface 308 can be implemented as a single-chip, highly integrated complementary metal-oxide-semiconductor (CMOS) solution for Power-over-Ethernet (PoE) applications such as Voice over IP (VoIP) Phones, Wireless LAN Access Point, Security and Web Cameras, Analog Telephone Adapters (ATA), Point-of-Sale (PoS) Terminals, and many other applications. The interface 308 can be implemented to minimize the number of components, thereby improving reliability. The interface 308 can be configured in compliance with standards for electro-magnetic interference (EMI) emissions, EMI immunity, and system capabilities for surge protection, power transmission and return loss specifications without the use of an external Ethernet networking transformer.

[0008] Other embodiments may be either multiple-chip or single-chip configurations, combinations of multiple discrete components and/or one or more integrated circuit chips, or the like. Similarly, other embodiments may include integrated circuits constructed using any suitable technology other than CMOS technology. Various embodiments may also be implemented in applications other than PoE standard applications and may be used for other functionality than the listed functions.

[0009] The port 304 can be a digital port. For example, in particular implementations the port can comprise a Universal Serial Bus (USB) port, a RETMA Standard (RS)-232 port, Inter- Integrated Circuit (I2C), Management Data Input/Output (MDIO), or any other suitable bus.

[0010] As depicted, the application device 302 can comprise an application processor 318 and an Ethernet Physical layer (PHY) 320 which is coupled between the network line 310 and the application processor 318. Although the interface can be a transformer interface, in the illustrative embodiment, the interface 308 can comprise a T-lessConnect™ solid-state transformer line interface 322 that connects the Ethernet PHY 320 to the network line 310 and transfers operating power and data to the powered device 306 in absence of networking line transformers.

[0011] In the illustrative embodiment, the interface 308 incorporates the T-lessConnect™ line interface (Transformerless) 322 made available by Akros Silicon, Inc. of Sacramento, CA, that connects PHY 320 directly to a twisted pair cable. The T-lessConnect™ solid-state transformer platform 322 feeds power, for example at a 48 volt supply, and data such as at a rate of 10/100/1000 megabits per second (Mbps) directly into integrated circuits without using networking line transformers. The interface 308 can couple to Ethernet physical layer transceivers and performs powered device (PD) power management functionality according to the IEEE Standard 802.3af-2003.

[0012] In conventional PoE systems, EMI noise can be primarily generated from switching of DC/DC converter elements or the common mode noise arising from an imbalance in the PHY transmit or receive differential signals. To achieve good EMI immunity, low common mode impedance is desirable especially at high frequencies. In the convention PoE system, EMI immunity is typically addressed by manual tweaking of a circuit board to limit EMI radiation, a technique which can detrimentally affect the performance of other sensitive circuits and signals on the board. The illustrative interface 308 can be an integrated circuit that reduces EMI while maintaining consistent performance without the manual tweaking of conventional systems, thereby attaining consistent performance with minimal effort.

[0013] Referring to FIGURE 3B, a schematic block diagram shows a connectivity circuit 300B without isolation which is included to simplify explanation of a configuration for EMI immunity and surge protection. The circuit 300B includes the interface 308 in combination with Ethernet PHY 320 and a DC/DC converter 330 in a non-isolated arrangement. Circuits that implement isolation can include similar structures for EMI immunity and surge protection. In an illustrative embodiment, the circuit 300 can facilitate immunity to overvoltage and surge events by including integrated diodes and protection circuitry in the interface 308, enabling a much faster response to the surge event. Protection circuitry in the T-lessConnect™ interface 322 can be configured to absorb most of the charge while developing a small voltage across the PHY terminals and ensuring that bridge diodes are not subjected to large voltage excursions that exceed the diode ratings. In typically Power-over-Ethernet operations are sourced from a typical 48 volt supply, the voltage excursions are added to the 48 volt supply, creating challenge in operating below the diode reverse bias voltage rating.

[0014] In the illustrative interface 308, the line reference 314 is the power reference from the line for example via an RJ45 connector and is transferred through the DC/DC converter 330 to the device reference 316, specifically shown in the example as the ground reference of the PHY/processor combination. Transfer of the line reference 314 to the PHY/processor enables the entire circuit 300B to be referenced to a common low ground, substantially improving surge protection and reducing EMI radiations due to ground loops. [0015] The surge resistance (Rsurge) 332 is coupled to the interface 308 and enables the interface 308 to control the connection of line reference 314 (Line_GND) and the device reference 316 (Board_GND). In an example embodiment, under normal operations Rsurge is very low impedance, for instance approximately 1.5ohms, and creates a low impedance ground return path for EMI noise, thus substantially reducing emissions and enabling a high level of immunity. EMI noise generated from switching of the DC/DC converter elements or the common mode noise arising from an imbalance in the PHY transmit or receive differential signals is shunted to line ground 314 through the low impedance Rsurge resistor 332 thus reducing the voltage of any radiated noise on the twisted pair cable. In addition the low Rsurge impedance forms a low impedance path to external common mode disturbers, thus giving high common mode immunity for the device or PHY/processor circuit board.

[0016] During a surge/lightning event, the crossover detect circuits 336 in the interface 308 respond by making Rsurge 332 relatively larger, for example an open circuit, thus increasing the impedance from the device reference 316 (Board_GND) to the line reference 314 (Line_GND). If Rsurge impedance is high during a surge event, all the surge energy is forced to flow through the T-lessConnect™ interface 322 which is configured to absorb surge strikes of 8kV contact discharge or 15kV air discharge. The crossover circuit 336 in the interface 308 is configured to respond to fast transients that exceed 70V. In an illustrative embodiment, the interface 308 can be constructed using a 100 volt CMOS process that enables very robust handling of high currents associated with the surges, for example currents in the range of 25 amperes. The interface 308 thus protects the PHY 320 and any down stream circuits from potentially hazardous overvoltage strikes.

[0017] A surge resistor 332 can be coupled between the interface 308 and the application device 302 and forms a low impedance ground return path for electromagnetic interference (EMI) noise under normal operation. The solid-state transformer line interface 322 can further comprise a cross-over detect circuit 336 that responds to surge/lightning events by increasing the surge resistance 332 to an open circuit, thereby increasing impedance from the device reference 316 to the line reference 314.

[0018] The circuit 300A shown in FIGURE 3 A extends functionality beyond capabilities of the circuit 300B in FIGURE 3B by addition of isolation of ground domains. The interface 308 performs the functions enabling Power-over-Ethernet (PoE) powered device (PD) applications. For configurations in which Universal Serial Bus (USB)/RS232 connections are used and are referenced to an isolated board ground (device reference 316) which is isolated from line ground (line reference 314), a digital isolator 312 can be added. The isolator 312 electrically isolates the different ground domains without usage of an opto-isolator needed in the DC/DC converter feedback loop. The isolator 312 thus enables isolation for those applications that demand isolation between the line and configuration ports 304 such as USB or RS-232 ports.

[0019] The circuit 300A illustrated in FIGURE 3A is a Power-over-Ethernet (PoE) implementation with isolation to USB or RS-232 ports 304 which can be compared to a transformer-based PoE implementation with isolation to USB/RS-232 ports shown in FIGURE 7A.

[0020] As shown by comparison of FIGURE 7A to FIGURE 3A, the digital isolator 312 replaces an opto-coupler 712 which can be used in DC/DC converters 730 in the transformer- based circuit 700A. The circuit 300A can be implemented using high volume cost effective CMOS technology. The circuit 300A moves the isolation boundary from inside a powered device (PD) circuit board to the location where the isolation is most appropriate, for example at relatively low speed digital ports 304 such as RS-232 or USB ports. The circuit 300A attains the robust performance in protecting the sensitive board integrated circuits from surge energy and controls EMI while enabling isolation to occur without compromising the system design specifications for high performance surge protection and EMI rejection.

[0021] Referring to FIGURE 3C, a schematic block diagram shows an embodiment of a circuit 300C that supports isolation of multiple ground domains. The illustrative interface 308 can be implemented in an integrated circuit configuration for EMI and surge protection, and isolation. The circuit 300C includes an Ethernet Physical layer (PHY) 320 and a DC/DC controller 330 with isolation supplied by a digital isolator 312. The digital isolator 312 can be included in a modular design of the circuit 300A that can be used for isolated applications and can be implemented as a board stuffing option, thus enabling additional flexibility to a system designer. The application device 302 comprises the application processor 318 and the Ethernet Physical layer (PHY) 320 coupled between the network line 310 and the application processor 318. A Media Independent Interface (Mil) 338 couples the Ethernet PHY 320 to the application processor 318 which can be operative as a Media Access Controller (MAC) device.

[0022] Illustratively, the T-lessConnect™ solid-state transformer line interface 322 can be a solid-state transformer line interface that comprises a rectification and electromagnetic interference (EMI) protection circuit 324 coupled to the network line 310, first and second power feed elements 326 coupled to the rectification and EMI protection circuit 324, a powered device (PD) controller 328 coupled between the first and second power feed elements 326, and a direct current-to-direct current (DC/DC) converter 330. The solid-state transformer line interface 322 transfers the line reference 314 through the DC/DC converter 330 to a ground reference of the application device 302 through a surge resistance 332, referencing the application device 302 and the solid-state transformer line interface 322 to a common ground. [0023] Referring to FIGURE 3D, a schematic block diagram shows an embodiment of circuit 300D that implements isolation for powered Universal Serial Bus (USB) applications. The circuit 300D illustrated in FIGURE 3D is a Power-over-Ethernet (PoE) implementation with isolation to a USB port 304 which can be compared to a transformer-based PoE implementation with isolation to powered USB ports shown in FIGURE 7B.

[0024] The interface 308 performs the functions used for Power-over-Ethernet PD applications in arrangements including powered USB connections which are referenced to an isolated board ground 316 which is isolated from line ground 314. A digital signal and power isolator 312 facilitates isolation and avoids usage of an opto-isolator in the DC/DC converter feedback loop. The digital signal and power isolator 312 thus enables ground domain isolation for applications that demand isolation between the line and configuration ports 304 such as a USB port and supplies isolated power to the USB port, for example up to 2.5 watts on a 5 volt supply.

[0025] As shown by comparison of FIGURE 7B to FIGURE 3D, the digital signal and power isolator 312 replaces an opto-coupler 712 which can be used in DC/DC converters 730 in the transformer-based circuit 700B. The circuit 300D can be implemented using high volume cost effective CMOS technology. Power is isolated without opto-isolators and uses a tiny power transformer designed to power, for example 2.5 watts. The circuit 300D moves the isolation boundary from inside a powered device (PD) circuit board to the location where the isolation is most appropriate. The circuit 300D attains the robust performance in protecting the sensitive board integrated circuits from surge energy and controls EMI while enabling isolation to occur without compromising the system design specifications for high performance surge protection and EMI rejection.

[0026] Referring to FIGURE 3E, a schematic block diagram illustrates another embodiment of a circuit 300 wherein the application device 302 comprises an Ethernet Physical layer (PHY) 320. The illustrative interface 308 comprises a T-lessConnect™ solid-state transformer line interface 322 that connects the Ethernet PHY 320 to the network line 310 and transfers operating power and data to the powered device 306 in absence of networking line transformers. In the depicted configuration, a Media Independent Interface (Mil) 338 couples the Ethernet PHY 320 to an application processor 318 that is operative as a Media Access Controller (MAC) device in the powered device 306. The Mil 338 forms an isolation boundary between distributed power and the powered device 306.

[0027] In various embodiments, the isolator 312 can be configured in different forms. For example, referring to FIGURE 4A, the isolator 312 can be a digital isolator 400 comprising capacitively-coupled interconnects 402 that capacitively communicate signals bi-directionally between the application device 302 and the powered device 306 whereby optical coupling between the device reference and the line reference can be omitted. Both sides of the interconnects 402 include drivers 404 that can be as simply implemented as one or move inverter stages. Digital signals can be modulated by a modulator 406 for each transmitting portion of the interconnects 402 then transferred across capacitors 408 that differentiate the communicated signal into leading and trailing pulses. Signals are received at drivers 404 in the receiving portion of the interconnects 402 and passed to a demodulator 410 and logic 412 for restoring the signals. In various configurations the receivers can be implemented as either single-ended or differential.

[0028] In another example, as shown in FIGURE 4B, the isolator 312 can be a digital isolator 420 comprising interconnects 402 that are inductively-coupled 422 and inductively transmit a signal from the application device 302 to the powered device 306 also enabling omission of optical coupling between the device reference 316 and the line reference 314.

[0029] In other embodiments, any suitable isolator may be used.

[0030] Referring to FIGURE 5, a schematic block diagram illustrates an embodiment of a system 500 that connects to and can be powered from a network. The system 500 comprises a powered device 506 and a line connector 540 that can be coupled to a network line 510. The system 500 further comprises an application device 502 that includes a port 504 adapted to interface to the powered device 506. An interface 508 is couples the network line 510 via the line connector 540 to the powered device 506 through the application device 502. The interface 508 functions to communicate operating power and data to the powered device 506 from the network line 510. The system 500 further comprises an isolator 512 coupled between the application device 502 and the powered device 506 which functions to isolate components referenced to a line reference 514, including the application device 502 and the interface 508, from components referenced to a device reference 516, for example including the powered device 506.

[0031] The system 500 can be adapted to supply power over the network line 510 to the powered device 506. The powered device 506 can be any suitable device such as a Voice-over- Internet-Protocol (VoIP) telephone, an Internet Protocol (IP) telephone, a wireless Local-Area- Network (LAN) Access Point, a security camera, a Web camera (webcam), an Analog Telephone Adapter (ADA), a Point-of-Sale (PoS) terminal, an Ethernet hub, a computer, an appliance, or the like. In some embodiments, the system 500 can be adapted to support an application device 502 and the interface 508 that comply with the Institute of Electrical and Electronics Engineers (IEEE) 802.3 Power over Ethernet standard.

[0032] As illustrated, the system 500 can further comprise a power source 542 coupled to the network line 510. The line connector 540 can be a Registered Jack (RJ)-45 connector and the network line 510 configured as two wire pairs coupled to the RJ-45 connector. [0033] The application device 502 can be configured with various components and functionality for coupling via the port 504 to the powered device 506. Suitable components in the application device 502 for usage in the system 500 can include an Ethernet Physical layer (PHY) 520 which is coupled to the network line 510, and the application processor 518 coupled to the PHY 520. The interface 508 can comprise a T-lessConnect™ solid-state transformer line interface 522 for interfacing the Ethernet PHY 520 to the network line 510 and transferring operating power and data to the powered device 506 without using networking line transformers.

[0034] The T-lessConnect™ solid-state transformer line interface 522 comprises a rectification and electromagnetic interference (EMI) protection circuit 524 coupled to the network line 510, multiple power feed elements 526 coupled to the rectification and EMI protection circuit 524, a powered device (PD) controller 528 coupled between the power feed elements 526, and a DC/DC converter 530. The T-lessConnect™ solid-state transformer line interface 522 transfers the line reference 514 through the DC/DC converter 530 to a ground reference of the application device 502 through a surge resistance 532, referencing the application device 502 and the solid- state transformer line interface 522 to a common ground.

[0035] The system 500 can further comprise a transformer 550 with first and second windings 552A, 552B. The first winding 552A couples to the interface 522 and the second winding 552B couples to the application device 502. A surge resistor 532 couples between the interface 522 and the application device 502 and forms a low impedance ground return path for electromagnetic interference (EMI) noise under normal operation. A diode 554 couples between the transformer second winding 552B and the application device 502. A low dropout regulator 556 can be coupled between the diode 554 and the application device 502. The T-lessConnect™ solid-state transformer line interface 522 can further comprise a cross-over detect circuit 558 that responds to surge/lightning events by increasing the surge resistance 532 to open circuit, thereby increasing impedance from the device reference 516 to the line reference 514.

[0036] Referring to FIGURES 6A and 6B, schematic flow diagrams depict a method 600 for isolating a powered device in a network configuration that forms multiple ground domains. Operating power and data are communicated 602 to the powered device from a network line. In some embodiments, operating power and data can be communicated 602 in compliance with the Institute of Electrical and Electronics Engineers (IEEE) 802.3 Power over Ethernet standard. The network line is referenced 604 to a line reference and the powered device is referenced 606 to a device reference that can be different from the line reference, the line reference and the device reference representing different ground domains. The method 600 further comprises isolating 608 the powered device from the network line and positioning 609 an isolation boundary between distributed power and the powered device at a digital port coupled to the powered device. [0037] In some embodiments the powered device can be isolated 608 from the network line using a capacitively-coupled interconnect that capacitively transmits a signal from the application device to the powered device whereby optical coupling between the device reference and the line reference can be omitted. In other embodiments, the powered device can be isolated 608 from the network line using an inductively-coupled interconnect that inductively transmits a signal from the application device to the powered device, also enabling optical coupling between the device reference and the line reference to be omitted.

[0038] In various embodiments, the isolation boundary can be positioned 609 between distributed power and the powered device at a digital port such as a Universal Serial Bus (USB) port, a RETMA Standard (RS)-232 port, or other suitable port.

[0039] The illustrative techniques enable operating power and data to be transferred to the powered device in absence of networking line transformers.

[0040] Referring to FIGURE 6B, a method 610 for isolating the ground domains further can comprise transferring 612 the line reference through a surge resistance that forms a low impedance ground return path for electromagnetic interference (EMI) noise under normal operation. In response 614 to surge/lightning events, the surge resistance is increased 616 to open circuit, increasing impedance from the device reference to the line reference.

[0041] Referring to FIGURE 8, a schematic block diagram illustrates an embodiment of a signal isolator 800 that enables a general analog transmission isolation method over an isolation barrier 802. The signal isolator 800 comprises a transmission path 804 forming the isolation barrier 802 and a signal conditioner 806 that is adapted to receive an input signal 808 and precondition the input signal 808 according to a modulation function to generate and pass a preconditioned signal 810 via the transmission path 804. A signal recovery circuit 812 that receives the preconditioned signal 810 via the transmission path 804 and demodulates the preconditioned signal 810, forming a feedback signal for usage in a control loop.

[0042] The signal conditioner 806 receives an input signal Vm that is passed through the transmission path 804 and isolation barrier to the signal recovery circuit 812 that generates the output signal Vout. The signal conditioner 806 can be any suitable circuit such as an analog-to- digital converter (ADC), a predriver that performs preconditioning, a simple flip-flop, digital-to- analog converter (DAC), or other device.

[0043] The signal isolator 800 can be configured to acquire an analog input signal, digitize the signal, and pass the digitized signal through a control system. The signal conditioner 806 can be any suitable modulator device such as a pulse width modulator, a delta modulator, a frequency modulator, and a phase modulator. For example, in a particular embodiment, the signal conditioner 806 can comprise an analog to digital converter that performs a modulation function, the transmission path 804 can comprise one or more capacitors, and the signal recovery circuit 812 can comprise a digital to analog converter or digital filter. A synchronized recovery signal is passed through a digital path 804. [0044] The illustrative signal isolator 800 depicts a general isolation scheme that be used for any kind of transmission, either analog or digital transmission, and forms an isolation barrier by operation of three functional blocks that perform signal conditioning, a transmission path and isolation barrier, and recovery.

[0045] The transmission path 804 can be considered to be a digital transmission path that communicates inherently digital signals. In another perspective, the transmission path 804 can pass a digital signal in which information is conveyed in an analog format with pulses passed through the path 804, for example through a capacitor, in characteristics of the signal such as frequency, phase, modulation index, or other attribute.

[0046] In a signal isolator implementation that inserts a sampling function in the pathway, an analog signal is converted to a digital form in which each sample has an associated digital value due to quantization of the original signal through the sampling function. The signal recovery circuit 812 can perform the sampling function to attain the digital signal by pulse modulation or other suitable type of general sampling conversion.

[0047] Other implementations can include a true analog signal, for example a direct current (DC) feedback voltage that is modulated and passes information through the transmission path 804, such as a capacitor, by oversampling and modulating up to a higher frequency, then using low pass filtering to recover the analog signal.

[0048] Referring to FIGURE 8 in combination with FIGURE 10, in some embodiments, the power converter 1000 can include a signal isolator 1060, 800 that further comprises a signal conditioner 806 coupled to a transmission path 804 in the secondary domain 1038 that receives and preconditions a signal 808 according to a modulation function and passes the resulting preconditioned signal via the transmission path 804. A signal recovery circuit 812 coupled to the transmission path 804 in the primary domain 1036 receives the preconditioned signal 810 via the transmission path 804 and demodulates the preconditioned signal 810, thereby forming a feedback signal V_FB' for usage in a control loop 1016.

[0049] The signal isolator 1060, 800 can be configured to modulate a direct current (DC) feedback voltage V_FB and pass the DC feedback voltage V_FB through one or more capacitors by oversampling and demodulating to a higher frequency. [0050] The signal conditioner 806 receives an input signal Vm that is passed through the transmission path 804 and isolation barrier to the signal recovery circuit 812 that generates the output signal Vout. In various embodiments, the signal conditioner 806 can be implemented as a pulse width modulator, a delta modulator, a frequency modulator, a phase modulator, an analog- to-digital converter (ADC), a predriver that performs preconditioning, a simple flip-flop, digital- to-analog converter (DAC), or other device. The signal recovery circuit 812 acquires an analog input signal, digitize the signal, and pass the digitized signal through a control system 1016.

[0051] The illustrative signal isolator 800 depicts a general isolation scheme that be used for any kind of transmission, either analog or digital transmission, and forms an isolation barrier by operation of three functional blocks that perform signal conditioning, a transmission path and isolation barrier, and recovery.

[0052] The transmission path 804 can be considered to be a digital transmission path that communicates inherently digital signals. In another perspective, the transmission path 804 can pass a digital signal in which information is conveyed in an analog format with pulses passed through the path 804, for example through a capacitor, in characteristics of the signal such as frequency, phase, modulation index, or other attribute.

[0053] In a signal isolator implementation that inserts a sampling function in the pathway, an analog signal is converted to a digital form in which each sample has an associated digital value due to quantization of the original signal through the sampling function. The signal recovery circuit 812 can perform the sampling function to attain the digital signal by pulse modulation or other suitable type of general sampling conversion.

[0054] Other implementations can include a true analog signal, for example a direct current (DC) feedback voltage that is modulated and passes information through the transmission path 804, such as a capacitor, by oversampling and modulating up to a higher frequency, then using low pass filtering to recover the analog signal.

[0055] Referring to FIGURE 9, a schematic block and circuit diagram illustrates an embodiment of an isolator circuit 900 that uses capacitors to couple a feedback signal across an isolation barrier 902. The illustrative isolator circuit 900 comprises an isolated transmission path 904 and a modulator 906 configured to receive an input signal 908 that conditions the signal for transmission via the isolated transmission path 904. A demodulator 912 that receives the transmitted signal and recovers a feedback signal 914 for usage in a control loop 916.

[0056] In various implementations, the modulator 906 can be selected from among suitable modulators such as an analog-to-digital converter (ADC); a pulse code modulator, a delta modulator, a voltage to frequency converter, a frequency modulator, a phase modulator, or other appropriate device. A modulator 906 that is an analog-to-digital converter can be a single-ended analog-to-digital converter (ADC) modulator, a differential ADC modulator, a capacitively- coupled ADC modulator, or the like.

[0057] The modulator 906 can be constructed as an analog-to-digital converter (ADC) that performs any appropriate modulation such as delta modulation or pulse width modulation to convert a voltage signal to a pulse width signal, frequency modulation to convert the voltage signal to frequency, and a phase modulator to convert the voltage signal to a phase. If the ADC is implemented as a pulse width modulator or delta modulator, the corresponding demodulator 912 is typically constructed as a low pass filter with frequency modulation constant. [0058] The illustrative transmission path 904 is implemented as a pair of capacitors with differential capacitor coupling. In other embodiments, the isolated transmission path can be constructed as one or more capacitors such as with single capacitor coupling, or can be constructed using other devices such as transformers, optical isolators, thermal isolating elements, or others. [0059] The illustrative demodulator 912 is implemented as a digital-to-analog converter (DAC).

[0060] A specific example of an isolation circuit 900 including an ADC modulator 906 or other modulation scheme such as a pulse code modulator, delta modulator, voltage to frequency conversion modulator, an isolated transmission path 904, and a DAC demodulator 912 can be a class D amplifier that receives and modulates an input signal such as an audio signal, and drives a speaker by passing the signal through a capacitor.

[0061] The illustrative isolation circuit 900 uses a capacitor, such as a high voltage capacitor, to couple a feedback signal across an isolation barrier. A DC feedback signal is sampled at high frequency or modulated on a secondary side, passed through a coupling capacitor, and demodulated on the primary side.

[0062] Referring to FIGURE 10, a schematic combined block and circuit diagram illustrates an embodiment of a signal isolator 1000. The signal isolator 1000 comprises a modulator 1006 configured to receive and modulate a signal, a rectifier 1012, and a full differential alternating current (AC) coupling 1004 that is configured for transmitting the modulated signal from the modulator 1006 to the rectifier 1012 with capacitive-coupled signal isolation. A digital filter 1018 coupled to the rectifier 1012 that recovers the modulated signal.

[0063] In the illustrative embodiment, a lowpass filter 1020 can be coupled to the digital filter 1018. The lowpass filter restores an analog signal. [0064] The signal isolator 1000 can be configured to modulate a direct current (DC) feedback voltage and pass the DC feedback voltage through one or more capacitors 1022 by oversampling and demodulating to a higher frequency.

[0065] FIGURE 10 shows a general transmission pathway 1004 over an isolation barrier 1002. The transmission pathway 1004 can be either an analog or digital pathway. A signal VFB is applied to a signal conditioner 1006 and then to a transmission link 1004 including the isolation barrier 1002. The signal is then passed through a signal recovery block 1012.

[0066] The illustrative circuit 1000 comprises a pulse width (PWM) or delta DM) modulator 1006, full differential alternating current (AC) coupling 1004, and a diode bridge rectifier 1012, for example implemented as digital flip-flop lowpass filter 1020. In an analog path, direct current (DC) feedback voltage is modulated and passed through the capacitor 1022 by oversampling and demodulating up to higher frequency, then low pass filtered to restore analog signal.

[0067] In an example embodiment, the transmission pathway 1004 can be a feedback pathway, for example a digitized form of feedback that forms a control loop 1016. A feedback signal is passed through a modulation function, then the transmission pathway 1004 for example passed through one or two capacitors, and through a demodulation of the modulation function. In various implementations, the modulation can be pulse width modulation, delta modulation, frequency modulation, phase modulation, or the like. In a general functional description, an analog input signal can be input to the transmission pathway, digitized, and then passed as a digitized signal through a control loop.

[0068] FIGURE 10 illustrates a power distribution system 1024 that includes a signal isolator 1000. An illustrative DC-DC converter 1026 in the power distribution system 1024 has a time base supplied by an oscillator 1028 and includes internal drivers 1030 and power field effect transistors (FETs) 1032 that are shown external to DC -DC converter 1026 but can be internal to the converter in some configurations. As shown, the DC -DC converter 1026 can be a pulse width modulator (PWM) converter. The drivers 1030 and power FETs 1032 drive a transformer 1034 and pass power from the primary side 1036 to the secondary side 1038 through the transformer 1034 to a rectifier 1040 that is depicted as diodes 1042. In other configurations, the rectifier 1040 can take other forms such as transmission gates or other devices for which a signal is used to drive the gates or devices on a communication pathway that is omitted in FIGURE 10.

[0069] Following the diodes 1042 is a filter 1044 with an inductor Ll and a capacitor Cl that passes an output voltage VO. The output voltage VO is applied to a resistor divider 1046 that forms a feedback voltage VFB and is returned on a feedback pathway 1048 by application to a modulator 1006, for example a pulse width modulator or a delta modulator. The feedback pathway 1048 passes the feedback signal from the secondary side 1038 to the primary side 1036 across the isolation barrier 1002, illustratively by differentially coupling the signal, although a single-ended embodiment can also be formed. Information, including feedback information, is passed from the modulator 1006 over the differential capacitors 1022 to the primary side 1036 where the modulated signal is demodulated. The demodulation has a low pass filtering functionality and is illustratively implemented in a recovery circuit 1050 that includes diodes in a diode bridge rectifier 1012, a resistor R3, and a D flip-flop 1052. The recovered feedback signal can be passed through a lowpass filter 1020 which can be a first-order, second-order, or other suitable lowpass filter. The recovered feedback signal VFB' following the lowpass filter 1020 is applied to an error amplifier (EA) 1054 and passed back to the DC-DC converter 1026. The feedback voltage VFB is thus returned to the primary side 1036 as recovered feedback signal VFB' and can be passed to the DC -DC converter 1026 either through the error amplifier (EA) 1054 or directly in some implementations, depending on whether the error amplifier 1054 is placed on the primary side 1036 or the secondary side 1038, or whether functionality is supplied by other circuits in the feedback pathway 1048. For example, the error function can be supplied via the illustrative digital (D) flip-flop, which is a positive-edge flip-flop that can perform the error function.

[0070] In an example operation of error amplifier functionality, the feedback voltage from 0 to a selected value has a linear transformation so that PWM modulator 1006 has a 0 to 100% duty cycle. The frequency does not change as the signal traverses the whole feedback path 1048 and information is contained in the duty cycle. For example, if full scale on the secondary side is 1 volt, then 100% would be 1 volt, 50% would be half volt, and 0% would be zero volts. The transformation and recovery reduces the same voltage at feedback voltage V_FB with some scale factor K that is arbitrarily chosen. For the selected gain or scale factor, the PWM circuitry uses the factor to set a servo value for the output signal to a predetermined fixed value.

[0071] Again referring to FIGURE 10, a schematic block diagram illustrates an embodiment of a power converter 1000 with signal isolation. The power converter 1000 comprises a direct current (DC)-DC converter 1026 configured to receive an input voltage in a primary domain 1036 and a transformer 1034 coupled to and driven by the DC -DC converter 1026 that supplies an output voltage in a secondary domain 1038. The power converter 1000 further comprises a transmission path 1004 that passes a digital feedback signal 1008 through an isolation barrier 1002 from the secondary domain 1038 to the primary domain 1036.

[0072] In some embodiments, the power converter 1000 can comprise a pulse wide modulator (PWM) direct current (DC)-DC converter 1026 that drives a full-bridge transformer 1034. An oscillator 1028 coupled to the PWM DC -DC converter 1026 generates an oscillator time base for synchronously driving the PWM DC -DC converter 1026. A rectifier 1040 can be coupled to the transformer 1034 and a filter 1044 can be coupled to the rectifier to supply a filtered output voltage.

[0073] In some implementations, the PWM DC-DC converter 1026 can comprise multiple internal drivers 1030 and multiple external power field effect transistors (FETs) 1032 that drive the transformer 1034. The rectifier 1040 can be implemented as multiple diodes 1042 or transmission gates coupled to the transformer 1034. The filter 1044 can be implemented as an inductor L₁ and a capacitor Ci coupled to the rectifier 1040 to supply a filtered output voltage.

[0074] In some embodiments, the power converter 1000 can further comprise the rectifier 1040 coupled to the transformer 1034 and a resistor divider 1046 coupled to the rectifier 1040 that produces a feedback voltage V_FB in the secondary domain 1038. A signal conditioner 1006 is coupled to the resistor divider 1046 and receives the feedback voltage V_FB, preconditioning the feedback voltage V_FB according to a modulation function. For example, the signal conditioner 1006 can be a pulse width modulator (PWM) or delta modulator (DM). One or more capacitors 1022 can be\coupled to the signal conditioner 1006 to function as an isolated transmission path 1004. A signal recovery circuit 1050 can be coupled to the isolated transmission path 1004 in the primary domain 1036 to receive the preconditioned feedback voltage and demodulate the preconditioned feedback voltage, thereby forming a feedback signal for usage in a control loop 1016. [0075] In the illustrative embodiment, the transmission path 1004 is configured as a differential transmission path with two capacitors 1022. In various embodiments, the transmission path 1004 can be single-ended or differential.

[0076] As depicted in FIGURE 10, the transmission path can be considered to comprise a modulator 1006 that receives and modulates a signal such as the feedback voltage V_FB, a diode bridge rectifier 1012, and a full differential alternating current (AC) coupling 1004 that can transmit the modulated signal from the modulator 1006 to the diode bridge rectifier 1012 with capacitive-coupled signal isolation. A D flip-flop 1052 coupled to the diode bridge rectifier 1012 is configured to recover the modulated signal.

[0077] In some embodiments, a digital filter 1018 coupled to the rectifier 1012 recovers the modulated signal. A lowpass filter 1020 coupled to the digital filter 1018 restores an analog signal.

[0078] FIGURE 10 shows a general transmission pathway 1004 over an isolation barrier 1002. The transmission pathway 1004 can be either an analog or digital pathway. A signal V_FB is applied to a signal conditioner 1006 and then to a transmission link 1004 including the isolation barrier 1002. The signal is then passed through a signal recovery block 1012.

[0079] The illustrative circuit 1000 comprises a pulse width (PWM) or delta (DM) modulator 1006, full differential alternating current (AC) coupling 1004, and a diode bridge rectifier 1012, for example implemented as digital flip-flop lowpass filter 1020. In an analog path, direct current (DC) feedback voltage is modulated and passed through the capacitor 1022 by oversampling and demodulating up to higher frequency, then low pass filtered to restore analog signal.

[0080] In an example embodiment, the transmission pathway 1004 can be a feedback pathway, for example a digitized form of feedback that forms a control loop 1016. A feedback signal is passed through a modulation function, then the transmission pathway 1004 for example passed through one or two capacitors, and through a demodulation of the modulation function. In various implementations, the modulation can be pulse width modulation, delta modulation, frequency modulation, phase modulation, or the like. In a general functional description, an analog input signal can be input to the transmission pathway, digitized, and then passed as a digitized signal through a control loop.

[0081] Referring to FIGURE HA, a schematic block diagram shows an example of an embodiment of a pulse width modulator 1100 that can be used in the signal isolators. Modulation can be implemented using techniques other than pulse width modulation and pulse with modulation can be implemented in many other forms. An input voltage VIN is applied to a voltage to current converter 1102 and passed to a delta modulator 1104 to product a digital signal DO. FIGURE HB shows an example implementation of the delta modulator 1104. FIGURE HC illustrates an example implementation of the voltage to current converter 1102.

[0082] Referring to FIGURE HB, the illustrative delta modulator 1102 has a self- oscillatory signal loop or hysteretic oscillation loop 1106 and performs simultaneous frequency derivation and pulse width modulation. The delta modulator 1102 uses a dual set of comparators 1108 coupled into the oscillatory signal loop 1106. The comparator 1108 in the feedback portion of the loop 1106 supplies two clock signals which are switched and passed back to the comparator 1108 in the input portion of the loop. Other embodiments of a delta modulator can include a fixed clock in place of the feedback loop. In another implementation, a clock signal can be driven as an input signal to produce a pulse width modulation output signal.

[0083] FIGURE 11C illustrates an embodiment of a voltage to current converter 1102 that can be used in the pulse width modulator HOO. [0084] Referring to FIGURES 12A, 12B, 12C, and 12D, a set of combined block and circuit diagrams depict several circuits and associated methods for transmitting an analog signal across an isolation boundary. Capacitive isolation generally can be used for passing alternative current (AC) or pulsed signals. [0085] FIGURE 12A shows an embodiment with a generalized structure and form for transmitting an analog signal. An isolator circuit 1200A includes an analog to digital converter (ADC) 1206A that receives an input voltage VI and converts the voltage signal to digital form for passage over an isolation barrier 1202A to a digital to analog converter (DAC) 1212A that converts the signal back to analog form as output voltage VO. Two different symbols are depicted for ground indicating that the ground potential for the primary side and secondary side of the isolation barrier can be different. The analog to digital conversion can take many forms such as a pulse code modulation or other digitization. Conversion can be made from voltage to frequency, voltage to phase, voltage to pulse width, or other suitable parameters.

[0086] FIGURE 12A is a schematic block diagram illustrating an embodiment of a signal isolator 1200A that enables a general analog transmission isolation method over an isolation barrier 1202A. Referring to FIGURE 12A in combination with FIGURE 10, in some embodiments, the power converter 1000 can include a signal isolator 1060, 1200A that further comprises a signal conditioner configured as an analog to digital converter 1206A coupled to the transmission path 1204A in the secondary domain 1036 that receives an input signal and preconditions the input signal according to an analog to digital conversion modulation function for passing a preconditioned signal via the transmission path 1204A. The transmission path 1204A can be configured as one or more capacitors C_ΪSo. A signal recovery circuit configured as a digital to analog converter 1212A or flip-flop coupled to the transmission path 1204A in the primary domain 1036 receives the preconditioned signal via the transmission path 1204A and demodulates the preconditioned signal, forming a feedback signal V_FB' for usage in the control loop 1016.

[0087] FIGURE 12A shows an embodiment with a generalized structure and form for transmitting an analog signal. An isolator circuit 1200A includes an analog to digital converter (ADC) 1206A that receives an input voltage VI and converts the voltage signal to digital form for passage over an isolation barrier 1202A to a digital to analog converter (DAC) 1212A that converts the signal back to analog form as output voltage Vo- Two different symbols are depicted for ground indicating that the ground potential for the primary side and secondary side of the isolation barrier can be different. The analog to digital conversion can take many forms such as a pulse code modulation or other digitization. Conversion can be made from voltage to frequency, voltage to phase, voltage to pulse width, or other suitable parameters. [0088] FIGURE 12B is a schematic block diagram illustrating an embodiment of a signal isolator 1200B enabling a general analog transmission isolation method over an isolation barrier 1202B. Referring to FIGURE 12B in combination with FIGURE 10, in some embodiments, the power converter 1000 can include a signal isolator 1060, 1200B that further comprises a signal conditioner configured as a pulse width modulator 1206B that can precondition a signal and a differential transmission isolation barrier 1202B coupled to the pulse width modulator 1206B that passes a preconditioned signal. A lowpass filter demodulator 1212B coupled to the differential transmission isolation barrier 1202B performs error recovery on the passed preconditioned signal.

[0089] FIGURE 12B depicts an embodiment of an isolator circuit 1200B that comprises a pulse width modulator 1206B that is configured to precondition a signal and a differential transmission isolation barrier 1202B coupled to the pulse width modulator 1206B that is configured to pass a preconditioned signal. A lowpass filter demodulator 1212B is coupled to the differential transmission isolation barrier 1202B and is configured to perform error recovery on the passed preconditioned signal. [0090] The isolator circuit 1200B includes a pathway 1204B for transmitting an analog signal across an isolation barrier 1202B wherein a voltage input signal VIN is applied to a pulse width (PWM) modulator 1206B and passed across a capacitively-coupled differential transmission pathway 1204B to a low pass filter demodulator 1212B. The isolator circuit 1200B includes a pulse width modulator (PWM) 1206B, a differential transmission isolation barrier 1202B, and a low pass filter (LPF) demodulator 1212B. The PWM 1206B is generally used for signal preconditioning. The LPF demodulator 1212B can be used for error recovery.

[0091] Referring to FIGURE 12C in combination with FIGURE 10, in some embodiments, the power converter 1000 can include a signal isolator 1060, 1200C that further comprises an error amplifier 1254C coupled to a signal input terminal of the pulse width modulator 1206B and is configured for comparing the signal to a reference. The isolation circuit 1200C forms a pathway including preconditioning and error recovery with an error amplifier 1254C on an input side for comparing an input voltage to a reference voltage, thereby generating an output voltage which is a K-function of the difference.

[0092] FIGURE 12D illustrates an embodiment of an isolation circuit 1200D further comprising an error amplifier 1254D coupled to the lowpass filter modulator 1206B that regulates the error recovered signal upon reconstruction. Referring to FIGURE 12D in combination with FIGURE 10, in some embodiments, the power converter 1000 can include a signal isolator 1060, 1200D that further comprises an error amplifier 1254D coupled to the lowpass filter modulator 1206B that regulates the error recovered signal upon reconstruction. The isolation circuit 1200D forms the pathway with the error function positioned after the signal is reconstructed. The error equation for the implementations shown in FIGURE 12C and 12D function according to the same basic equation. The error function is typically included in the pathway, although some embodiments may omit the function.

[0093] Referring to FIGURE 13A, a combined block and circuit diagram illustrates an embodiment of a signal isolator configured as a dual-channel bidirectional isolator 1300 coupling a primary domain 1302 and a secondary domain 1304. Referring to FIGURE 13A, a combined block and circuit diagram illustrates an embodiment of a power controller 1300 that includes a bidirectional signal isolator 1332. The illustrative power controller 1300 comprises a direct current (DC)-DC converter 1334 configured to receive an input voltage V_ΪN in a primary domain 1302, a transformer 1336 coupled to and driven by the DC-DC converter 1334 that supplies an output voltage V_OUT in a secondary domain 1304, and a dual-channel bidirectional isolator 1332 forming a transmission path 1314, 1324 that passes a signals through an isolation barrier 1316, 1326 between the primary domain 1302 and the secondary domain 1304. The dual-channel bidirectional isolator 1300 comprises a digital isolator 1306 and an analog isolator 1308 coupled in parallel between the primary domain 1302 and the secondary domain 1304 and configured to transmit data in opposing directions.

[0094] The digital isolator 1306 can be configured to pass digital data transmission signals from the primary domain 1302 to the secondary domain 1304 and the analog isolator 1308 can be configured to pass analog information back from the secondary domain 1304 to the primary domain 1302.

[0095] The digital isolator 1306 passes digital information such as shut down, power-on- reset, status information, control information, and the like.

[0096] In some embodiments, the dual-channel bidirectional isolator 1300 can further comprise an error amplifier 1330 coupled to the dual-channel bidirectional isolator 1300 at a primary domain connection or a secondary domain connection. The error amplifier 1330 performs feedback regulation.

[0097] FIGURE 13A depicts a power distribution system 1332 including the signal isolator 1300. The power distribution system 1332 includes a DC -DC converter 1334 with an isolated path 1314, 1324 for varied kinds of signal. The illustrative version of the signal isolator 1300 includes digital signal isolation barrier transmission.

[0098] The illustrative power distribution system 1332 shows a structure and associated technique for transmitting signals across an isolation barrier 1316, 1326. The DC-DC converter 1334 in a primary domain 1302 passes power to a transformer 1336. The transformer 1336 transfers power to a secondary domain 1304 which includes a rectifier 1338 and several discrete components. The rectifier 1338 is a functional block that can perform rectification or signal conditioning in many ways. Signals are passed between the primary domain 1302 and the secondary domain 1304 in two communication pathways. The DC -DC converter 1334 in the primary domain 1302 passes a digital signal to the secondary domain 1304 via a digital isolator 1306. A feedback signal VFB is returned from the secondary domain 1304 to the DC-DC converter 1334 in the primary domain 1302 over an isolating pathway that includes analog-to- digital conversion (ADC) 1308. The ADC 1308 can be implemented using a variety of different structures and functional methods. The ADC can be single-ended or differential, and can have capacitive- coupling. [0099] Referring again to FIGURE 13 A, a return communication signal path from the secondary domain 1304 to the primary domain 1302 is also a transmission path incorporating an isolation barrier 1302. The return transmission path can carry a feedback signal VFB back to the primary domain 1302 and to the DC -DC converter 1334. The return transmission pathway can include an error amplifier 1330 which is shown on the primary domain 1302 but can otherwise be positioned on the secondary domain 1304, as shown in dotted lines. For an analog return signal pathway, the feedback signal VFB is used to control the power distribution system feedback loop. The feedback loop of the DC -DC converter 1334 passes through the transformer 1336, the rectifier 1338, a capacitor Co, a resistor divider 1340, through the analog digital transmission path, and back into the DC -DC converter 1334. The loop is a regulatory loop for regulating power distribution. The error amplifier 1330 is included to complete the regulation functionality. Error amplifier functionality can be on either the primary domain 1302 or the secondary domain 1304 of the isolation barrier 1302.

[0100] A signal from the DC-DC converter 1334 is passed through the digital isolator 1306 and into the rectifier 1338 to enable synchronous rectification. The digital information pathway through the digital isolator 1306 can carry various other information elements in addition to the rectification signal including shut down, enable, power on reset, or a variety of different types of different status or information data which is desired to be send back and forth between the primary domain 1302 and the secondary domain 1304. [0101] The forward path is depicted as a DC -DC converter 1334 but other types of paths can be formed. Some implementations can replace the transformer with another type of transmission path and isolation barrier, for example high voltage capacitors. Accordingly, some other type of power path can be implemented and controlled via a feedback loop. One of paths is a feedback path that transmits a digitized form of the feedback and forms a control loop. In various embodiments, the forward path and feedback path can form a servo loop or other type of digital path that can communicate in either direction across the isolation barrier.

[0102] The feedback signal is represented as a digital signal passing through a capacitor that is fed back to the DC-DC converter 1334 for controlling power passed through the power isolation barrier from the primary domain 1302 to the secondary domain 1304.

[0103] Referring to FIGURE 13B, a block and circuit diagram shows an embodiment of a digital isolator 1306 that can be implemented in the isolator 1300. The digital isolator 1306 comprises a pre-conditioner 1310 adapted to receive an input signal 1312 and precondition the input signal 1312 using a modulation function and a transmission path 1314 comprising an isolation barrier 1316 coupled to the pre-conditioner 1310 for passing a preconditioned signal. The digital isolator 1306 can further comprise a digital recovery circuit 1318 coupled to the transmission path 1314.

[0104] The transmission path 1314 is illustratively shown as an isolation barrier 1316 formed by a capacitor Ciso- The isolation barrier 1316 can be constructed in a variety of forms such as a capacitive isolation barrier, an electrostatic isolation barrier, a transformer isolation barrier, a magnetic isolation barrier, an optical isolation barrier, a thermal isolation barrier, a resistive isolation barrier, a piezoelectric isolation barrier, or others.

[0105] The digital isolator 1306 is shown as a digital transmission block with a dashed-line indicating the isolation boundary. One example of a component that can be implemented for passing data or other information across the boundary is a capacitor Ciso- Accordingly, the digital isolator 1306 can be configured as one or more capacitors although other embodiments can be any type of barrier transmission path. In various implementations the type of isolation and associated digital isolator can be electrostatic isolation as a capacitor, a magnetic isolation formed as a transformer, a light isolation formed as an optical isolator. Other techniques can also transmit information across the boundary using other effects such as thermal, resistive, or more unusual forms such as piezoelectric and the like. Accordingly, information data signals can be passed, for example as digital information, from the primary domain 1302 to the secondary domain 1304, and information that can include feedback signals is communicated back from the secondary domain 1304 to the primary domain 1302, usually as analog signals although some implementations can return digital signals.

[0106] Referring to FIGURE 13C, a block and circuit diagram shows an embodiment of an analog isolator 1308 that can be implemented in the isolator 1300. The analog isolator 1308 can comprise an analog-to-digital converter (ADC) 1320 adapted to receive and precondition a feedback signal 1322 and a transmission path 1324 comprising an isolation barrier 1326 coupled to the ADC 1320 for passing a preconditioned signal. The analog isolator 1308 also comprises a digital-to-analog converter (DAC) 1328 coupled to the transmission path 1324.

[0107] The transmission path 1324 is illustratively shown as an isolation barrier 1326 formed by a capacitor C_ΪSo- In other embodiments, the isolation barrier 1326 can be a capacitive isolation barrier, an electrostatic isolation barrier, a transformer isolation barrier, a magnetic isolation barrier, an optical isolation barrier, a thermal isolation barrier, a resistive isolation barrier, a piezoelectric isolation barrier, or the like.

[0108] In various embodiments, the analog-to-digital converter (ADC) 1320 can be configured to convert, sample, and modulate and analog signal into digital format and pass the digital format signal through a capacitor C_ΪSo in the transmission path 1324. The digital-to-analog converter (DAC) 1328 can be configured to recover the signal to a baseband analog signal.

[0109] FIGUREs 13B and 13C can also show example embodiments of the digital isolator 1306 depicted in FIGURE 13A. FIGURE 13B illustrates the digital isolator 1306 in a form that receives a digital input signal and passes the digital signal to a driver 1310 or other pre-conditioner. The preconditioned signal passes through an isolation capacitor Ciso to a digital recovery block 1318 and then to a digital data output terminal.

[0110] FIGURE 13C can also illustrate an analog signal implementation of the digital isolator 1306. An analog signal path has an analog signal that is passed through an analog-to- digital converter (ADC) of some type. Many types of components or devices can be implemented to perform the conversion function to convert, sample, and modulate the analog signal into a digital format for passage through a transmission path with an isolation barrier, such as a capacitor. The digital signal passes to a signal recovery device or component such as a digital-to- analog converter (DAC) to return a base-band analog signal.

[0111] Referring to FIGURE 14, a schematic block and circuit diagram illustrates an embodiment of a power controller 1400 including a signal isolator 1460 that uses capacitors to couple a feedback signal across an isolation barrier 1402. The illustrative power controller 1400 comprises a power converter 1426 configured to receive an input voltage Vπv in a primary domain 1402, and a transformer 1434 coupled to and driven by the power converter 1426 that supplies an output voltage V_Ouτ in a secondary domain 1404. An isolated transmission path 1404 couples the primary domain 1402 and the secondary domain 1404. A modulator 1406 receives the output voltage V_OUT and conditions the signal for transmission via the isolated transmission path 1404. A demodulator 1412 receives the transmitted signal and recovers a feedback signal V_FB ^Γ for usage in a control loop 1416. [0112] In various embodiments, the modulator 1406 can be implemented as an analog-to- digital converter; a pulse code modulator, a delta modulator, a voltage to frequency converter, a frequency modulator, a phase modulator, a single-ended analog-to-digital converter (ADC) modulator, a differential ADC modulator, or a capacitively-coupled ADC modulator, or other suitable device.

[0113] The modulator 1406 can be constructed as an analog-to-digital converter (ADC) that performs any appropriate modulation such as delta modulation or pulse width modulation to convert a voltage signal to a pulse width signal, frequency modulation to convert the voltage signal to frequency, and a phase modulator to convert the voltage signal to a phase. If the ADC is implemented as a pulse width modulator or delta modulator, the corresponding demodulator 1412 is typically constructed as a low pass filter with frequency modulation constant.

[0114] The illustrative transmission path 1404 is implemented as a pair of capacitors with differential capacitor coupling. In other embodiments, the isolated transmission path can be constructed as one or more capacitors such as with single capacitor coupling, or can be constructed using other devices such as transformers, optical isolators, thermal isolating elements, or others.

[0115] The illustrative isolation circuit 1460 uses a capacitor, such as a high voltage capacitor, to couple a feedback signal across an isolation barrier. A DC feedback signal is sampled at high frequency or modulated on a secondary side, passed through a coupling capacitor, and demodulated on the primary side.

[0116] The illustrative demodulator 1412 is depicted as a digital-to-analog converter (DAC). In other implementations, the demodulator 1412 can be other suitable devices.

[0117] A specific example of an isolation circuit 1460 including an ADC modulator 206 or other modulation scheme such as a pulse code modulator, delta modulator, voltage to frequency conversion modulator, an isolated transmission path 1404, and a DAC demodulator 1412 can be a class D amplifier that receives and modulates an input signal such as an audio signal, and drives a speaker by passing the signal through a capacitor.

[0118] Referring to FIGURE 15, a schematic block diagram illustrates an embodiment of an isolated power converter that includes a DC -DC converter and optical coupler isolation. The power distribution circuit has an input supply voltage applied into the DC-DC converter, a transformer, a rectifying function include in the integration, and an opto-isolator for crossing the barrier with the information. An error function is formed on the secondary side as a light-emitting diode (LED) stacked on a voltage so the output feedback voltage is compared to an internal reference voltage and the difference of the comparison is represented by the current in the transistor Ql which is labeled a feedback error signal.

[0119] In contrast, in the various embodiments shown in FIGURES 8 through 13, the feedback signal is passed through some type of modulation scheme, transmitted on a pathway that includes an isolation barrier, then passed to some type of demodulation. Any suitable type of modulation can be implemented, for example a simple analog-to-digital converter or other simple rectifier. The transmission pathway including an isolation barrier can be any suitable technology, for example one or more capacitors, or other technology. Generally, demodulation can be selected to suitably recover a signal according to the implemented type of modulation. [0120] Modulation can be implemented in a variety of different ways, including but not limited to pulse width modulation (PWM), delta modulation (DM), frequency modulation (FM), phase modulation, and others. Modulation can be used to generate samples in any kind of sample system to produce a serial bit stream with information represented by packets. For example, in classic pulse code modulation, sampling can be implemented to form an eight-bit word so that packets of eight-bit words represent a sample.

[0121] In contrast, other embodiment may implement modulation in a form that is not a true sampled data system where the information is carried in a set number of bits like an eight-bit or other size word.

[0122] For example, an entire framed serial path can be embedded that transmits information as packets that may be 64-bits long and transmitted at 1 OMHz or 100MHz and used to control the feedback loop. Other information can also be communicated on the serial path, for example data or control information such as temperature issues, control signals for shutdown, or any other information that can be usefully passed.

[0123] A simpler implementation of the feedback path can convey in the feedback as a relative variation in feedback voltage end up, whether higher or lower, in a continuous analog approach.

[0124] In contrast to a power converter that uses optical techniques for isolation, the illustrative embodiments shown in FIGURES 8 through 13, can enable production of a circuit with the entire path formed in a single integrated circuit or within a single package. For example, isolation barriers formed using capacitors can be integrated into a single integrated circuit chip.

In some implementations, the isolation barrier can be formed using magnetic inductors that can be implemented with the entire loop in a single package. Optical isolators cannot easily be integrated into a single package with the DC-DC converter because an optical isolator system includes three disparate components: a light emitting diode (LED), a photo transistor, and an error amplifier or reference, to perform communication with optical isolation alone. The embodiments shown in FIGURES 8 through 13 enable production of a realizable circuit in simple packaging and lower cost.

[0125] Referring to FIGURES 16A and 16B, a group of flow charts depict aspects of methods that can be implemented individually or in combination in one or more embodiments for transmitting an information signal across an isolation barrier. FIGURE 16A shows a method 1600 for transmitting a signal across an isolation barrier that comprises receiving 1602 an input signal, preconditioning 1604 the input signal based on a selected modulation function, and passing 1606 the preconditioned signal through the isolation barrier. The method 1600 further comprises recovering 1608 the passed signal according to a demodulation function corresponding to the modulation function. The recovered signal is a feedback signal.

[0126] The illustrative technique for transmitting an analog signal across an isolation boundary fundamentally involves receiving an analog signal, digitizing the signal, and passing the digitized signal through a control system. Digitizing the signal can include some type of analog to digital conversion or a modulation scheme. The signal can be passed over an isolation capacitor to a digital to analog converter.

[0127] In various embodiments, preconditioning 1604 the input signal can comprise converting the input signal from an analog signal to a digital signal based on a modulation function such as pulse width modulation, delta modulation, frequency modulation, and phase modulation.

[0128] The preconditioned signal can be passed 1606 through an isolation barrier that can be a capacitive isolation barrier, an electrostatic isolation barrier, a transformer isolation barrier, a magnetic isolation barrier, an optical isolation barrier, a thermal isolation barrier, a resistive isolation barrier, a piezoelectric isolation barrier, or other suitable isolation barrier. In various embodiments, the preconditioned signal can be passed 1606 through a single-ended isolation barrier or a differential isolation barrier. In some embodiments, the passed signal can be recovered 1608 according to a bistable multivibrator operation, digital to analog conversion, or other suitable operation. In some embodiments, the feedback signal can be regulated 1610 by comparison with a reference signal. [0129] Referring to FIGURE 16B, another embodiment of a method 1620 for transmitting an information signal across an isolation barrier is shown that comprises modulating 1622 a direct current (DC) feedback voltage signal and passing 1624 the modulated DC feedback voltage signal through a capacitor by oversampling. The passed voltage can be demodulated 1626 to recover the baseband signal. The demodulated voltage signal can be lowpass filtered 1628 to restore an analog signal.

[0130] Referring to FIGURES 17A through 17E, a group of flow charts depict aspects of methods that can be implemented individually or in combination in one or more embodiments for controlling power in an electrical system. FIGURE 17A shows a method 1700 comprising receiving 1702 an input voltage in a primary domain, converting 1704 the input voltage from a first direct current (DC) level to a second DC level, and passing 1706 the converted voltage to a load at a secondary domain. The converted voltage is modulated 1708 into a feedback signal and the feedback signal is transmitted 1710 from the secondary domain to the primary domain across an isolation barrier. The feedback signal is demodulated 1712 in the primary domain, controlling 1714 conversion of the input voltage from the first to the second DC level using the demodulated feedback signal.

[0131] In various embodiments, passing 1706 the preconditioned signal through the isolation barrier can be implemented by passing the signal through a capacitive isolation barrier, an electrostatic isolation barrier, a transformer isolation barrier, a magnetic isolation barrier, an optical isolation barrier, a thermal isolation barrier, a resistive isolation barrier, a piezoelectric isolation barrier, or other barrier.

[0132] In various embodiments, the preconditioned signal can be passed 1706 through a single-ended isolation barrier or a differential isolation barrier. [0133] In some embodiments, the method 1700 can further comprise regulating 1716 the feedback signal by comparison with a reference signal.

[0134] Referring to FIGURE 17B, controlling power can include a method for transmitting 1720 a signal across the isolation barrier comprising sampling 1722 the converted voltage in the secondary domain whereby the converted voltage is modulated and coupling 1724 the feedback signal across the isolation barrier from the secondary domain to the primary domain through a capacitor. The feedback signal can be demodulated 1726 in the primary domain.

[0135] Referring to FIGURE 17C, controlling power can include a method for transmitting 1730 a signal across the isolation barrier can further comprise performing 1732 analog to digital conversion of the converted voltage whereby the converted voltage is modulated into the feedback signal. The feedback signal can be lowpass filtered 1734 whereby the feedback signal is demodulated in the primary domain.

[0136] Referring to FIGURE 17D, controlling power can include a method for transmitting 1740 a signal across the isolation barrier comprising receiving 1742 the converted voltage in the secondary domain as the feedback signal, preconditioning 1744 the feedback signal according to a modulation function, and passing 1746 the preconditioned signal through the isolation barrier. The passed signal can be recovered 1748 according to a demodulation function corresponding to the modulation function, the recovered signal being operative as a feedback signal.

[0137] In various embodiments, preconditioning 1744 the feedback signal can comprise converting the feedback signal from an analog signal to a digital signal according to a modulation function such as pulse width modulation, delta modulation, frequency modulation, phase modulation, or other suitable modulation.

[0138] Recovering 1748 the passed signal can be implemented according to a bistable multivibrator operation or digital to analog conversion. [0139] Referring to FIGURE 17E, controlling power can include a method for transmitting 1750 a signal across the isolation barrier comprising modulating 1752 a direct current (DC) feedback voltage, passing 1754 the modulated DC feedback voltage through a capacitor by oversampling, and demodulating 1756 the passed voltage to an increased frequency, thereby recovering a baseband signal. The demodulated voltage can be lowpass filtered 1758 to restore an analog signal.

[0140] Referring to FIGURE 18A, a schematic circuit diagram illustrates an embodiment of a signal isolator 1800A that is configured as a digital isolator with capacitors arranged to create magnetic and electrical differentiality. The signal isolator 1800A comprises an integrated circuit substrate 1802 and an isolation barrier 1804 formed by two or more interlay er metal dielectric capacitors 1806 that isolate a first domain 1808A from a second domain 1808B in the substrate 1802. A transmitter 1810 in the first domain 1808A is configured to transmit an information signal through the isolation barrier 1804. A differentiator 1812 in the second domain 1808B is configured to differentiate the transmitted information signal. A feedback device 1814 in the second domain 1808A is coupled to the differentiator 1812 and is used to recover an output information signal based on the differentiated information signal. The feedback device 1814 can be configured to recover the output information signal using positive feedback.

[0141] The isolation barrier 1804 can form a differential transmission pathway 1816 made up of multiple differential lines 1818 each having parallel capacitive pathways 1820 configured to create magnetic and electrical differentiality. For example, by dividing the capacitors 1806 into multiple units, such as four units as shown, magnetic and electrical differentiality can be attained.

[0142] In the illustrative embodiment, the differential transmission pathway 1816 can have first and second differential lines 1818. Each differential line 1818 can have two parallel pathways 1820 with each pathway including first and second capacitors 1806 coupled at a bond pad 1822. [0143] The bond pads 1822 can be arranged in positions that attain first-order common- centroiding of the capacitors 1806, thereby removing distance effects. In an illustrative embodiment first-order common-centroiding of the capacitors 1806 can attain a suitable improvement, for example on the order of 2OdB or other suitable improvement. [0144] In the illustrative example, four capacitors 1806 and associated bond wires are placed in a physical configuration whereby the differential current flow in the loops 1840 and 1842 are in balance to the first order and generate magnetic fields that cancel, creating a magnetic dipole with greatly reduced far-fields. The same principle also enables the device to reject magnetic interference so that the circuit attains a magnetically differential characteristic. [0145] In various embodiments, the isolation barrier 1804 can be configured in any suitable arrangement such as two or more interlayer metal dielectric capacitors 1806 formed in the first domain 1808A and two or more interlayer metal dielectric capacitors 1806 formed in the second domain 1808B. In another arrangement, the two or more interlayer metal dielectric capacitors 1806 can be formed partly in the first domain 1808A and partly in the second domain 1808B. Also, the two or more interlayer metal dielectric capacitors 1806 can be formed between the first 1808A and second 1808B domains. Furthermore, the interlayer metal dielectric capacitors 1806 can be formed partly in the first domain 1808A, partly in the second domain 1808B, and partly between the first and second domains. Also, the isolation barrier 1804 can be constructed completely in one domain as illustrated in FIGURE 18B. [0146] The differentiator 1812 separates a common-mode to differential component from true differential components. Common mode suppression element 1832 can be used to maintain the differentiator 1812 is linear range.

[0147] The differentiator 1812 is shown with resistive feedback and connected to the common mode control element 1832. In some embodiments, the common mode control element 1832 can be omitted through usage of common mode techniques in configuring the differentiator. As long as common mode feedback is maintained, low impedance input is inherent, enabling elimination of the common mode control element 1832. Other designs can include multiple differentiators coupled in series to form a low impedance input condition to the receiving side of the isolation barrier. Accordingly, several techniques can be used to implement a differentiator that forms a low impedance input condition which is desirable for usage with capacitors, as opposed to inductors. In some embodiments, the differentiator 1812 can be configured as a current mode differentiator.

[0148] In accordance with another embodiment of a signal isolator 1800A, also as depicted in FIGURE 18A, can comprise an isolation barrier 1804 isolating first 1808A and second 1808B domain, a modulator 1824, a differentiator 1812, and a recovery circuit 1826. The modulator 1824 is in the first domain 1808A and coupled to the isolation barrier 1804. The modulator 1824 can be configured to convert an information signal to a digital signal that contains all information in the information signal in an edge of a single transition and passes the digital signal across the isolation barrier 1804 to the second domain 1808B. The differentiator 1812 is positioned in the second domain 1808B and is also coupled to the isolation barrier 1804. The differentiator 1812 differentiates the passed digital signal. The recovery circuit 1826 is also located in the second domain 1808B coupled to the differentiator 1812. The recovery circuit 1826 is configured to recover an output information signal from the differentiated digital signal based on the information in the single transition edge.

[0149] The recovery circuit 1826 can comprise a comparator 1834 coupled to the differentiator 1812 and a feedback device 1814 coupled to the comparator 1834. The comparator 1834 accesses data out of the differentiator 1812 based on a reference level that may be fixed or the output signal from a peak detector. [0150] In various implementations, modulation can be implemented in a variety of different ways, including but not limited to pulse width modulation (PWM), delta modulation (DM), frequency modulation (FM), phase modulation, and others.

[0151] In an illustrative example implementation, a powered system 1828 can be formed in the first domain 1808A and an isolated system 1830 in the second domain 1808A. The illustrative signal isolator 1800A has a channel formed by the transmitter 1810 that passes a single signal to the modulator 1824 which operates as a differential receiver.

[0152] Referring to FIGURE 18B, a schematic circuit diagram illustrates an embodiment of a signal isolator 1800B that is configured as a digital isolator with an isolation capacitor on one die. The illustrative signal isolator 1800B comprises an isolation barrier 1804, a transmitter 1810, a differentiator 1812, and a feedback device 1814. The transmitter 1810 is coupled to a first side 1808A of the isolation barrier and is configured to receive and convert an information signal to a differential signal that encodes information in the information signal in a single transition edge. The differentiator 1812 is coupled to a second side 1808B of the isolation barrier 1804 which is isolated from the first side 1808A of the isolation barrier 1804. The differentiator 1812 differentiates the differential signal. The feedback device 1814 is coupled to the differentiator 1812 and configured to recover an output information signal based on the information in the single transition edge.

[0153] The signal isolator 1800B, as depicted, can be implemented with all isolation on a single die. In various embodiments, a signal isolator can be implemented in which the first and second dies are not on the same wafer, or even from the same process. For example, in some arrangements the transmitter can be formed on a high-voltage process that is different from the process of the receiver side of the isolator. The feedback device 1814 can be configured to recover the output information signal using positive feedback. [0154] In some embodiments, the differentiator 1812 can be configured to separate a common-mode-to-differential signal component, which can result for example from mismatch of capacitors 1806, from true differential signal components. For example, the differentiator 1812 can be configured as a current mode differentiator. A common mode suppression control circuit 1832 can be coupled to the differentiator 1812 and configured to maintain the differentiator 1812 in a linear range.

[0155] In accordance with another embodiment of a signal isolator 1800B, also as depicted in FIGURE 18B, can comprise an isolation barrier 1804, a modulator 1824, a differentiator 1812, and a recovery circuit 1826. The modulator 1824 is coupled to an input side 1808A of the isolation barrier 1804 and can receive a logic signal with first and second transition edges that shift the logic signal between two states. The modulator 1824 converts the logic signal to a differential signal and passes the differential signal across the isolation barrier 1804. The differentiator 1812 is coupled to an output side 1808B of the isolation barrier 1804 and functions to differentiate the communicated differential signal. The recovery circuit 1826 is coupled to the differentiator 1812 and recovers a signal indicative of the first and second transition edges from the differentiated signal. The recovery circuit 1826 can be configured to recover the output information signal using positive feedback.

[0156] The modulator 1824 can be implemented to create the differential signals that contain all information in the logic signals in a single transition edge. In a particular embodiment, the modulator 1824 can be implemented as a differential comparator. A differential comparator 1834 can be coupled to a set/reset latch 1836 to form the recovery circuit 1826.

[0157] A powered system 1828 can be constructed on the input side 1808A of the isolation barrier 1804 and an isolated system 1830 can be constructed on the output side 1808B of the isolation barrier 1804. The differentiator 1812 can be configured as a current mode differentiator. A common mode suppression circuit 1832 can be coupled between the isolation barrier 1804 and the recovery circuit 1826. The common mode suppression circuit 1832 can be configured to maintain differentiation in a linear range.

[0158] Referring to FIGURE 18C, a schematic block diagram illustrates an embodiment of a signal isolator 1800C configured as a digital isolator with multiple differentiators. The signal isolator 1800C comprises an isolation barrier 1804, a transmitter 1810, and a recovery circuit 1826. The isolation barrier 1804 forms a differential transmission pathway 1816 comprising multiple differential lines 1818, each comprising multiple parallel capacitive pathways 1820 configured to create magnetic and electrical differentiality. A transmitter 1810 coupled to a first side 1808A of the isolation barrier 1804 is configured to receive and convert an information signal to a differential signal that encodes information in the information signal in a single transition edge. The recovery circuit 1826 is coupled to the differentiator 1812 and configured to recover an output information signal based on the information in the single transition edge.

[0159] The signal isolator 1800C can further comprise a differentiator 1812 coupled to the second side 1808B of the isolation barrier 1804 which is isolated from the first side 1808A of the isolation barrier 1804. The differentiator 1812 differentiates the differential signal. In the illustrative embodiment, multiple differentiators 1812A, 1812B can be coupled to the second side 1808B of the isolation barrier 1804 and configured to separate a common error signal from differential.

[0160] Double differentiation further separates the common mode error signal from the differential signal. The first differentiator 1812A can be implemented to saturate gracefully during common-mode events, including for example some surge protection, preventing generation of a differential error. Accordingly, implementation of multiple differentiators enables omission of a common-mode suppression circuit.

[0161] The illustrative signal isolator 1800C can include a parasitic capacitor 1838 between the differentiators 1812A and 1812B. The parasitic capacitors 1838 can be positioned to attain power estimation. Parasitic poles can limit performance in the first 1812A and second 1812B differentiators. For example, the second differentiator can have a parasitic pole at ω=l/RC. To avoid the parasitic poles in the voltage domain, a possible solution can use implementation in current mode. Accordingly, in some embodiments the differentiator or differentiators 1812 can be configured as current mode differentiators.

[0162] The recovery circuit 1826 for the multiple differentiator implementation of the signal isolator 1800C is generally more complex than that for a single differentiator implementation. A single edge from the transmitter 1810 produces two pulses from the differentiator 1812. A unique quality of the pulses is that spacing is a function of rise time of the transmitter 1810. Common- mode interference resulting from mismatches that leak into the differential creates pulses that are not as closely spaced. A timer in the recovery circuit 1826 only changes the output state when spacing between pulses are sufficiently close, leading to production of another level of immunity and enabling reduction of the power requirements for the receiver with the tradeoff that speed on the isolator is reduced. [0163] The signal isolators 1810A, 1800B, and 1800C are typically configured with fully differential paths to attain predetermined skew requirements, for example rise-to-fall edge delay mismatch of less than about lnsec although any suitable specification may be implemented.

[0164] Referring to FIGURES 19A and 19B, a schematic circuit diagram and associated system respectively illustrate an embodiment of a current-mode differentiator 1900 that can be implemented in various implementations of a signal isolator. The illustrative structure is a single- ended input current-mode differentiator. The differentiator 1900 can be implemented using current mode techniques. The illustrative differentiator 1900 can be formed using a current-in, current-out design which has low input impedance. The illustrative common-mode techniques can have a hidden open-loop characteristic which is typically tolerable in the illustrative application. FIGURES 19A and 19B depict a differentiator with a single-ended input terminal and differential output terminals. A fully-differential configuration can be implemented wherein the common-mode feedback in the design provides the common-mode suppression that is used to maintain the design in the linear range during common-mode transients. [0165] Other embodiments may employ a differential current conveyor technique, as depicted in FIGURE 19C which operates according to equation Z(I) =V(Yi - Y₂)Z(Xi - X₂).

[0166] A suitable voltage mode differentiator can be difficult to implement in the digital isolator due to the presence of parasitic poles. Accordingly, current mode techniques can be used to avoid parasitic poles. FIGURES 19A and 19B illustrate a current mode differentiator 1900 that passes a current with low impedance that is useful for pulling current from capacitors on the isolation boundary. Accordingly, the common mode differentiator 1900 can be used so that the transmission signal is passed through the isolation barrier to a low impedance node. In contrast, other isolation barrier embodiments, such as a transformer barrier that produces a voltage, passes the signal to a high impedance node, for example a latch. [0167] The differentiator, particular the current mode differentiator, enables faster response to a differential signal, better bandwidth, and also forms an inherently low impedance input that facilitates common mode rejection and handling of high common mode transients. A differentiator formed according to a current mode approach has low impedance that is inherently better to handle the high common mode transients affecting the isolator. [0168] In general, an isolation barrier implemented with capacitors is better for passing signals to low impedance node than a barrier formed from inductors.

[0169] Referring to FIGURE 20, a schematic circuit diagram illustrates an embodiment of a differentiator 2000 that can be implemented in a digital signal isolator. [0170] Referring to FIGURE 21, a schematic circuit diagram shows an embodiment of a comparator 2100 that can be implemented in a digital signal isolator.

[0171] Referring to FIGURES 22A, 22B, and 22C, a set of time waveforms illustrate aspects of operation of a first differentiator output signal. FIGURE 22A shows an example of a data output signal and the portion of the signal that results from common -mode noise. The data output signal shows output voltage of the first differentiator output terminal, illustratively showing a 50kV/μsec test at true ground. A single pulse is generated for the normal differential which is overlaid by the response to a normal fast transmission edge out of the first differentiator, which is a pulse. The common-mode noise signal results from capacitive mismatch, for example of about the order of one percent, and leads to some differential signal but is rejected by the differentiator and does not produce a large output pulse so the differentiator.

[0172] FIGURE 22B shows results of a 50kV/μsec slew test and indicates how two grounds can move apart. FIGURE 22C illustrates differential input drive as the normal differential edge that does the transmission. The differential pulse produces a large output signal whereas the common-mode implementation leads to differential pulse due to capacitor mismatch, but with a much slower edge leading to smaller pulse amplitude.

[0173] Referring to FIGURES 23A, 23B, and 23C, several cross-sectional views depict an embodiment of a semiconductor device 2300 that can be used for implementing the illustrative signal isolators including integration of capacitors. The semiconductor device 2300 comprises an integrated circuit 2304 formed on a substrate 2306 and has a signal interface with one or more isolator capacitors. The integrated circuit 2304 comprises multiple interleaved inter-metal dielectric layers and interlayer dielectrics 2308 formed on the substrate 2306, a thick passivation layer 2312 formed on the multiple interleaved inter-metal dielectric layers and interlayer dielectrics 2308, and a thick metal layer 2310 formed on the thick passivation layer 2312. The thick passivation layer 2312 has a thickness selected to be greater than the thickness warranted for sufficient isolation so that testing for detects can be eliminated. The one or more isolator capacitors are formed by the thick metal layer 2310 and a metal layer in the multiple interleaved inter-metal dielectric layers and interlayer dielectrics 2308 separated by the thick passivation layer 2312 as an insulator. The increased thickness of the passivation layer 2312 results in elimination or reduction of parasitic capacitance because a higher layer or level of metal can be used for a bottom plate of the capacitor, for example metal layer M4. Without the thick passivation layer 2312, a much lower layer of metal or polysilicon might be used, for example Ml, to attain sufficient isolation.

[0174] In some embodiments, the integrated circuit 2304 comprising multiple interleaved inter-metal dielectric layers and interlayer dielectrics 2308 in a stack 2302 formed on the substrate 2306, a thick passivation layer 2310 formed on the metal and dielectric layer stack 2302, and a thick metal layer 2310 formed on the thick passivation layer 2312. Multiple isolator capacitors can be formed on separate dies and configured with a reduced ratio of parasitic capacitance to primary capacitance since only a fraction of the isolation is allocated to each die. [0175] In a particular implementation, isolator capacitors can be configured with the thick passivation layer 2312 functioning as an insulator with a thickness that is selected to reduce parasitic capacitance by enabling the lower metal plate of the capacitor to be located on a higher level or layer of metal. Passivation layer thickness can further be selected to improve high-speed operation of the interface. [0176] The integrated circuit 2304 can be implemented using standard processing to construct the substrate 2306, the multiple interleaved inter-metal dielectric layers and interlayer dielectrics 2308, the thick passivation layer 2312, and the thick metal layer 2310. However, improvements in performance can be attained by constructing the integrated circuit 2304 so that the thickness of the thick passivation layer 2312 is selected to be larger than for standard processing to reduce the impact of oxide defects. The increased thickness of the thick passivation layer 2312 can enable elimination or minimization of usage of high-voltage production testing, if sufficient margin is included in the design. For example for an isolation specification of 1500V_RMS for one minute such as dictated in Institute of Electrical and Electronics Engineers (IEEE) 802.3, the oxide on each die supports 1500V_RMS, SO that even if one of the two capacitor fails, isolation support is still maintained. In practice the effect of margin is more distributed, but achieves the same result of removing the need for isolation testing.

[0177] In an example embodiment, the integrated circuit 2304 can be configured with the multiple interleaved inter-metal dielectric layers and interlayer dielectrics 2308 distributed within silicate glass dielectric layers, separated by thin silicon nitride layers and overlying inter-layer dielectric layers. The thick metal layer 2310 can be a redistribution layer (RDL) with the thick passivation layer 2312 constructed as an undoped silicate glass (USG) layer.

[0178] The illustrative semiconductor device 2300 comprises an integrated circuit 2304 formed on a substrate 2306 and includes a signal interface with at least one isolator capacitor. The integrated circuit 2304 comprises multiple interleaved inter-metal dielectric layers and interlayer dielectrics 2308 formed on the substrate 2306, a thick metal layer 2310 formed on the multiple interleaved inter-metal dielectric layers and interlayer dielectrics 2308, and a passivation layer 2312 formed on the thick metal layer 2310. The one or more isolator capacitors can be configured to use the thick oxide layer as an insulator whereby thickness of the oxide layer is selected to reduce parasitic capacitance. The passivation layer 2312 can be formed from tetra- ethyl-ortho-silicate (TEOS) oxide, P-doped silicate glass (PSG), thick oxide, or other suitable materials.

[0179] The illustrative semiconductor structure enables capacitor matching. The thick metal layer 2310 can be used for the complementary metal-oxide semiconductor (CMOS) processes for radio frequency inductors and typically have a thickness of 2-3 microns although any suitable thickness may be appropriate for a particular structure or application. In the illustrative integration, the thick metal 2310 is present due to usage for the inductors and the passivation layer 2312 is also available, a condition which can be exploited for usage in forming isolation capacitors. The integrated circuit 2304 can also include a redistribution layer (RDL) overlying the passivation layer 2312 which can be an extra thick and high quality layer. The combination of the metal stack and passivation layer 2312 can be configured in combination to form capacitors with a low level of parasitic capacitance and that facilitate high-speed operation. For example, the capacitors can be formed from metal layers positioned adjacent and on the two sides of the passivation layer 2312, enabling construction of a high-speed isolator. Reduced-size capacitors that can be formed using the illustrative metal layers and passivation layer 2312 and generally, the smaller the capacitors, the more easily a high-speed circuit can be attained without consuming an inordinate amount of power.

[0180] The illustrative process enables a lower parasitic capacitance, for example as shown for capacitance at the input current to the differentiator 600 in FIGURE 28A and the parasitic capacitance CPl at the transmitter 3324 in the isolation interface 3300 in FIGURE 33. The small capacitors enable high-speed operation since large capacitors make difficult a high-speed implementation.

[0181] The illustrative integrated circuit 2304 can be formed using a digital process which is standard for example for radio frequency circuits. The integrated circuit 2304 can otherwise be constructed by creating additional distribution layers for building the oxides at the possible detriment to reliability. By forming offset layers as a part of a standard process inherently helps to mitigate variation in the layers since in a nonstandard process, each layer introduces an independent variable in processing so that overall oxide thickness can be variable.

[0182] Another possible disadvantage of a nonstandard process is the risk of introducing defects in the oxide layers that can limit reliability. If a defect exists in the oxide, a capacitor can fail. To enhance reliability, the standard process can be used to construct an extra thick oxide layer, for example an oxide layer with thickness greater than specified by the standard, thereby increasing reliability in parallel with improving high-speed performance. The increased reliability attained by forming a thicker oxide layer avoids the impact of defects and enables a reduction in testing and the expenses of testing. [0183] The capacitors formed on a single wafer can be split into two dies, enabling improvement in high-speed isolator performance by reducing the ratio of parasitic capacitance to primary capacitance. Increasing the thickness of the oxide layer also reduces the ratio of parasitic capacitance to primary capacitance. [0184] The metal stack 2302 can be formed of multiple metal layers in interleaved inter- metal dielectric layers and interlayer dielectrics 2308, for example distributed within multiple silicate glass dielectric layers, for example formed from tetra-ethyl-ortho-silicate (TEOS) and fluorine -doped TEOS (FTEOS) separated by thin silicon nitride (SiN) layers, and overlying interlayer dielectric layers (ILDl, ILD2) that function as an insulator to separate two or more conductive layers.

[0185] FIGURE 23A shows processing of the metal stack 2302 and thick metal layer 2310 and passivation 2312 that can be used to construct capacitors. In an illustrative embodiment, the thick metal layer 2310 can be a redistribution layer with a metal via 2314 formed beneath the RDL preventing deposition of undesirable passivation material. FIGURE 23B illustrates an RDL metal via 2314 to one or more metal layers, for example layer M8. The via 2314 is shown under the RDL metal layer 2310, locally replacing the passivation layer 2312, a design rule violation that facilitates or enables operation of the capacitor.

[0186] Metal vias 2314 can be formed to prevent deposition of materials with unfavorable breakdown voltages. In various applications, arrangements, and/or embodiments, metal vias 2314 for preventing material deposition can be formed in association with the thick metal layer 2310 and metal layers within the stack 2302, or independent of either or both metal layers.

[0187] One or more metal layers selected formed among the multiple interleaved inter-metal dielectric layers and interlayer dielectrics 2308 can be formed underlying the metal via 2314 to extend laterally so that the lateral extension of the metal via 2314 overlaps the metal layer or layers. FIGURE 23C shows formation of the via 2314 in an arrangement that overlaps metal layer M4, preventing or reducing a fringing effect.

[0188] Referring to FIGURE 23D, a schematic pictorial view shows an arrangement of first 2320 and second 2322 metal plates for an isolation capacitor 2324 with the first plate 2320 smaller than the second plate 2322. In an example embodiment, the first plate 2320 can be a top plate, and the second plate 2322 a bottom plate. FIGURE 23E is a pictorial view depicting a top plate 2320 larger than a bottom plate 2322 with a metal via 2314 offset from the bottom plate 2322. In an illustrative embodiment, the thick metal layer 2310 can be functional as the first plate 2320 and a predetermined metal layer, for example M4, in the interleaved inter-metal dielectric layers and interlayer dielectrics 2308 functional as the second plate 2322 in the isolation capacitor 2324. The first plate 2320 and the second plate 2322 can be arranged as substantially parallel planes extending laterally with an overlap selected to compensate for dielectric leakage and fringe fields from creating voltage gradients. [0189] In some embodiments, the first plate 2320 and the second plate 2322 can be formed with rounded or oblique angles so that electric fields and/or voltage gradients are reduced or minimized.

[0190] Referring to FIGURE 24, a schematic block diagram illustrates an embodiment of an interface 2400 that can be implemented to operate a high speeds, for example in the gigabit per second range. The interface 2400 comprises a converter 2402 that is configured to track process characteristics across an isolation barrier 2404 and modify the amplitude of a fast differential edge modulation as a function of the speed of an active device 2406 on a transmitting side 2408 of the isolation barrier 2404. The interface 2400 also has a differentiator 2410 that is configured to differentiate the fast differential edge modulation on the receiving side 2412 of the isolation barrier 2404 whereby differentiation bandwidth tracks slope rate of the differential edge modulation.

[0191] A digital input signal is converted to a fast differential edge modulation that tracks process characteristics across the isolation barrier 2404. For example, process characteristics can be selected to track by incorporating integrated circuits on the two sides of the isolation barrier that are cut from the same processed semiconductor wafer.

[0192] FIGURE 24 is a high-level block diagram depicting general elements of an embodiment of an isolator interface 2400 that can be implemented as a high-speed isolator but may be used in other applications. The interface 2400 is operative to perform information communication across an isolation barrier 2404 by a modulation technique which converts an information signal to a digital signal containing all information in the information signal in an edge of a single transition.

[0193] In some embodiments, the interface 2400 can have a capacitive isolation barrier 2404 coupled between the converter 2402 and the differentiator 2410 that is operative for passing the fast differential edge modulation. The converter 2402 and differentiator 2410 can be configured for tracking the differentiation bandwidth and slope rate of the differential edge modulation whereby capacitor size in the isolation barrier 2404 is reduced or minimized and low frequency components in the passed fast differential edge modulation are attenuated so that common mode noise is rejected. Common-mode noise between the two sides of the isolation is converted into differential error due to capacitor mismatch, which could create an error whereby the receiver interprets the noise as data. In general, external noises between the grounds that are large (1-2 kV) have less bandwidth than the internally generated differential signal. Differentiation tends to suppress the external signal relative to the internal signals. Faster, external signal that are smaller in amplitude are rejected by the differential nature of the circuit. [0194] The interface 2400 is configured for transmitting a signal through the isolation barrier 2404 by converting a digital signal to a fast differential edge modulation that tracks process characteristics across the isolation barrier 2404 and passes the fast differential edge modulation through the isolation barrier 2404. The fast differential edge modulation that is passed through the isolation barrier 2404 is differentiated to form a pulse according to a transfer function that amplifies the pulse.

[0195] Process characteristics across the isolation barrier can be tracked by modifying the amplitude of the fast differential edge modulation as a function of speed of an active device 2406 on a transmitting side 2408 of the isolation barrier 2404. The edge rate and amplitude of the fast differential edge modulation is controlled to characterize information in the digital signal. In embodiments that pass the fast differential edge modulation through a capacitive isolation barrier, the fast differential edge modulation that is passed through the isolation barrier 2404 is differentiated to form the pulse according to a transfer function that amplifies the pulse whereby capacitor size in the isolation barrier is reduced or minimized.

[0196] Referring to FIGURE 25A in combination with FIGURE 24, in some embodiments the interface 2400 can be implemented with a capacitive isolation barrier 2404 coupled between the converter 2402 and the differentiator 2410 that comprises multiple inter-level metal dielectric (IMD) capacitors 2502. A feedback control loop 2504 can be configured to match a metal- insulator-metal (MIM) capacitor 2506 to the IMD capacitors 2502 so that differential bandwidth tracks over process variations. [0197] In some implementations, the capacitive isolation barrier 2404 can comprise a multiple inter-level metal dielectric (IMD) capacitors 2502 formed on first and second sides of the isolation barrier 2404 from respective separate first and second integrated circuit dies cut from adjacent portions of a common wafer.

[0198] The fast differential edge modulation is passed through the capacitive isolation barrier 2404 which can be implemented as multiple inter-level metal dielectric capacitors 2502 formed on both sides of the isolation barrier 2404 that can be constructed from respective separate first and second integrated circuit dies from adjacent portions of the common wafer.

[0199] The fast differential edge modulation can be passed through the capacitive isolation barrier 2404 constructed from multiple inter-level metal dielectric (IMD) capacitors 2502. A metal-insulator-metal (MIM) capacitor 2506 can be matched to the inter-level dielectric capacitors 2502 by feedback control so that differential bandwidth tracks over process variations.

[0200] Referring to FIGURE 25B, a circuit diagram depicts an embodiment of a positive feedback recovery circuit including a high-speed latch that can be used to reclaim a digital signal from a sliced pulse signal. A high-speed positive feedback signal can be used to recover the digital data at the output of the slicer. An N-channel metal-oxide semiconductor (NMOS)-only design can be used to ensure the fastest possible bandwidth with the least possibility of meta- stability.

[0201] Referring again to FIGURE 24, another embodiment of the signal interface 2400 can comprise an isolation barrier 2404, a converter 2402, and a differentiator 2410. The converter 2402 is coupled to a transmitting side 2408 of the isolation barrier 2404 and configured for receiving a digital signal and converting the digital signal to a fast differential edge modulation that tracks process characteristics across the isolation barrier 2404. The differentiator 2410 coupled to a receiving side 2412 of the isolation barrier 2404 and configured for receiving the fast differential edge modulation passed through the isolation barrier 2404 and differentiating the passed fast differential edge modulation to form a pulse according to a transfer function that amplifies the pulse. The converter 2402 is configured for controlling edge rate and amplitude of the fast differential edge modulation to characterize information in the digital signal. Typically, the differentiator 2410 can be a first or second order differentiator, although any suitable differentiator or high-pass^andpass filter may be incorporated into the signal interface 2400.

[0202] The isolation barrier 2404 can be a capacitive isolation barrier that passes the fast differential edge modulation. The differentiator 2410 can be configured for differentiating the passed fast differential edge modulation and forming a pulse according to a transfer function that amplifies the pulse whereby capacitor size in the isolation barrier 2404 is reduced or minimized. [0203] Referring to FIGURES 23A, 23B, and 23C in combination with FIGURES 24 and

25A, the integrated circuit 2304 can be divided into two dies arranged across the isolation barrier 2404 wherein capacitors 2502, 2506 respectively formed on separate dies are configured with a reduced ratio of parasitic capacitance to primary capacitance.

[0204] For example, the integrated circuit 2304 can be divided into two or more dies where adjacent dies from the integrated circuit 2304 are arranged across the isolation barrier 2404 and capacitors 2502, 2506 are matched.

[0205] In another example implementation, the integrated circuit 2304 can be divided into two or more dies where adjacent dies from the integrated circuit 2304 are arranged across an isolation barrier 2404. A capacitor 2502, 2506 can be a combination of two parts, for example halves, with the different capacitor parts formed on different dies but constructed from the same wafer with matched characteristics.

[0206] The semiconductor device 2300 can be implemented with the integrated circuit 2304 divided into first 2408 and second 2412 dies and an isolation barrier 2404 formed between the first 2408 and second 2412 dies. Multiple capacitors 2502, 2506 can be formed on separate dies. A converter 2402 in the first die 2408 can be configured to track process characteristics across the isolation barrier 2404 and modify the amplitude of a fast differential edge modulation as a function of speed of an active device on a transmitting side of the isolation barrier 2404. A differentiator 2410 in the second die 2412 can be configured to differentiate the fast differential edge modulation on a receiving side 2412 of the isolation barrier 2404 so that differentiation bandwidth tracks slope rate of the differential edge modulation.

[0207] In an example implementation, the differentiator 2410 can include a calibrated capacitor that matches the capacitors 2502, 2506.

[0208] In another example embodiment, the semiconductor device 2300 can be constructed which includes a capacitive isolation barrier 2404 coupled between the converter 2402 and the differentiator 2410 that passes a fast differential edge modulation. The converter 2402 and differentiator 2410 track the differentiation bandwidth and slope rate of the differential edge modulation to enable capacitor size in the isolation barrier to be reduced or minimized. Low frequency components in the passed fast differential edge modulation are attenuated and common mode noise is reduced.

[0209] In another example embodiment, the semiconductor device 2300 can further include a capacitive isolation barrier 2404 coupled between the converter 2402 and the differentiator 2410 constructed to include multiple inter-level metal dielectric capacitors 2502. A feedback control loop can be used to balance the plurality of inter-level metal dielectric capacitors 2502. [0210] The capacitive isolation barrier 2404 can be formed with multiple inter-level metal dielectric capacitors 2502 formed on first 2408 and second 2412 sides of the isolation barrier 2404 from respective separate first and second integrated circuit dies from adjacent portions of a common wafer.

[0211] For example, referring to FIGURES 26A, 26B, and 26C, a schematic graph, a circuit diagram showing a more typical implementation, and a block diagram illustrating a system using a differentiator respectively show a technique for amplifying the pulse to reduce capacitor size in the isolation barrier.

[0212] FIGURE 26B depicts a typical capacitive isolation arrangement 2610 with a digital input voltage VIN that is passed across the capacitive isolation 2612 to a receiver side 2614 as an output voltage VOUT. Usually the receiver 2614 has either a clocked or an asynchronous flip-flop 2616 tied to the output line of the capacitor 2612. Implicitly or explicitly, the receiver side 2614 includes a resistor 2618, a capacitor 2620, or both. Referring to the frequency response graph 2600 shown in FIGURE 26A, the frequency response of the typical isolation arrangement 2610 is attenuated as shown in dashed line 2602 due to ac-coupling of low frequency signal components, causing gain to flatten once the capacitor 2620 becomes a short-circuit in comparison to the circuit path formed by the resistor 2618. At higher frequencies, the typical arrangement 2610 can only attain a maximum gain of OdB. Depending on the parasitic capacitance of the receiver side 2614, the signal can be slightly attenuated.

[0213] Frequency response performance of the typical isolation arrangement 2610 can be insufficient to meet desired common-mode immunity frequency testing specifications unless very large capacitors are used to ensure good matching. Signals passed over the isolation barrier can include components at frequencies near the highest frequency of interest of a digital switching event. The illustrative isolation arrangement 2630 including a differentiator 2640 as shown in FIGURE 26C enables amplification of the signal passed through the isolation barrier in comparison to the typical isolation arrangement 2610. The signal is passed through the capacitor 2632 to a small signal ground 2638 and the differentiator 2640. The differentiator 2640 produces a pulse so that the isolation arrangement 2630 has a transfer function that includes amplification. At the highest frequency of interest, the isolation arrangement 2630 has substantially more gain than the typical isolation arrangement 2610 and enables the size of the capacitor 2632 to be reduced in comparison to capacitor 2612 in the typical arrangement 2610. A reduced capacitor size decreases the common mode noise by reducing the gain at lower frequencies, thus attenuating common mode movement between ground potentials on the two sides of the isolation barrier. Reducing the size of the capacitor 2632 attenuates common mode noise because the high gain is only maintained at the highest frequency of interest for the passed signal, a direct result from processing on the receiving side 2634 of the isolation barrier including differentiating. The slope can be controlled on the transmitter so that the amplitude of the passed signal coincides is relatively constant at the output terminal of the differentiator 2634. The differentiated signal is passed to the slicer 2542 and then to the recovery circuit 2644 that can be a set/reset (S/R) flip/flop in an implementation that is fully differential and balanced.

[0214] Accordingly, the illustrative isolation arrangement 2630 functions more as a communication channel than simply an isolation capacitor with the addition of gain and enhanced handling of the passed signal. The illustrative isolation arrangement 2630, overall architecture, and corresponding operating technique take a digital input signal and convert the signal to more of an analog-type signal through isolation and differentiation. Thus the isolation arrangement 2630 functions in an analogous manner to a digital-to-analog conversion then an analog-to-digital conversion, or in essence a one-bit digital to analog converter or digital-to-slope converter followed by a slope-to-digital converter. Using the isolation barrier as a communication channel enables much higher bandwidths to be attained. Common-mode noise can be addressed as an impairment to develop a higher bandwidth as defined by Shannon information transmission capacity according to Equation (1):

C=Wlog₂(S/N+l), (1) where W is channel bandwidth, S is signal power and N is noise power which is primarily a common-mode error term. Although the depicted embodiment only shows one configuration, the concept can be extended using communication theory techniques, such as trellis coding and decoding and other error correction techniques to increase channel capacity. For example, multiple-slope transmission and reception can be implemented so that a change in the slope thus changes the amplitude of the output pulse and number of bits per second that can be transmitted. [0215] Referring again to FIGURE 24, the converter 2402 can track process characteristics across the isolation barrier 2404 by modifying the amplitude of the fast differential edge modulation as a function of speed of an active device 2406 on the transmitting side 2408 of the isolation barrier 2404.

[0216] The illustrative signal interface 2400 further comprises a digital input source 2414 that supplies a digital signal to the converter 2402. A pulse slicer 2416 can be coupled to the differentiator 2410 and configured for slicing a pulse from the differentiator 2410 so that a reduced duration pulse is formed with signals below a threshold level rejected. The rejected subthreshold signals include common-mode noise between the isolated ground planes. A positive feedback recovery element 2418 receives the shortened pulse from the pulse slicer 2416 and recovers an output digital signal from the reduced duration pulse, thus generating a positive feedback signal.

[0217] The converter 2402 can be configured for converting the digital signal to the fast differential edge modulation in a transition that contains all information in the digital signal as a slope. [0218] Referring to FIGURE 27, a schematic block and circuit diagram depicts an embodiment of a converter 2700 that can be used in the interface. The illustrative converter 2700 comprises a pair of differential transistors 2702 coupled to load resistors AR₁ and configured to transmit differential signals to the isolation barrier 2704. A digital to matched differential driver 2706 can be coupled to control the differential transistor pair 2702. A process tracking circuit 2708 coupled to the differential transistor pair 2702 controls amplitude of voltage as a function of transistor speed.

[0219] The converter 2700 can be operative to convert the digital signal to the fast differential edge modulation in a transition that contains all information in the digital signal as a slope.

[0220] The converter 2700 is depicted in a simplified representation as a transmitter with differential p-channel metal oxide semiconductor (PMOS) transistor devices 2702 and functional elements to facilitate process tracking of circuits integrated on one or more dies. In some embodiments the transmitter 2700 can be integrated on a different integrated circuit die than a corresponding receiver. In other embodiments, a bidirectional implementation can have the transmitter and receiver on the same die.

[0221] The illustrative converter 2700 has the PMOS devices 2702 coupled to ground through load resistors A*Ri and power supplied to the PMOS devices 2702 that are regulated by the process tracking circuit 2708. In an illustrative example, the process tracking circuit 2708 changes voltage amplitude depending on speed of PMOS device 2710. Resistors Ri in the process tracking circuit 2708 are matched to resistors A*Rχ. Through selection of components, the edge rate of the signal is made less dependent on process and enables improved tracking on the receiver wafer. Accordingly, conversion to fast differential edge modulation involves modulation of signal amplitude dependent on the process in a manner that differs from operation of a digital interface. The converter 2700 thus operates as a digital to analog differential driver.

[0222] Referring to FIGURES 28A and 28B, a schematic circuit and block diagram and a symbolic representation depict an embodiment of a differentiator 2410, 2800 that can be used in the signal interface 2400. The converter 2402 can be configured for modifying amplitude of the fast differential edge modulation as a function of speed of an active device 2406 on a transmitting side 2408 of the isolation barrier 2404 and the differentiator 2410, 2800 configured for differentiating the passed fast differential edge modulation. The differentiator 2410, 2800 comprises an amplifier 2802 on a receiving side 2412 of the isolation barrier 2404 that tracks the active device 2406 on the isolation barrier 2404 transmitting side 2408 whereby differentiation bandwidth tracks slope rate of the differential edge modulation. [0223] The high-level block diagram of the high-speed differentiator 2800 shown in

FIGURE 28A has a current input terminal and voltage output terminal. Amplifiers AG_Mi and AG_M2 2802 form a fully differential implementation with common-mode feedback 2806 and a GM stage 2804. The GM stage 2804 includes an amplifier G_MI that tracks drivers in the transmitter across the isolation barrier, for example PMOS drivers 2702 shown in FIGURE 27, which can be integrated from the same wafer as the differentiator 2800 so that the bandwidth of differentiator 2800 tracks the slope rate of the converter or differential pulse generator, enabling improved amplitude control. Gain bandwidth, amplitude, and slope can be set by calibration of capacitors in the differentiator 2800. Capacitors can be metal-metal, metal-insulator-metal (MIM), thin metal oxide semiconductor (MOS), or any suitable capacitor type.

[0224] The illustrative differentiator 2800 also includes a feedback loop 2808 that controls the DC common-mode and differential of the output of the differentiator amplifiers 2804. The differentiator 2800 for usage in a high-speed isolator interface includes amplifiers G_Mi and G_M2 that are fast circuits. Such fast circuits generally have large offsets, and mismatches. The differentiator 2800 thus includes a slow loading stage 2808 that ensures that differential offset and common mode offset are suppressed. Gain is set by various techniques. For example, gain can be set by the ratio of the differentiator bandwidth and the output GM stage G_M2 times resistance Rl. In an implantation that omits the resistor Rl, common mode can be compensated by placing a feedback capacitor on amplifier G_M4, resulting in a slightly different gain. Various other techniques can be implemented to stabilize the differentiator 2800 depending on circuit speed, enabling control of gain amplitude. Additional input signals can otherwise be applied to control the differentiator amplifier stage and perform calibration to attain accurate amplitude from the differentiator or other type of pulse generator.

[0225] For an implementation of an interface 2400 with a capacitive isolation barrier 2404, the converter 2402 and differentiator 2410 can be configured for tracking the differentiation bandwidth and slope rate of the differential edge modulation whereby capacitor size in the isolation barrier 2404 is reduced or minimized, low frequency components in the passed fast differential edge modulation are attenuated, and common mode noise is reduced.

[0226] Referring to FIGURE 25A in combination with FIGURE 24, in some embodiments the interface 2400 can be implemented with a capacitive isolation barrier 2404 coupled between the converter 2402 and the differentiator 2410 that comprises multiple inter-level metal dielectric (IMD) capacitors 2502.

[0227] A feedback control loop 2504 can be configured to match a metal-insulator-metal (MIM) capacitor 2506 to the IMD capacitors 2502 so that differential bandwidth tracks over process variations. A recovery device 2406 coupled to the differentiator 2410 can be configured for matching a metal-insulator-metal (MIM) capacitor 2506 to the inter-level dielectric (IMD) capacitors 2502 so that differential bandwidth tracks over process variations by feedback control.

[0228] The capacitive isolation barrier 2404 can comprise a plurality of inter-level metal dielectric (IMD) capacitors 2502 formed on first and second sides of the isolation barrier from respective separate first and second integrated circuit dies from adjacent portions of a common wafer.

[0229] The inter-layer metal dielectric (IMD) capacitors 2502 are cross-coupling and matched, and are part of the isolation barrier 104. An additional isolation capacitor is included on the die but is not used a part of the isolation barrier. The IMD capacitors 2502 and the additional isolation capacitor are on the same die and thus matched. The additional isolation capacitor is coupled to multiple metal-insulator-metal (MIM) capacitors 2506 which can be configured similar to a successive approximation converter for functionality as a capacitor balancing circuit 2508. The set of MIM capacitors 2506 can be formed between two metal layers with a thinner well- controlled oxide that is typical 1-2 fF/um².

[0230] Inherently, the interlay er dielectric is not well-controlled so that gain of the differentiator would vary if capacitors were not matched. The circuit can include a dummy capacitor on each die that match, relying upon a capability to track the process of the two die wafers. One technique for ensuring process tracking is to cut the two dies from adjacent positions on a single wafer, ensuring that the capacitors track to a good degree. Thus, although a capacitor may be measured only on the receiver side, the transmitter interlayer dielectric capacitor does match the receiver side capacitor.

[0231] The MIM capacitors 2504 are formed between two thin layers of oxide and are matched. A tracking circuit 2510 can be used to perform a tracking procedure, for example a binary search or a linear search using a successive approximation converter to set capacitor amplitude, thus functioning as part of the amplifier. In some embodiments, one or more data paths and/or one or more clock signal paths can cross the isolation barrier that is integrated on the same integrated circuit die.

[0232] Other techniques can be used to control the gain of the differentiator, such as a self- calibrating loop that adjusts receiver gain during a test pattern such that the amplitude of a peak detector matches a threshold level set by a slower highly accurate comparator.

[0233] The operating technique for the illustrative interface 2400 can further comprise passing data and clock signal paths across the isolation barrier 2404 via the fast differential edge modulation and integrating the data and clock signal paths on a same integrated circuit die. [0234] Referring to FIGURE 29, a schematic block and circuit diagram illustrates an embodiment of a signal interface 2900 comprising an integrated circuit substrate 2920 and an isolation barrier 2904 formed by at least two interlayer metal dielectric capacitors 2922 that isolate a first domain 2908 from a second domain 2912 in the substrate 2920. A converter 2902 in the first domain 2908 is coupled to the isolation barrier 2904 and configured to convert a digital signal to a fast differential edge modulation that tracks process characteristics across the isolation barrier 2904 and pass the fast differential edge modulation across the isolation barrier 2904. A differentiator 2910 in the second domain 2912 is coupled to the isolation barrier 2904 and configured to differentiate the passed fast differential edge modulation to form a pulse according to a transfer function that amplifies the pulse.

[0235] The signal interface 2900 can further comprise a digital input source 2914 configured to supply a digital signal to the converter 2902. A pulse slicer 2916 coupled to the differentiator 2910 is configured for slicing the pulse from the differentiator whereby a reduced duration pulse is formed. A positive feedback recovery element 2918 coupled to the pulse slicer 2916 recovers the output information signal using positive feedback.

[0236] One or more signal paths 2930 including data paths and/or clock signal paths across the isolation barrier 2904 can be integrated on a same integrated circuit die 2934.

[0237] In some embodiments, the interface 2900 can comprise a low voltage differential signaling (LVDS) at an input/output (I/O) terminal of the integrated circuit. The differentiator can be used to pass the LVDS signals across an isolation barrier. The converter 2902 performs conversion of the digital input signal to fast differential edge modulation, controlling edge rate and creating a differential signal that is passed across the isolation barrier 2904. The signal is passed through the isolation barrier, differentiated by the differentiator 2910, typically with either first or second order differentiation, and passed to the feedback recovery circuit 2918. The output signal from the differentiator 2910 is a pulse.

[0238] High-speed communication over the isolation barrier 2904 can be facilitated by ensuring that blocks of the first 2908 and second 2912 domains track, which can be attained by ensuring process tracking of the wafers or dies upon which circuits are integrated. Other calibration techniques can be used to achieve the same result. [0239] Process characteristics are tracked across the isolation barrier 2904 by modifying the amplitude of the fast differential edge modulation as a function of speed of an active device 2906 on the transmitting side 2908 of the isolation barrier 2904. The fast differential edge modulation which is passed through the isolation barrier 2904 can be differentiated using an amplifier 2936 on the receiving side 2908 of the isolation barrier 2904 that tracks the active device 2906 on the isolation barrier transmitting side 2912 so that differentiation bandwidth tracks slope rate of the differential edge modulation.

[0240] The fast differential edge modulation can be passed through a capacitive isolation barrier 2904 and the differentiation bandwidth and slope rate of the differential edge modulation can be tracked so that capacitor size in the isolation barrier is reduced or minimized, low frequency components in the passed fast differential edge modulation are attenuated, and common mode noise is reduced. By varying the slope, the output amplitude can be modulated so that two bits can be transmitted across the barrier using two-bit pulse-amplitude modulation (PAM-4) signaling. Modulation can be adjusted to many more levels and with more complexity additional I and Q channels can be created further expanding channel capacity.

[0241] Referring to FIGURE 3OA through 3OC, multiple flow charts illustrate one or more embodiments or aspects of a method 3000 for transmitting a signal through an isolation barrier. A digital signal is converted 3002 to a fast differential edge modulation and the fast differential edge modulation passed 3004 through a capacitive isolation barrier. The passed fast differential edge modulation is differentiated 3006 to form the pulse according to a transfer function that amplifies the pulse whereby capacitor size in the isolation barrier is reduced or minimized.

[0242] Referring to FIGURE 3OB, a method 3010 can further comprise tracking 3012 process characteristics across the capacitive isolation barrier, for example by modifying 3014 the amplitude of the fast differential edge modulation as a function of speed of an active device on a transmitting side of the capacitive isolation barrier.

[0243] Referring to FIGURE 3OC, a method 3020 can further comprise tracking 3022 process characteristics across the capacitive isolation barrier, for example by modifying 3024 the amplitude of the fast differential edge modulation as a function of speed of an active device on the transmitting side of the capacitive isolation barrier and differentiating 3026 the passed fast differential edge modulation using an amplifier on the receiving side of the capacitive isolation barrier that tracks the active device on the capacitive isolation barrier transmitting side whereby differentiation bandwidth tracks slope rate of the differential edge modulation.

[0244] In some embodiments, the method 3020 can further comprise tracking 3028 the differentiation bandwidth and slope rate of the differential edge modulation whereby capacitor size in the capacitive isolation barrier is reduced or minimized, low frequency components in the passed fast differential edge modulation are attenuated, and common mode noise is reduced.

[0245] Referring to FIGURES 31A through 31D, a set of flow charts illustrates embodiments and aspects of various embodiments of a method for constructing a signal isolator. FIGURE 31A shows an embodiment of a method 3100 that comprises forming 3102 first and second separate dies from a common wafer and separating 3104 the first and second dies by an isolation barrier. A converter is formed 3106 on the first die that is configured to convert a digital signal to a fast differential edge modulation that tracks process characteristics across the isolation barrier. A differentiator is formed 3108 on the second die in a configuration that differentiates the fast differential edge modulation to form a pulse according to a transfer function that amplifies the pulse.

[0246] Referring to FIGURE 31B, an embodiment of a method 3110 can further comprise configuring 3112 the converter to control edge rate and amplitude of the fast differential edge modulation to characterize information in the digital signal. In some embodiments, the converter can be configured 3114 to convert the digital signal to the fast differential edge modulation in a transition that contains all information in the digital signal as a slope. The differentiator can be configured 3116 to differentiate a fast differential edge modulation passed through the isolation barrier to form the pulse according to a transfer function that amplifies the pulse whereby capacitor size in the isolation barrier is reduced or minimized.

[0247] For example, the converter and the differentiator can be configured to track process characteristics across the isolation barrier by modifying amplitude of the fast differential edge modulation as a function of speed of an active device on a transmitting side of the isolation barrier and differentiating the passed fast differential edge modulation using an amplifier on the receiving side of the isolation barrier that tracks the active device on the isolation barrier transmitting side whereby differentiation bandwidth tracks slope rate of the differential edge modulation.

[0248] Referring to FIGURE 31C, an embodiment of a method 3120 for constructing an interface can further comprise configuring 3122 the isolation barrier as a capacitive isolation barrier which is adapted to pass the fast differential edge modulation through. The converter and the differentiator can be configured 3124 to track the differentiation bandwidth and slope rate of the differential edge modulation whereby capacitor size in the isolation barrier is reduced or minimized, low frequency components in the passed fast differential edge modulation are attenuated, and common mode noise is reduced.

[0249] In some embodiments, the isolation barrier can be configured 3122 by forming 3126 a plurality of inter-level metal dielectric capacitors on first and second sides of the isolation barrier from respective separate first and second integrated circuit dies from adjacent portions of a common wafer.

[0250] Referring to FIGURE 31D, an embodiment of a method 3130 for constructing an interface can further comprise integrating 3132 data and clock signal paths on a same integrated circuit die and configuring 3134 the data and clock signal paths for passage across the isolation barrier via the fast differential edge modulation.

[0251] Referring to FIGURES 32A through 32E, multiple flow charts illustrate one or more embodiments or aspects of a method 3200 for constructing a semiconductor device. As shown in FIGURE 32A, an illustrative method 3200 comprises forming 3202 multiple interleaved inter- metal dielectric layers and interlayer dielectrics on a substrate, forming 3204 a thick passivation layer on the multiple interleaved inter-metal dielectric layers and interlayer dielectrics, and forming 3206 a thick metal layer on the thick passivation layer. An integrated circuit is formed 3208 on the substrate which includes a signal interface with one or more isolator capacitors. The isolator capacitors are formed 3210 comprising the thick passivation layer as an insulator whereby thickness of the thick passivation layer is selected greater than thickness sufficient for isolation so that testing for defects is eliminated. Thickness of the thick passivation layer also reduces parasitic capacitance.

[0252] For example, the multiple interleaved inter-metal dielectric layers and interlayer dielectrics can be formed 3202 by distributing the metal layers within silicate glass dielectric layers, separated by thin silicon nitride layers and overlying inter-layer dielectric layers. The thick passivation layer can be formed 3204 as an undoped silicate glass (USG) layer. The thick metal layer can be formed 3206 as a redistribution layer (RDL).

[0253] The isolator capacitor or capacitors can be formed 3210, for example, with the thick passivation layer used as an insulator whereby thickness of the passivation layer is selected 3212 to reduce parasitic capacitance and improve high-speed operation of the interface. In another example implementation, the thickness of the passivation layer can be selected to reduce capacitor size of the one or more isolator capacitors.

[0254] In an example arrangement, the substrate, the multiple interleaved inter-metal dielectric layers and interlayer dielectrics layers, the thick passivation layer, and the thick metal layer can be formed by standard processing techniques. However, performance can be improved by forming the thick passivation layer with thickness selected to be larger than for standard processing so that oxide defects are reduced.

[0255] In some embodiments, an isolator capacitor can be formed 3210 with the thick metal layer functional as a first plate and a predetermined metal layer in the interleaved inter-metal dielectric layer and interlayer dielectric plurality functional as a second plate. The first and second plates are separated by the thick passivation layer. The first plate and the second plate can be arranged as substantially parallel planes extending laterally with an overlap selected to compensate for dielectric leakage and fringe fields from creating voltage gradients. [0256] The first and second plates can be formed with rounded or oblique angles so that electric fields and/or voltage gradients are reduced or minimized.

[0257] Referring to FIGURE 32B, an embodiment of a method 3220 for constructing a semiconductor device can comprise forming 3222 the thick metal layer as a redistribution layer (RDL) and forming 3224 a metal via beneath the RDL. One or more metal layers in the interleaved inter-metal dielectric layers and interlayer dielectrics can be formed 3226 underlying the metal via and extending laterally so that lateral extension of the metal via overlaps the predetermined metal layer.

[0258] One or more metal layers can be formed in selected layer or layers of the interleaved inter-metal dielectric layers and interlayer dielectrics in positions underlying a metal via and extending laterally so that lateral extension of the metal via overlaps the predetermined metal layer.

[0259] In some embodiments, at least one metal via can be formed to prevent deposition of materials with unfavorable breakdown voltages. [0260] Referring to FIGURE 32C, an embodiment of a method 3230 for fabricating a semiconductor device can comprise dividing 3232 the integrated circuit into at least two dies and arranging 3234 the dies across an isolation barrier so that capacitors respectively formed on separate dies are configured with a reduced ratio of parasitic capacitance to primary capacitance. In addition, the adjacent dies from the integrated circuit can be arranged 3236 across an isolation barrier so that capacitors are matched.

[0261] In some embodiments, parts of capacitors can be formed on different dies, taken from the same wafer. The different dies are combined into a package with the parts of the capacitors arranged to form complete capacitors with matched characteristics.

[0262] Referring to FIGURE 32D, an embodiment of a method 3240 for constructing a semiconductor device comprises dividing 3242 the integrated circuit into first and second dies, forming 3244 an isolation barrier between the first and second dies, and forming 3246 multiple capacitors respectively on separate dies. A converter can be configured 3248 in the first die to track process characteristics across the isolation barrier and modify amplitude of a fast differential edge modulation as a function of speed of an active device on a transmitting side of the isolation barrier. A differentiator in the second die can be configured 3250 to differentiate the fast differential edge modulation on a receiving side of the isolation barrier whereby differentiation bandwidth tracks slope rate of the differential edge modulation.

[0263] The differentiator can be configured to include a calibrated capacitor that matches the multiple capacitors on the separate dies. [0264] In some embodiments, the method 3240 can further comprise forming 3244 a capacitive isolation barrier between the converter and the differentiator for passing the fast differential edge modulation. The converter and differentiator can be configured 3252 for tracking the differentiation bandwidth and slope rate of the differential edge modulation so that capacitor size in the isolation barrier is reduced or minimized, low frequency components in the passed fast differential edge modulation are attenuated, and common mode noise is reduced.

[0265] Referring to FIGURE 32E, an embodiment of a method 3260 for constructing a semiconductor device can further comprise forming 3262 a capacitive isolation barrier between the converter and the differentiator comprising a plurality of inter-level metal dielectric capacitors. A feedback control loop can be configured 3264 to balance the plurality of inter-level metal dielectric capacitors.

[0266] The capacitive isolation barrier can be formed 3262 by forming 3266 multiple inter- level metal dielectric capacitors on first and second sides of the isolation barrier from respective separate first and second integrated circuit dies from adjacent portions of a common wafer.

[0267] FIGURE 33 is a schematic circuit diagram showing an embodiment of a signal isolator 3300 that implements process tracking enabling high-speed performance for the differentiator 3340, thereby facilitating high-speed performance of the isolator interface 3300. The differentiator 3340 has a current input signal and voltage output signal. The voltage output signal from the differentiator 3340 is passed to slicers 3342 that have a reference voltage and operate upon the differential output. Slicers 3342 operate according to a threshold which is set either through use of a peak detector, through calibration, or other suitable threshold technique. Process tracking enables predetermination of the amplitude of the signal passed from the slicers 3342 to the recovery element 3326. In some embodiments, the threshold can be set using a peak detector for adjusting the slicers 3342, at the expense of detriment to margin operation. In other embodiments, the threshold can be set without harm to margin operation, by implementing the transmitter 3310 as is illustrated and described with respect to FIGURE 26 and by implementing the differentiator 3340 as is illustrated and described with respect to FIGURES 27A and 27B.

[0268] The signal isolator 3300 functions essentially as a digital-to-analog converter followed by an analog-to-digital converter (D/A -> AfD) due to operation of the slicer 3342, which functions almost like a digital communication channel but communicates information using analog techniques that are reliant on process matching. [0269] In the illustrative example, capacitors 3306 and associated bond wires are placed in a physical configuration whereby the differential current flow in the loops 3312 are in balance to the first order and generate magnetic fields that cancel, creating a magnetic dipole with greatly reduced far-fields. The same principle also enables the device to reject magnetic interference so that the circuit attains a magnetically differential characteristic. [0270] In the illustrative example, capacitors 3306 and associated bond wires are placed in a physical configuration whereby the differential current flow in the loops 3312 is in balance to the first order and generates magnetic fields that cancel, creating a magnetic dipole with greatly reduced far-fields. The same principle also enables the device to reject magnetic interference so that the circuit attains a magnetically differential characteristic.

[0271] In various embodiments, the isolation barrier 3304 can be configured in any suitable arrangement such as two or more interlay er metal dielectric capacitors 3316A formed in the first domain 3308A and two or more interlayer metal dielectric capacitors 3316B formed in the second domain 3308B. In another arrangement, the two or more interlayer metal dielectric capacitors 3306 can be formed partly in the first domain 3308A and partly in the second domain 3308B.

Also, the two or more interlayer metal dielectric capacitors 3306 can be formed between the first 3308A and second 3308B domains. Furthermore, the interlayer metal dielectric capacitors 3306 can be formed partly in the first domain 3308A, partly in the second domain 3308B, and partly between the first and second domains. The differentiator 3340 separates a common-mode to differential component from true differential components. Common mode suppression element 3332 can be used to maintain the differentiator 3340 is linear range.

[0272] The differentiator 3340 is shown with resistive feedback and connected to the common mode control element 3332. In some embodiments, the common mode control element 3332 can be omitted through usage of common mode techniques in configuring the differentiator. As long as common mode feedback is maintained, low impedance input is inherent, enabling elimination of the common mode control element 3332. Other designs can include multiple differentiators coupled in series to form a low impedance input condition to the receiving side of the isolation barrier. Accordingly, several techniques can be used to implement a differentiator that forms a low impedance input condition which is desirable for usage with capacitors, as opposed to inductors.

[0273] The differentiator 3340 is shown with resistive feedback and connected to the common mode control element 3332. In some embodiments, the common mode control element 3332 can be omitted through usage of common mode techniques in configuring the differentiator. As long as common mode feedback is maintained, low impedance input is inherent, enabling elimination of the common mode control element 3332. Other designs can include multiple differentiators coupled in series to form a low impedance input condition to the receiving side of the isolation barrier. Accordingly, several techniques can be used to implement a differentiator that forms a low impedance input condition which is desirable for usage with capacitors, as opposed to inductors. [0274] In some embodiments, the differentiator 3340 can be configured as a current mode differentiator. In various implementations, modulation can be implemented in a variety of different ways, including but not limited to pulse width modulation (PWM), delta modulation (DM), frequency modulation (FM), phase modulation, and others. [0275] Referring to FIGURE 34A, a schematic block diagram illustrates an embodiment of a signal isolator 3400 that implements channel management. The signal isolator 3400 comprises an isolation barrier 3404 that isolates first 3408A and second 3408B domains and one or more fully differential transmitters 3410 in the first domain 3408A which are configured to transmit a digital signal containing all information in an information signal in an edge of a single transition across the isolation barrier 3404 to the second domain 3408B. The signal isolator 3400 further comprises one or more fully differential receiver 3412 in the second domain 3408B which are configured to receive and differentiate the transmitted digital signal.

[0276] In some implementations, the illustrative slicer can be used to set a threshold base either through process tracking or by usage of a peak detector that monitors signal amplitude. A peak detector can be omitted by using a management channel to set signal amplitude. Referring to FIGURES 34B and 34C, schematic block and circuit diagrams illustrate an embodiment of an isolator interface 3400 that implements a management channel that can operate continuously to set amplitude.

[0277] The signal isolator 3400 including a management channel has an oscillator 3414 driving a transmitter 3410. A receiver 3412 receives signals from the transmitter 3410 from across the isolation barrier 3404, and passes the signals to a differentiator 3416 then to a slicer 3420 and latch 3422. The differentiator 3416 can operate continuously and feed a differentiated signal to a peak detector 3424 that determines peak amplitude that can be used to set the threshold of the slicer 3420 in the main channel, and determine the voltage and divide the voltage down by two. The management channel approach can be used in some implementations as an alternative to setting amplitude to a particular reference by setting amplitude using a peak detector and relying on process tracking to ensure that the amplitude has sufficient margin.

[0278] In contrast to the isolator 3400, the implementation of the signal isolator 340 shown in FIGURE 23 can avoid the cost and complexity of a second isolator channel and logic to set slicer threshold by using the differentiator 2310 on the receiving side 2312 of the isolation barrier 2304 to track the active device 2306 on the transmitter 2302 so that differentiation bandwidth tracks slope rate of the differential edge modulation, thereby enabling reduction in the size of the capacitor or capacitors in the isolation barrier 2304 and facilitating attenuation of low frequency. The signal isolator 2300 exploits the spectral separation of common mode noise that results from the differential passage of the signal across the isolation barrier 2304 so that gain is added to the circuit while reducing the size of the capacitors.

[0279] The depicted signal isolator 3400 comprises an isolation barrier 3404 that isolates first 3408A and second 3408B domains and one or more fully differential transmitters 3410 in the first domain 3408A which are configured to transmit a digital signal containing all information in an information signal in an edge of a single transition across the isolation barrier 3404 to the second domain 3408B. The signal isolator 3400 further comprises one or more fully differential receiver 3412 in the second domain 3408B which are configured to receive and differentiate the transmitted digital signal. [0280] In a particular embodiment, the signal isolator 3400 can comprise an isolation barrier 3404, and first 3408A and second 3408B separate dies from a common wafer. The signal isolator 3400 can comprise a transmitter 3410 on the first die 3408A and a receiver 3412 on the second die 3408B in a configuration that communicates an information signal across the isolation barrier 3404 as a digital signal that contains all information in a single transition edge. The signal isolator 3400 can further comprise oscillators 3414 on the first 3408A and second 3408B dies that are to be matched to a reasonable tolerance due to close location of the dies on the integrated circuit wafer.

[0281] The illustrative signal isolator 3400 implements a management channel concept and includes a structure with two or more channels, each of which has a transmitter 3410 and receiver 3412 positioned across the isolation boundary 3404 with the multiple channels positioned side-by- side to enable comparison of timing or frequency signals. The two or more channels are positioned side-by-side to maintain state if the state is corrupted for some reason or condition. The multiple channels enable state to be maintained when clock signals are corrupted. Maintenance of the channels is useful in the illustrative edge-based system because corruption that results in termination of edge transitions could possibly enter state that cannot be restored. Corruption can occur during operation of the system or during power-up. The illustrative signal isolator 3400 can include a power-on reset (POR) element 3430 that functions in combination with the state machine 3432 and fail-safe control logic 3418. For example, initially upon system power-up no edge transitions may be generated. Control logic in the signal isolator 3400, including the POR function element 3430 and failsafe logic control 3418, ensures that the correct system state can be determined.

[0282] Referring to FIGURE 34C, a schematic block diagram illustrates an example embodiment or implementation of management control structures on the second die 3408B. The signal isolator 3400 can further comprise a state machine 3432 coupled to the receiver 3412 on the second die 3408B and a failsafe logic 3418 coupled to the state machine 3432 on the second die. The state machine 3432 and the failsafe logic 3418 can be configured to determine frequency of a signal transmitted across the isolation barrier 3404, compare frequency of a local oscillator signal to the frequency of the transmitted signal, and correct transmitted state based on the comparison. [0283] Referring to FIGURE 34D in combination with FIGURE 34B, a set of time waveforms depicts digital signals at several locations in the digital isolator 3400 including a signal A generated by the oscillator 3414 on the first die 3408A, a signal B that results from passage of the signal from the oscillator through a divider, and a signal C passed by the receiver 3412 on the second die 3408B that receives a signal transmitted across the isolation barrier 3404. Signal A' is generated by the oscillator 3414 on the second die 3408B. The time waveforms illustrate usage of a second isolator channel to ensure fail-safe operation. Dotted lines for signal A depict clock frequency variation, for example ±44%, due to process variability. In an example implementation, the variation in clock frequency from die-to-die can be limited to a suitable amount, for example ±5% by using two dies from the same wafer with additional improvement attained by using dies that are adjacent from the same wafer.

[0284] The separate dies can be constructed from the same wafer, or from adjacent locations on the same wafer, so that the constructed package has circuit dies that are mirror images of one another with one die implementing a transmitter and the other die implementing a receiver, and each die implementing an oscillator. The mirror images ensure relative matching of clock signals. [0285] Signals B(I) and B(O), and signals C(I) and C(O) depict signals at common positions in different channels. Signals B(I) and B(O) are transmitted from the output terminal of the divider on first die 3408A based on whether the transmitted data bit is either a one or a zero. Signals C(I) and C(O) depict signals recovered on second die 3408B that can then be compared in the state-machine which use the oscillator 3414 on die 3408B to measure the frequency of the transmitted data. Transmission is much slower than the normal path but can be used to ensure that the receive data is correct should the data be incorrect and enable failsafe startup operation by ensuring that output data remains fixed until both dies 3408A and 3408B are powered and operational.

[0286] Referring to FIGURE 34E in combination with the structures shown in FIGURES 34B and 34C, a state diagram 3450 illustrates an embodiment of operation of the state machine 3432 and failsafe logic 3418 for managing channels in the signal isolator 3400. Also referring to FIGURE 34F in combination with FIGURES 34B and 34C, a set of time waveforms depicts digital signals at several locations in the digital isolator 3400 including a power-on-reset (POR) signal, the signal C which is passed by the receiver 3412 on the second die 3408B that receives a signal transmitted across the isolation barrier 3404, and signals S and R that are passed from the receiver 3412 to the failsafe logic 3418. Waveforms further include a signal E that passes as control from the state machine 3432 to the failsafe logic 3418, and an output signal O.

[0287] A first data bit is delayed until power-up of side 1 is verified. The control logic ensures that the digital isolator 3400 changes state due to power-up transients. Delay time is variable for a particular implementation although a common range can be 0.32-1.44 μsec.

[0288] The illustrative channel management technique has two aspects including usage of two separate dies for the respective transmitter and receiver channels with oscillators on each die, and a control logic to ensure the correct state on power-up. The two side-by-side channels include one channel enabling high-speed operation to the main channel so that no modulation technique is implemented except for the edge transition. The second channel is a maintenance or management channel to ensure that a state that becomes corrupted for any reason which results in no edge transmission will be corrected.

[0289] The state diagram 3450 can be configured to initially avoid transition based on any type of noise, for example by controlling a secondary channel, which can be a management channel, to initially ignore changes on the primary channel but only respond to changes in the secondary channel. In operation subsequent to initialization, the secondary channel can respond to changes in the primary channel.

[0290] The oscillators are located on both sides of the package, in each of the separate dies, and are presumed to be well-matched to a selected tolerance such as ±5%. Digital frequency measuring can be used to measure the frequency transmit state, as shown in waveform C in FIGURE 34F, so that when a logical 1 is transmitted the waveform frequency is higher, and when transmitting a logic 0 the frequency is lower, for example by approximately half. Accordingly, the logic signal is communicated as a shift in frequency.

[0291] On the second die, the receiver 3412 receives transmitted information and passes the information to the state machine 3432 that uses the local oscillator 3414 to detect frequency local to the second die. Because the timing components on the two dies are taken from the same wafer and have suitable relative matching, the transmitted timing signals and timing signals generated locally to the second die can be compared, enabling detection of the transmission state for parallel channel management. [0292] The state diagram 3450 shows operation wherein a departure from normal operation detectable as a state on the second die that does not match the transmitted state through the management channel that endures for a selected time, for example a microsecond or several microseconds, activates correction of the state. The corrupted state from any cause, for example an alpha particle or other noise, can be detected and corrected on the second side. The management channel ensures that the state is corrected.

[0293] In the illustrative embodiment, the power-on-reset (POR) element 3430, the failsafe logic 3418 and the state machine 3432 operate in combination to control the management channel interaction in normal operation without impacting high-speed operation. If an error condition causes a mismatch in the transmitted and local timing signals on the second side that is maintained for a particular number of time periods, for example five time periods as shown, the control logic will correct the state. The frequency handling in shown in FIGURE 34F at line C with the frequency changing from a higher frequency to a lower frequency. [0294] Referring to FIGURE 35A with regard to the structures shown in FIGURES 34A and 34B, a flow chart illustrates an embodiment of a method 3500 for constructing a signal isolator. The method 3500 comprises forming 3502 first and second separate dies from a common wafer. A transmitter is formed 3504 on the first die and a receiver formed 3506 on the second die in a configuration that communicates an information signal across an isolation barrier as a digital signal that contains all information in a single transition edge. Oscillators are formed 3508 that are matched to a selected tolerance on the first and second dies.

[0295] In some embodiments, the first and second separate dies can be formed 3502 from adjacent positions on the common wafer, enabling a reduction in clock frequency variation between the two dies. The transmitter and the receiver can be formed with matching on the first and second dies whereby communication correctness is ensured. The oscillators can be configured to communicate information across the isolation barrier by frequency modulation.

[0296] Referring to FIGURE 35B, a flow chart illustrates an embodiment of a method 3510 for constructing a signal isolator that further comprises forming 3512 two or more transmitter- receiver channels in the first and second separate dies enabling comparison of communication signals between channels and correction of corrupted edge transmission.

[0297] Referring to FIGURE 36 with regard to the structures shown in FIGURES 6A and

6B, a flow chart illustrates an embodiment of a method 3600 for operating a signal isolator. First and second separate dies are provided 3602 from a common wafer comprising a transmitter on the first die and a receiver on the second die in a configuration that communicates an information signal across an isolation barrier as a digital signal that contains all information in a single transition edge, and oscillators that are matched to a selected tolerance on the first and second dies. The method 3600 further comprises determining 3604 frequency of a signal transmitted across the isolation barrier and comparing 3606 frequency of a local oscillator signal to the frequency of the transmitted signal. Transmitted state is corrected 3608 based on the comparison. [0298] Referring to FIGURES 37A through 37C, a set of flow charts illustrates embodiments and aspects of various embodiments of a method for communicating an information signal across an isolation barrier. FIGURE 37A shows an embodiment of a method 3700 for transmitting an information signal from a first side to a second side of an isolation barrier comprising receiving 3702 the information signal at the first side and forming 3704 a differential signal from the information signal as a transition that contains all information in a single transition edge. The differential signal is passes 3706 to the second side of the isolation barrier and differentiated 3708. An output information signal is recovered 3710 on the second side of the isolation barrier based on the information in the single transition edge. [0299] In some embodiments, the output information signal can be recovered 3710 on the second side of the isolation barrier using positive feedback. In various embodiments, the differential signal can be passed through any suitable isolation barrier, for example the differential signal can be passes across a capacitive isolation barrier, an inductive isolation barrier, or other barrier. In some embodiments, the passed signal can be differentiated 3708 so that a common- mode-to-differential component is separated from true differential components.

[0300] In one implementation, the passed signal can be differentiated 3708 in a single stage with differentiation maintained in a linear range by common mode suppression. In another implementation, the passed signal can be differentiated in multiple stages so that linear differentiation is maintained without common mode suppression.

[0301] FIGURE 37B shows an embodiment of a method 3720 for transmitting an information signal from a first side to a second side of an isolation barrier that comprises receiving 3722 a logic signal with first and second transition edges that shift the logic signal between two states and communicating 3724 a differential signal across an isolation barrier that contains all information in the logic signals in a single transition edge. The communicated differential signal is differentiated 3726 and a signal indicative of the first and second transition edges from the differentiated signal is recovered 3728. The differential signal can be communicated 3724 across the isolation barrier on a fully differential pathway.

[0302] FIGURE 37C illustrates another embodiment of a method 3730 for transmitting a signal from a transmitting circuit across an isolation barrier to a receiving circuit comprising converting 3732 an information signal to a digital signal that contains all information in the information signal in a single transition edge and passing 3734 the digital signal across the isolation barrier. The passed digital signal is differentiated 3736 and an output information signal is recovered 3738 from the differentiated digital signal based on the information in the single transition edge, for example using positive feedback.

[0303] Referring to FIGURE 38, a schematic circuit diagram illustrates an embodiment of a high-speed differentiator 3800 that can be implemented in a digital signal isolator. [0304] Referring to FIGURE 39A, a schematic block and circuit diagram shows an implementation of blocking on an isolated interface 3900 in a low voltage differential signaling (LVDS) system. LVDS is a differential signaling system that transmits two differential voltages for comparison at a receiver, using the difference between the voltages to encode information.

[0305] Blocking on the high-speed interface that isolates VDDl and VDD2 is implemented to meet high-frequency specifications of LVDS, and serial gigabit media independent interface (SGMII) depicted in FIGURE 39B. LVDS has a differential drive capability, as indicated with the plus and minus DATA IN lines on the VDD2 side of the isolation barrier 3902. On one side of the LVDS isolated interface 3900 are power VDDl and ground GNDl and differential DATA OUT lines. On the opposing side of the LVDS interface 3900 are power VDD2, ground GND2, differential DATA IN lines and a clock signal.

[0306] FIGURE 39B is a schematic block and circuit diagram showing an implementing of blocking on an isolated interface 3950 in a serial gigabit media independent interface (SGMII) system. SGMII 3950 is an interface used to connect an Ethernet media access control (MAC) 3952 to a PHY 3962 in an Ethernet gigabit application. An isolation barrier 3954 at the SGMII 3950 isolates management data input/output (MDIO) 3956 and a management data clock (MDC) pin 3958. MDIO 3956 is an Ethernet protocol bus structure that connects MAC devices with PHY devices and enables a user to change configuration information during operation and to read PHY status information. SGMII 3950 can be implemented to support both data and a clock signals including DATA IN and DATA OUT pins, and a CLOCK OUT pin, in combination with support of sufficiently exact timing to support the high-speed functionality of the interface. In an example implementation, the timing specifications can be satisfied by integrating clock and data paths onto the same die. Some configurations can include two data input pins integrated into the same die in an isolator package to further facilitate timing performance. In the illustrative high-speed interface, skew and jitter specifications can be attained by integrating the clock and data paths on the same die and balancing the pathways. The interface supports clock and data input signals through the isolation barrier 3954 to clock and data output signals, and thus produces data in and data out with isolation of data and clock signals. [0307] The SGMII isolator 3950 includes a transmission stream with data flowing to a receiver with signals SGIN and SGOUT passing through the isolation barrier 3954 which can be capacitive or other isolation. To facilitate performance according to specifications for high-speed operation, both sides of the isolation barrier 3954 can be fabricated on the same die. Communication between the PHY 3962 and the MAC 3952 goes through the SGMII 3950 which forms the isolation barrier 3954 to that PHY 3962.

[0308] The SGMII isolator 3950 can be implemented with the MDIO 3956 and MDC 3958 and thus can be formed without differential in and differential out pins. The MDIO 3956 can form a differential interface to the PHY 3962. In other configurations, the SGMII isolator 3950 can be implemented with differential input and differential output lines.

[0309] The balancing and matching of signal pathways is most feasible by integration of the isolator 3900, 3950 since usage of an external capacitor creates mismatches and/or is physically too large for suitable implementation.

[0310] The illustrative isolator embodiments enable support of LDVS and SGMII signaling through a high-speed isolator at speeds that have heretofore made such isolation impossible.

[0311] The isolators 3900 and 3950 can be constructed as matched dies separated by an isolation barrier of any suitable type, for example a capacitor, an inductor, or other isolation element. Matching of the dies can be attained by fabricating the dies on the same process, thereby enabling both balancing and matching of the dies. [0312] Referring to FIGURES 4OA, 4OB, and 4OC, a set of time waveforms illustrate aspects of operation of a first differentiator output signal. FIGURE 4OA shows an example of a data output signal and the portion of the signal that results from common -mode noise. The data output signal shows output voltage of the first differentiator output terminal, illustratively showing a 50kV/μsec test at true ground. A single pulse is generated for the normal differential which is overlaid by the response to a normal fast transmission edge out of the first differentiator, which is a pulse. The common-mode noise signal results from capacitive mismatch, for example of about the order of one percent, and leads to some differential signal but is rejected by the differentiator and does not produce a large output pulse so the differentiator.

[0313] FIGURE 4OB shows results of a 50kV/μsec slew test and indicates how two grounds can move apart. FIGURE 4OC illustrates differential input drive as the normal differential edge that does the transmission. The differential pulse produces a large output signal whereas the common-mode implementation leads to differential pulse due to capacitor mismatch, but with a much slower edge leading to a smaller pulse amplitude. [0314] The IEEE 802.3 Ethernet Standard, which is incorporated herein by reference, addresses loop powering of remote Ethernet devices (802.3af). Power over Ethernet (PoE) standard and other similar standards support standardization of power delivery over Ethernet network cables to power remote client devices through the network connection. The side of link that supplies power is called Powered Supply Equipment (PSE). The side of link that receives power is the Powered device (PD). Other implementations may supply power to network attached devices over alternative networks such as, for example, Home Phoneline Networking alliance (HomePNA) local area networks and other similar networks. HomePNA uses existing telephone wires to share a single network connection within a home or building. In other examples, devices may support communication of network data signals over power lines.

[0315] In various configurations described herein, a magnetic transformer of conventional systems may be eliminated while transformer functionality is maintained. Techniques enabling replacement of the transformer may be implemented in the form of integrated circuits (ICs) or discrete components. [0316] FIGURE IA is a schematic block diagram that illustrates a high level example embodiment of devices in which power is supplied separately to network attached client devices 112 through 116 that may benefit from receiving power and data via the network connection. The devices are serviced by a local area network (LAN) switch 110 for data. Individual client devices 112 through 116 have separate power connections 118 to electrical outlets 120. FIGURE IB is a schematic block diagram that depicts a high level example embodiment of devices wherein a switch 110 is a power supply equipment (PSE)-capable power-over Ethernet (PoE) enabled LAN switch that supplies both data and power signals to client devices 112 through 116. Network attached devices may include a Voice Over Internet Protocol (VOIP) telephone 112, access points, routers, gateways 114 and/or security cameras 116, as well as other known network appliances. Network supplied power enables client devices 112 through 116 to eliminate power connections 118 to electrical outlets 120 as shown in FIGURE IA. Eliminating the second connection enables the network attached device to have greater reliability when attached to the network with reduced cost and facilitated deployment. [0317] Although the description herein may focus and describe a system and method for coupling high bandwidth data signals and power distribution between the integrated circuit and cable that uses transformer-less ICs with particular detail to the IEEE 802.3af Ethernet standard, the concepts may be applied in non-Ethernet applications and non-IEEE 802.3af applications. Also, the concepts may be applied in subsequent standards that supersede or complement the IEEE 802.3af standard. [0318] Various embodiments of the depicted system may support solid state, and thus nonmagnetic, transformer circuits operable to couple high bandwidth data signals and power signals with new mixed-signal IC technology, enabling elimination of cumbersome, real-estate intensive magnetic-based transformers. [0319] Typical conventional communication systems use transformers to perform common mode signal blocking, 1500 volt isolation, and AC coupling of a differential signature as well as residual lightning or electromagnetic shock protection. The functions are replaced by a solid state or other similar circuits in accordance with embodiments of circuits and systems described herein whereby the circuit may couple directly to the line and provide high differential impedance and low common mode impedance. High differential impedance enables separation of the physical layer (PHY) signal from the power signal. Low common mode impedance enables elimination of a choke, allowing power to be tapped from the line. The local ground plane may float to eliminate a requirement for 1500 volt isolation. Additionally, through a combination of circuit techniques and lightning protection circuitry, voltage spike or lightning protection can be supplied to the network attached device, eliminating another function performed by transformers in traditional systems or arrangements. The disclosed technology may be applied anywhere transformers are used and is not limited to Ethernet applications.

[0320] Specific embodiments of the circuits and systems disclosed herein may be applied to various powered network attached devices or Ethernet network appliances. Such appliances include, but are not limited to VoIP telephones, routers, printers, and other similar devices.

[0321] Referring to FIGURE 2, a functional block diagram depicts an embodiment of a network device 200 including a T-Less Connect™ solid-state transformer. The illustrative network device comprises a power potential rectifier 202 adapted to conductively couple a network connector 232 to an integrated circuit 270, 272 that rectifies and passes a power signal and data signal received from the network connector 232. The power potential rectifier 202 regulates a received power and/or data signal to ensure proper signal polarity is applied to the integrated circuit 270, 272.

[0322] The network device 200 is shown with the power sourcing switch 270 sourcing power through lines 1 and 2 of the network connector 232 in combination with lines 3 and 6. [0323] In some embodiments, the power potential rectifier 202 is configured to couple directly to lines of the network connector 232 and regulate the power signal whereby the power potential rectifier 202 passes the data signal with substantially no degradation.

[0324] In some configuration embodiments, the network connector 232 receives multiple twisted pair conductors 204, for example twisted 22-26 gauge wire. Any one of a subset of the twisted pair conductors 204 can forward bias to deliver current and the power potential rectifier 202 can forward bias a return current path via a remaining conductor of the subset.

[0325] FIGURE 2 illustrates the network interface 200 including a network powered device (PD) interface and a network power supply equipment (PSE) interface, each implementing a non-magnetic transformer and choke circuitry. A powered end station 272 is a network interface that includes a network connector 232, non-magnetic transformer and choke power feed circuitry 262, a network physical layer 236, and a power converter 238. Functionality of a magnetic transformer is replaced by circuitry 262. In the context of an Ethernet network interface, network connector 232 may be a RJ45 connector that is operable to receive multiple twisted wire pairs. Protection and conditioning circuitry may be located between network connector 232 and non-magnetic transformer and choke power feed circuitry 262 to attain surge protection in the form of voltage spike protection, lighting protection, external shock protection or other similar active functions. Conditioning circuitry may be a diode bridge or other rectifying component or device. A bridge or rectifier may couple to individual conductive lines 1-8 contained within the RJ45 connector. The circuits may be discrete components or an integrated circuit within non-magnetic transformer and choke power feed circuitry 262.

[0326] In an Ethernet application, the IEEE 802.3af standard (PoE standard) enables delivery of power over Ethernet cables to remotely power devices. The portion of the connection that receives the power may be referred to as the powered device (PD). The side of the link that supplies power is called the power sourcing equipment (PSE).

[0327] In the powered end station 272, conductors 1 through 8 of the network connector 232 couple to non-magnetic transformer and choke power feed circuitry 262. Non-magnetic transformer and choke power feed circuitry 262 may use the power feed circuit and separate the data signal portion from the power signal portion. The data signal portion may then be passed to the network physical layer (PHY) 236 while the power signal passes to power converter 238.

[0328] If the powered end station 272 is used to couple the network attached device or PD to an Ethernet network, network physical layer 236 may be operable to implement the 10 Mbps, 100 Mbps, and/or 1 Gbps physical layer functions as well as other Ethernet data protocols that may arise. The Ethernet PHY 236 may additionally couple to an Ethernet media access controller

(MAC). The Ethernet PHY 236 and Ethernet MAC when coupled are operable to implement the hardware layers of an Ethernet protocol stack. The architecture may also be applied to other networks. If a power signal is not received but a traditional, non-power Ethernet signal is received the nonmagnetic power feed circuitry 262 still passes the data signal to the network PHY. [0329] The power signal separated from the network signal within non-magnetic transformer and choke power feed circuit 262 by the power feed circuit is supplied to power converter 238. Typically the power signal received does not exceed 57 volts SELV (Safety Extra Low Voltage). Typical voltage in an Ethernet application is 48 -volt power. Power converter 238 may then further transform the power as a DC to DC converter to provide 1.8 to 3.3 volts, or other voltages specified by many Ethernet network attached devices.

[0330] Power-sourcing switch 270 includes a network connector 232, Ethernet or network physical layer 254, PSE controller 256, non-magnetic transformer and choke power supply circuitry 266, and possibly a multiple-port switch. Transformer functionality is supplied by non- magnetic transformer and choke power supply circuitry 266. Power-sourcing switch 270 may be used to supply power to network attached devices. Powered end station 272 and power sourcing switch 270 may be applied to an Ethernet application or other network-based applications such as, but not limited to, a vehicle-based network such as those found in an automobile, aircraft, mass transit system, or other like vehicle. Examples of specific vehicle-based networks may include a local interconnect network (LIN), a controller area network (CAN), or a flex ray network. All may be applied specifically to automotive networks for the distribution of power and data within the automobile to various monitoring circuits or for the distribution and powering of entertainment devices, such as entertainment systems, video and audio entertainment systems often found in today's vehicles. Other networks may include a high speed data network, low speed data network, time-triggered communication on CAN (TTCAN) network, a J1939- compliant network, ISOl 1898-compliant network, an ISOl 1519-2-compliant network, as well as other similar networks. Other embodiments may supply power to network attached devices over alternative networks such as but not limited to a HomePNA local area network and other similar networks. HomePNA uses existing telephone wires to share a single network connection within a home or building. Alternatively, embodiments may be applied where network data signals are provided over power lines.

[0331] Non-magnetic transformer and choke power feed circuitry 262 and 266 enable elimination of magnetic transformers with integrated system solutions that enable an increase in system density by replacing magnetic transformers with solid state power feed circuitry in the form of an integrated circuit or discreet component.

[0332] In some embodiments, non-magnetic transformer and choke power feed circuitry 262, network physical layer 236, power distribution management circuitry 254, and power converter 238 may be integrated into a single integrated circuit rather than discrete components at the printed circuit board level. Optional protection and power conditioning circuitry may be used to interface the integrated circuit to the network connector 232. [0333] The Ethernet PHY may support the 10/100/1000 Mbps data rate and other future data networks such as a 10000 Mbps Ethernet network. Non-magnetic transformer and choke power feed circuitry 262 supplies line power minus the insertion loss directly to power converter 238, converting power first to a 12V supply then subsequently to lower supply levels. The circuit may be implemented in any appropriate process, for example a 0.18 or 0.13 micron process or any suitable size process.

[0334] Non-magnetic transformer and choke power feed circuitry 262 may implement functions including IEEE 802.3. af signaling and load compliance, local unregulated supply generation with surge current protection, and signal transfer between the line and integrated Ethernet PHY. Since devices are directly connected to the line, the circuit may be implemented to withstand a secondary lightning surge.

[0335] For the power over Ethernet (PoE) to be IEEE 802.3af standard compliant, the PoE may be configured to accept power with various power feeding schemes and handle power polarity reversal. A rectifier, such as a diode bridge, a switching network, or other circuit, may be implemented to ensure power signals having an appropriate polarity are delivered to nodes of the power feed circuit. Any one of the conductors 1, 4, 7 or 3 of the network RJ45 connection can forward bias to deliver current and any one of the return diodes connected can forward bias to form a return current path via one of the remaining conductors. Conductors 2, 5, 8 and 4 are connected similarly. [0336] Non-magnetic transformer and choke power feed circuitry 262 applied to PSE may take the form of a single or multiple port switch to supply power to single or multiple devices attached to the network. Power sourcing switch 270 may be operable to receive power and data signals and combine to communicate power signals which are then distributed via an attached network. If power sourcing switch 270 is a gateway or router, a high-speed uplink couples to a network such as an Ethernet network or other network. The data signal is relayed via network PHY 254 and supplied to non-magnetic transformer and choke power feed circuitry 266. PSE switch 270 may be attached to an AC power supply or other internal or external power supply to supply a power signal to be distributed to network-attached devices that couple to power sourcing switch 270. Power controller 256 within or coupled to non-magnetic transformer and choke power feed circuitry 266 may determine, in accordance with IEEE standard 802.3af, whether a network-attached device in the case of an Ethernet network-attached device is a device operable to receive power from power supply equipment. When determined that an IEEE 802.3af compliant powered device (PD) is attached to the network, power controller 256 may supply power from power supply to non-magnetic transformer and choke power feed circuitry 266, which is sent to the downstream network-attached device through network connectors, which in the case of the Ethernet network may be an RJ45 receptacle and cable.

[0337] IEEE 802.3af Standard is to fully comply with existing non-line powered Ethernet network systems. Accordingly, PSE detects via a well-defined procedure whether the far end is PoE compliant and classify sufficient power prior to applying power to the system. Maximum allowed voltage is 57 volts for compliance with SELV (Safety Extra Low Voltage) limits.

[0338] For backward compatibility with non-powered systems, applied DC voltage begins at a very low voltage and only begins to deliver power after confirmation that a PoE device is present. In the classification phase, the PSE applies a voltage between 14.5V and 20.5V, measures the current and determines the power class of the device. In one embodiment the current signature is applied for voltages above 12.5V and below 23 Volts. Current signature range is 0-44mA.

[0339] The normal powering mode is switched on when the PSE voltage crosses 42 Volts where power MOSFETs are enabled and the large bypass capacitor begins to charge. [0340] A maintain power signature is applied in the PoE signature block - a minimum of

1 OmA and a maximum of 23.5kohms may be applied for the PSE to continue to feed power. The maximum current allowed is limited by the power class of the device (class 0-3 are defined). For class 0, 12.95W is the maximum power dissipation allowed and 400ma is the maximum peak current. Once activated, the PoE will shut down if the applied voltage falls below 30V and disconnect the power MOSFETs from the line.

[0341] Power feed devices in normal power mode provide a differential open circuit at the Ethernet signal frequencies and a differential short at lower frequencies. The common mode circuit presents the capacitive and power management load at frequencies determined by the gate control circuit. [0342] Terms "substantially", "essentially", or "approximately", that may be used herein, relate to an industry-accepted tolerance to the corresponding term. Such an industry-accepted tolerance ranges from less than one percent to twenty percent and corresponds to, but is not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, and/or thermal noise. The term "coupled", as may be used herein, includes direct coupling and indirect coupling via another component, element, circuit, or module where, for indirect coupling, the intervening component, element, circuit, or module does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. Inferred coupling, for example where one element is coupled to another element by inference, includes direct and indirect coupling between two elements in the same manner as "coupled". [0343] While the present disclosure describes various embodiments, these embodiments are to be understood as illustrative and do not limit the claim scope. Many variations, modifications, additions and improvements of the described embodiments are possible. For example, those having ordinary skill in the art will readily implement the steps necessary to provide the structures and methods disclosed herein, and will understand that the process parameters, materials, and dimensions are given by way of example only. The parameters, materials, and dimensions can be varied to achieve the desired structure as well as modifications, which are within the scope of the claims. Variations and modifications of the embodiments disclosed herein may also be made while remaining within the scope of the following claims. For example, various aspects or portions of a network interface are described including several optional implementations for particular portions. Any suitable combination or permutation of the disclosed designs may be implemented.

Claims

WHAT IS CLAIMED IS:

1. An apparatus comprising: a circuit comprising: an application device comprising a port for interfacing to a powered device; an interface configured for coupling a network line to the powered device via the application device and communicating operating power and data to the powered device from the network line; and an isolator coupled between the application device and the powered device isolating the application device and the interface referenced to a line reference from the powered device referenced to a device reference.

2. An apparatus comprising: a system comprising: a powered device; a line connector configured for coupling to a network line; an application device comprising a port for interfacing to the powered device; an interface configured for coupling the network line via the line connector to the powered device via the application device and communicating operating power and data to the powered device from the network line; and an isolator coupled between the application device and the powered device isolating the application device and the interface referenced to a line reference from the powered device referenced to a device reference.

3. The apparatus according to Claim 1 further comprising: the application device and the interface configured to a Institute of Electrical and Electronics Engineers (IEEE) 802.3 Power over Ethernet standard.

4. The apparatus according to Claim 1 or Claim 2 further comprising: the application device comprising an application processor and an Ethernet Physical layer

(PHY) coupled between the network line and the application processor; and the interface comprising a T-lessConnect™ solid-state transformer line interface that connects the Ethernet PHY to the network line and transfers operating power and data to the powered device in absence of networking line transformers.

5. The apparatus according to Claim 1 or Claim 2 further comprising: the application device comprising an application processor and an Ethernet Physical layer (PHY) coupled between the network line to the application processor; and a solid-state transformer line interface comprising a rectification and electromagnetic interference (EMI) protection circuit coupled to the network line, first and second power feed elements coupled to the rectification and EMI protection circuit, a powered device (PD) controller coupled between the first and second power feed elements, and a direct current-to-direct current (DC/DC) converter, the solid-state transformer line interface transferring the line reference through the DC/DC converter to a ground reference of the application device through a surge resistance, referencing the application device and the solid-state transformer line interface to a common ground.

6. The apparatus according to Claim 5 further comprising: a surge resistor coupled between the interface and the application device that forms a low impedance ground return path for electromagnetic interference (EMI) noise under normal operation; and the solid-state transformer line interface further comprising a cross-over detect circuit that responds to surge/lightning events by increasing the surge resistance to open circuit, increasing impedance from the device reference to the line reference.

7. The apparatus according to Claim 1 or Claim 2 further comprising: the isolator is a digital isolator comprising a capacitively-coupled interconnect that capacitively transmits a signal from the application device to the powered device whereby optical coupling between the device reference and the line reference can be omitted.

8. The apparatus according to Claim 1 or Claim 2 further comprising: the isolator is a digital isolator comprising an inductively-coupled interconnect that inductively transmits a signal from the application device to the powered device whereby optical coupling between the device reference and the line reference can be omitted.

9. The apparatus according to Claim 1 or Claim 2 further comprising: the isolator is a digital and power isolator comprising an interconnect and a power transformer.

10. The apparatus according to Claim 1 or Claim 2 further comprising: the application device comprising an Ethernet Physical layer (PHY); and the interface comprising a T-lessConnect™ solid-state transformer line interface that connects the Ethernet PHY to the network line and transfers operating power and data to the powered device in absence of networking line transformers.

11. The apparatus according to Claim 1 or Claim 2 further comprising: the port comprises a digital port.

12. The apparatus according to Claim 1 or Claim 2 further comprising: the port comprises a Universal Serial Bus (USB) port or a RETMA Standard (RS)-232 port.

13. The apparatus according to Claim 1 or Claim 2 further comprising: the application device comprising an application processor and an Ethernet Physical layer

(PHY) coupled between the network line and the application processor; and a Media Independent Interface (Mil) coupling the Ethernet PHY to the application processor operative as a Media Access Controller (MAC) device.

14. The apparatus according to Claim 1 or Claim 2 further comprising: the application device comprising an Ethernet Physical layer (PHY); and a Media Independent Interface (Mil) coupling the Ethernet PHY to an application processor operative as a Media Access Controller (MAC) device in the powered device, the Mil on an isolation boundary between distributed power and the powered device.

15. The apparatus according to Claim 2 further comprising: the powered device comprising a device selected from a group consisting of a Voice- over-Internet-Protocol (VoIP) telephone, an Internet Protocol (IP) telephone, a wireless Local-Area-Network (LAN) Access Point, a security camera, a Web camera (webcam), an Analog Telephone Adapter (ADA), a Point-of-Sale (PoS) terminal, an Ethernet hub, a computer, and an appliance; and the application device and the interface configured to a Institute of Electrical and Electronics Engineers (IEEE) 802.3 Power over Ethernet standard.

16. The apparatus according to Claim 2 further comprising: a power source coupled to the network line; the line connector comprising a Registered Jack (RJ)-45 connector; and the network line configured as two wire pairs coupled to the RJ-45 connector.

17. The apparatus according to Claim 2 further comprising: a transformer comprising first and second windings, the first winding coupled to the interface and the second winding coupled to the application device; a surge resistor coupled between the interface and the application device that forms a low impedance ground return path for electromagnetic interference (EMI) noise under normal operation; a diode coupled between the transformer second winding and the application device; a low dropout regulator coupled between the diode and the application device; and the solid-state transformer line interface further comprising a cross-over detect circuit that responds to surge/lightning events by increasing the surge resistance to open circuit, increasing impedance from the device reference to the line reference.

18. A signal isolator comprising: a transmission path comprising an isolation barrier; a signal conditioner adapted to receive an input signal and precondition the input signal according to a modulation function for passing a preconditioned signal via the transmission path; and a signal recovery circuit that receives the preconditioned signal via the transmission path and demodulates the preconditioned signal, forming a feedback signal for usage in a control loop.

19. The signal isolator according to Claim 28 further comprising: the signal conditioner comprising an analog to digital converter that performs a modulation function; the transmission path comprising at least one capacitor; and the signal recovery circuit comprising a digital to analog converter or digital filter.

20. The signal isolator according to Claim 28 further comprising: the signal conditioner comprising a modulator selected from a group consisting of a pulse width modulator, a delta modulator, a frequency modulator, and a phase modulator.

21. The signal isolator according to Claim 28 further comprising: the signal isolator configured to acquire an analog input signal, digitize the signal, and pass the digitized signal through a control system.

22. An isolator circuit comprising: an isolated transmission path; a modulator configured to receive an input signal that conditions the signal for transmission via the isolated transmission path; and a demodulator that receives the transmitted signal and recovers a feedback signal for usage in a control loop.

23. The isolator circuit according to Claim 23 further comprising: the modulator selected from a group consisting of an analog-to-digital converter; a pulse code modulator, a delta modulator, a voltage to frequency converter, a frequency modulator, and a phase modulator.

24. The isolator circuit according to Claim 23 further comprising: the modulator comprising a single-ended analog-to-digital converter (ADC) modulator, a differential ADC modulator, or a capacitively-coupled ADC modulator.

25. The isolator circuit according to Claim 23 further comprising: the isolated transmission path comprises at least one capacitor.

26. The isolator circuit according to Claim 23 further comprising: the demodulator comprising a digital-to-analog converter (DAC).

28. A signal isolator comprising: a modulator configured to receive and modulate a signal; a rectifier; full differential alternating current (AC) coupling configured for transmitting the modulated signal from the modulator to the rectifier with capacitive-coupled signal isolation; and a digital filter coupled to the rectifier and configured to recover the modulated signal.

29. The signal isolator according to Claim 28 further comprising: a lowpass filter coupled to the digital filter.

30. The signal isolator according to Claim 28 further comprising: the signal isolator configured to modulate a direct current (DC) feedback voltage and pass the DC feedback voltage through at least one capacitor by oversampling and demodulating to a higher frequency.

31. The signal isolator according to Claim 28 further comprising: a lowpass filter coupled to the digital filter; and the signal isolator configured to modulate a direct current (DC) feedback voltage and pass the DC feedback voltage through at least one capacitor by oversampling and demodulating to a higher frequency, the lowpass filter configured to restore an analog signal.

32. An isolator circuit comprising: a pulse width modulator configured to precondition a signal; a differential transmission isolation barrier coupled to the pulse width modulator and configured to pass a preconditioned signal; and a lowpass filter demodulator coupled to the differential transmission isolation barrier and configured to perform error recovery on the passed preconditioned signal.

33. The isolator circuit according to Claim 32 further comprising: an error amplifier coupled to a signal input terminal of the pulse width modulator and configured for comparing the signal to a reference.

34. The isolator circuit according to Claim 32 further comprising: an error amplifier coupled to the lowpass filter modulator and configured for regulating the error recovered signal upon reconstruction.

35. A signal isolator comprising: a dual-channel bidirectional isolator coupling a primary domain and a secondary domain comprising: a digital isolator and an analog isolator coupled in parallel between the primary domain and the secondary domain and configured to transmit data in opposing directions.

36. The signal isolator according to Claim 35 further comprising: the digital isolator configured to pass digital data transmission signals from the primary domain to the secondary domain; and the analog isolator configured to pass analog information back from the secondary domain to the primary domain.

37. The signal isolator according to Claim 35 further comprising: the digital isolator configured to pass digital information including shut down, power-on- reset, status information, and control information.

38. The signal isolator according to Claim 35 further comprising: the digital isolator comprising: a pre-conditioner adapted to receive an input signal and precondition the input signal according to a modulation function; a transmission path comprising an isolation barrier coupled to the pre-conditioner for passing a preconditioned signal; and a digital recovery circuit coupled to the transmission path.

39. The signal isolator according to Claim 38 further comprising: the transmission path comprising an isolation barrier selected from a group consisting of a capacitive isolation barrier, an electrostatic isolation barrier, a transformer isolation barrier, a magnetic isolation barrier, an optical isolation barrier, a thermal isolation barrier, a resistive isolation barrier, and a piezoelectric isolation barrier.

40. The signal isolator according to Claim 35 further comprising: the analog isolator comprising: an analog-to-digital converter (ADC) adapted to receive a feedback signal and precondition the feedback signal; a transmission path comprising an isolation barrier coupled to the ADC for passing a preconditioned signal; and a digital-to-analog converter coupled to the transmission path.

41. The signal isolator according to Claim 40 further comprising: the transmission path comprising an isolation barrier selected from a group consisting of a capacitive isolation barrier, an electrostatic isolation barrier, a transformer isolation barrier, a magnetic isolation barrier, an optical isolation barrier, a thermal isolation barrier, a resistive isolation barrier, and a piezoelectric isolation barrier.

42. The signal isolator according to Claim 40 further comprising: the analog-to-digital converter configured to convert, sample, and modulate and analog signal into digital format and pass the digital format signal through a capacitor in the transmission path; and the digital-to-analog converter configured to recover to a baseband analog signal.

43. The signal isolator according to Claim 35 further comprising: an error amplifier coupled to the dual-channel bidirectional isolator at a primary domain connection or a secondary domain connection and configured for feedback regulation.

44. A power converter comprising: a direct current (DC)-DC converter configured to receive an input voltage in a primary domain; a transformer coupled to and driven by the DC -DC converter and supplying an output voltage in a secondary domain; and a transmission path configured to pass a digital feedback signal through an isolation barrier from the secondary domain to the primary domain.

45. The power converter according to Claim 44 further comprising: a signal conditioner coupled to the transmission path in the secondary domain and adapted to receive an input signal and precondition the input signal according to a modulation function for passing a preconditioned signal via the transmission path; and a signal recovery circuit coupled to the transmission path in the primary domain that receives the preconditioned signal via the transmission path and demodulates the preconditioned signal, forming a feedback signal for usage in a control loop.

46. The power converter according to Claim 44 further comprising: a signal conditioner comprising an analog to digital converter coupled to the transmission path in the secondary domain and adapted to receive an input signal and precondition the input signal according to a modulation function for passing a preconditioned signal via the transmission path; the transmission path comprising at least one capacitor; and a signal recovery circuit comprising a digital to analog converter or flip-flop coupled to the transmission path in the primary domain that receives the preconditioned signal via the transmission path and demodulates the preconditioned signal, forming a feedback signal for usage in a control loop.

47. The power converter according to Claim 44 further comprising: a signal conditioner comprising a modulator selected from a group consisting of a pulse width modulator, a delta modulator, a frequency modulator, and a phase modulator coupled to the transmission path in the secondary domain and adapted to receive an input signal and precondition the input signal according to a modulation function for passing a preconditioned signal via the transmission path; and a signal recovery circuit coupled to the transmission path in the primary domain and configured to acquire an analog input signal, digitize the signal, and pass the digitized signal through a control system.

48. The power converter according to Claim 44 further comprising: a pulse wide modulator (PWM) direct current (DC)-DC converter coupled to drive a full- bridge transformer; and an oscillator coupled to the PWM DC -DC converter and generating an oscillator time base for synchronously driving the PWM DC -DC converter.

49. The power converter according to Claim 44 further comprising: a rectifier coupled to the transformer; and a filter coupled to the rectifier configured to supply a filtered output voltage.

50. The power converter according to Claim 44 further comprising: a pulse wide modulator (PWM) direct current (DC)-DC converter comprising a plurality of internal drivers and a plurality of external power field effect transistors (FETs) that drive the transformer; a rectifier comprising a plurality of diodes or transmission gates coupled to the transformer; and a filter comprising an inductor and a capacitor coupled to the rectifier configured to supply a filtered output voltage.

51. The power converter according to Claim 44 further comprising: a rectifier coupled to the transformer; a resistor divider coupled to the rectifier and producing a feedback voltage in the secondary domain; a signal conditioner coupled to the resistor divider and adapted to receive the feedback voltage and precondition the feedback voltage according to a pulse width modulator (PWM) or delta modulator (DM) modulation function; at least one capacitor coupled to the signal conditioner and operative as an isolated transmission path; and a signal recovery circuit coupled to the isolated transmission path in the primary domain and configured to receive the preconditioned feedback voltage and demodulate the preconditioned feedback voltage, forming a feedback signal for usage in a control loop.

52. The power converter according to Claim 51 further comprising: the at least one capacitor configured as a single-ended or differential transmission path.

53. The power converter according to Claim 44 further comprising: the transmission path comprising: a modulator configured to receive and modulate a signal; a diode bridge rectifier; full differential alternating current (AC) coupling configured for transmitting the modulated signal from the modulator to the diode bridge rectifier with capacitive-coupled signal isolation; and a D flip-flop coupled to the diode bridge rectifier and configured to recover the modulated signal.

54. The power converter according to Claim 53 further comprising: a lowpass filter coupled to the D flip-flop.

55. The power converter according to Claim 44 further comprising: the signal isolator configured to modulate a direct current (DC) feedback voltage and pass the DC feedback voltage through at least one capacitor by oversampling and demodulating to a higher frequency whereby a baseband signal is recovered.

56. The power converter according to Claim 44 further comprising: a pulse width modulator configured to precondition a signal; a differential transmission isolation barrier coupled to the pulse width modulator and configured to pass a preconditioned signal; and a lowpass filter demodulator coupled to the differential transmission isolation barrier and configured to perform error recovery on the passed preconditioned signal.

57. The power converter according to Claim 56 further comprising: an error amplifier coupled to a signal input terminal of the pulse width modulator and configured for comparing the signal to a reference.

58. The power converter according to Claim 44 further comprising: an error amplifier coupled to the lowpass filter modulator and configured for regulating the error recovered signal upon reconstruction.

59. A power controller comprising: a direct current (DC)-DC converter configured to receive an input voltage in a primary domain; a transformer coupled to and driven by the DC -DC converter and supplying an output voltage in a secondary domain; and a dual-channel bidirectional isolator forming a transmission path that passes signals through an isolation barrier between the primary domain and the secondary domain comprising: a digital isolator and an analog isolator coupled in parallel between the primary domain and the secondary domain and configured to transmit data in opposing directions.

60. The power controller according to Claim 59 further comprising: the digital isolator configured to pass digital data transmission signals from the primary domain to the secondary domain; and the analog isolator configured to pass analog information back from the secondary domain to the primary domain.

61. The power controller according to Claim 59 further comprising: the digital isolator configured to pass digital information including shut down, power-on- reset, status information, and control information.

62. The power controller according to Claim 59 further comprising: the digital isolator comprising: a pre-conditioner adapted to receive an input signal and precondition the input signal according to a modulation function; a transmission path comprising an isolation barrier coupled to the pre-conditioner for passing a preconditioned signal; and a digital recovery circuit coupled to the transmission path.

63. The power controller according to Claim 62 further comprising: the transmission path comprising an isolation barrier selected from a group consisting of a capacitive isolation barrier, an electrostatic isolation barrier, a transformer isolation barrier, a magnetic isolation barrier, an optical isolation barrier, a thermal isolation barrier, a resistive isolation barrier, and a piezoelectric isolation barrier.

64. The power controller according to Claim 59 further comprising: the analog isolator comprising: an analog-to-digital converter adapted to receive a feedback signal and precondition the feedback signal; a transmission path comprising an isolation barrier coupled to the pre-conditioner for passing a preconditioned signal; and a digital-to-analog converter coupled to the transmission path.

65. The power controller according to Claim 64 further comprising: the transmission path comprising an isolation barrier selected from a group consisting of a capacitive isolation barrier, an electrostatic isolation barrier, a transformer isolation barrier, a magnetic isolation barrier, an optical isolation barrier, a thermal isolation barrier, a resistive isolation barrier, and a piezoelectric isolation barrier.

66. The power controller according to Claim 65 further comprising: the analog-to-digital converter configured to convert, sample, and modulate and analog signal into digital format and pass the digital format signal through a capacitor in the transmission path; and the digital-to-analog converter configured to recover to a baseband analog signal.

67. The power controller according to Claim 59 further comprising: an error amplifier coupled to the dual-channel bidirectional isolator at a primary domain connection or a secondary domain connection and configured for feedback regulation.

68. A power controller comprising: a power converter configured to receive an input voltage in a primary domain; a transformer coupled to and driven by the power converter and supplying an output voltage in a secondary domain; an isolated transmission path coupled between the primary domain and the secondary domain; a modulator configured to receive the output voltage that conditions the signal for transmission via the isolated transmission path; and a demodulator that receives the transmitted signal and recovers a feedback signal for usage in a control loop.

69. The power controller according to Claim 68 further comprising: the modulator selected from a group consisting of an analog-to-digital converter; a pulse code modulator, a delta modulator, a voltage to frequency converter, a frequency modulator, and a phase modulator.

70. The power controller according to Claim 68 further comprising: the modulator comprising a single-ended analog-to-digital converter (ADC) modulator, a differential ADC modulator, or a capacitively-coupled ADC modulator.

71. The power controller according to Claim 68 further comprising: the isolated transmission path comprises at least one capacitor.

72. The power controller according to Claim 68 further comprising: the demodulator comprising a digital-to-analog converter (DAC).

73. A signal isolator comprising: an isolation barrier; a transmitter coupled to a first side of the isolation barrier and configured to receive and convert an information signal to a differential signal that encodes information in the information signal in a single transition edge; a differentiator coupled to a second side isolated from the first side of the isolation barrier that differentiates the differential signal; and a recovery circuit coupled to the differentiator and configured to recover an output information signal based on the information in the single transition edge.

74. The signal isolator according to Claim 73 further comprising: the recovery circuit configured to recover the output information signal using positive feedback.

75. The signal isolator according to Claim 73 further comprising: the differentiator configured to separate a common-mode-to-differential signal component from true differential signal components.

76. The signal isolator according to Claim 73 further comprising: the differentiator configured as a current mode differentiator.

77. The signal isolator according to Claim 73 further comprising: a common mode suppression control circuit coupled to the differentiator and configured to maintain the differentiator in a linear range.

78. The signal isolator according to Claim 73 further comprising: a plurality of differentiators coupled to the second side of the isolation barrier and configured to separate a common error signal from differential.

79. The signal isolator according to Claim 73 further comprising: the recovery circuit comprising a comparator coupled to the differentiator and a feedback device coupled to the comparator.

80. The signal isolator according to Claim 73 further comprising: the recovery circuit comprising a peak detector coupled to the differentiator and a feedback device coupled to the peak detector.

81. A signal isolator comprising: an integrated circuit substrate; an isolation barrier formed by at least two interlayer metal dielectric capacitors that isolates a first domain from a second domain in the substrate; a transmitter in the first domain coupled to the isolation barrier and configured to transmit an information signal through the isolation barrier; a differentiator in the second domain coupled to the isolation barrier and configured to differentiate the transmitted information signal; and a recovery circuit in the second domain coupled to the differentiator and configured to recover an output information signal based on the differentiated information signal.

82. The signal isolator according to Claim 81 further comprising: the isolation barrier forming a differential transmission pathway comprising a plurality of differential lines each comprising a plurality of parallel capacitive pathways configured to create magnetic and electrical differentiality.

83. The signal isolator according to Claim 81 further comprising: the differential transmission pathway comprising first and second differential lines, each differential line comprising two parallel pathways, each pathway comprising first and second capacitors coupled at a bond pad.

84. The signal isolator according to Claim 83 further comprising: the bond pads arranged in positions attaining first-order common-centroiding of the capacitors.

85. The signal isolator according to Claim 81 further comprising: the isolation barrier configured in an arrangement selected from arrangements comprising the at least two interlayer metal dielectric capacitors formed in the first domain, the at least two interlayer metal dielectric capacitors formed in the second domain, the at least two interlayer metal dielectric capacitors formed partly in the first domain and partly in the second domain, the at least two interlayer metal dielectric capacitors formed between the first and second domains, and the at least two interlayer metal dielectric capacitors formed partly in the first domain, partly in the second domain, and partly between the first and second domain.

86. The signal isolator according to Claim 81 further comprising: the differentiator configured as a current mode differentiator.

87. A signal isolator comprising: an isolation barrier forming a differential transmission pathway comprising a plurality of differential lines each comprising a plurality of parallel capacitive pathways configured to create magnetic and electrical differentiality; a transmitter coupled to a first side of the isolation barrier and configured to receive and convert an information signal to a differential signal that encodes information in the information signal in a single transition edge; and a recovery circuit coupled to the differentiator and configured to recover an output information signal based on the information in the single transition edge.

88. The signal isolator according to Claim 87 further comprising: a differentiator coupled to a second side isolated from the first side of the isolation barrier that differentiates the differential signal.

89. The signal isolator according to Claim 87 further comprising: a common mode suppression circuit coupled between the isolation barrier and the recovery circuit, the common mode suppression circuit configured to maintain differentiation in a linear range.

90. A signal isolator comprising: an isolation barrier; a modulator coupled to an input side of the isolation barrier configured to receive a logic signal with first and second transition edges that shift the logic signal between two states, convert the logic signal to a differential signal, and pass the differential signal across the isolation barrier; a differentiator coupled to an output side of the isolation barrier that differentiates the communicated differential signal; and a recovery circuit coupled to the differentiator that recovers a signal indicative of the first and second transition edges from the differentiated signal.

91. The signal isolator according to Claim 90 further comprising: the modulator configured to create the differential signals that contains all information in the logic signals in a single transition edge.

92. The signal isolator according to Claim 90 further comprising: a differential comparator comprising the modulator.

93. The signal isolator according to Claim 90 further comprising: a differential comparator coupled to a set/reset latch comprising the recovery circuit.

94. The signal isolator according to Claim 90 further comprising: a powered system on the input side of the isolation barrier and an isolated system on the output side of the isolation barrier.

95. A signal isolator comprising: an isolation barrier isolating first and second domains; a modulator in the first domain coupled to the isolation barrier configured to convert an information signal to a digital signal that contains all information in the information signal in an edge of a single transition and passes the digital signal across the isolation barrier to the second domain; a differentiator in the second domain coupled to the isolation barrier that differentiates the passed digital signal; and a recovery circuit in the second domain coupled to the differentiator and configured to recover an output information signal from the differentiated digital signal based on the information in the single transition edge.

96. The signal isolator according to Claim 95 further comprising: a powered system in the first domain and an isolated system in the second domain.

97. A signal isolator comprising: an isolation barrier isolating first and second domains; at least one fully differential transmitter in the first domain coupled to the isolation barrier configured to transmit a digital signal containing all information in an information signal in an edge of a single transition across the isolation barrier to the second domain; at least one fully differential receiver in the second domain coupled to the isolation barrier configured to receive and differentiate the transmitted digital signal.

98. A signal isolator comprising: an isolation barrier; first and second separate dies from a common wafer comprising a transmitter on the first die and a receiver on the second die in a configuration that communicates an information signal across the isolation barrier as a digital signal that contains all information in a single transition edge; and oscillators on the first and second dies that are matched to a selected tolerance.

99. The signal isolator according to Claim 98 further comprising: a state machine coupled to the receiver on the second die; and a failsafe logic coupled to the state machine on the second die, the state machine and the failsafe logic configured to determine frequency of a signal transmitted across the isolation barrier, compare frequency of a local oscillator signal to the frequency of the transmitted signal, and correct transmitted state based on the comparison.

100. An interface comprising: a converter configured to track process characteristics across an isolation barrier and modify amplitude of a fast differential edge modulation as a function of speed of an active device on a transmitting side of the isolation barrier; and a differentiator configured to differentiate the fast differential edge modulation on a receiving side of the isolation barrier whereby differentiation bandwidth tracks slope rate of the differential edge modulation.

101. The interface according to Claim 100 further comprising: a capacitive isolation barrier coupled between the converter and the differentiator configured for passing the fast differential edge modulation; and the converter and differentiator configured for tracking the differentiation bandwidth and slope rate of the differential edge modulation whereby capacitor size in the isolation barrier is reduced or minimized, low frequency components in the passed fast differential edge modulation are attenuated, and common mode noise is rejected.

102. The interface according to Claim 100 further comprising: a capacitive isolation barrier coupled between the converter and the differentiator comprising a plurality of inter-level metal dielectric capacitors; and a feedback control loop configured to match a metal-insulator-metal capacitor to the inter- level dielectric capacitors so that differential bandwidth tracks over process variations.

103. The interface according to Claim 27 further comprising: the capacitive isolation barrier comprising a plurality of inter-level metal dielectric capacitors formed on first and second sides of the isolation barrier from respective separate first and second integrated circuit dies from adjacent portions of a common wafer.

104. The interface according to Claim 100 further comprising: the converter comprising differential transistors coupled to load resistors that transmit differential signals to the isolation barrier, a digital to matched differential driver coupled to control the differential transistor pair, and a process tracking circuit coupled to the differential transistors for controlling amplitude of voltage as a function of transistor speed.

105. The interface according to Claim 100 further comprising: the converter and differentiator configured for communicating signals using multiple- slope transmission and reception whereby a change in slope changes output pulse amplitude and number of bits per second that can be transmitted.

106. The interface according to Claim 100 further comprising: a positive feedback recovery circuit including a high-speed latch that reclaims a digital signal from a sliced pulse signal.

107. A signal interface comprising: an isolation barrier; a converter coupled to the isolation barrier and configured for receiving a digital signal and converting the digital signal to a fast differential edge modulation that tracks process characteristics across the isolation barrier; and a differentiator coupled to the isolation barrier and configured for receiving the fast differential edge modulation passed through the isolation barrier and differentiating the passed fast differential edge modulation to form a pulse according to a transfer function that amplifies the pulse.

108. The interface according to Claim 107 further comprising: the differentiator comprising a first order or higher order differentiator.

109. The interface according to Claim 107 further comprising: the converter configured for controlling edge rate and amplitude of the fast differential edge modulation to characterize information in the digital signal.

110. The interface according to Claim 107 further comprising: a capacitive isolation barrier that passes the fast differential edge modulation; and the differentiator configured for differentiating the passed fast differential edge modulation and forming a pulse according to a transfer function that amplifies the pulse whereby capacitor size in the isolation barrier is reduced or minimized.

111. The interface according to Claim 107 further comprising: a digital input source configured to supply a digital signal to the converter; a pulse slicer coupled to the differentiator configured for slicing the pulse from the differentiator whereby a reduced duration pulse is formed; and a positive feedback recovery element coupled to the pulse slicer and configured for recovering an output digital signal from the reduced duration pulse and generating a positive feedback signal.

112. The interface according to Claim 107 further comprising: the converter comprising: a pair of differential transistors coupled to load resistors and configured to transmit differential signals to the isolation barrier; a digital to matched differential driver coupled to control the differential transistor pair; and a process tracking circuit coupled to the differential transistor pair configured to control amplitude of voltage as a function of transistor speed and threshold voltage.

113. The interface according to Claim 107 further comprising: the converter configured for converting the digital signal to the fast differential edge modulation in a transition that contains all information in the digital signal as a slope.

114. The interface according to Claim 107 further comprising: the converter configured tracking process characteristics across the isolation barrier including modifying amplitude of the fast differential edge modulation as a function of speed of an active device on a transmitting side of the isolation barrier.

115. The interface according to Claim 107 further comprising: the converter configured for modifying amplitude of the fast differential edge modulation as a function of speed of an active device on a transmitting side of the isolation barrier; and the differentiator configured for differentiating the passed fast differential edge modulation and comprising an amplifier on a receiving side of the isolation barrier that tracks the active device on the isolation barrier transmitting side whereby differentiation bandwidth tracks slope rate of the differential edge modulation.

116. The interface according to Claim 115 further comprising: a capacitive isolation barrier; and the converter and differentiator configured for tracking the differentiation bandwidth and slope rate of the differential edge modulation whereby capacitor size in the isolation barrier is reduced or minimized, low frequency components in the passed fast differential edge modulation are attenuated, and common mode noise is reduced.

117. The interface according to Claim 107 further comprising: a capacitive isolation barrier comprising a plurality of inter-level metal dielectric capacitors; and a recovery device coupled to the differentiator configured for matching a metal-insulator- metal capacitor to the inter-level dielectric capacitors so that differential bandwidth tracks over process variations by feedback control.

118. The interface according to Claim 107 further comprising: at least one data and at least one clock signal path across the isolation barrier integrated on a same integrated circuit die.

119. A signal interface comprising: an integrated circuit substrate; an isolation barrier formed by at least two interlayer metal dielectric capacitors that isolate a first domain from a second domain in the substrate; a converter in the first domain coupled to the isolation barrier and configured to convert a digital signal to a fast differential edge modulation that tracks process characteristics across the isolation barrier and pass the fast differential edge modulation across the isolation barrier; and a differentiator in the second domain coupled to the isolation barrier and configured to differentiate the passed fast differential edge modulation to form a pulse according to a transfer function that amplifies the pulse.

120. The interface according to Claim 119 further comprising: a digital input source configured to supply a digital signal to the converter; a pulse slicer coupled to the differentiator configured for slicing the pulse from the differentiator whereby a reduced duration pulse is formed; and a positive feedback recovery element coupled to the pulse slicer and configured to recover the output information signal using positive feedback.

121. The interface according to Claim 119 further comprising: the interface comprising a low voltage differential signaling (LVDS) interface configured for passing fast differential edge modulation.

122. A semiconductor device comprising: an integrated circuit formed on a substrate and comprising a signal interface with at least one isolator capacitor, the integrated circuit comprising: a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate; a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics with selected thickness of the thick passivation layer being greater than thickness sufficient for isolation so that testing for defects is eliminated; and a thick metal layer formed on the thick passivation layer, the at least one isolator capacitor formed comprising the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator.

123. A semiconductor device comprising: an integrated circuit formed on a substrate and divided into at least two dies arranged across an isolation barrier, the integrated circuit comprising: a plurality of interleaved inter-metal dielectric layers and interlay er dielectrics formed on the substrate; a thick passivation layer formed on the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics layers; a thick metal layer formed on the thick passivation layer; and a plurality of isolator capacitors respectively formed of the thick metal layer and at least one metal layer in the interleaved inter-metal dielectric layers and interlayer dielectrics arranged as substantially parallel planes extending laterally with an overlap selected to compensate for dielectric leakage and fringe fields from creating voltage gradients, the isolator capacitor plurality formed on separate dies from a single wafer whereby ratio of parasitic capacitance to primary capacitance is reduced.

124. A semiconductor device comprising: an integrated circuit formed on a substrate and comprising a signal interface with at least one isolator capacitor, the integrated circuit comprising: a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate; a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics; a thick metal layer formed on the thick passivation layer, the at least one isolator capacitor formed comprising the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator; and at least one metal via formed in the thick passivation layer to prevent deposition of materials with unfavorable breakdown voltages.

125. A semiconductor device comprising: an integrated circuit formed on a substrate and comprising a signal interface with at least one isolator capacitor, the integrated circuit comprising: a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate; a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlay er dielectrics; and a thick metal layer formed on the thick passivation layer, the at least one isolator capacitor formed comprising the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator, the thick metal layer functional as a first plate and a predetermined metal layer in the interleaved inter-metal dielectric layer and interlayer dielectric plurality functional as a second plate in an isolation capacitor, the first plate and the second plate arranged as substantially parallel planes extending laterally with an overlap selected to compensate for dielectric leakage and fringe fields from creating voltage gradients.

126. A semiconductor device comprising: an integrated circuit formed on a substrate and divided into at least two dies arranged across an isolation barrier, the integrated circuit comprising: a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate; a thick passivation layer formed on the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics layers; a thick metal layer formed on the thick passivation layer; a plurality of isolator capacitors respectively formed of the thick metal layer and at least one metal layer in the interleaved inter-metal dielectric layers and interlayer dielectrics; at least one metal via formed to prevent deposition of materials with unfavorable breakdown voltages.

127. A semiconductor device comprising: an integrated circuit formed on a substrate and divided into at least two dies arranged across an isolation barrier, the integrated circuit comprising: a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate; a thick passivation layer with thickness greater than thickness sufficient for isolation so that testing for defects is eliminated formed on the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics layers; a thick metal layer formed on the thick passivation layer; and a plurality of isolator capacitors respectively formed of the thick metal layer and at least one metal layer in the interleaved inter-metal dielectric layers and interlayer dielectrics.

128. The device according to Claim 122 or 123 further comprising: the thick metal layer comprising a redistribution layer (RDL); and a metal via formed beneath the RDL preventing deposition of passivation.

129. The device according to Claim 122 or 123 further comprising: at least one metal via formed to prevent deposition of materials with unfavorable breakdown voltages .

130. The device according to Claim 122 or 123 further comprising: a predetermined metal layer in the interleaved inter-metal dielectric layer and interlayer dielectric plurality underlying the metal via and extending laterally whereby lateral extension of the metal via overlaps the predetermined metal layer.

131. The device according to Claim 122 or 124 further comprising: the thick metal layer functional as a first plate and a predetermined metal layer in the interleaved inter-metal dielectric layer and interlayer dielectric plurality functional as a second plate in an isolation capacitor, the first plate and the second plate arranged as substantially parallel planes extending laterally with an overlap selected to compensate for dielectric leakage and fringe fields from creating voltage gradients.

132. The device according to Claim 131 further comprising: the first plate and the second plate formed with rounded or oblique angles whereby electric fields and/or voltage gradients are reduced or minimized.

133. The device according to Claim 122 or 123 further comprising: a plurality of metal layers distributed within silicate glass dielectric layers, separated by thin silicon nitride layers and overlying inter-layer dielectric layers; the thick metal layer comprising a redistribution layer (RDL); the thick passivation layer comprising an undoped silicate glass (USG) layer.

134. The device according to Claim 122 or 123 further comprising: the at least one isolator capacitor configured comprising the thick passivation layer as an insulator whereby thickness of the passivation layer is selected to reduce parasitic capacitance and improve high-speed operation of the interface.

135. The device according to Claim 122 or 123 further comprising: the at least one isolator capacitor configured comprising the thick passivation layer as an insulator whereby thickness of the passivation layer is selected to reduce capacitor size of the at least one isolator capacitor.

136. The device according to Claim 122 or 123 further comprising: the integrated circuit configured wherein the substrate, the plurality of interleaved inter- metal dielectric layers and interlayer dielectrics, the thick passivation layer, and the thick metal layer are formed by standard processing.

137. The device according to Claim 122 or 123 further comprising: the integrated circuit configured wherein thickness of the thick passivation layer is selected to be larger than for standard processing and impact of oxide defects are reduced.

138. The device according to Claim 122 further comprising: the integrated circuit divided into at least two dies arranged across an isolation barrier wherein capacitors respectively formed on separate dies are configured with a reduced ratio of parasitic capacitance to primary capacitance.

139. The device according to Claim 122 or 123 further comprising: the integrated circuit divided into at least two dies wherein adjacent dies from the integrated circuit are arranged across an isolation barrier and capacitors are matched.

140. The device according to Claim 122 or 123 further comprising: the integrated circuit divided into at least two dies wherein adjacent dies from the integrated circuit are arranged across an isolation barrier and parts of a capacitor on different dies are formed from the same wafer and matched.

141. The device according to Claim 122 further comprising: the integrated circuit divided into first and second dies; an isolation barrier between the first and second dies; a plurality of capacitors respectively formed on separate dies; a converter in the first die configured to track process characteristics across the isolation barrier and modify amplitude of a fast differential edge modulation as a function of speed of an active device on a transmitting side of the isolation barrier; and a differentiator in the second die configured to differentiate the fast differential edge modulation on a receiving side of the isolation barrier whereby differentiation bandwidth tracks slope rate of the differential edge modulation.

142. The device according to Claim 141 further comprising: the differentiator comprising a calibrated capacitor that matches the capacitor plurality.

143. The device according to Claim 141 further comprising: a capacitive isolation barrier coupled between the converter and the differentiator configured for passing the fast differential edge modulation; and the converter and differentiator configured for tracking the differentiation bandwidth and slope rate of the differential edge modulation whereby capacitor size in the isolation barrier is reduced or minimized, low frequency components in the passed fast differential edge modulation are attenuated, and common mode noise is reduced.

144. The device according to Claim 141 further comprising: a capacitive isolation barrier coupled between the converter and the differentiator comprising a plurality of inter-level metal dielectric capacitors; and a feedback control loop configured to balance the plurality of inter-level metal dielectric capacitors.

145. The device according to Claim 144 further comprising: the capacitive isolation barrier comprising a plurality of inter-level metal dielectric capacitors formed on first and second sides of the isolation barrier from respective separate first and second integrated circuit dies from adjacent portions of a common wafer.

146. The device according to Claim 122 further comprising: the thick passivation layer comprising a thick oxide layer.

147. The device according to Claim 146 further comprising: the thick metal layer and at least one metal layer in the interleaved inter-metal dielectric layers and interlayer dielectrics formed with rounded or oblique angles whereby electric fields and/or voltage gradients are reduced or minimized.

148. The device according to Claim 123 further comprising: the thick passivation layer has thickness greater than thickness sufficient for isolation so that testing for defects is eliminated.