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WO2008049104A3 - Interface to full and reduced pin jtag devices - Google Patents

Interface to full and reduced pin jtag devices

Info

Publication number
WO2008049104A3
WO2008049104A3 PCT/US2007/081914 US2007081914W WO2008049104A3 WO 2008049104 A3 WO2008049104 A3 WO 2008049104A3 US 2007081914 W US2007081914 W US 2007081914W WO 2008049104 A3 WO2008049104 A3 WO 2008049104A3
Authority
WO
Grant status
Application
Patent type
Prior art keywords
jtag
devices
pin
interface
reduced
Prior art date
Application number
PCT/US2007/081914
Other languages
French (fr)
Other versions
WO2008049104A2 (en )
Inventor
Lee D Whetsel
Original Assignee
Texas Instruments Inc
Lee D Whetsel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31712Input or output aspects
    • G01R31/31713Input or output interfaces for test, e.g. test pins, buffers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2815Functional tests, e.g. boundary scans, using the normal I/O contacts
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2884Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302Contactless testing
    • G01R31/3025Wireless interface with the DUT
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31703Comparison aspects, e.g. signature analysis, comparators
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31725Timing aspects, e.g. clock distribution, skew, propagation delay
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31727Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3177Testing of logic operation, e.g. by logic analysers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558Addressing or selecting of subparts of the device under test
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]

Abstract

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
PCT/US2007/081914 2006-10-18 2007-10-19 Interface to full and reduced pin jtag devices WO2008049104A3 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US82997906 true 2006-10-18 2006-10-18
US60/829,979 2006-10-18
US11874594 US7818641B2 (en) 2006-10-18 2007-10-18 Interface to full and reduce pin JTAG devices
US11/874,594 2007-10-18

Publications (2)

Publication Number Publication Date
WO2008049104A2 true WO2008049104A2 (en) 2008-04-24
WO2008049104A3 true true WO2008049104A3 (en) 2008-06-26

Family

ID=39314860

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/081914 WO2008049104A3 (en) 2006-10-18 2007-10-19 Interface to full and reduced pin jtag devices

Country Status (2)

Country Link
US (8) US7818641B2 (en)
WO (1) WO2008049104A3 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7003707B2 (en) 2000-04-28 2006-02-21 Texas Instruments Incorporated IC tap/scan test port access with tap lock circuitry
US7818641B2 (en) * 2006-10-18 2010-10-19 Texas Instruments Incorporated Interface to full and reduce pin JTAG devices
US8294482B2 (en) 2008-03-14 2012-10-23 Apple Inc. Systems and methods for testing a peripheral interfacing with a processor according to a high-speed serial interface protocol
CN101645055B (en) * 2009-09-10 2011-09-07 成都市华为赛门铁克科技有限公司 Logic device on-line loaded method, system and processor
KR20160081521A (en) * 2014-12-31 2016-07-08 삼성전자주식회사 System and method for matching between application and device
DE102016100837B3 (en) * 2016-01-19 2017-03-16 Elmos Semiconductor Aktiengesellschaft Eindrahtlichtsteuerbus
DE102016123400B3 (en) 2016-01-19 2017-04-06 Elmos Semiconductor Aktiengesellschaft Eindrahtlichtsteuerbus multi-level
DE102016101181B3 (en) 2016-01-23 2017-03-30 Elmos Semiconductor Aktiengesellschaft Eindrahtdatenbus concatenated with a plurality of levels for the bidirectional transmission of light data based on the JTAG protocol

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030056154A1 (en) * 1999-10-01 2003-03-20 Edwards David Alan System and method for communicating with an integrated circuit
US20040037303A1 (en) * 2002-08-08 2004-02-26 Joshi Rakesh N. Linking addressable shadow port and protocol for serial bus networks
US20040187049A1 (en) * 2003-02-27 2004-09-23 Nptest, Inc. Very small pin count IC tester
US20040210805A1 (en) * 2003-04-17 2004-10-21 Paul Kimelman Communication interface for diagnostic circuits of an integrated circuit
US20060100810A1 (en) * 2003-02-10 2006-05-11 Koninklijke Philips Electronics N.V. Testing of integrated circuits
US20060156113A1 (en) * 2004-12-10 2006-07-13 Whetsel Lee D Reduced signaling interface method & apparatus
US20060179374A1 (en) * 2005-02-08 2006-08-10 Gayle Noble Wireless hardware debugging
US20060212760A1 (en) * 2005-03-21 2006-09-21 Texas Instruments Incorporated System and method for sharing a communications link between multiple communications protocols

Family Cites Families (17)

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US6704895B1 (en) * 1987-06-02 2004-03-09 Texas Instruments Incorporated Integrated circuit with emulation register in JTAG JAP
US5887001A (en) * 1995-12-13 1999-03-23 Bull Hn Information Systems Inc. Boundary scan architecture analog extension with direct connections
US5898859A (en) * 1996-10-01 1999-04-27 Intel Corporation Address shadow feature and methods of using the same
US6052808A (en) * 1997-10-31 2000-04-18 University Of Kentucky Research Foundation Maintenance registers with Boundary Scan interface
US6425100B1 (en) * 1998-04-24 2002-07-23 Texas Instruments Incorporated Snoopy test access port architecture for electronic circuits including embedded core with built-in test access port
US6966021B2 (en) * 1998-06-16 2005-11-15 Janusz Rajski Method and apparatus for at-speed testing of digital circuits
US6684362B1 (en) * 1999-02-18 2004-01-27 International Business Machines Corporation Method and apparatus for connecting manufacturing test interface to a global serial bus including an I2 c bus
US6418545B1 (en) * 1999-06-04 2002-07-09 Koninklijke Philips Electronics N.V. System and method to reduce scan test pins on an integrated circuit
US6539507B1 (en) * 1999-11-10 2003-03-25 Agilent Technologies, Inc. Integrated circuit with alternately selectable state evaluation provisions
US6813739B1 (en) * 2000-04-04 2004-11-02 Silicon Graphics, Inc. Scan interface chip (SIC) system and method for scan testing electronic systems
US6754863B1 (en) * 2000-04-04 2004-06-22 Silicon Graphics, Inc. Scan interface chip (SIC) system and method for scan testing electronic systems
US6760876B1 (en) * 2000-04-04 2004-07-06 Silicon Graphics, Inc. Scan interface chip (SIC) system and method for scan testing electronic systems
US6470485B1 (en) * 2000-10-18 2002-10-22 Lattice Semiconductor Corporation Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device
US7139947B2 (en) * 2000-12-22 2006-11-21 Intel Corporation Test access port
US6934898B1 (en) * 2001-11-30 2005-08-23 Koninklijke Philips Electronics N.V. Test circuit topology reconfiguration and utilization techniques
US7487419B2 (en) * 2005-06-15 2009-02-03 Nilanjan Mukherjee Reduced-pin-count-testing architectures for applying test patterns
US7818641B2 (en) * 2006-10-18 2010-10-19 Texas Instruments Incorporated Interface to full and reduce pin JTAG devices

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030056154A1 (en) * 1999-10-01 2003-03-20 Edwards David Alan System and method for communicating with an integrated circuit
US20040037303A1 (en) * 2002-08-08 2004-02-26 Joshi Rakesh N. Linking addressable shadow port and protocol for serial bus networks
US20060100810A1 (en) * 2003-02-10 2006-05-11 Koninklijke Philips Electronics N.V. Testing of integrated circuits
US20040187049A1 (en) * 2003-02-27 2004-09-23 Nptest, Inc. Very small pin count IC tester
US20040210805A1 (en) * 2003-04-17 2004-10-21 Paul Kimelman Communication interface for diagnostic circuits of an integrated circuit
US20060156113A1 (en) * 2004-12-10 2006-07-13 Whetsel Lee D Reduced signaling interface method & apparatus
US20060179374A1 (en) * 2005-02-08 2006-08-10 Gayle Noble Wireless hardware debugging
US20060212760A1 (en) * 2005-03-21 2006-09-21 Texas Instruments Incorporated System and method for sharing a communications link between multiple communications protocols

Also Published As

Publication number Publication date Type
US20110185242A1 (en) 2011-07-28 application
US8225157B2 (en) 2012-07-17 grant
US20110010594A1 (en) 2011-01-13 application
US20170192058A1 (en) 2017-07-06 application
US8839060B2 (en) 2014-09-16 grant
US9645198B2 (en) 2017-05-09 grant
US20080255791A1 (en) 2008-10-16 application
US20150338462A1 (en) 2015-11-26 application
US9128152B2 (en) 2015-09-08 grant
US20160259003A1 (en) 2016-09-08 application
US20140351665A1 (en) 2014-11-27 application
US7818641B2 (en) 2010-10-19 grant
US20120246530A1 (en) 2012-09-27 application
WO2008049104A2 (en) 2008-04-24 application
US9372230B2 (en) 2016-06-21 grant
US7945832B2 (en) 2011-05-17 grant

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