WO2008047845A1 - Transistor à semi-conducteur de composé de nitrure et son procédé de fabrication - Google Patents

Transistor à semi-conducteur de composé de nitrure et son procédé de fabrication Download PDF

Info

Publication number
WO2008047845A1
WO2008047845A1 PCT/JP2007/070293 JP2007070293W WO2008047845A1 WO 2008047845 A1 WO2008047845 A1 WO 2008047845A1 JP 2007070293 W JP2007070293 W JP 2007070293W WO 2008047845 A1 WO2008047845 A1 WO 2008047845A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
compound semiconductor
gate insulating
insulating film
nitride compound
Prior art date
Application number
PCT/JP2007/070293
Other languages
English (en)
Japanese (ja)
Inventor
Shusuke Kaya
Yuki Niiyama
Takehiko Nomura
Seikoh Yoshida
Original Assignee
The Furukawa Electric Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2006282772A external-priority patent/JP2008103408A/ja
Priority claimed from JP2006293026A external-priority patent/JP2008112750A/ja
Application filed by The Furukawa Electric Co., Ltd. filed Critical The Furukawa Electric Co., Ltd.
Publication of WO2008047845A1 publication Critical patent/WO2008047845A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • Nitride compound semiconductor transistor and manufacturing method thereof Nitride compound semiconductor transistor and manufacturing method thereof
  • the present invention relates to a nitride compound semiconductor transistor and a method for manufacturing the same, and more particularly to a semiconductor transistor having a nitride compound semiconductor as a channel region and a method for manufacturing the same.
  • Wide bandgap semiconductors represented by III-V nitrides have high breakdown voltage, good electron transport properties, good thermal conductivity, and are very useful as devices for large power at high temperatures. It is.
  • the AlGaN / GaN heterojunction structure has a high two-dimensional electron gas with high electron mobility and carrier density due to the piezo effect! .
  • HFET heterojunction field effect transistor
  • FIG. 7 is a cross-sectional view showing an example of an HFET.
  • a substrate 101 such as sapphire
  • a GaN nofer layer 102, a GaN electron transit layer 103, and an A1GAN electron supply layer 104 are sequentially formed by MOCVD or the like. Further, a protective film 105 made of silicon oxide is formed on the surface.
  • Openings are respectively formed in the source region and the drain region of the protective film 105, and a source electrode 106s is formed on the electron supply layer 104 through the opening in the source region, and the drain is formed through the other opening.
  • An electrode 106d is formed.
  • another opening is formed between the source electrode 106s and the drain electrode 106d in the protective film 105, and the gate electrode 107 is in Schottky contact with the electron supply layer 104 through the opening.
  • HFET has low! /, On-resistance, fast! /, Switching characteristics, is capable of high-temperature operation, is very suitable for the application of noise switching, and can simplify the cooling system of the system become.
  • a normal HFET performs a normally-on operation in which a current flows when the gate electrode 107 is not biased, and a negative voltage bias is applied to the gate to expand the depletion layer to the channel region and cut off the current.
  • a GaN buffer layer 112 and a p-type (p—) Ga N layer 113 are grown in order by the MOCVD method or the like.
  • an n-type source region 114s and a drain region 114d are formed by ion implantation.
  • a silicon oxide film is formed as a gate insulating film 115 on the p-GaN layer 113.
  • a gate electrode 116 is formed in the gate region of the p-GaN layer 113 with a gate insulating film 115 interposed therebetween. Further, the gate insulating film 115 over the source region 114s and the drain region 114d is removed by etching, and a source electrode 117s and a drain electrode 117d are formed thereon, respectively.
  • a MOSFET is described in Patent Document 2, for example.
  • a silicon dioxide film obtained by thermally oxidizing the surface of a silicon substrate is used as a gate insulating film, and a very good interface is realized.
  • Patent Document 1 Japanese Unexamined Patent Publication No. 2003-59946
  • Patent Document 2 JP 2000-150503 A
  • Patent Document 3 Japanese Patent Laid-Open No. 2001-320054
  • a SiO film using thermal oxidation can be formed as a gate insulating film, so a high quality gate insulating film that can maintain a good interface state between the gate insulating film layer and the Si substrate is formed. It is possible.
  • a chemical vapor deposition method cannot be used in a semiconductor element formed using a compound semiconductor layer because a thermal oxidation method cannot be used.
  • CVD method chemical vapor deposition
  • PVD method physical vapor deposition
  • a SiO film that functions as a gate insulating film is formed on the GaN active layer using the CVD method, which is a surface reaction
  • the gate insulation is caused by nitrogen desorption from the surface of the GaN active layer due to radicals.
  • the interface state between the film layer and the GaN active layer became unstable and it was difficult to form a high quality gate insulating film.
  • a SiO film is formed on the GaN active layer by vapor deposition among PVD methods that are not surface reactions, a high-quality gate insulating film must be formed because of poor film adhesion and large compositional deviation.
  • An object of the present invention is to provide a nitride compound semiconductor transistor having a gate insulating film having a high carrier breakdown mobility and a high dielectric breakdown strength in the channel region of the nitride compound semiconductor layer, and a method for manufacturing the same. It is to provide.
  • Another object of the present invention is to provide a method for manufacturing a nitride compound semiconductor transistor capable of forming a gate insulating film having a good film quality on a nitride compound semiconductor layer.
  • a nitride compound semiconductor transistor for solving the above-mentioned problems is provided on a nitride compound semiconductor layer formed on a substrate and on the nitride compound semiconductor layer.
  • a first gate insulating film formed of a silicon nitride film or an aluminum nitride film, and a first gate insulating film formed on the first gate insulating film and made of a material having a higher dielectric breakdown strength than the first gate insulating film.
  • the second gate insulating film is made of any one of an alumina film and a silicon oxide film.
  • the nitride compound semiconductor transistor according to another aspect of the present invention is characterized in that the ohmic electrode is a source electrode and a drain electrode formed on both sides of the gate electrode.
  • the nitride compound semiconductor layer is of one conductivity type, and an opposite conductivity type region is formed under the ohmic electrode. It is characterized by.
  • the nitride compound semiconductor transistor according to another aspect of the present invention is characterized in that the nitride compound semiconductor layer has a heterojunction multi-layer structure in which a two-dimensional electron gas is generated.
  • the first gate insulating film made of the silicon nitride film or the aluminum nitride film is formed by a catalytic chemical vapor deposition method, a plasma It is a film formed by any one of the chemical vapor deposition methods.
  • At least the second gate insulating film of the first gate insulating film and the second gate insulating film is formed by an ECR sputtering method. It is a formed film.
  • a method for manufacturing a nitride compound semiconductor transistor according to a second aspect of the present invention for solving the above-described problems includes a step of growing a nitride compound semiconductor layer on a substrate, and a surface of the nitride compound semiconductor layer. Forming a first gate insulating film made of a silicon nitride film or an aluminum nitride film on the first gate insulating material, and a material strength having a higher dielectric breakdown strength than the first gate insulating film on the first gate insulating film.
  • the first gate insulating film is formed by either catalytic chemical vapor deposition or plasma enhanced chemical vapor deposition.
  • At least the second gate insulating film of the first gate insulating film and the second gate insulating film is formed by an ECR sputtering method. It is formed.
  • the second gate insulating film is made of any one of an alumina film and a silicon oxide film, and is formed by an ECR sputtering method.
  • the nitride compound semiconductor layer is a one-conductivity-type semiconductor, and a counter-conductivity-type semiconductor region is formed under the ohmic electrode. It further has these.
  • the nitride compound semiconductor layer has a multilayer structure having a heterojunction in which a two-dimensional electron gas is generated at a junction interface.
  • the method of manufacturing a nitride compound semiconductor transistor according to another aspect of the present invention provides the first method.
  • the equivalent oxide thickness of the gate insulating film and the gate insulating film having the second gate insulating film force is 20 nm or more and lOOnm or less.
  • the method for manufacturing a nitride compound semiconductor transistor according to another aspect of the present invention is characterized in that the first gate insulating film nitride film is formed with a thickness of 2 nm or more and 30 nm or less.
  • a nitride compound semiconductor transistor having a high carrier mobility in the channel region of the nitride compound semiconductor layer and a high dielectric breakdown strength and having a gate insulating film.
  • a gate insulating film having a good film quality can be formed on the nitride compound semiconductor layer.
  • FIG. 1 shows the thickness of a silicon nitride film and the start of gate leak when the equivalent oxide thickness of the silicon oxide film in the nitride compound transistor according to the embodiment of the present invention is 50 nm and lOO nm. It is a figure which shows the relationship of a voltage.
  • FIGS. 2 (a) to 2 (d) are cross-sectional views showing a process of forming a nitride compound semiconductor transistor according to the first embodiment of the present invention.
  • FIGS. 3 (a) to 3 (d) are cross-sectional views showing a step of forming a nitride compound semiconductor transistor following FIG. 2 (d).
  • FIG. 4 is a schematic configuration diagram showing a film forming apparatus used for forming a nitride compound transistor according to an embodiment of the present invention.
  • FIGS. 5 (a) to 5 (d) are cross-sectional views showing the steps of forming a nitride compound semiconductor transistor according to the second embodiment of the present invention.
  • FIGS. 6 (a) to 6 (d) are cross-sectional views illustrating a nitride compound semiconductor transistor formation step subsequent to FIG. 5 (d).
  • FIG. 7 is a cross-sectional view showing a conventional HFET.
  • FIG. 8 is a cross-sectional view showing a MOSFET according to a conventional example.
  • FIG. 9 is a schematic diagram of a nitride compound semiconductor transistor according to a third embodiment of the present invention. It is a figure explaining a process.
  • FIG. 10 is a cross-sectional view showing a manufacturing step of the nitride compound semiconductor transistor according to the third embodiment.
  • FIGS. 11 (a) and 11 (b) are cross-sectional views showing manufacturing steps of the nitride compound semiconductor transistor according to the third embodiment.
  • FIG. 12 is a diagram showing the relationship between the inversion carrier density and the thickness of the gate insulating film of the nitride compound semiconductor transistor according to the third embodiment.
  • FIG. 13 is a diagram showing the relationship between the pinch-off voltage, the gate insulating film, and the mutual conductance of the nitride compound semiconductor transistor according to the third embodiment.
  • 14 (a) and 14 (b) are cross-sectional views showing another example of the manufacturing process of the nitride compound semiconductor transistor according to the third embodiment.
  • FIG. 15 is a cross-sectional view showing a manufacturing step of the nitride compound semiconductor transistor according to the fourth embodiment.
  • FIG. 16 is a cross-sectional view showing a manufacturing step of the nitride compound semiconductor transistor according to the fourth embodiment.
  • FIGS. 17 (a) and 17 (b) are cross-sectional views showing manufacturing steps of the nitride compound semiconductor transistor according to the fourth embodiment.
  • FIG. 18 is a diagram illustrating Si N films and gates of the nitride compound semiconductor transistor according to the fourth embodiment.
  • FIG. 3 4 is a diagram showing a relationship with a one-treak start voltage.
  • FIGS. 19 (a) and 19 (b) are cross-sectional views showing another example of the manufacturing process of the nitride compound semiconductor transistor according to the fourth embodiment.
  • FIGS. 20 (a) and 20 (b) are cross-sectional views showing another example of the manufacturing process of the nitride compound semiconductor transistor according to the fourth embodiment.
  • FIGS. 21 (a) and 21 (b) are cross-sectional views showing another example of the manufacturing process of the nitride compound semiconductor transistor according to the fourth embodiment.
  • Drain electrode 80 Gate electrode
  • nitride film Since nitrogen constituting the silicon nitride film has good compatibility with the nitride compound semiconductor layer, plasma damage of the nitride compound semiconductor layer is less than when silicon dioxide is formed using oxygen plasma. However, the dielectric breakdown strength of the silicon nitride film is about half that of the silicon dioxide film, and the breakdown voltage is low. Therefore, a silicon nitride film is formed on the nitride compound semiconductor layer, and a silicon dioxide film or the like is formed on the silicon nitride film, thereby reducing damage on the surface of the nitride compound semiconductor layer and increasing the pressure resistance. / A gate insulating film can be formed.
  • the method of forming a silicon nitride film is a force that can adopt a thermal CVD method as a plasma-free film-forming method, especially by a catalytic chemical vapor deposition method (Cat-CVD method (Catalytic Chemical Vap or Deposition)).
  • Cat-CVD method Catalytic Chemical Vap or Deposition
  • the damage on the surface of the nitride compound semiconductor layer can be reduced, and a dense silicon nitride film can be formed.
  • the thickness of the silicon nitride film is preferably 2 nm or more and 30 nm or less. When the thickness is 2 nm or less, it is difficult to form a dense film. When the thickness is 30 nm or more, the gate voltage is 10 V or less and leakage current is generated. To do.
  • the thickness of the silicon nitride film is preferably 5 nm or more and 10 nm or less.
  • the thickness of the silicon dioxide film is preferably 50 nm or more and lOOnm or less.
  • FIG. 1 shows an equivalent oxide thickness EOT of a silicon oxide film of 50 nm when a silicon dioxide film is formed as a second gate insulating film on a first gate insulating film made of a silicon nitride film. It is a figure which shows the relationship between the case and the leak start voltage in lOOnm.
  • the concept of the equivalent oxide film is used because a plurality of materials selected as insulating films are made of SiO. This is because it is convenient to convert the thickness.
  • the equivalent oxide thickness EOT of the silicon oxide film is defined by the following equation.
  • EOT is the equivalent oxide thickness.
  • ⁇ , ⁇ , and d are the SiO dielectric constant, the relative dielectric constant of the gate insulating film, and the thickness of the gate insulating film, respectively.
  • FIGS. 2 and 3 are cross-sectional views showing the manufacturing steps of the nitride compound semiconductor transistor according to the first embodiment of the present invention.
  • a buffer layer made of A1N or GaN and having a thickness of about 20 nm is formed on a substrate 1 made of sapphire, Si C, Si or the like by a metal organic chemical vapor deposition (MOCVD) method.
  • MOCVD metal organic chemical vapor deposition
  • 2 and a p-GaN layer 3 with a thickness of about 1 m are grown in order.
  • Mg is used as the p-type dopant, and the dopant concentration is, for example, 1 ⁇ 10 16 to 1 ⁇ 10 17 / cm 3 .
  • HVPE hydride vapor phase epitaxy
  • MBE molecular beam epitaxy
  • a photoresist 4 is applied on the p-GaN layer 3, and this is exposed and developed to form openings in the source region and the drain region.
  • An n + type dopant for example, silicon is implanted through the opening to form an n + type source region 5s and an n + type drain region 5d.
  • the n-type dopant concentration is, for example, 1 ⁇ 10 18 to 2 ⁇ 10 2 ° / cm 3 .
  • a silicon nitride film (SiN) film 6 is formed to a thickness of, for example, 5 nm by plasma-free catalytic chemical vapor deposition (Cat-CVD). ; Grows to Onm thickness.
  • the Cat-CVD method is performed, for example, using a film forming apparatus 11 as shown in FIG.
  • the chamber 12 is provided with an exhaust port 13 and a substrate transfer port 14.
  • a gas diffusion plate 16 is arranged for ejecting a reaction gas introduced from the outside toward the substrate placement table 15, and the substrate placement table 15 and the gas diffusion plate 16 are made of tandasten.
  • a linear catalyst body 17 is arranged. [0033] Then, the substrate 1 on which the p-GaN layer 3 is formed is placed on the substrate mounting table 15, the inside of the chamber 12 is decompressed, and a current is supplied to the catalyst body 17 from an AC power source (not shown) to 1800 ° C. ⁇ ; In a state where the temperature is raised to about 1900 ° C, the source gas of silane (SiH) and ammonia (NH) is
  • the source gas When released from the gas diffusion plate 16 toward the p-GaN layer 3, the source gas is decomposed by the catalyst body 17 to generate active species, and thereby a silicon nitride film 6 is formed on the surface of the P-GaN layer 3. It is.
  • a silicon oxide film (SiO film) 7 is formed on the silicon nitride film 6 to a thickness of about 50 nm to about OO nm. Since the underlying silicon oxide film 7 is the silicon nitride film 6, the p-GaN layer 3 is hardly damaged by either the Cat-CVD method or the plasma CVD method. In this case, for example, silane and oxygen are used as the reaction gas.
  • An alumina (Al 2 O 3) film may be formed instead of the silicon oxide film 7.
  • a conductive film 8 is formed on the silicon oxide film 7.
  • the conductive film 8 may be a metal film such as a force S, Ni / Al, or WSi in which polysilicon is generally used.
  • polysilicon As, P (phosphorus), B (boron), etc. are doped and grown by the CVD method, and in the case of a metal film, it is formed by sputtering or the like.
  • a photoresist 9 is applied on the conductive film 8, and is exposed and developed to leave it in the gate region, and is removed from above the source region 5s and the drain region 5d.
  • the conductive film 8 the silicon oxide film 7 and the silicon nitride film 6 were etched using the patterned photoresist 9 as a mask and left in the gate region.
  • the conductive film 8 is used as a gate electrode 8g.
  • the silicon oxide film 7 and the silicon nitride film 6 under the gate electrode 8g function as a gate insulating film.
  • FIG. 3 (c) After removing the photoresist 9, a lift-off method using another photoresist (not shown) is used, as shown in FIG. 3 (d). At the same time as forming the source electrode 10s on the region 5s, the drain electrode 10d is formed on the drain region 5d.
  • the source electrode 10s and the drain electrode 10d are made of a film such as Ti / Al, Ti / AlSi, and Mo, and are in ohmic contact with the n + —GaN layer constituting the drain region 5d and the source region 5s. .
  • a normally-off type MOSFET is formed by the above process.
  • the lower part of the gate insulating film is composed of the silicon nitride film 6.
  • the formation of the silicon nitride film 6 by the Cat-CVD method causes little damage to the p-GaN layer 3 below it. Compared with the thermal CVD method, it becomes a dense film.
  • the dielectric breakdown strength can be increased.
  • the film thickness is thicker than that of the silicon nitride film 6, the dielectric breakdown strength can be made to depend on the silicon oxide film 7 or the alumina film. Therefore, it is sufficient that the silicon nitride film 6 has a thickness that can avoid damage to the p-GaN layer 3 when the silicon oxide film 7 or the alumina film is formed.
  • a force S, n-type GaN layer in which the p-GaN layer 3 is formed as the channel region may be used, or other III-V group nitride compound semiconductor layers may be formed. Also good.
  • FIG. 5 and FIG. 6 are cross-sectional views showing the manufacturing process of the nitride compound semiconductor transistor according to the second embodiment of the present invention.
  • a running layer 23 and an electron supply layer 24 made of AlGaN having a thickness of about 20 nm are sequentially formed.
  • the electron transit layer 23 and the electron supply layer 24 are heterojunction, and two-dimensional electron gas 3D is generated at the interface.
  • the substrate is not limited to a sapphire substrate, but other substrates such as SiC, Si, and GaN may be used! /.
  • the electron supply A silicon nitride film 25 is grown on the layer 24 by a Cat-CVD method to a thickness of, for example, 5 nm to! Onm.
  • the growth of the silicon nitride film 25 by the Cat-CVD method is the same as in the first embodiment.
  • a silicon oxide film 26 is formed on the silicon nitride film 25. 50 nm ⁇ ; formed to a thickness of about OOnm.
  • the silicon oxide film 26 has the silicon nitride film 25 underneath, so that neither the Cat-CVD method nor the plasma CVD method causes any damage to the p-GaN layer 3.
  • An alumina film may be formed instead of the silicon oxide film 26.
  • a photoresist 27 is applied on the silicon oxide film 26, and this is exposed and developed to form windows 27s and 27d in the source region and the drain region, respectively. .
  • the silicon oxide film 27 and the silicon nitride film 26 are etched using the photoresist 27 as a mask to form openings 26s and 26d.
  • the Ti / A metal film is formed on the electron supply layer 24 through the openings 26s and 26d and is selectively left in the source region and the drain region, and is applied as the source electrode 28s and the drain electrode 28d.
  • the source electrode 28s and the drain electrode 28d are in ohmic contact with the electron supply layer 24.
  • the metal film to be the source electrode 28s and the drain electrode 28d may be a metal such as Ti / AlSi / Mo that is in ohmic contact with the electron supply layer 24.
  • Photoresist 29 is applied on 28d, and this is exposed and developed to form a window 29g in the gate region.
  • the window 29g is formed in a region between the drain electrode 28d and the source electrode 28s.
  • the 28d force is arranged at an interval of about 15-20 tim and at an interval of about 3 ⁇ m from the source electrode 28s.
  • an n-type or p-type polysilicon film or a metal film such as Ni / Au or WSi is sequentially laminated on the electron supply layer 24 through the window 29g by sputtering or the like. Then, by removing the photoresist 29, the gate electrode 30 is formed on the electron supply layer 4 via the silicon oxide film 26 and the silicon nitride film 25 as shown in FIG. 6 (d).
  • an HFET having a MIS (metaHnsulator-semiconductor) structure is formed.
  • the silicon oxide film 26 and the silicon nitride film 25 under the gate electrode 30 function as a gate insulating film.
  • the lower layer portion of the gate insulating film is composed of the silicon nitride film 25, and when the silicon nitride film 25 is formed by the Cat-CVD method, the damage to the electron supply layer 24 below it is small.
  • the combing force is also a dense film compared to the thermal CVD method.
  • Mobility force S larger than conventional.
  • the dielectric breakdown strength can be increased.
  • the film thickness is thicker than that of the silicon nitride film 25, the dielectric breakdown strength can be made to depend on the silicon oxide film 26 or the alumina film. Therefore, it is sufficient that the silicon nitride film 25 has a thickness that can avoid damage to the electron supply layer 24 and the electron transit layer 23.
  • the AlGaN / GaN heterojunction structure is formed on the substrate 21, but other group IIIV nitride semiconductor layers may be formed on the substrate.
  • the nitride compound semiconductor device transistor according to the first embodiment and the nitride compound semiconductor device transistor according to the second embodiment as described above are a multi-current multi-current operation transistor formed on the same substrate. Even if it constitutes a finger FET, multilayer wiring is formed as necessary and unit FETs are connected.
  • the transistor described above has the force S described for the planar type, and the vertical type in which the nitride compound semiconductor layer is formed in a mesa shape and the gate electrode is formed on the side surface of the transistor is nitrided with the gate electrode.
  • a gate insulating film having a Cat-CVD silicon nitride film as described above may be formed between the physical compound semiconductor layers.
  • the gate insulating film has a two-layer structure, it may have more than one structure! /
  • MOSFET oxide semiconductor field effect transistor
  • a buffer layer 2 made of A1N having a thickness of, for example, lOOnm is formed on a substrate 1 that is a Si substrate by a metal organic chemical vapor deposition (MOCV D) method.
  • MOCV D metal organic chemical vapor deposition
  • the buffer layer 2 is grown by setting the substrate temperature to 1100 ° C. and using trimethylaluminum (TMA) and ammonia (NH 3) as reaction gases.
  • TMA trimethylaluminum
  • NH 3 ammonia
  • the GaN layer 3 is grown by setting the substrate temperature to 1100 ° C. and using trimethyl gallium (TMG) and NH as reaction gases.
  • the GaN layer 3 can be doped with magnesium (Mg) as a p-type dopant.
  • Mg magnesium
  • the addition amount of Mg is set to 5 ⁇ 10 15 cm ⁇ 3 to 5 ⁇ 10 17 cm ⁇ 3 .
  • a substrate such as alumina or silicon carbide can also be used as the substrate 1.
  • a halide vapor phase epitaxy method (HVPE method) or a molecular beam epitaxy method (MBE) can be used.
  • an element isolation region 3a is formed through a photolithographic process and an etching process.
  • an opening region corresponding to the element isolation region 3a is formed by applying a photoresist after exposure and developing, and as an etching process, a reactive ion etching (RIE) method, inductively coupled plasma ( The GaN layer 3 corresponding to the opening region is etched using the (ICP) etching method, and the photoresist is removed.
  • RIE reactive ion etching
  • a photoresist 13 is applied and exposed and developed, so that the source formation region and the drain formation region are formed.
  • An opening is formed in Then, the mask layer 12 corresponding to the opening is etched using buffered hydrofluoric acid to form the opening 12s and the opening 12d as shown in FIG. 9 (c).
  • silicon that is an n-type dopant is implanted into the GaN layer 3 by ion implantation. As a result, n + -type dose regions 4a and 4b are formed in the openings 12s and 12d.
  • the mask layer 12 is removed using a hydrofluoric acid aqueous solution.
  • the impurities in the n + -type dose regions 4a and 4b are activated by annealing, for example, at 1300 ° C for 5 minutes in a nitrogen (N) atmosphere.
  • a source region 4s and a drain region 4d are obtained.
  • an inert gas such as argon (Ar) may be introduced instead of the nitrogen atmosphere to activate the impurities in the n + -type dose regions 4a and 4b.
  • the source region 4s and the drain region 4d may use a selective growth method or a thermal diffusion method in which an n-type layer is grown using a dielectric film such as a silicon oxide film or a silicon nitride film as a mask.
  • an SiO 2 film 5 that functions as a gate insulating film is formed on the surface of the GaN layer 3.
  • This SiO film is formed in the ECR sputtering apparatus 15 by using an ECR sputtering method using electron cyclotron resonance (ECR).
  • ECR electron cyclotron resonance
  • a source electrode 60 and a drain electrode 70 made of Ti / Al are formed on the source region 4s and the drain region 4d exposed from the opening 50s and the opening 50d, respectively.
  • the source electrode 60 and the drain electrode 70 are formed using a lift-off method in which a photoresist is removed after forming a metal by a sputtering method or an EB method with a region other than the electrode formation region covered with a photoresist.
  • the source electrode 60 and the drain electrode 70 are in ohmic contact with the n + -type dose regions 4a and 4b in the p-type GaN layer 3, respectively. Note that the source electrode 60 and the drain electrode 70 need only be able to achieve ohmic contact with the n + -type dose regions 4a and 4b, and may be formed using a material other than Ti / Al.
  • poly-Si polycrystalline silicon
  • LP low pressure
  • sputtering method a heat treatment in a phosphorus trichloride (POC1) gas is performed, whereby poly — Doping P into the Si film.
  • the impurity doping into the poly-Si film may be performed by adding impurities during film formation or by performing thermal diffusion after film formation.
  • the gate electrode 8 includes a boron-doped poly-Si film, polycrystalline silicon germanium (SiGe) film, aluminum (A1), gold (Au), palladium (Pd), platinum (Pt), nickel (Ni ), Tantalum (Ta), molybdenum (Mo), tungsten (W), or a silicide film of these metals.
  • the MOSFET 10 in which the SiO film 5 as the gate insulating film is formed between the GaN layer 3 and the gate electrode 8 stacked on the substrate is manufactured.
  • the step of forming the SiO film 5 which is a gate insulating film using the ECR sputtering method will be described in detail.
  • cyclotron resonance occurs by applying a microwave W m having the same frequency as the cyclotron frequency at which electrons in the magnetic field perform cyclotron motion, and rotates around the magnetic field lines at high speed.
  • High-density plasma is generated by collision of electrons with gas molecules in an Ar—O mixed gas with a large flow rate of O introduced into the plasma chamber.
  • the generated plasma is drawn out from the ECR region 16 as a plasma flow, sputters a target 17 that is silicon, enters the surface of the GaN layer 3, and forms a SiO film 5 on the GaN layer 3.
  • the film formation temperature is preferably 400 ° C. or higher in order to obtain a good film quality with reduced fixed charges in the film interface or film, which causes fluctuations in the threshold voltage of the MOSFET.
  • the energy of the particles incident on the sample became 50 eV or more, the atoms constituting the GaN layer were knocked out, and the damage to the GaN layer was significant.
  • the energy of the incident particles was as low as 0 leV, so the film adhesion was poor and the composition deviation was large.
  • the ECR sputtering method it is possible to change the energy of particles incident on the sample surface by changing the pressure or the like. For example, it is possible to maintain a stable high-density plasma at a low pressure on the order of 0. OlPa, and it can be incident on the sample surface with an energy of about 10-30 eV. Therefore, in the ECR sputtering method, energy suitable for film formation can be given to the particles incident on the sample surface, and thin film growth proceeds in a state where high-density particles whose energy is controlled are incident on the sample surface.
  • ECR sputtering it is possible to form a thin film with high bonding strength that is chemically stable, and good film quality close to that of the SiO film formed by thermal oxidation. Can be held.
  • the ECR sputtering method does not perform surface reaction, nitrogen desorption from the surface of the GaN layer, which is a problem in the CVD method, which is a surface reaction, can be reduced, and contamination by reaction products in the CVD method occurs. Therefore, a SiO film having a good film quality can be formed.
  • the gate insulating film is formed using the ECR sputtering method, a gate insulating film having a good film quality can be formed on the GaN layer.
  • This equivalent oxide thickness (EOT) is defined by the following equation.
  • ⁇ is the dielectric constant of SiO
  • ⁇ is the dielectric constant of the gate insulating film
  • d is the thickness of the gate insulating film.
  • the minimum value of the equivalent oxide film thickness in the SiO film 5 in the MOSFET 10 is preferably 20 nm or more in order to suppress the occurrence of gate leakage.
  • Figure 12 shows the relationship between the inversion carrier density and the gate insulating film thickness. Since the inversion carrier density is desirably as large as 5 ⁇ 10 U C m ⁇ 2 or more, for example, the gate insulating film is preferably 140 nm or less as shown in FIG.
  • Figure 13 shows the relationship between the pinch-off voltage, gate insulating film, and mutual conductance of MOS FET 10.
  • the maximum value of the gate insulating film is preferably equal to or less than l OOnm in consideration of a decrease in on-resistance and field effect mobility. Therefore, it is desirable that the equivalent oxide thickness of the SiO film 5 constituting the gate insulating film is 20 nm or more and lOOnm or less.
  • FIG. 14 (a) illustrates the case where the SiO film 5 having an energy band gap of 9. OeV is formed as the gate insulating film.
  • an Al 2 O film 5a having an energy band gap of 8.8 eV and a high energy band gap similar to the SiO film may be formed.
  • the Al 2 O film 5a can be formed on the GaN layer 3 by using the target 17a that is A1.
  • the source electrode 60, the drain electrode 70, and the gate electrode 80 are formed by performing the same process as the process shown in FIG. As a result, it is possible to manufacture MOSFET I Oa shown in FIG. 14 (b).
  • a fourth embodiment of the present invention will be described.
  • a MOSFET which is a nitride compound semiconductor transistor according to the fourth embodiment! /
  • gate insulation is performed between the GaN layer and the SiO film together with the SiO film.
  • a nitride film functioning as a film is formed.
  • 15 to 17 are diagrams for explaining the MOSFET manufacturing method according to the present embodiment.
  • an ECR sputtering method is used.
  • a SiN film 250 is formed on the GaN layer 3.
  • nitrogen gas is allowed to flow through the ECR region 16.
  • a SiN film can be formed on the surface of the GaN layer 3.
  • the SiO film 5 is formed on the Si N film 250 by flowing an Ar—O mixed gas having a large flow rate of O into the ECR region 16 as in the case shown in FIG. Form.
  • the oxide film thickness is preferably 20 nm or more and lOOnm or less.
  • the openings are formed on the source region 4s and the drain region 4d. 25s and opening 25d are formed.
  • the gate electrode 80 is formed on the SiO film 5 to manufacture the MOSFET 20.
  • the SiN film 250 is formed between the GaN layer 3 and the SiO film 5 that is the gate insulating film by using the ECR sputtering method. La Since surface reaction using dical is not performed, it is possible to suppress nitrogen desorption from the surface of the GaN layer due to radicals.
  • nitrogen in the GaN layer 3 is formed in order to form the SiN film 250 in a nitrogen atmosphere by flowing nitrogen gas.
  • the Si N film 250 is formed using the ECR sputtering method.
  • the Si N film 250 is provided between the SiO film 5 and the GaN layer 3.
  • FIG. 50 is preferably 2 nm or more because a film having a thickness of 2 nm or more can be stably formed.
  • the maximum value of the SiN film 250 will be described.
  • Figure 18 shows the fourth embodiment.
  • a curve 110 in FIG. 18 shows the case where the equivalent oxide thickness of the gate insulating film is lOOnm
  • the curve 120 shows a case where the equivalent oxide thickness of the gate insulating film is 50 nm.
  • the equivalent oxide thickness of the gate insulating film is lOOnm, as shown by the curve 110, the thickness of the SiN film 25 is desirably 30 nm or less.
  • the equivalent oxide thickness is 50
  • the film thickness of the Si N film 250 is 15 nm or less as shown by the curve 120.
  • the film thickness of the Si N film 250 formed on the GaN layer 3 is 2 nm.
  • the Si N film 250 is used as a nitride film formed on the GaN layer 3.
  • the source electrode 60, the drain electrode 70, and the gate electrode 80 are formed.
  • the MOSFET 20a shown in FIG. 19 (b) can be manufactured.
  • the thickness of the A1N film 250a is the same as that of the Si N film.
  • an A1N film 250a is formed on the GaN layer 3 by flowing nitrogen gas using an A1 target 17a, and then replaced with a Si target 17 and mixed with Ar—O.
  • the SiO film 5 may be formed on the A1N film 250a by flowing a gas.
  • the source electrode 60, the drain electrode 70, and the gate electrode 80 are formed by performing the same process as the process shown in FIG. As a result, the MOSFET 20b shown in FIG. 20 (b) can be manufactured.
  • a SiN film 250 is formed on the GaN layer 3 by flowing nitrogen gas using the target 17, and then replaced with the target 17a of A1, and an Ar—O mixed gas Shed
  • the Al 2 O film 5a may be formed on the Si N film 250. Then, as shown in FIG.
  • the source electrode 60, the drain electrode 70, and the gate electrode 80 are formed by performing the same process as described above. As a result, the MOSFET 20b shown in FIG. 21 (b) can be manufactured.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne un transistor à semi-conducteur de composé de nitrure qui comprend une couche à semi-conducteur de composé de nitrure (3) formée sur un substrat (1), un premier film isolant de grille composé d'un film de nitrure de silicium (6) formé sur la couche à semi-conducteur de composé de nitrure (3), un second film isolant de grille composé d'un film d'oxyde de silicium (7) formé sur le film de nitrure de silicium (6) et qui présente une résistance au claquage diélectrique supérieure au film de nitrure de silicium (6), une électrode grille (8g) formée sur le second film isolant de grille, et des électrodes ohmiques (10s, 10d) en contact ohmique avec des couches à semi-conducteur de composé de nitrure (5s, 5d) sur les côtés de l'électrode grille (8g).
PCT/JP2007/070293 2006-10-17 2007-10-17 Transistor à semi-conducteur de composé de nitrure et son procédé de fabrication WO2008047845A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2006-282772 2006-10-17
JP2006282772A JP2008103408A (ja) 2006-10-17 2006-10-17 窒化物化合物半導体トランジスタ及びその製造方法
JP2006-293026 2006-10-27
JP2006293026A JP2008112750A (ja) 2006-10-27 2006-10-27 半導体素子製造方法

Publications (1)

Publication Number Publication Date
WO2008047845A1 true WO2008047845A1 (fr) 2008-04-24

Family

ID=39314067

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/070293 WO2008047845A1 (fr) 2006-10-17 2007-10-17 Transistor à semi-conducteur de composé de nitrure et son procédé de fabrication

Country Status (1)

Country Link
WO (1) WO2008047845A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017055136A (ja) * 2010-04-23 2017-03-16 株式会社半導体エネルギー研究所 半導体装置の作製方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000252458A (ja) * 1999-03-04 2000-09-14 Sony Corp 半導体素子
JP2005251877A (ja) * 2004-03-02 2005-09-15 Semiconductor Leading Edge Technologies Inc シリコン窒化膜の形成方法
JP2006222191A (ja) * 2005-02-09 2006-08-24 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
JP2006269673A (ja) * 2005-03-23 2006-10-05 Nec Electronics Corp 半導体装置およびその製造方法
JP2007067240A (ja) * 2005-08-31 2007-03-15 Toshiba Corp 窒化物系半導体装置
JP2007227621A (ja) * 2006-02-23 2007-09-06 Toyota Central Res & Dev Lab Inc 絶縁ゲート構造体を有する半導体装置とその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000252458A (ja) * 1999-03-04 2000-09-14 Sony Corp 半導体素子
JP2005251877A (ja) * 2004-03-02 2005-09-15 Semiconductor Leading Edge Technologies Inc シリコン窒化膜の形成方法
JP2006222191A (ja) * 2005-02-09 2006-08-24 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
JP2006269673A (ja) * 2005-03-23 2006-10-05 Nec Electronics Corp 半導体装置およびその製造方法
JP2007067240A (ja) * 2005-08-31 2007-03-15 Toshiba Corp 窒化物系半導体装置
JP2007227621A (ja) * 2006-02-23 2007-09-06 Toyota Central Res & Dev Lab Inc 絶縁ゲート構造体を有する半導体装置とその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MAEDA N. ET AL.: "Al2O3/Si3N4 Insulated Gate Channel-Doped AlGaN/GaN Heterostructure Field-Effect Transistors with Regrown Ohmic Structure: Low Gate Leakage Current with High Transconductance", JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 44, no. 4B, 2005, pages 2747 - 2750, XP055035642, DOI: doi:10.1143/JJAP.44.2747 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017055136A (ja) * 2010-04-23 2017-03-16 株式会社半導体エネルギー研究所 半導体装置の作製方法

Similar Documents

Publication Publication Date Title
CA2634068C (fr) Procedes de fabrication de transistors a electrodes de grilles supportees et dispositifs connexes
US7230284B2 (en) Insulating gate AlGaN/GaN HEMT
JP5730481B2 (ja) 自己整合した耐熱性コンタクトを備える半導体デバイス及びその作製方法
EP3413353A1 (fr) Transistor hemt normalement à l&#39;arrêt avec génération sélective de canal 2deg et son procédé de fabrication
US8093627B2 (en) Nitride semiconductor device and method for producing nitride semiconductor device
JPH10223901A (ja) 電界効果型トランジスタおよびその製造方法
WO2005015642A1 (fr) Dispositif a semi-conducteur et procede de fabrication correspondant
JP2008103408A (ja) 窒化物化合物半導体トランジスタ及びその製造方法
EP2544240B1 (fr) Transistor semi-conducteur
JP2010171416A (ja) 半導体装置、半導体装置の製造方法および半導体装置のリーク電流低減方法
JP4776162B2 (ja) 高電子移動度トランジスタ及び高電子移動度トランジスタの製造方法
KR20080011647A (ko) Ⅲ-ⅴ족 질화물계 화합물 반도체장치 및 전극형성방법
US20100047976A1 (en) Method for forming nitride semiconductor laminated structure and method for manufacturing nitride semiconductor element
JP4906023B2 (ja) ＧａＮ系半導体装置
JP2008091699A (ja) 半導体トランジスタの製造方法
JP2004165387A (ja) ＧａＮ系電界効果トランジスタ
JP3423598B2 (ja) ＧａＮ系絶縁ゲート型トランジスタ及びその形成方法
JP2008112750A (ja) 半導体素子製造方法
JP5101143B2 (ja) 電界効果トランジスタ及びその製造方法
JP2001102565A (ja) 半導体装置及びその製造方法
JP4228250B2 (ja) 化合物半導体装置
WO2008047845A1 (fr) Transistor à semi-conducteur de composé de nitrure et son procédé de fabrication
JP2006261474A (ja) 窒化物系半導体デバイス
CN114864505A (zh) 一种GaN HEMT和GaOx MOSFET异构反相器的制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07830027

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07830027

Country of ref document: EP

Kind code of ref document: A1