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Methods of controlling morphology during epitaxial layer formation

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Publication number
WO2008033186A1
WO2008033186A1 PCT/US2007/017053 US2007017053W WO2008033186A1 WO 2008033186 A1 WO2008033186 A1 WO 2008033186A1 US 2007017053 W US2007017053 W US 2007017053W WO 2008033186 A1 WO2008033186 A1 WO 2008033186A1
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Patent type
Prior art keywords
epitaxial
process
substrate
deposition
method
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PCT/US2007/017053
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French (fr)
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Yihwan Kim
Andrew M. Lam
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Applied Materials, Inc.
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL-GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL-GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639Preparation of substrate for selective deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02658Pretreatments
    • H01L21/02661In-situ cleaning

Abstract

A first aspect of the invention provides a method of selectively forming an epitaxial layer on a substrate. The method includes heating the substrate to a temperature of less than about 800°C and employing both silane and dichlorosilane as silicon sources during epitaxial film formation. Numerous other aspects are provided.

Description

METHODS OF CONTROLLING MORPHOLOGY DURING EPITAXIAL LAYER FORMATION

The present application claims priority from U.S.

Provisional Patent Application Serial No. 60/820,956, filed July 31, 2006, which is hereby incorporated by reference herein in its entirety.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is related to the following co-pending applications, each of which is hereby incorporated by reference herein in its entirety:

U.S. Patent Application Serial No. 11/001,774, filed December 1, 2004 (Docket No. 9618); and

U.S. Patent Application Serial No. 11/227,974, filed September 14, 2005 (Docket No. 9618/P01) .

FIELD OF THE INVENTION The present invention relates to semiconductor device manufacturing, and more particularly to methods of controlling morphology during epitaxial layer formation.

BACKGROUND As smaller transistors are manufactured, ultra shallow source/drain junctions are becoming more challenging to produce. Generally, sub-100 nm CMOS (complementary metal-oxide semiconductor) devices require a junction depth to be less than 30 nm. Selective epitaxial deposition is often utilized to form epilayers of silicon-containing materials (e.g., Si, SiGe and SiC) into the junctions. Generally, selective epitaxial deposition permits growth of epilayers on silicon moats with no growth on dielectric areas. Selective epitaxy can be used within semiconductor devices, such as elevated source/drains, source/drain extensions, contact plugs or base layer deposition of bipolar devices.

Generally, a selective epitaxy process involves a deposition reaction and an etch reaction. The deposition and etch reactions occur simultaneously with relatively different reaction rates to an epitaxial layer and to a polycrystalline layer. During the deposition process, the epitaxial layer is formed on a monocrystalline surface while a polycrystalline layer is deposited on at least a second layer, such as an existing polycrystalline layer and/or an amorphous layer. However, the deposited polycrystalline layer is generally etched at a faster rate than the epitaxial layer. Therefore, by changing the concentration of an etchant gas, the net selective process results in deposition of epitaxy material and limited, or no, deposition of polycrystalline material. For example, a selective epitaxy process may result in the formation of an epilayer of silicon-containing material on a monocrystalline silicon surface while no deposition is left on a spacer region.

Selective epitaxy deposition of silicon-containing materials has become a useful technique during formation of elevated source/drain and source/drain extension features, for example, during the formation of silicon-containing MOSFET (metal oxide semiconductor field effect transistor) devices. Source/drain extension features are manufactured by etching a silicon surface to make a recessed source/drain feature and subsequently filling the etched surface with a selectively grown epilayer, such as a silicon germanium (SiGe) material. Selective epitaxy permits near complete dopant activation with in-situ doping, so that the post annealing process is omitted. Therefore, junction depth can be defined accurately by silicon etching and selective epitaxy. On the other hand, the ultra shallow source/drain junction inevitably results in increased series resistance. Also, junction consumption during suicide formation increases the series resistance even further. In order to compensate for junction consumption, an elevated source/drain is epitaxially and selectively grown on the junction. Typically, the elevated source/drain layer is undoped silicon.

However, current selective epitaxy processes have some drawbacks. In order to maintain selectivity during present epitaxy processes, chemical concentrations of the precursors, as well as reaction temperatures must be regulated and adjusted throughout the deposition process. If not enough silicon precursor is administered, then the etching reaction may dominate and the overall process is slowed down. Also, harmful over etching of substrate features may occur. If not enough etchant precursor is administered, then the deposition reaction may dominate reducing the selectivity to form monocrystalline and polycrystalline materials across the substrate surface. Also, current selective epitaxy processes usually require a high reaction temperature, such as about 8000C, 1,0000C or higher. Such high temperatures are not desirable during a fabrication process due to thermal budget considerations and possible uncontrolled nitridation reactions to the substrate surface.

Therefore, there is a need to have a process for selectively and epitaxially depositing silicon and silicon- containing compounds with optional dopants. Furthermore, the process should be versatile to form silicon-containing compounds with varied elemental concentrations while having a fast deposition rate, smooth surface morphology and maintaining a process temperature, such as about 8000C or less, and preferably about 7000C or less. SUMMARY OF INVENTION

A first aspect of the invention provides a method of selectively forming an epitaxial layer on a substrate. The method includes heating the substrate to a temperature of less than about 8000C and employing both silane and dichlorosilane as silicon sources during selective epitaxial film formation.

In another aspect of the invention a method of selectively forming an epitaxial layer on a substrate is provided. The method includes at least one deposition step and at least one etching step which are alternated. The method includes heating the substrate to a temperature of less than about 8000C. The deposition step employs both silane and dichlorosilane as silicon sources. Each of the silicon source gases are flowed at a rate from about 10 to 100 seem at a chamber pressure of about 5 to 50 Torr. The etching step includes flowing at least one of hydrogen chloride and chlorine . In another aspect of the invention, a method of forming an epitaxial layer on a substrate is provided. The method includes (1) heating the substrate to a temperature of less than about 8000C; and (2) performing a selective epitaxial film formation process on the substrate so as to form the epitaxial layer by employing both silane and dichlorosilane as silicon sources during the selective epitaxial film formation process. A ratio of silane to dichlorosilane is greater than 1. Numerous other aspects are provided. Other features and aspects of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings. DESCRIPTION OF DRAWINGS

FIG. 1 is a flowchart of a first exemplary method for forming an epitaxial film in accordance with the present invention . FIG. 2 is a flowchart of a second exemplary method for forming an epitaxial film in accordance with the present invention .

DETAILED DESCRIPTION During a selective epitaxial growth process on a silicon substrate patterned with dielectric films, formation of single-crystal semiconductor occurs only on the exposed silicon surfaces (e.g., not on the dielectric surfaces). Selective thickness is defined as the maximum film thickness obtained on the silicon surfaces prior to the onset of film growth or nucleation on the dielectric surfaces .

Selective epitaxial growth processes may include simultaneous etch-deposition processes as well as alternating gas supply processes. In a simultaneous etch- deposition process, both etchant species and deposition species are flowed simultaneously. As such, an epitaxial layer is simultaneously deposited and etched during its formation .

U.S. Patent Application Serial No. 11/001,774, filed December 1, 2004 (Docket No. 9618), describes an alternating gas supply (AGS) process for forming epitaxial layers on a substrate. During an AGS process, an epitaxial deposition process is conducted on a substrate, and then an etching process is conducted on the substrate. The cycle of an epitaxial deposition process followed by an etching process is repeated until a desired thickness of an epitaxial layer is formed.

An alternative precursor for selective silicon epitaxy at deposition temperatures less than 8000C is silane (SiH4) . At such lower temperatures, SiH4 has a higher growth rate than dichlorosilane (DCS) . However, the present inventors have observed that an SiH4-based process may introduce morphology issues (e.g., surface roughness or pitting) . In at least one embodiment of the invention, observed morphology issues associated with the use of SiH4 may be reduced and/or eliminated by employing both SiH4 and DCS (e.g., by mixing SiH4 and DCS during film growth). This approach is believed to alter the diffusion mechanism on the film's surface, allowing greater morphology control.

In some embodiments, the present invention may be employed with the AGS process described in U.S. Patent Application Serial No. 11/001,774, filed December 1, 2004 (Docket No. 9618), although the present invention may be used with other selective epitaxial processes.

Silicon epitaxial films formed using a selective process with only SiH4 as a silicon source (e.g., during an AGS process) were found to have surfaces that are rough and pitted. Silicon epitaxial films formed using a selective process with both SiH4 and DCS as silicon sources (e.g., during an AGS process) were found to have improved film morphology, such as improved surface smoothness (e.g., without pitting) . Unlike other approaches such as a post- deposition smoothing step, the use of SiH4 and DCS allows for in-situ control of film morphology (e.g., during epitaxial film formation) without additional process steps.

In some embodiments, an example of a process which may use a silicon source as described above may include about 10 seem to about 100 seem of silane. In addition, the silicon source may include about 10 seem to about 100 seem of dichlorosilane. In this example, during a deposition cycle in an AGS process, a chamber pressure in a range of about 5 Torr to about 50 Torr with a deposition time of about 2 to 250 seconds, and more preferably about 5 to 10 seconds and a temperature in a range between about 7000C and about 7500C may be employed. In some embodiments, an SiH4 to DCS ratio of greater than 1 may be employed, such as 2:1, 3:1, 4:1, 5:1, 7:1, 10:1, etc., (SiH4:DCS). After the deposition cycle, an etchant process may be employed, for example, with about 50 seem to about 500 seem of hydrogen chloride (HCl) as the etchant, a chamber pressure of about 5 Torr to about 100 Torr with a deposition time of about 2 to 250 seconds, and more preferably about 5 to 10 seconds, and a temperature in a range between about 7000C and about 7500C. After the etch cycle, a purge cycle may be conducted for about 10 seconds at a pressure of about 5 to about 50 Torr at a temperature in a range between about 7000C and about 7500C. Other process times, temperatures and/or flow rates may be used during deposition, etching and/or purging. For example, chlorine (Cl2) or a combination of Cl2 and HCl may be employed during each etch step as described in U.S. Patent Application Serial No. 11/227,974, filed September 14, 2005 (Docket No. 9618/P01) .

FIG. 1 is a flowchart of a first exemplary method 100 for forming an epitaxial film in accordance with the present invention. With reference to FIG. 1, in step 101, a substrate is loaded into a process chamber and is heated to a temperature of about 800 0C or less. In some embodiments, a lower temperature range may be used during epitaxial film formation, such as less than 7500C, less than 7000C or less than 6500C.

In step 102, silane and dichlorosilane are flowed into the process chamber, along with a suitable carrier gas and/or dopant (s) so as to form an epitaxial film on the substrate. In some embodiments, one or more etchant gases such as HCl, Cl2, a combination of HCl and Cl2, etc., may be flowed at the same time as the silicon source gasses (e.g., during a simultaneous deposition-etch process). In other embodiments, a separate etchant step may be employed following deposition (e.g., during an AGS process) . Deposition and etching are continued until the desired epitaxial film thickness is achieved. In some embodiments, an SiH4 to DCS ratio of greater than 1 may be employed, such as 2:1, 3:1, 4:1, 5:1, 7:1, 10:1, etc., (SiH4:DCS). Other silicon source ratios may be used.

FIG. 2 is a flowchart of a second exemplary method 200 for forming an epitaxial film in accordance with the present invention. With reference to FIG. 2, in step 201, a substrate is loaded into a process chamber and is heated to a temperature of about 800 0C or less. In some embodiments, a lower temperature range may be used during epitaxial film formation, such as less than 7500C, less than 7000C or less than 6500C.

In step 202, silane and dichlorosilane are flowed into the process chamber, along with a suitable carrier gas and/or dopant (s) so as to form an epitaxial film on the substrate. In some embodiments, about 10 seem to about 100 seem of silane may be employed, as may be about 10 seem to about 100 seem of dichlorosilane. A pressure in a range of about 5 Torr to about 50 Torr may be employed. Deposition may be performed for about 2 to 250 seconds, and more preferably about 5 to 10 seconds. In some embodiments, an SiH4 to DCS ratio of greater than 1 may be employed, such as 2:1, 3:1, 4:1, 5:1, 7:1, 10:1, etc., (SiH4:DCS). Other flow rates, pressures, temperatures, times and/or SiH4: DCS ratios may be used.

In step 203, an etchant gas such as HCl and/or CI2 is flowed into the process chamber, along with a suitable carrier gas so as to etch material deposited during step 202 For example, the substrate may be etched with about 50 seem to about 500 seem of hydrogen chloride (HCl) as the etchant at a chamber pressure of about 5 Torr to about 100 Torr for about 2 to 250 seconds, and more preferably about 5 to 10 seconds. Other etchants, flow rates, pressures and/or times may be used. In step 204, after the etch cycle, a purge cycle may be conducted for about 2 to 250 seconds, and more preferably about 5 to 10 seconds. Other purge times may be used. In step 205, a determination is made whether the desired epitaxial film thickness has been reached. If so, the process ends in step 206; otherwise, the process returns to step 202 to deposit additional epitaxial material on the substrate . The foregoing description discloses only exemplary embodiments of the invention. Modifications of the above disclosed apparatus and methods which fall within the scope of the invention will be readily apparent to those of ordinary skill in the art. For instance, a lower temperature range may be used during epitaxial film formation, such as less than 7500C, less than 7000C or less than 6500C.

Accordingly, while the present invention has been disclosed in connection with exemplary embodiments thereof, it should be understood that other embodiments may fall within the spirit and scope of the invention, as defined by the following claims.

Claims

THE INVENTION CLAIMED IS:
1. A method of forming an epitaxial layer comprising: providing a substrate; heating the substrate to a temperature of less than about 8000C; and performing a selective epitaxial film formation process on the substrate so as to form the epitaxial layer by employing both silane and dichlorosilane as silicon sources during the selective epitaxial film formation process.
2. The method of claim 1 wherein heating the substrate comprises heating the substrate to a temperature of less than about 7500C.
3. The method of claim 1 wherein heating the substrate comprises heating the substrate to a temperature of less than about 7000C.
4. The method of claim 1 wherein heating the substrate comprises heating the substrate to a temperature of less than about 650°C.
5. The method of claim 1 wherein performing the selective epitaxial film formation process comprises: flowing silane and dichlorosilane; and flowing an etching gas that includes at least one of hydrogen chloride (HCl) and chlorine (CI2) .
6. The method of claim 1 wherein performing the selective epitaxial film formation process comprises performing a deposition step followed by an etching step.
7. The method of claim 6 wherein performing the deposition step includes providing a flow of silane and a flow of dichlorosilane .
8. The method of claim 7 wherein the flow of silane is about 10 to 100 seem.
9. The method of claim 7 wherein the flow of dichlorosilane is about 10 to 100 seem.
10. The method of claim 7 wherein performing the deposition step includes employing a process pressure of about 5 to 50 Torr .
11. The method of claim 7 wherein performing the deposition step includes flowing silane and dichlorosilane for up to about 10 seconds.
12. The method of claim 6 wherein performing the etching step includes flowing an etching gas that includes at least one of hydrogen chloride (HCl) and chlorine (CI2) •
13. The method of claim 12 wherein the flow of etching gas is about 50 to 500 seem.
14. The method of claim 12 wherein performing the etching step includes employing a process pressure of about 5 to 100 Torr.
15. The method of claim 12 wherein the etching step includes flowing etching gas for up to about 10 seconds.
16. The method of claim 6 further comprising at least one purging step.
17. A method of forming an epitaxial layer comprising: providing a substrate; heating the substrate to a temperature of less than about 8000C; performing a selective epitaxial film formation process comprising at least one deposition step and at least one etching step: wherein the deposition step and etching step are alternated; wherein the deposition step includes flowing silane and dichlorosilane each at a flow rate from about 10 to 100 seem at a deposition pressure from about 5 to 50 Torr; and wherein the etching step includes flowing at least one of hydrogen chloride and chlorine.
18. The method of claim 17 wherein the selective epitaxial film formation processes further comprises at least one purging step.
19. The method of claim 17 wherein heating the substrate comprises heating the substrate to a temperature of less than about 7500C.
20. The method of claim 17 wherein heating the substrate comprises heating the substrate to a temperature of less than about 7000C.
21. The method of claim 17 wherein heating the substrate comprises heating the substrate to a temperature of less than about 6500C.
22. A method of forming an epitaxial layer comprising: providing a substrate; heating the substrate to a temperature of less than about 8000C; and performing a selective epitaxial film formation process on the substrate so as to form the epitaxial layer by employing both silane and dichlorosilane as silicon sources during the selective epitaxial film formation process; wherein a ratio of silane to dichlorosilane is greater than 1.
23. The method of claim 22 wherein the ratio of silane to dichlorosilane is greater than 2.
24. The method of claim 23 wherein the ratio of silane to dichlorosilane is greater than 5.
PCT/US2007/017053 2006-07-31 2007-07-30 Methods of controlling morphology during epitaxial layer formation WO2008033186A1 (en)

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US60/820,956 2006-07-31

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DE200711001813 DE112007001813T5 (en) 2006-07-31 2007-07-30 A method for controlling the morphology during the formation of an epitaxial layer
KR20097003879A KR101369355B1 (en) 2006-07-31 2007-07-30 Methods of controlling morphology during epitaxial layer formation
CN 200780028486 CN101496150B (en) 2006-07-31 2007-07-30 Methods of controlling morphology during epitaxial layer formation
JP2009522826A JP5175285B2 (en) 2006-07-31 2007-07-30 It forms a control method in the epitaxial layer formed

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