WO2008019277A2 - Substrate bonding process with integrated vents - Google Patents

Substrate bonding process with integrated vents Download PDF

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Publication number
WO2008019277A2
WO2008019277A2 PCT/US2007/075024 US2007075024W WO2008019277A2 WO 2008019277 A2 WO2008019277 A2 WO 2008019277A2 US 2007075024 W US2007075024 W US 2007075024W WO 2008019277 A2 WO2008019277 A2 WO 2008019277A2
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
capping
sealing
base substrate
vents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/075024
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French (fr)
Other versions
WO2008019277A3 (en
Inventor
Buu Quoc Diep
Osvaldo Enriquez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
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Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of WO2008019277A2 publication Critical patent/WO2008019277A2/en
Publication of WO2008019277A3 publication Critical patent/WO2008019277A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer

Definitions

  • This invention relates in general to controlling pressures associated with bonding substrates together, and, in particular, to an improved method of manufacturing the same.
  • MEMS microelectromechanical system
  • a microelectromechanical system (MEMS) device formed in or on a semiconductor wafer is often capped by a second wafer or glass substrate, forming a package comprising a cavity that protects and encloses the MEMS device.
  • MEMS devices protected in this manner include digital micromirrors (DMD), pressure sensors, and accelerometers etc.
  • DMD digital micromirrors
  • Certain MEMS devices, such as DMDs have conductive runners electrically interconnected to bond pads that are external to the sealed cavity. In many applications, these bond pads must also be sealed within the bonded substrate assembly in order to continue conventional assembly and packing processes that might otherwise corrode or oxidize the bond pads.
  • a method for bonding a capping substrate to a base substrate comprises providing a capping substrate with a plurality of vents extending through the capping substrate and sealing the capping substrate to the base substrate.
  • an apparatus comprising a base substrate, a capping substrate sealed to the base substrate and formed with a plurality of vents extending through the capping substrate, and sealant closing each of the plurality of vents.
  • FIG. 1 is a top view of a conventional dispense pattern of epoxy on a digital micromirror device wafer.
  • FIG. 2A is a top view of one embodiment of a base substrate.
  • FIG. 2B is a cross sectional view illustrating one example of a method of bonding a capping substrate to a base substrate.
  • FIG. 3 is a flow chart illustrating one example of a method of bonding a capping substrate to a base substrate.
  • FIG. 1 is a top view of a conventional dispense pattern of epoxy on a semiconductor wafer 100 that comprises a plurality of digital micromirror devices (DMD) 102.
  • the epoxy pattern forms a perimeter 104 around each DMD 102 that seals the microelectromechanical system (MEMS) portion of each DMD die 102.
  • the epoxy pattern comprises an incomplete epoxy perimeter 106 around semiconductor wafer 100 with a plurality of openings 108.
  • the openings 108 release air pressure buildup resulting from bonding semiconductor wafer 100 to a glass substrate (not explicitly shown) that might otherwise compromise sealant perimeters 104.
  • Bonding semiconductor wafer 100 to a glass substrate forms a bonded substrate assembly comprising a plurality of packages, each package comprising a cavity that protects and encloses the MEMS portion of each DMD die 102.
  • Each DMD die 102 has conductive runners electrically connected to bond pads (not explicitly shown) external to its respective epoxy perimeter 104. Because the open openings 108 expose the bond pads to the outside environment, at some point each opening 108 is typically sealed to continue conventional assembly processing of the DMDs that might otherwise corrode or oxidize the bond pads. Sealing openings 108 completes epoxy perimeter 106 around semiconductor wafer 100, thereby protecting the bond pads while strengthening the seal between substrates.
  • each opening 108 is typically sealed manually. This limitation is partially due to automation costs associated with accessing the sides of the bonded substrate assembly. Another reason is the location and dimensional dependency of each opening 108 upon the repeatability of the epoxy dispensing process.
  • FIG. 2A is a perspective view of one embodiment of forming a substrate assembly 200 by bonding a capping substrate (not explicitly shown) to a base substrate 208 according to the teachings of the invention.
  • Capping substrate and base substrate 208 may comprise any suitable material used in semiconductor fabrication and packaging, such as silicon, poly- silicon, indium phosphide, germanium, gallium arsenide, or glass.
  • base substrate 208 comprises a plurality of digital micromirror device (DMD) die 202 disposed outwardly from a CMOS wafer.
  • DMD digital micromirror device
  • any semiconductor die and/or micromachined structure, including any microelectromechanical system (MEMS), may be used without departing from the scope of the present disclosure.
  • MEMS microelectromechanical system
  • base substrate 208 further comprises a sealant disposed outwardly from base substrate 208 that forms a complete sealant perimeter 204 around at least a portion, in this example the microelectromechanical system (MEMS) portion, of each DMD die 202.
  • base substrate 208 further comprises a complete sealant perimeter 206 around base substrate 208.
  • Sealant perimeters 204 and 206 may comprise any suitable material used to bond substrates together.
  • sealant perimeters 204 and 206 both comprise an epoxy that may be cured by ultraviolet light (UV).
  • UV ultraviolet light
  • sealant perimeter 206 forms a complete perimeter around base substrate 200, sealant perimeter 206 avoids conventional process limitations associated with an incomplete perimeter.
  • Forming sealant perimeters 204 and 206 may be effected through any of a variety of processes.
  • sealant perimeters 204 and 206 may be formed by dispensing epoxy using automated equipment, such as, for example, equipment associated with jetting technology.
  • FIG. 2B is a cross sectional view illustrating one example of a method of forming a portion of substrate assembly 200 by bonding a capping substrate 216 to base substrate 208.
  • capping substrate 216 comprises a glass wafer.
  • sealant perimeter 204 and an interposer layer 212 enclose at least a portion of DMD 202 within a cavity 210 between capping substrate 216 and base substrate 208, thereby forming a protective package.
  • Interposer layer 212 may comprise any suitable material used to space at least a portion of capping substrate 216 from at least a portion of base substrate 208.
  • interposer layer 212 comprises a grid of glass sealed to capping substrate 216 by UV cured epoxy.
  • interposer layers may be formed by selectively removing a portion of capping substrate 216, and/or by coupling an interposer layer to base substrate 208 prior to bonding substrates 216 and 208 together.
  • vents 214 release a buildup of pressure resulting from bonding substrates 216 and 208 together.
  • Forming vents 214 may be effected through any of a variety of processes.
  • vents 214 are formed by drilling a hole through capping substrate 216 and interposer layer 212 at some point prior to bonding capping substrate 216 to base substrate 208.
  • vents 214 may form an opening in cavity 210 disposed outwardly from a non-functional die coupled to base substrate 208.
  • vents 214 are shown as being formed through capping substrate 216 and interposer layer 212, any vent that extends through capping substrate 216 and/or base substrate 208 may be formed without departing from the scope of the present disclosure.
  • vents 214 are sealed. Sealing vents 214 may be effected through any of a variety of processes. For example, vents 214 may be sealed by forming a sealing cap 322 outwardly from and/or within vents 214. In this particular example, vents 214 are sealed by dispensing an epoxy cap 218 on the outwardly disposed surface of capping substrate 216.
  • vents 214 and sealant cap 218 may coincide with or be aligned relative to elements used to align capping substrate 216 to base substrate 208.
  • FIG. 3 is a flow chart 300 illustrating one example of a method of bonding a capping substrate to a base substrate.
  • Method 300 beings in step 302, in which an interposer layer is formed on at least a portion of the capping substrate surface.
  • step 304 a plurality of vents are formed that extend through the capping substrate and the interposer layer.
  • step 306 a sealant is formed on the base substrate layer in a pattern that corresponds to the interposer layer.
  • Step 308 involves bonding the capping substrate to the base substrate.
  • the vents are externally sealed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Micromachines (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

In one method embodiment, a method for bonding a capping substrate (216) to a base substrate (208) comprises providing a capping substrate with a plurality of vents (214) extending through the capping substrate and sealing the capping substrate to the base substrate. In one embodiment, an apparatus comprising a base substrate, a capping substrate sealed to the base substrate and formed with a plurality of vents extending through the capping substrate, and sealant closing each of the plurality of vents.

Description

SUBSTRATE BONDING PROCESS WITH INTEGRATED VENTS
This invention relates in general to controlling pressures associated with bonding substrates together, and, in particular, to an improved method of manufacturing the same. BACKGROUND Within the semiconductor industry, numerous applications require bonding substrates together. For example, a microelectromechanical system (MEMS) device formed in or on a semiconductor wafer is often capped by a second wafer or glass substrate, forming a package comprising a cavity that protects and encloses the MEMS device. Examples of MEMS devices protected in this manner include digital micromirrors (DMD), pressure sensors, and accelerometers etc. Certain MEMS devices, such as DMDs, have conductive runners electrically interconnected to bond pads that are external to the sealed cavity. In many applications, these bond pads must also be sealed within the bonded substrate assembly in order to continue conventional assembly and packing processes that might otherwise corrode or oxidize the bond pads. SUMMARY
In one method embodiment, a method for bonding a capping substrate to a base substrate comprises providing a capping substrate with a plurality of vents extending through the capping substrate and sealing the capping substrate to the base substrate.
In one embodiment, an apparatus comprising a base substrate, a capping substrate sealed to the base substrate and formed with a plurality of vents extending through the capping substrate, and sealant closing each of the plurality of vents. BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a top view of a conventional dispense pattern of epoxy on a digital micromirror device wafer. FIG. 2A is a top view of one embodiment of a base substrate.
FIG. 2B is a cross sectional view illustrating one example of a method of bonding a capping substrate to a base substrate.
FIG. 3 is a flow chart illustrating one example of a method of bonding a capping substrate to a base substrate. DETAILED DESCRIPTION OF THE EMBODIMENTS
Particular examples and dimensions specified throughout this document are intended for example purposes only, and are not intended to limit the scope of the present disclosure. In particular, this document is not intended to be limited to bonding particular substrates together, such as a DMD substrate to a glass substrate.
FIG. 1 is a top view of a conventional dispense pattern of epoxy on a semiconductor wafer 100 that comprises a plurality of digital micromirror devices (DMD) 102. The epoxy pattern forms a perimeter 104 around each DMD 102 that seals the microelectromechanical system (MEMS) portion of each DMD die 102. In addition, the epoxy pattern comprises an incomplete epoxy perimeter 106 around semiconductor wafer 100 with a plurality of openings 108. The openings 108 release air pressure buildup resulting from bonding semiconductor wafer 100 to a glass substrate (not explicitly shown) that might otherwise compromise sealant perimeters 104. Bonding semiconductor wafer 100 to a glass substrate forms a bonded substrate assembly comprising a plurality of packages, each package comprising a cavity that protects and encloses the MEMS portion of each DMD die 102. Each DMD die 102 has conductive runners electrically connected to bond pads (not explicitly shown) external to its respective epoxy perimeter 104. Because the open openings 108 expose the bond pads to the outside environment, at some point each opening 108 is typically sealed to continue conventional assembly processing of the DMDs that might otherwise corrode or oxidize the bond pads. Sealing openings 108 completes epoxy perimeter 106 around semiconductor wafer 100, thereby protecting the bond pads while strengthening the seal between substrates.
Conventional processing associated with sealing openings 108 has limited manufacturability for a variety of reasons. For example, each opening 108 is typically sealed manually. This limitation is partially due to automation costs associated with accessing the sides of the bonded substrate assembly. Another reason is the location and dimensional dependency of each opening 108 upon the repeatability of the epoxy dispensing process.
FIG. 2A is a perspective view of one embodiment of forming a substrate assembly 200 by bonding a capping substrate (not explicitly shown) to a base substrate 208 according to the teachings of the invention. Capping substrate and base substrate 208 may comprise any suitable material used in semiconductor fabrication and packaging, such as silicon, poly- silicon, indium phosphide, germanium, gallium arsenide, or glass. In this example, base substrate 208 comprises a plurality of digital micromirror device (DMD) die 202 disposed outwardly from a CMOS wafer. Although this example uses DMDs 202, any semiconductor die and/or micromachined structure, including any microelectromechanical system (MEMS), may be used without departing from the scope of the present disclosure.
In this example, base substrate 208 further comprises a sealant disposed outwardly from base substrate 208 that forms a complete sealant perimeter 204 around at least a portion, in this example the microelectromechanical system (MEMS) portion, of each DMD die 202. In addition, base substrate 208 further comprises a complete sealant perimeter 206 around base substrate 208. Sealant perimeters 204 and 206 may comprise any suitable material used to bond substrates together. In this example, sealant perimeters 204 and 206 both comprise an epoxy that may be cured by ultraviolet light (UV). Each DMD die 202 has conductive runners electrically connected to bond pads (not explicitly shown) external to its respective sealant perimeter 204. Because sealant perimeter 206 forms a complete perimeter around base substrate 200, sealant perimeter 206 avoids conventional process limitations associated with an incomplete perimeter. Forming sealant perimeters 204 and 206 may be effected through any of a variety of processes. For example, sealant perimeters 204 and 206 may be formed by dispensing epoxy using automated equipment, such as, for example, equipment associated with jetting technology.
FIG. 2B is a cross sectional view illustrating one example of a method of forming a portion of substrate assembly 200 by bonding a capping substrate 216 to base substrate 208. In this example, capping substrate 216 comprises a glass wafer. Although this example uses a glass wafer, other substrates may be used without departing from the scope of the present disclosure. In this example, sealant perimeter 204 and an interposer layer 212 enclose at least a portion of DMD 202 within a cavity 210 between capping substrate 216 and base substrate 208, thereby forming a protective package. Interposer layer 212 may comprise any suitable material used to space at least a portion of capping substrate 216 from at least a portion of base substrate 208. In this particular example, interposer layer 212 comprises a grid of glass sealed to capping substrate 216 by UV cured epoxy. In other embodiments, interposer layers may be formed by selectively removing a portion of capping substrate 216, and/or by coupling an interposer layer to base substrate 208 prior to bonding substrates 216 and 208 together.
In this example, a plurality of vents 214 release a buildup of pressure resulting from bonding substrates 216 and 208 together. Forming vents 214 may be effected through any of a variety of processes. In this particular example, vents 214 are formed by drilling a hole through capping substrate 216 and interposer layer 212 at some point prior to bonding capping substrate 216 to base substrate 208. In other embodiments, vents 214 may form an opening in cavity 210 disposed outwardly from a non-functional die coupled to base substrate 208. Although vents 214 are shown as being formed through capping substrate 216 and interposer layer 212, any vent that extends through capping substrate 216 and/or base substrate 208 may be formed without departing from the scope of the present disclosure.
In this example, at some point vents 214 are sealed. Sealing vents 214 may be effected through any of a variety of processes. For example, vents 214 may be sealed by forming a sealing cap 322 outwardly from and/or within vents 214. In this particular example, vents 214 are sealed by dispensing an epoxy cap 218 on the outwardly disposed surface of capping substrate 216. One aspect of this disclosure recognizes that the formation and sealing of vents 214 may be effected by high-precision, automated equipment. In addition, vents 214 and sealant cap 218 may coincide with or be aligned relative to elements used to align capping substrate 216 to base substrate 208. FIG. 3 is a flow chart 300 illustrating one example of a method of bonding a capping substrate to a base substrate. Method 300 beings in step 302, in which an interposer layer is formed on at least a portion of the capping substrate surface. In step 304, a plurality of vents are formed that extend through the capping substrate and the interposer layer. Next, in step 306 a sealant is formed on the base substrate layer in a pattern that corresponds to the interposer layer. Step 308 involves bonding the capping substrate to the base substrate. In the final step 310, the vents are externally sealed.
Those skilled in the art to which the invention relates will appreciate that the described examples are just some of the many ways in which the claimed invention may be implemented.

Claims

CLAIMSWhat is claimed is:
1. A method for bonding a capping substrate to a base substrate, comprising: providing a capping substrate with a plurality of vents extending through the capping substrate; and sealing the capping substrate to the base substrate.
2. The method of claim 1, further comprising: separating at least a portion of the capping substrate from at least a portion of the base substrate by an interposer layer; wherein the plurality of vents are provided to extend through the capping substrate and through the interposer layer; wherein sealing the capping substrate to the base substrate, includes sealing a first sealed perimeter around the base substrate and sealing a plurality of second sealed perimeters within the first sealed perimeter; and sealing the vents after the capping substrate is sealed to the base substrate.
3. The method of Claim 1 or 2, wherein providing a plurality of vents extending through the capping substrate comprises providing vents that are capable of relieving air pressure associated with bonding the capping substrate to the base substrate.
4. The method of Claim 1 or 2, wherein sealing the capping substrate to the base substrate comprises sealing a capping substrate to a semiconductor wafer comprising a plurality of semiconductor devices; and wherein sealing a plurality of second sealed perimeters within the first sealed perimeter comprises sealing a perimeter around at least a portion of each semiconductor device.
5. The method of Claim 1 or 2, wherein sealing the capping substrate to a base substrate comprises sealing glass to the base substrate.
6. The method of Claim lor 2, wherein sealing the capping substrate to a base substrate comprises sealing a capping substrate to a semiconductor wafer comprising a plurality of semiconductor devices.
7. The method of Claim 6, wherein providing a plurality of vents extending through the capping substrate comprises providing at least one vent formed outwardly from a non-functional semiconductor device.
8. The method of Claim 6, wherein sealing a capping substrate to a semiconductor wafer comprises sealing a perimeter around at least a portion of each semiconductor device.
9. The method of Claim 8, wherein providing a plurality of vents extending through the capping substrate comprises providing a plurality of vents exterior to the sealed perimeters around at least a portion of each semiconductor device.
10. An apparatus comprising: a base substrate; a capping substrate sealed to the base substrate and formed with a plurality of vents extending through the capping substrate; and and sealant closing each of the plurality of vents.
11. The apparatus of Claim 10, wherein the capping substrate comprises glass; wherein the base substrate comprises a semiconductor wafer including a plurality of semiconductor devices.
12. The apparatus of Claim 11, wherein at least a portion of each semiconductor device is sealed within a cavity formed at least in part by a sealant coupling the capping substrate to the base substrate.
13. The apparatus of Claim 11, wherein each vent is exterior to each cavity.
14. The apparatus of Claim 11, 12 or 13, wherein at least one vent is disposed outwardly from a non-functional semiconductor device.
15. The apparatus of Claim 11, 12 or 13, wherein the plurality of semiconductor devices comprises a plurality of digital micromirror devices.
PCT/US2007/075024 2006-08-04 2007-08-02 Substrate bonding process with integrated vents Ceased WO2008019277A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/499,080 2006-08-04
US11/499,080 US20080032484A1 (en) 2006-08-04 2006-08-04 Substrate bonding process with integrated vents

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WO2008019277A2 true WO2008019277A2 (en) 2008-02-14
WO2008019277A3 WO2008019277A3 (en) 2008-07-17

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US20080303129A1 (en) * 2007-06-11 2008-12-11 Wang Qing Ya Michael Patterned contact sheet to protect critical surfaces in manufacturing processes
US9673169B2 (en) * 2013-02-05 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a wafer seal ring
US9287188B2 (en) * 2013-02-05 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a seal ring structure
US9633883B2 (en) 2015-03-20 2017-04-25 Rohinni, LLC Apparatus for transfer of semiconductor devices
US10329142B2 (en) * 2015-12-18 2019-06-25 Samsung Electro-Mechanics Co., Ltd. Wafer level package and method of manufacturing the same
US10141215B2 (en) 2016-11-03 2018-11-27 Rohinni, LLC Compliant needle for direct transfer of semiconductor devices
US10504767B2 (en) 2016-11-23 2019-12-10 Rohinni, LLC Direct transfer apparatus for a pattern array of semiconductor device die
US10471545B2 (en) 2016-11-23 2019-11-12 Rohinni, LLC Top-side laser for direct transfer of semiconductor devices
US10297478B2 (en) * 2016-11-23 2019-05-21 Rohinni, LLC Method and apparatus for embedding semiconductor devices
US10062588B2 (en) 2017-01-18 2018-08-28 Rohinni, LLC Flexible support substrate for transfer of semiconductor devices
US10410905B1 (en) 2018-05-12 2019-09-10 Rohinni, LLC Method and apparatus for direct transfer of multiple semiconductor devices
US11094571B2 (en) 2018-09-28 2021-08-17 Rohinni, LLC Apparatus to increase transferspeed of semiconductor devices with micro-adjustment

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US6537892B2 (en) * 2001-02-02 2003-03-25 Delphi Technologies, Inc. Glass frit wafer bonding process and packages formed thereby
US7204737B2 (en) * 2004-09-23 2007-04-17 Temic Automotive Of North America, Inc. Hermetically sealed microdevice with getter shield

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US20080032484A1 (en) 2008-02-07
TWI344184B (en) 2011-06-21
TW200816332A (en) 2008-04-01
WO2008019277A3 (en) 2008-07-17

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