WO2007149752A1 - Method, apparatus and system for thermal management using power density feedback - Google Patents
Method, apparatus and system for thermal management using power density feedback Download PDFInfo
- Publication number
- WO2007149752A1 WO2007149752A1 PCT/US2007/071103 US2007071103W WO2007149752A1 WO 2007149752 A1 WO2007149752 A1 WO 2007149752A1 US 2007071103 W US2007071103 W US 2007071103W WO 2007149752 A1 WO2007149752 A1 WO 2007149752A1
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- Prior art keywords
- regions
- activity
- thermal relationship
- thermal
- measuring
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/20—Cooling means
- G06F1/206—Cooling means comprising thermal management
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
Definitions
- Some embodiments of the present invention generally relate to computer systems, and more specifically, some embodiments may relate to system thermal management.
- thermal management becomes more important to prevent device overheating or failure.
- an overheated device such as a processor
- the activity level of the system or device may be adjusted, such as by reducing the operating speed of the processor.
- this approach to thermal management considers only the temperature of the device itself, and does not take into consideration thermal coupling or power density in the system.
- FIGS. 1 and 2 are flowcharts of the process for thermal management using power density feedback according to some embodiments of the system;
- FIG. 3 is an illustration of examples of density factor change and thermal relationship coefficient calculations according to some embodiments of the invention.
- FIG. 4 is an illustration of examples of thermal relationship tables according to some embodiments of the invention.
- FIG. 5 is an illustration of examples of a power distribution register according to some embodiments of the invention.
- FIG. 6 includes a schematic diagram of a computer system according to some embodiments of the invention.
- the method may be implemented within a computing system.
- the system described with respect to FIG. 6, below, may be used to perform the operations described herein with respect to FIGS. 1 - 5, as one of ordinary skill in the relevant arts would appreciate based at least on the teachings provided herein.
- FIGS. 1 and 2 are flowcharts of the process for thermal management using power density feedback according to some embodiments of the system.
- the method or process of FIG. 1 may start at 100 and proceed to 102, where the operation may measure activity in one or more regions of a system, where the system may include one or more dies.
- the one or more regions may include, as part of all of a system, a microprocessor, a memory controller hub, an input/output controller hub, a memory, a core, a chipset, a graphics memory controller hub, or other components.
- the measuring of activity may also include measuring a change in power density in the one or more regions on a die (202) and/or measuring a change in temperature in the one or more regions of a system (204).
- the system may include one or more dies.
- the measuring activity may include measuring current changes or voltage changes in the one or more regions.
- the process may then proceed to 104, where it may generate a thermal relationship coefficient (TRC) for the one or more regions, where the TRC may be based on at least the measured activity. Examples of TRCs are illustrated in FIG. 3 and described elsewhere herein.
- the TRC may be based on one or more power states, voltage differences, power differences and/or current differences.
- the one or more power states may include at least one or an active state or a sleep state.
- the process may then proceed to 106, where it may generate a thermal relationship table (TRT) based on one or more of the TRCs.
- TRT thermal relationship table
- Examples of TRTs are illustrated in FIG. 4 and described elsewhere herein.
- the TRT may provide one or more relationships between the one or more regions, where the one or more relationships may be used to predict temperature distributions in the one or more regions.
- the one or more relationships may include information that allow for calculation of the amount or level of power change required to achieve a given temperature change in the one or more regions.
- the process may then proceed to 108, where it may generate a power distribution register (PDR) to track one or more status indicators for the one or more regions. Examples of PDRs are illustrated in FIG. 5 and described elsewhere herein.
- the one or more status indicators may include information about whether the one or more regions are active or inactive, or in another power state or activity level.
- the process may then proceed to 110, where it may determine an activity configuration from the PDR, where the activity configuration may include at least a workload condition appropriate to the activity in the one or more regions.
- the activity configuration may be matched to a configuration measured by one or more TRCs and stored in a TRT.
- the workload condition may include changes to the power or activity levels of components in the one or more regions of the system, where the system may include one or more dies.
- the process may then proceed to 112, where it may apply the TRT based on the activity configuration.
- the process at 112 may include increasing heat dissipation to the one or more regions, or decreasing activity of the one or more regions.
- the process may then proceed to 114, where it may store the TRT or the PDR in a memory location.
- the memory location may be a system memory, a cache memory, a disk drive, or a main memory.
- FIG. 3 is an illustration of examples 300 of density factor change and TRC calculations according to some embodiments of the invention.
- the examples may illustrate how a change in power density can have an impact on the thermal behavior of a component.
- the circuits in 302 and 306 show a system 304 or die 304, based on some embodiments of the invention, with two active regions that may be consuming power and a system 308 or die 308 with one active region that may be consuming power.
- the active regions may be consuming more power relative to the inactive regions, while the inactive regions may still consume power.
- the total power being used on the systems or dies 304 and 308 may be the same.
- the calculations in 302 and 206 may illustrate that the change in power distribution may have an impact in the junction-heat pipe resistance of the component and an overall impact on the junction-ambient resistance. These changes may require a determination of TRCs that are specific to each scenario or activity configuration. As such, in some embodiments, a TRC may be calculated for each configuration, as shown in the examples 302 and 306 by the Theta(j-amb) [ ⁇ j - am b]- The different results in the TRC in each example are due to at least the differences in power density.
- the ability to establish a thermal relationship may be useful when more than one component or heat generating regions exist within thermal proximity to each other.
- being aware of the thermal relationships between regions may allow a system to apply more appropriate workload conditions, as well as determine which regions have influence over the temperature of other regions, to solve or assist in resolving thermal issues.
- the system may have a thermal management policy that uses the information in the TRTs, among other things, to determine which region(s) should be thermally managed, as described above in some embodiments with respect to FIGS. 1 - 2.
- the thermal management policy may include implementation of Advanced Configuration and Power Interface (ACPI) information, in accordance with the ACPI Specification, Revision 3.0, published September 2, 2004.
- ACPI Advanced Configuration and Power Interface
- FIG. 4 is an illustration of examples 400 of thermal relationship tables according to some embodiments of the invention.
- the examples 402, 404, and 406 may describe structures of TRTs, as well as how the TRCs in the TRTs may be used to predict at least the temperature of components, according to some embodiments.
- the units of the coefficients in the tables are in °C/W, but are not limited to these units, as one of ordinary skill in the relevant art would appreciate based at least on the teachings described herein.
- Example 402 may illustrate a format, where two regions of a die, CPU and GMCH, and may be read in the following manner:
- CPU-CPU Temperature change of CPU for every Watt change in CPU Power
- GMCH-CPU Temperature change of CPU for every Watt change in GMCH Power
- GMCH-GMCH Temperature change of GMCH for every Watt change in GMCH Power
- CPU - GMCH Temperature change of GMCH for every Watt change in CPU Power.
- the example 402 may show, in some embodiments, that there may be potentially two different tables that mat be used to describe the relationship between the CPU and GMCH or other regions.
- the CPU-CPU TRT coefficient may change depending upon how the power is distributed on the die. This change in coefficient may impact that temperature prediction made by the process in embodiments of the invention.
- the corresponding TRCs and resultant temperature calculations, as shown in 410 and 412 may provide a more accurate prediction of temperature as the thermally adjacent regions are being considered.
- FIG. 5 is an illustration of examples of a power distribution register 500 according to some embodiments of the invention.
- the example 504 describes one of several approaches that may be used to assess how power is being distributed on a particular die, system, or component.
- the PDR may have bits assigned to indicate the status of regions on the die and whether they are active or not, according to some embodiments of the invention.
- the example 504 shows a system or die with four regions. In some embodiments, with four regions, the PDR may be implemented with four bits in a register. In some embodiments, each bit would be assigned to a specific region; and a "0" may indicate that the region is inactive and/or does not have one or more utilization rates.
- a value of "1" may indicate an active region with one or more utilization rate.
- the PDR could be polled by the system, such as system 600 described elsewhere herein.
- the value from the PDR and/or an overall component power reading may provide enough information to apply an appropriate TRT that would provide an appropriate the workload condition.
- FIG. 6 includes a schematic diagram of a computer system according to some embodiments of the invention.
- the computer system 600 includes a frame (or computing device) 602 and a power adapter 604 (e.g., to supply electrical power to the computing device 602).
- the computing device 602 may be any suitable computing device such as a laptop (or notebook) computer, a personal digital assistant, a desktop computing device (e.g., a workstation or a desktop computer), a rackmounted computing device, and the like.
- Electrical power may be provided to various components of the computing device 602 (e.g., through a computing device power supply 606) from one or more of the following sources: One or more battery packs, an alternating current (AC) outlet (e.g., through a transformer and/or adaptor such as a power adapter 604), automotive power supplies, airplane power supplies, and the like.
- the power adapter 604 may transform the power supply source output (e.g., the AC outlet voltage of about I IOVAC to 240VAC) to a direct current (DC) voltage ranging between about 7VDC to 12.6VDC.
- the power adapter 604 may be an AC/DC adapter.
- the computing device 602 may also include one or more central processing unit(s) (CPUs) 608 coupled to a bus 610.
- the CPU 608 may be one or more processors in the Pentium® family of processors including the Pentium® II processor family, Pentium® III processors, Pentium® IV processors available from Intel® Corporation of Santa Clara, California.
- other CPUs may be used, such as Intel's Itanium®, XEONTM, and Celeron® processors.
- processors from other manufactures may be utilized.
- the processors may have a single or multiple core design.
- a chipset 612 may be coupled to the bus 610.
- the chipset 612 may include a memory control hub (MCH) 614.
- the MCH 614 may include a memory controller 616 that is coupled to a main system memory 618.
- the main system memory 618 stores data and sequences of instructions that are executed by the CPU 608, or any other device included in the system 600.
- the main system memory 618 includes random access memory (RAM); however, the main system memory 618 may be implemented using other memory types such as dynamic RAM (DRAM), synchronous DRAM (SDRAM), and the like. Additional devices may also be coupled to the bus 610, such as multiple CPUs and/or multiple system memories.
- the MCH 614 may also include a graphics interface 620 coupled to a graphics accelerator 622.
- the graphics interface 620 is coupled to the graphics accelerator 622 via an accelerated graphics port (AGP).
- AGP accelerated graphics port
- a display (such as a flat panel display) 640 may be coupled to the graphics interface 620 through, for example, a signal converter that translates a digital representation of an image stored in a storage device such as video memory or system memory into display signals that are interpreted and displayed by the display.
- the display 640 signals produced by the display device may pass through various control devices before being interpreted by and subsequently displayed on the display.
- a hub interface 624 couples the MCH 614 to an input/output control hub (ICH) 626.
- the ICH 626 provides an interface to input/output (I/O) devices coupled to the computer system 600.
- the ICH 626 may be coupled to a peripheral component interconnect (PCI) bus.
- PCI peripheral component interconnect
- the ICH 626 includes a PCI bridge 628 that provides an interface to a PCI bus 630.
- the PCI Bridge 628 provides a data path between the CPU 608 and peripheral devices.
- other types of I/O interconnect topologies may be utilized such as the PCI ExpressTM architecture, available through Intel® Corporation of Santa Clara, California.
- the PCI bus 630 may be coupled to an audio device 632 and one or more disk drive(s) 634. Other devices may be coupled to the PCI bus 630.
- the CPU 608 and the MCH 614 may be combined to form a single chip.
- the graphics accelerator 622 may be included within the MCH 614 in other embodiments.
- the MCH 614 and ICH 626 may be integrated into a single component, along with a graphics interface 620.
- peripherals coupled to the ICH 626 may include, in various embodiments, integrated drive electronics (IDE) or small computer system interface (SCSI) hard drive(s), universal serial bus (USB) port(s), a keyboard, a mouse, parallel port(s), serial port(s), floppy disk drive(s), digital output support (e.g., digital video interface (DVI)), and the like.
- IDE integrated drive electronics
- SCSI small computer system interface
- USB universal serial bus
- the computing device 602 may include volatile and/or nonvolatile memory.
- the system 600 may include one or more regions on a die, where each of the one or more regions may have a thermal relationship with other regions of the die.
- the one or more regions may be within the frame 602, on the chipset 612, the MCH 614, ICH 626, graphics accelerator 622, or other component, as one of ordinary skill in the relevant art would appreciate may be implemented on the same die or chip as other components of the system 600.
- the system 600 may include a thermal relationship coefficient (TRC), described elsewhere herein with respect to FIG. 3 in embodiments, to describe the thermal relationship between the one or more regions of the die.
- TRCs may be implemented in a main memory 618 or other memory or storage device, within other components of the system 600, as one of ordinary skill in the relevant art would appreciate based at least on the teachings provided herein.
- a thermal relationship table may be generated from the TRCs.
- the TRT may include at least a comparison of each of the TRCs for each of the one or more regions.
- a power distribution register may also be generated to track one or more status indicators, where the status indicators include information as to whether a region is active or inactive or in another state.
- the PDR is capable of thermally managing the system by tracking activity in the one or more regions.
- the system 600 may be capable of utilizing the TRC, TRT, and/or PDR, such as those described above in FIGS. 3 - 5, to determine which of the one or more regions may require thermal management.
- thermal management may involve altering the power state of the region or die or system. In some embodiments, thermal management may include increasing the cooling effort in one or more regions of the die or system.
- the embodiments of the invention may be implemented in one or more regions on a die, where the one or more regions include the microprocessor 608 or in a multiple processor environment, one or more cores, the MCH 614 or its sub-components 616 or 620, the ICH 626 or its sub-components 628, the main memory 618, the chipset 612, the graphics memory controller hub (GMCH) 620 or 622, or another component or components.
- GMCH graphics memory controller hub
- the frame or computing device 602 may include more than one die, as one of ordinary skill in the relevant arts would appreciate based at least on the teachings described herein.
- the embodiments of the invention may be practiced in systems with more than one die; thus, the one or more regions may be on more than one die, and references to "on a die” are includes to "on one or more dies," as one of ordinary skill in the relevant arts would appreciate based at least on the teachings described herein.
- Embodiments of the invention may be described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural, logical, and intellectual changes may be made without departing from the scope of the present invention. Moreover, it is to be understood that various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described in some embodiments may be included within other embodiments. Those skilled in the art can appreciate from the foregoing description that the techniques of the embodiments of the invention can be implemented in a variety of forms.
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Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020117005552A KR101306452B1 (en) | 2006-06-23 | 2007-06-13 | Method, apparatus and system for thermal management using power density feedback |
| JP2009508016A JP4825301B2 (en) | 2006-06-23 | 2007-06-13 | Thermal management method, apparatus and system using power density feedback |
| DE112007001433.4T DE112007001433B4 (en) | 2006-06-23 | 2007-06-13 | A method, apparatus and system for thermal management using power density feedback |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/474,023 US20080011467A1 (en) | 2006-06-23 | 2006-06-23 | Method, apparatus and system for thermal management using power density feedback |
| US11/474,023 | 2006-06-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2007149752A1 true WO2007149752A1 (en) | 2007-12-27 |
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ID=38833759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2007/071103 Ceased WO2007149752A1 (en) | 2006-06-23 | 2007-06-13 | Method, apparatus and system for thermal management using power density feedback |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20080011467A1 (en) |
| JP (1) | JP4825301B2 (en) |
| KR (2) | KR101306452B1 (en) |
| CN (1) | CN101479685A (en) |
| DE (1) | DE112007001433B4 (en) |
| TW (1) | TWI340315B (en) |
| WO (1) | WO2007149752A1 (en) |
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| US9152473B2 (en) | 2012-12-29 | 2015-10-06 | Intel Corporation | Table driven multiple passive trip platform passive thermal management |
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| US8064197B2 (en) * | 2009-05-22 | 2011-11-22 | Advanced Micro Devices, Inc. | Heat management using power management information |
| US8375349B2 (en) * | 2009-09-02 | 2013-02-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for constant power density scaling |
| KR101942027B1 (en) * | 2012-03-28 | 2019-04-11 | 삼성전자 주식회사 | Method for predicting temperature in device |
| US20140188302A1 (en) * | 2012-12-28 | 2014-07-03 | Vasudevan Srinivasan | Priority based intelligent platform passive thermal management |
| US20140245028A1 (en) * | 2013-02-22 | 2014-08-28 | Qualcomm Incorporated | System and method for temperature driven selection of voltage modes in a portable computing device |
| US20160153922A1 (en) * | 2014-11-27 | 2016-06-02 | Mediatek Inc. | System and method for adaptive thermal analysis |
| US10606338B2 (en) | 2017-12-29 | 2020-03-31 | Intel Corporation | Energy-aware power sharing control |
| CN113568457B (en) * | 2021-06-09 | 2022-05-03 | 安徽翔弘仪器科技有限公司 | Dynamic temperature intelligent protection system based on sensing technology |
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| US9152473B2 (en) | 2012-12-29 | 2015-10-06 | Intel Corporation | Table driven multiple passive trip platform passive thermal management |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20090029732A (en) | 2009-03-23 |
| JP2009535722A (en) | 2009-10-01 |
| US20080011467A1 (en) | 2008-01-17 |
| TWI340315B (en) | 2011-04-11 |
| KR20110041570A (en) | 2011-04-21 |
| KR101306452B1 (en) | 2013-09-09 |
| JP4825301B2 (en) | 2011-11-30 |
| DE112007001433B4 (en) | 2016-07-21 |
| TW200819959A (en) | 2008-05-01 |
| CN101479685A (en) | 2009-07-08 |
| DE112007001433T5 (en) | 2009-04-30 |
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