WO2007147756A1

WO2007147756A1 - A processor and a method for a processor

Info

Publication number: WO2007147756A1
Application number: PCT/EP2007/055777
Authority: WO
Inventors: Jakob CARLSTRÖM
Original assignee: Xelerated Ab
Priority date: 2006-06-22
Filing date: 2007-06-12
Publication date: 2007-12-27
Also published as: ATE445277T1; US20120210327A1; TWI435574B; DE602007002718D1; US8171478B2; US20090183164A1; US8997105B2; TW200818781A; EP2036267A1; US20130326530A1; EP2036267B1; US8522246B2

Abstract

The present invention relates to a processor (1) and a method for a processor comprising processing means (2), the method comprising the steps of - admitting a data packet (D1, D2, D3) to the processing means (2) based at least partly on a value (CS1) of a first credit, parameter and a first limit (L1S1) of the first credit parameter, - decreasing the value (CS1) of the first credit parameter if the data packet (D1, D2, D3) is admitted to the processing means (2), and - increasing the value (CS1) of the first credit parameter, in dependence on a value (CS2) of a second credit parameter, based on which a data packet (D1, D2, D3) is admitted to the processing means (2).

Description

A PROCESSOR AND A MFTIIOD FOR Λ PROCFSSOR

I FC HXICAL FIELD

* The present invention relates to a processor and a method for a processor comprising processing meant,, the method comprising the steps of admitting a data packet to the processing means based at least partly on a value of a first credit parameter and a first limit of the first credit parameter, and decreasing the value of the first credit parameter if the data packet is admitted to the processing means,

10

BACKGROUND

In data processings it is desired to reduce buffer capacity, i.e. storage capacity provided for storing data durmg queuing.

15

In some known processors, incoming data traffic is admitted as quickly as possible without controlled admittance limitation, whereby limitations are given by processing capabilities. This will result in large requirements on buffer capacities in ihc processor Also, data shaping can be used so that incoming data traffic is :o admitted to the processing element(s) of the processor so as to accomplish a constant bit rate, and/or a constant packet rate.

In a processor, a shaper might be used for controlling incoming traffic based on a first resource of the processor, for example the bit rate capacity, and another shaper

2^ might be used to control incoming traf fic based on a second resource of the processor, for example the data packet rate capacity. Such shapers usually have some credit parameter, for example in the form of a token bucket, based on which packets are admitted to the processing element(s) of the processor. 1 lie credit values arc increased periodically with predetermined amounts, data packets are not j<> admitted unless credit values of the shapers have reached a limit value, and the credit v alues are decreased when data packets are admitted. In such a processor. n

bursts might occur in the processor reasons illustrated by the following example: After a sequence of packets consuming a relative!)_' large amount of the first resource and a relative!)' small amount of the second resource, e.g. relatively long data packets, the credit value of one of the shapers will reach a relatively high level.

5 If such a packet sequence consuming a lot of the first resource and little of the second resource is followed by a sequence of packets consuming a relative!)_' small amount of she first resource, e.g. relatively short data packets, a hurst of packets will be permitted until the credit value having reached a relatively high level falls below the limit for admittance of packets. The risk of such data bursts will require a large

K) buffer capacity downstream of the shapers.

SΓMMΛRY

It is an object of the invention to reduce buffer capacity in a processor.

15

This object is reached with a method of the type mentioned initially, comprising the step of increasing the value of the first credit parameter, in dependence on a value of a second credit parameter, based on which a data packet is admitted to the processing means, :o

Λs described closer below, the data packet, the admission of which is based on the value of the second credit parameter, can be identical or not identical with the data packet, the admission of which is based on the value of the first credit parameter,

:5 The invention is especially advantageous where the value of the first credit parameter is compared to a first Hunt of the first credit parameter, the data packet not being admitted to the processing means if the value of the first credit parameter is lower than the first limit, l he invention will make it possible to compare the value of the first credit parameter to a second limit of the first credit parameter, the j(> value of the first credit parameter not being increased, so as to become larger that the second limit of the first credit parameter, if the value of the second credit parameter is below a first limit of the second credit parameter,

In particular, none of the credit values are allowed to increase while any of the other 5 credit values aie below a predetermined limit. This will avoid a build-up of large credit values, and will significantly reduce burst sizes, which in turn will allow lower downstream butler capacity requirements.

The first limit and the second limit of the first credit parameter can be different or so equal.

Preferably, the step of increasing the value of the first credit parameter is based at least partly on a first resource or a second resource of the processing means, Thereby, the credit levels, and therefore data admittance is adapted to chosen

15 resources of the processing means, which will reduce buffer capacity requirements of the latter. As explained further below, the processing means resources can be any of a large amount of different types of features of the processing means. For example, one or more of the resources can be performance parameters relating to the processing means, e.g. !he first resource can be a bit rate capacity of the

?M processing means, and the second resource can be a data packet rate capacity of the processing means. Alternatively, one or more of the resources can be processing elements, adapted to process data. Alternatively or in addition, the step of increasing the value of the first credit parameter and/or the value of the second credit parameter, and-'or decreasing the values of the first and the second credit parameter

: ^; if the data packet is admitted to the processing means, can be based at least partly on an expected time period of residence in the processing means in the form of a processing pipeline, as described in the International patent application No PC 1 /SE2005/00196^Q. tiled by the applicant, arid incorporated herein by reference, Herein, the term ""credit parameter" implies a parameier. the value of which is adjusted based on the admission of data packets, fhυs, also the value of the second credit parameter is decreased if the data packet is admitted to the processing means.

5 1 he object of the invention is also reached with a method of the type mentioned initially, comprising the step of increasing the value of the first credit parameter, in dependence on a data storage level in a buffer in which the data packet is stored before admitted to the processing means. This prevent a build-up of a large credit at a processor data input interface not receiving traffic, or receiving a relatively small i o flow of traffic, for a period time, so that data burst from such an interlace can be avoided when such a time period has passed. Preferably, the value of the first credit parameter is not increased, so as to become larger that a second limit of the first credit parameter, if the buffer is empty.

! 5 The object of the invention is also reached with a processor according to any of the claims 9-16,

DhSCRlPTIOK OF THF FIGURES

20 Below, the invention w ill be described in the detailed description with reference to ihc drawings, in which:

- fig. 1 is a block diagram corresponding to a processor according to one embodiment of the present invention.

Hg. 2 is a block diagram corresponding to a part of the processor to which 25 the diagram in fig. 1 corresponds, fig, 3 is a block diagram corresponding to a processor according to another embodiment of the present invention, and

- tig. 4 is a block diagram corresponding to a processor according io a further embodiment of the present invention.

JO

DFTAILED DhSCRTPTION Fig. I illustrates one embodiment of the present invention. A network processor 1 comprises processing means 2. 1 wo features of the processing means 2 are in this presentation referred ro as a firsi and a second resource Rl , R2. A resource as 5 understood in this presentation can be any of a large amount of different types of features, and a few examples are given herein, Tn addition, in general, the processing means can present more than two resources, see below with reference to fig. 3. One or more of the resources Rl . R2 can be processing elements, adapted to process data. Alternatively, one or more of the resources Rl , R2 can be i n performance parameters related to the processing means 2, In this embodiment of the invention, boih performance parameters are performance parameters. More specifically, the first resource R l is the bit rate capacity of the processing means 2. and the second resource R2 is the packet rate capacity of the processing means 2.

15 The processing means 2 can be any of a variety of known types, including an asynchronous processing pipeline, as described in said International patent application No, PCT/SF2005/001969, incorporated herein by reference. 1 hereby, any or all of the resources Rl, R2 can be performance parameters related to the processing means 2, or processing elements of the processing pipeline, the amount

2υ of which can be considerably larger than two. Any of such processing elements can be an access point for access to a processing device, or engine, as describes in WO2004/01028S, included herein by reference.

Alternatively, the processing means 2 can be a RISC (Reduced Instruction Set ?.<; Computer) processor, microcoded engine, hard.cod.ed. engine, or a combination of multiple processing means of one type or many types.

Data traffic is forwarded from left to right in fig. 1. Data packets Dl , D2. D3 enter the processor through a data input interface comprising an input port 3, and are 30 stored in an input buffer 4 before admitted to the processing means 2 in a manner described below. After exiting the processing means 2. the packets are stored in an output buffer 6 before being transmitted through an output port 7.

Admission to the processing means 2 is determined by a first and a second shaper S l . S2, in the form of a bit rate shaper S l and a packet rate shaper S2, respectively. I he bit rate shaper S l limits the bit rate to the processing means 2. The limitation property of the bit rate shaper S l is chosen based on the first resource R l , i.e. the bit rate capacity of the processing means 2. The packet rate shaper S2 limits the flow of data packets to the processing means 2. The limitation property of the packet rate shaper S2 is chosen based on the second resource R2. i.e. the packet rate capacity of the processing means 2.

The shapcrs S l , S2 can be provided in any suitable form, for example as a software program, or part thereof, or as digital or analogue circuits of electrical, optical or mechanical components

Reference is made to fig. 2. Both simpers S l, S2 use token bucket algorithms, so that admittance of data is based on a respective value CS l, CS2 of a credit parameter, L-ach of these values CS l , CS2, herein also referred to as credit values CS l , CS2. are compared to a respective first limit L1 S2, L1S2. If any of the credit values CS L CS2 is below the respective first limit I i S2. L l S2, no data traffic is allowed to pass the respective shaper,

If neither of the credit values CS l, CS2 is below the respective first limits L 1 S2, Ll S2 in the token buckets of the shapers S 1 , S2, the next packet L⁾ 1 in turn in the input buffer 4 is admitted to the processing means 2. When the packet Dl is admitted to the processing means, the credit value CS lof the bit rate shaper S I is reduced by an amount corresponding amount of bits ot the packet DL and the credit value CS2 of the packet rate shaper S2 is reduced by an amount corresponding to the number of packets admitted, i.e. one packet. As an alternative, ihc credit value CS2 of the packet rate shapcr S2 can be adjusted as described in said International patent application No. PCl /8122005 -OGl 969, incorporated herein by reference. Accordingly, each data packet D l , D2, D 3 can comprise a header with information, and the packet rate shaper S2 can be adapted to

5 read the information, which can be related to the cost of the data packet, i.e. to the longest time that the respective data packet Dl, 1)2, D 3 keeps any processing element of the processing means 2 busy from accepting new data packets. Alternatively or in addition, such header information can be used to establish the identity of the resource, i.e. the processing element, to be engaged in processing of

10 the respective packet Dl, D2. D3. further, the header can also include information about the size of the respective data packet. When the packet is admitted to the processing means, the credit value CS2 of the packet rate shaper S2 is reduced by an amount corresponding to the header information, e.g. cost infoi mation.

15 Λ second limit I 2S 1 , 1 2S2 of the respective shaper S K S2 is higher than the respective first limit L 1 S2, L 1 S2, as indicated in Hg. 2. Alternatively the second limit L2S 1. L2S2 of the respective shaper M, S2 can be identical with the respective first limit L I S2. L 1 S2. If the credit value CbI of the bit rate shaper S 1 is below the second limit L2S 1 , the credit value CS l is periodically, e.g. every clock za cycle of the processor 1 , incremented by a fixed credit amount. The value of the fixed credit amount is based on the frequency of the periodic increments (e.g. every clock cycle) and the first resource Rl, i.e. the bit rate capacity of the processing means 2. Similarly, if the credit value of the packet rate shaper S2 is below the second limit 1 2S2. the credit value CS2 is periodically incremented by a fixed

\" credit amount, which is based on the frequency of the periodic increments and the second resource R2. i.e. the packet rate capacity of the processing means 2.

Pi eferably, the shapers S l, S2 use a so called loose token bucket algorithm, i.e. the first limits Ll b l , L1 S2 are zero, and when the both credit values CS l , CS2 are non- Ji) negative, the next packet Dl in turn in the input buffer 4 is admitted to the processing means 2. If the credit value of any of the shapes SL S2 is below the first limit L 1S2. L 1 S2. the credit value of the other shaper S L S2 is not incremented above a respective second limit L2s l , L2S2. Limiting the credit value of any of the shapers S i , S2 to ^ the respective second limit L2S 1. L2S2. if the credit value of any other of the shapers S L S2 is below the first limit L1 S2, L1 S2, will reduce buffer capacity requirements of the processing means 2. This is explained by the following example:

io Independent shapers, allowing unlimited increase of credit levels regardless of credit levels in other shapers, can not prevent the situations described as follows; After a sequence of packets consuming a relatively large amount oϊ the first resource Rl and a relatively small amount of the second resource R2, i.e. in this example relatively long data packets, the credit value of the second shaper S2 will

S 5 reach a relatively high level. If such a packet sequence consuming a lot of the first resource Rl and little of the second resource R2 is followed by a sequence of packets consuming a relatively small amount of the first resource R i , i.e. in this example relatively short data packets, a burst of packets will be permitted until credit value CS2 of the second shaper S2 falls below the first limit I 1 S2,

?.-,■ Correspondingly, after a sequence of packets consuming a lot of the second resource R2 and a only a little of the first resource Rl, i.e. in this example relatively short data packets, the credit value of the first shaper S l will reach a high level, allowing a hurst of a following sequence of packets consuming a relatively small amount of the second resource R2, i.e. in this example relatively short data packels,

2^ until credit value CSl of the first shaper S l fails below the first limit L l S l .

The invention will prevent a build-up of large credit values during data sequences consuming a large amount of one resource in relation to another resource of the processor. This will significantly reduce burst sizes, which in turn will allow lower iθ downstream buffer capacity requirements In the case of the processing means 2 being an asynchronous processing pipeline, as described in said International patent application No. PCT/SE20SS5/0O I ^Q69, the invention will reduce requirements on processing clement buffers, in the form of a FIFO buffers, provided before the processing elements.

5 As mentioned, the shapers S l , S2 preferably use a loose token bucket algorithm, but alternatively, any other suitable admittance algorithm can be used, in case a so called strict token bucket algorithm is used, the first limits Ll S [ , Ll S2 can be positive, and the packet Dl is admitted to the processing means 2 when the credit values CS l, CS2 are at least as large so as to correspond to the respective first limits ;o L I S l . L 1 S2.

Where a strict token bucket algorithm is used, the first limit L I S L L 1 S2 of any or all of the shapcrs can be predetermined and identical for all data packets passing the respective shaper S l ₅ S2. Alternatively, the first limit L l S L I 1 S2 can be individual

15 for each packet, in which case the respective shaper S l , S2 is adapted to read, before admittance, header information (e.g. of the type described above) of each data packet D i , D2, D3, and set the fust limit T 1 S 1 , Ll S2 based on the header information, For example, ihc header information of the respective daia packet Dl , D2, D3 could include a cost C l, C2, C3, corresponding to a first limit value I I S l,

^O L 1 S2 of one of the shapers, Sl. h2. fhus, from the header information of the first packet Dl in the input buffer 4, the cost C l is read, and the firsi limit value L l S l. L 1 S2 is determined a* I I S 1 (or L 1 S2 ) - C 1.

Further, where a strict token bucket algorithm is used, the second limit 1 2S L L2S2, ?^■" (above which the credit value of the respective shaper Sl , S2 is not incremented sf the credit value of the other shaper S i , S2 is below its first limit L1 S2, L1 S2), can either be identical with or higher than the first limit Ll S2. 1 1 S2, In the latter case, the second limit L2S 1 , L2S2 can be set individually for each packet to a value exceeding the first limit Ll S 1 , Ll S2 by a predetermined amount. Hg, 3 illustrates a further embodiment of the present invention, fhe processing means 2 presents more than two features in the form of resources Rl, R2... RX, which each can be any of a large amount of different types of fed? ures, For example, a first and a second resource Rl, R2 can be the bit rate capacity and the packet rate capacity, respectively, of the processing means 2, and farther resources can be processing elements, adapted to process data.

Admission to the processing means 2 is determined by shapers Sl. S2... SN, the amount of which is the same as the amount of processor means resources Rl, Ri ... !0 RN, The limitation property of the first shaper Sl is chosen based on the first resource Rl, and the limitation property oϊ the second shaper S2 is chosen based on the second resource R2, etc.

Preferably, each shaper Sl, S2... SN uses a token bucket algorithm, so that 15 admittance of data i^ based on a respective value CSl, CS2... CSN of a credit parameter. If a credit value CSl, CS2.,, CSN is below a first limit L1S2, L1S2. . LlSN, no data traffic is allowed to pass the respective shaper. Admittance of data traffic is carried out in a manner corresponding to what has been described above with reference to fig.1 and 2. fhυs, if the credit value CSl, CS2... CSN of any of Za the shapers Sl, S2... SN is below the respective first limit L1S2, L1S2... I ISN, the respective credit value CSL CS2 ,,. CSX is periodically, e.g. every clock cycle of the processor 1 , incremented by a respective fixed credit amount. The value of the respective fixed credit amount is based on the frequency of the periodic increments (e.g. every clock cycle) and the respective resource Ri , R2... RN.

If the credit value of any of the shapers Sl, S2 ,,. SN is below the respective first limit 1_1S2, 1_1S2 ,,. LlSX, the credit value of the other shapers Sl, S2... SN is not incremented above a respective second limit I 2Sl, 12S2. , L2SN, lhe second limit L2Sl, L2S2. , , I 2SN can be above or identical with the respective first limit ;-«i I IS2, 11S2...LlSN. In !hc embodiments described with reference io fig. 1-3, the data packet D l , D2, D3. the admission of which is based on the value CS2 of^" the second credit parameter, is identical with the data packet, the admission of which is based on the value CS l of the first credit parameter. However, as exemplified below with

5 reference to fig. 4, the invention is also adaptable so that admittance of a first data packet to the processing means 2 is based on a value of a first credit parameter, the value of the first credit parameter being increased in dependence on a value of a second credit parameter, based on W'hich a second data packet is admitted to the processing means, the second data packet not being identical with the first data io packet. In the example in fig, 4, the first and second data packets enter the processor through separate interfaces.

Referring to fig. 4, a further embodiment of the invention is illustrated. Λ network processor 1 comprises processing means 2 in the form of an asynchronous

\ s processing pipeline 2, as described closer in said International patent application No. PCT7'SE2U05/ϋ01 %^c', included herein by reference, including asynchronous processing elements Pl , ... PK and a synchronous element 8. with elastic buffering 9, 10. As in the case of the embodiment described with reference to fig, 1 and 2, the processing means 2 can alternatively be provided in another form, for example as

20 provided in a RISC-processor.

As described closer in said International patent application No. PCT^/S1I2005/00 ^{! 969}- included herein by reference, data packets D I l , . . DIM enter the processor through interfaces each comprising an input port 3 1 , 32, ... 3\1

?.5 and are stored in respective input buffers 41 . 42. 4M. in addition to which a pipeline arbiter 1 1, S L S2, . .. SM comprises a scheduler 1 1 and a plurality of shapers S I, S2, ... SM. In particular, for each pair of input port 31 , 32. ... 3 M and input buffer 4 1 , 42, ... 4M, a shaper S L S2, ... SM is provided. Admission to the pipeline 2 is determined by the shapers S L S2. ... SM and the scheduler 1 1. which operates

^"io according to a Round Robin algorithm, access io the pipeline being given to the shapes s S L S2. ... SM in a continuous sequence of pollings by the scheduler 1 1. Besides the Round Robin algorithm, alternative scheduling disciplines could be used, for example weighted fair queuing, deficit round robin, deficit weighted round robin, strict priority queuing, earliest deadline first, and first-come first-serve.

5 Preferably, each shaper S l. S2 . .. SM uses a token bucket algorithm, so thai admittance of data is based on a respective value CS l, CS2 . .. CSM of a credit parameter. If a credit value Cb I, CS2 ... CSM is below a first limit Ll S2, Ll S2 . .. L I SM, no data traffic is allowed to pass the respective shaper. If the credit value CS i , CS2 ... CSM of any of the shapcrs S l, S2 ... bM is below the respective first

Ki limit L I S2. L1 S2 ... L l SM, the respective credit value CSl , CS2 ... CSM is periodically, e.g. every clock cycle of the processor I , incremented by a respective fixed credit amount. The value of the respective fixed credit amount is based on a resource of the processing means 2. for example the packet rate capacity thereof, the frequency of the periodic increments (e.g. every clock cycle) and the amount of

15 input ports 31. 32, ... 3M. The resource of the processing means 2, on which the fixed credit amount increments of the shapers S l , S2 . .. SM are based, can alternatively be the bit rate capacity of the processing means 2, or any other performance parameter thereof. As a further alternative, the fixed credit amount increments of different shapers S l . S2 ... SM can be based on different processing o elements P l , ... PK, 8 to which traffic from the respective shaper is addressed.

11 the credit value of any of the shapers SL S2 . .. SM is below the respective first limit I 1 S2, 1 1 S2 .. . L l SN, the credit value of the other shapers S l , S2 . .. SM is not incremented above a respective second limit L2S1 , 1 2S2 ... L2SM. fhe second zs limit L2S 1 , L2S2 . . L2SM can be above or identical with the respective first limit L1 S2. J 1 S2 .. . L 1 SM. 1 his prevents a build-up of a large credit in a shaper at an interface not receiving traffic, or receiving a relatively small How of traffic for a period time, so thai data burst from such an interface can be avoided when such a time period has passed, (It should be noted that in this presentation, a shaper being

:-o provided at an interface or an input port, indicates that it is either physically provided by, or functionally connected to the interface or the input port.) Still referring Io fig. 4. it should be mentioned that at each of the interfaces or input ports 31, 32, ... 3 M a plurality of shapers can be provided as described above with reference to fig. 1-3., the credit of the shapers at each interlace being respectively

S adjusted based on respective resources of the processing means. Thus, if the credit value of any of the shapers is below the respective first limit, the credit value of the other shapers at the same interface is not incremented above a respective second limit. Alternatively, if the credit value of any of the shapers is below the respective first limit, the credit value of ail other shapers, including the ones at other interfaces,

Ϊ O is not incremented above a respective second limit.

Alternatively or in addition, any of the embodiments described above with reference to fig, 1-4 can be adjusted so that, if any of the input buffers 4, 4 L 42, ... 4 M is empty, the credit value of the shaper (or shapers}, adapted to receive traffic from ! 5 this input buffer 4, 41 , 42, ... 4M, is not incremented above the second limit L2S 1 , L2S2 ... L2SM. This prevent a build-up of a large credit in a shaper at an interface noi receiving traffic, or receiving a relatively small flow of traffic for a period time, so that data burst from such an interface can be avoided when such a time period has passed.

20

Claims

CI AIMS

1. A method for a processor (1 ) comprising processing means (2 s, the method comprising the steps of

^: - admitting a data packet (Dl, D2. D3) to the processing means (2) based at least partly on a -value (CS l) of a first credit parameter and a first limit (L l S D of the first credit paramo! er. and

- decreasing the value (CS I j of the first credit parameter if the data packet (L)L D2, D3) is admitted to the processing means (2), characterized by the

) step of

- increasing the value (CSl ) of the first credit parameter, in dependence on a value (CS2) υf a second credit parameter, hascd on which a data packet (Dl , D2. D3) is admitted to the processing means (2)

5 2. A method according to claim 1. comprising the step of comparing the value

(CS l) of the first credit parameter to a second limit (L2S 1) of the first credit parameter, the value (CS 1) of the first credit parameter not being increased, so as to become larger that the second limit (L 2S l ) of the firs! credit parameter, if the value (CS2) of the second credit parameter is below a first limit (Ll S2) of the second credit parameter,

3 A method according to claim 2, wherein the second limit (L 2 S i ) of the first credit paiameter is higher than the first limit (Ll S Ij of the first credit parameter.

4. Λ method according to an> of she preceding claims, wherein the step of increasing the value (CS l) of the first credit parameter is based at least partly on a firs! resource (Rl ) or a second resource (R2) of the processing means (2)

5. A method according to claim 4, wherein the first resource (R l) is a bit rate capacity of the processing means (2), and the second resource (R2) is a data packet rate capacity of she processing means. (2).

6. A method according to any of the preceding claims, wherein the value

(CS2) of the second credit parameter is decreased if the data packet (D l , U2, D3) is admitted to the processing means (2).

7 A method for a processor ( I ) comprising processing means (2), the method comprising the steps of

- admitting a data packet (Dl . D2, D3) to the processing means (2) based at least partly on a value ^CSl) of a first credit parameter and a first limit

(J , I S i ) of the first credit parameter, and

- decreasing the value (CS 1) of the first credit parameter if the data packet (D 1 , D2. D3) is admitted to the processing means (2), characterized by the step of

- increasing the value (CS l ) of the first credit parameter, in dependence on a data storage level in a buffer (4, 4 1 , 42, ... 4M) in which the data packet is stored before admitted to the processing means (2),

8 A method according to claim 7, wherein the value (CS I j of the first credit parameter is not increased, so as to become larger that the second limit (L2S 1 ) of the first credit parameter, if the buffer (4, 41, 42, ... 4M) is empϊy.

9, A processor (1) comprising processing means (2), the processor being adapted to

- admit a data packet (D l, 1)2, D3) to the processing means (2) based at least πartlv on a value (CS i ) of a first credit parameter and a first limit (Ll Sl) of the first credit parameter, and - decrease the value (CS 1 ) of the first credit parameter if the data packet (D 1 , D2, D3) is admitted to the processing means (2). characterized in that the processor is adapted to increase the value (CS l) of the first credit parameter, in dependence on a 5 value (CS2) of a second credit parameter, ba^ed on which a data packet (D ! ,

D2, D3) is admitted to the processing means (2).

10, A processor according to claim 9. bemg adapted to compare the value

(CSl ) of the first credit parameter to a second limit (L2S 1 ) υf the first 10 credit parameter, and to not increase the value (CS l ) of the first credit parameter, so as to become larger that the second limit (L2S 1 ) of the first credit parameter, if the value (CS2) of the second credit parameter is below a first limit (Ll S2) of the second credit parameter.

\ 5

1 1. A processor according to claim 10, wherein the second limit (L2S 1) of the first credit parameter is higher than the first limit (I I SO of the first credit parameter.

12. A processor according to any of the claims 9-11 , adapted to increase, based Λ> at least partly on a first resource (R l) or a second resource (Rl) of the processing means (2). the value (CS 1) of the first credit parameter.

13. A processor according to claim 12, wherein the first resource (R l) is a bit rate capacity of the processing means (2), and the second resource ( R2) 25 is a data packet rate capacity of the processing means (2).

14. A processor according to any of the claims ^c'~ !3, adapted to decrease the value (CS2) of the second credit parameter if the data packet (D l, D2, D3 ) is admitted to the processing means (2 ).

15, A processor tor a processor f_vl) comprising processing means (2). the processor being adapted io

~ admit a data packet { D i , D2, F) 3 ) to the processing means (2) based at least partly on a value (Cb I) of a first credit parameter and a first limit (Ll Sl) of the first credit parameter, and

- decrease the value (CS l) of the first credit parameter if the data packet (D L D2, 1)3) is admitted to the processing means (2), characterized in that the processor is adapted to increase the value (CS 1 ) of die first credit parameter, in dependence on a data storage level in a buffer (4, 4 L 42. ... 4M) adapted to store the data packet before admitted to the processing means (2).

16. Λ processor according to claim IS, being adapted to not increase the value

(CSl ) of the first credit parameter, so as to become larger that the second limit (L2S 1) of the first credit parameter, if the buffer (4. 4 L 42,

... 4M) is empty,