WO2007146532A2 - Data register with efficient erase, program verify, and direct bit-line memory access features - Google Patents

Data register with efficient erase, program verify, and direct bit-line memory access features

Info

Publication number
WO2007146532A2
WO2007146532A2 PCT/US2007/068947 US2007068947W WO2007146532A2 WO 2007146532 A2 WO2007146532 A2 WO 2007146532A2 US 2007068947 W US2007068947 W US 2007068947W WO 2007146532 A2 WO2007146532 A2 WO 2007146532A2
Authority
WO
Grant status
Application
Patent type
Prior art keywords
memory
verify
circuit
line
dma
Prior art date
Application number
PCT/US2007/068947
Other languages
French (fr)
Other versions
WO2007146532A3 (en )
Inventor
Nicola Telecco
Original Assignee
Atmel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure

Abstract

A programmable memory device circuit comprising a sense and programming circuit (20) , a latch, circuit (21) , a verify circuit (26) for coupling the latch circuit logic value to a shared indicator line (57) , and a direct memory access circuit (23) coupled to the verify circuit. The DMA circuit couples a bit line (65) to the verify circuit, and the verify circuit couples the direct memory access circuit to a shared verify indicator and DMA line.

Description

Description

DATA REGISTER WITH EFFICIENT ERASE, PROGRAM VERIFY,

AND DIRECT BIT-LINE MEMORY ACCESS FEATURES

TECHNICAL FIELD

This invention relates generally to semiconductor electrically programmable read only memories (EPROM) , electrically erasable programmable read only memories (EEPROM) , and Flash memories. This invention relates specifically to a circuit and method for programming and testing nonvolatile memory cells.

BACKGROUND Nonvolatile memory devices include a memory array containing a plurality of memory cells, addressing, and programming circuits. Included in the memory device are memory data registers which are generally used to store and retrieve data information stored in a memory cell. A data register can be used to store information that is to be written into a memory cell and may also be used to retrieve and store the information from a memory cell. An internal verify function within the data register includes the ability to verify, at a bit level, the expected polarity or data value stored in a memory cell and to communicate the verification status to a memory controller. Data registers are essential building blocks present in modern semiconductor memories, such as high-density flash memory devices, providing efficient programming and erase functions to verify the data to be stored in the memory cells.

Referring to Fig. 1, a memory array 10, within a memory device, has a plurality of storage or memory cells (not shown) and is coupled to a bit line (BL) select circuit 12. The bit line select circuit 12 _ o —

selects a bit -line coupled to a memory array 10 of memory cells. In conjunction with a word line selection circuit (not shown) , a memory cell is selected and coupled to a sense and program circuit 14. Generally, a selected memory cell is programmed to store an associated data value. During a program operation, data values are loaded into a page data register 16. For example, 512 or 1024 data values may be loaded into the data register 16. A selected memory cell is associated with a single data value in the data register 16. Next, a read operation is performed to determine whether the data value stored in the selected memory cell is correctly programmed.

A latch and verify circuit 17 stores the data value read from the memory cell . A comparison between the data value stored in the selected memory cell and the associated data value in the data register 16 is performed. If the data value read from the selected memory cell and the data value stored in the data register 16 match, then the data value programmed in the selected memory cell is verified, and the programming operation for the selected memory cell ends. If the data value read from the selected memory cell and the associated data value stored in the data register 16 do not match, additional programming steps must be performed on the selected memory cell. Iterative programming steps continue until all of the selected memory cells associated with a page of data values in the data register 16 have been verified.

A direct memory access (DMA) circuit 18 may be included within a memory device to facilitate testing operations of the memory device. External pads on the memory device integrated circuit are used to access specific bit lines during probe and test operations. Examples of operations performed during a test operation include: applying predetermined voltages to specific memory cells, measuring leakage current, measuring operating currents, and measuring a variety of memory cell characteristics.

Conventional DMA circuitry requires decoding components 19 for selecting a specific bitline. In Fig. 1, the NOR gate 3 represents the final stage of this DMA decoding circuitry 19. In the DMA circuit, the DMA decoding block 19 and the DMA select device 4 selectively couple a selected bit line to a global DMA access line 5. The global DMA access line 5 may be coupled to a pad on the memory device integrated circuit to directly access bit line information from the memory array 10 during a probe or testing operation. It is desirable to use as few devices as possible in the verify circuit 17, and in the DMA decoding circuit 19. Since, a DMA circuit 19 is associated with each data value stored in the data register 16, reducing the number of transistors in the DMA decoding circuit 19 may provide a substantial savings in the layout of the memory device.

SUMMARY OF THE INVENTION

A memory device and method of controlling the memory device in accord with the present invention includes a common verify and DMA (direct memory access) line. Verify and DMA circuits provide an efficient circuit design and layout to perform an internal erase verification or a program verification and provide DMA access to memory device bit lines. DMA access is implemented here without requiring separate DMA decoding circuitry. The DMA (direct memory access) circuit, having direct bit line access, is used for testing and characterizing memory cells within a memory array. The verification circuit and DMA circuit provide an efficient design having a reduced number of transistors. BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram of verification and DMA functions within a prior art memory device.

Fig. 2 is an exemplary circuit configured to perform verification and DMA operations.

Fig. 3 is an exemplary internal verify timing diagram for the exemplary circuit of Fig. 2.

Fig. 4 is an exemplary circuit diagram configured to perform verification and DMA operations with multiple data registers.

Fig. 5 is an exemplary circuit diagram configured to perform verification and DMA operations with four data registers.

DETAILED DESCRIPTION OF THE INVENTION

An innovative data register circuit which includes the functions of setting, resetting, internal verification, and DMA access are performed by shared circuits that greatly reduce the transistor count and routing congestion within the memory device or integrated circuit. Shared circuits may provide a more compact and efficient memory layout . The concept of sharing circuits between groups of data registers provides an improvement to the layout efficiency of the memory device. A controller, internal to a memory device, controls a program operation on a selected memory cell . When the selected memory cell is programmed, the data value in the selected memory cell is compared to the associated single data value stored in a data register to verify that the selected memory cell is properly programmed .

Referring to Fig. 2, an exemplary circuit within a memory device includes a memory array 9, a bit line select circuit 11, a data register multiplexer (MUX) circuit 13, a sense and program driver circuit 20, a latch circuit 21, a DMA circuit 23, and a verify circuit 26.

The sense and program driver circuit 20 biases selected memory cells within the memory array 9 via the bit line select circuit 11. A bit line precharge device 58 is coupled to a voltage source λ/cc and is controlled via the bit line precharge (ZBLPCEB) line 59. The precharge device 58 may be used to precharge a sense node (SNODE) 33 coupled to the gate of a verify pass transistor 67, and to apply bias voltages to selected memory cells through a voltage bias device 62 which is controlled by the voltage bias control (VBIAS) line 60. A verify transistor 68 is coupled to a verify pass transistor 67 and controlled at verify (ZVFY) line 69. The verify pass transistor 67 is also coupled to ground. Transistors 71-74 form a program driver controlled by complementary programmable signals (PGMEN and PGMENB) and an input level from the ENODE 63 of the latch circuit 21. When the program driver is enabled, the SNODE 33 is driven to a value that is the logical inverse of the

ENODE value, which then is placed onto the bit line 65 via the voltage bias device 62.

An exemplary embodiment of the latch circuit 21 is implemented using four transistor devices 21A-D configured as two cross-coupled inverters. A first inverter comprised of two transistor devices 2 IA-B has its input coupled to a (latch) output 64 of a second inverter comprised of two transistor devices 21C-D. The second inverter has its (latch) input 63 coupled to the output of the first inverter. When the input of one of the inverters is driven to a predetermined logic value, its inverted output drives the other inverter and the predetermined logic value is latched into the cross coupled inverters circuit. The latch circuit 21 may be implemented to include tri-state devices 21E-H. An exemplary embodiment of the verify circuit 26 is implemented using transistor devices 41, 42, 45, 46, and 48. The first verify transistor device 41 is used to set the latch circuit 21 to a predetermined value, and is coupled to a first node (VNODE) 64 of the latch circuit 21. This first verify transistor device 41 is activated via a set (ZSET) line 52. The second verify transistor device 42 is used to reset the latch circuit 21 to a predetermined value, and is coupled to a second node (ENODE) 63 of the latch circuit 21. The second verify transistor device 42 is activated via a reset (ZRST) line 53. The third verify (driver) transistor device 45 is used to drive a global verify indicator and shared DMA (ZVFYSTAT) line 57. The junction of the first and second verify transistors 41, 42 will be referred to as the verify failure (ZVFYFAIL) line 54, which drives the third verify transistor device 45. The fourth verify (discharge) transistor device 46 is controlled by a verify reset (ZVFYRST) line 55, and is used to discharge the verify failure (ZVFYFAIL) line 54, through device 48. Device 48 is activated by a control (ZDMAB) line 61, and is generally used to couple the verify circuit 26 to ground. In particular, the transistor device 48 is generally used in conjunction with the fourth verify transistor device 46 to discharge the verify failure line 54.

An exemplary embodiment of the DMA circuit 23 is implemented using a DMA transistor device 47. The DMA (pass) transistor device 47 is activated by a DMA control (ZDMA) line 56. The DMA transistor device 47 when activated in conjunction with the third verify transistor device 45 electrically couples a selected bit line 65 to the global verify indicator and shared DMA (ZVFYSTAT) line 57. The ZVFYSTAT line 57 can be coupled to an external VCC voltage via a global pull-up device (not shown) of the memory. The discharge transistor device 48 is shut off during all DMA operations. Control lines 56 and 61 are complementary, so only one of DMA transistor 47 and verify discharge device 48 is activated at one time.

The verify circuitry 26 and the DMA circuitry 23 have been illustrated in this example using NMOS transistor devices. Alternatively, they could be constructed using PMOS devices, or using both NMOS and PMOS devices.

The DMA circuit and its test functions are activated by loading a predetermined pattern of l's and O's into associated data registers to activate or deactivate the third and fourth verify transistor devices 45, 46. The first DMA pass transistor device 47 is also activated to couple at least one bit line 65 to the global verify indicator and shared DMA (ZVFYSTAT) line 57 during, for example, a test operation.

During a memory transistor programming operation, a programming or voltage pulse is applied to a selected memory cell . If in the course of programming a plurality of memory cells at least one cell has not been properly programmed, additional programming pulses must be applied to complete the programming of those cells. After each programming pulse is applied to a memory cell, the memory cell is read and the logic value stored in the memory cell is verified.

A read (verify) operation is performed on each cell after each respective programming voltage pulse has been applied to the cell, in order to determine whether the resulting voltage of the memory cell is close to a desired stored value. A memory cell is read to verify whether the desired stored value in the memory cell has been reached. During successive write and read operations, a write pulse voltage is increased in amplitude. Write pulses to a selected memory cell are decoupled from the voltage pulse circuits after the information read from the selected memory cell has been verified to equal the value held in the latch circuit that is associated with the selected memory cell .

For this particular nonvolatile memory technology, in order to program a particular memory cell, the bit line 65 is discharged to ground. In order to inhibit programming of a selected memory cell, the bit line 65 is coupled to a supply voltage Vcc or a programming bias voltage. During a program operation, a particular memory cell is coupled to the bit line through the program driver circuit (transistors 71-74) and the bias device 62. The latch node 63 will initially assume a high logic state if the memory cell is intended to be programmed, and will initially assume a low logic state if programming of that cell is inhibited. The latch circuit 21 is driven to this pre-programmed state by applying any positive pulse to the reset (ZRST) line 53. The verify fail (2VFYFAIL) line 54 must be at ground in order to accomplish the reset .

During an internal program verify operation, the set (ZSET) line 52 and reset (ZRST) line 53 are initially held to a "0" or a low logic state. In this initial state, the latch output 64 will not be coupled to the verify fail line 54. After sensing, the latch node 63 will flip to a low logic state to indicate the associated memory cell has been correctly programmed, but will remain at a high state if the programming of the memory cell is incomplete.

Referring to Fig. 3, with continued reference to Fig. 2, at the start of a verify operation, a positive voltage 310 is applied to the second DMA control (ZDMAB) line 61, and stays high for the duration of the verify operation. Node 49 discharges to ground. A positive pulse 311 applied to the verify reset (ZVFYRST) line 55 selectively activates the DMA and verify discharge transistors 46 and 48, and thereby discharges the verify fail (ZVFYFAIL) line 54. A positive pulse 313 applied to the reset (ZRST) line activates the program verify transistor 42 and couples the verify fail (ZVFYFAIL) line 54 to ENODE 63 of the latch circuit 21. If the verify fail (ZVFYFAIL) is now high, transistor 45 is active and couples the ZVFYSTAT line 57 to ground via transistor 48 at node 49. Thus, if all bits have been programmed successfully (no fails) , ZVFYSTAT line 57 stays high, indicating that the program verify has passed. If any one bit has not been completely programmed yet, ZVFYSTAT line 57 will be pulled low, indicating a failure. A similar operation is performed during an erase operation, except that VNODE 64 will be coupled to the verify fail (ZVFYFAIL) line via transistor 41 using a positive pulse on ZSET.

Referring to Fig. 1, the DMA line 5 of the prior art is generally implemented as a single NOR gate providing a coupling to a selected bit line. Referring to Fig. 2, the global verify indicator and shared DMA line 57 combine the verify and DMA indicators into a single line. Each verify and DMA circuit is generally associated with a single data register. A reduction in the transistor count in implementing a verify circuit and in a DMA circuit may be realized by combining a global verify indicator line and a global DMA line. A further reduction in the transistor count may be realized by sharing portions of the verify circuit and the DMA circuit between multiple data registers.

For a single data register in a specific exemplary embodiment, six transistors are used. When functions are shared between two data registers, a total of nine transistors are used, or 4 1/2 transistors average per data register. When functions are shared between four data registers, a total of 15 transistors are used, or 4 1/4 transistors average per data register. In comparison, the prior art circuit using the NOR gate 3 used 11 transistors for each data register, and therefore the new circuit provides a substantial savings in the device area and savings in the complexity of interconnect lines .

The memory array may also have a global verify indicator line for a group of memory cells within the entire memory array. For example, the memory array may be divided into eight segments (1-8) with each segment having a global verify indicator line (also used for DMA operations) associated with each segment (1-8) . In alternate embodiments, portions of the verify and DMA circuits are shared between multiple or a plurality of data registers. For example, referring to Fig. 4, two data registers share portions of the same verify and DMA circuit. In a shared configuration, the DMA (pull down) transistor 403, the verify (reset) transistor 404, and the verify (driver) transistor 405, are shared between a plurality of data registers and/or bit lines. In a shared configuration, each data register 413A-B or bit line 465A7 465B continues to have an associated DMA pass gate transistor 401A, 401B. Each DMA pass gate transistor 401A, 401B may be coupled to a bit line that is associated with either an even or odd bit line. In another example, referring to Fig. 5, four data registers share portions of the same verify and DMA circuit. Each data register 513A-D or bit line 565A-D, continues to have an associated DMA pass gate transistor 501A-D. A DMA (pull down) transistor 503, the verify (reset) transistor 504, and the verify (driver) transistor 505, are shared. Referring again to Fig. 4, DMA pass gate transistors 401A, 401B are normally activated during testing and characterization operations. DMA pass gate transistors 401A, 401B, when activated, provide the ability to couple an individual bit line, or simultaneously couple multiple bit lines to a global verify indicator and shared DMA line 457. The verify transistor 405 is coupled to both DMA select transistors 401A, 401B and activated in conjunction with either DMA select transistors 401A, 401B to couple an individual bit line or multiple bit lines to the global verify indicator and shared DMA line 457. When more than one DMA pass transistor 401A, 401B is activated, and the global verify indicator and shared DMA line 457 is shared, individual data values, or specific patterns of data values, are loaded into the data register to load specific values into each latch 420A, 420B. The verify transistor 405 is selectively activated to couple the DMA pass transistors 401A, 401B to the global verify indicator and shared DMA line 457 by coupling the set transistor 441. For example, the set transistor 441 may be activated to pass a logic value from the latch 420A, 420B to the verify transistor 405.

Additionally, all of the DMA pass transistors may be simultaneously activated, coupling all of the bit lines to the global verify indicator and shared DMA line 457 during a test procedure to test the overall leakage of the entire memory array. Other tests may also be conducted on an entire memory array, or selected portions, or selected memory cells, for example, for characterization tests without the need for a decode circuit to drive the DMA circuits .

Claims

ClaimsWhat is claimed is:
1. A programmable memory device comprising: a sense and programming circuit configured to be selectively coupled to a memory cell bit line; a latch circuit coupled to the sense and program circuit, the latch circuit configured to store a predetermined logic value; a verify circuit coupled to the latch circuit, the verify circuit including a verify driver transistor coupled to a shared indicator line and a verify discharge transistor configured to discharge a control input of the verify driver transistor; a direct memory access (DMA) circuit including a DMA pass transistor coupled to the verify discharge transistor and also coupled to a selected bit line, the direct memory access circuit further including a DMA discharge transistor coupled to the verify discharge transistor and also coupled to a ground voltage and configured to couple the verify discharge transistor to the ground voltage; and the verify circuit and the direct memory access circuit each being configured to selectively couple the selected bit line to the shared indicator line.
2. The programmable memory device of claim 1, wherein the latch circuit includes tri-state devices that enable or disable the latch circuit.
3. The programmable memory device of claim 1, wherein the verify circuit is shared between a plurality of data register circuits.
4. The programmable memory device of claim 1, wherein the verify circuit, in combination with the direct memory access circuit, is configured to couple the ground voltage to the control input of the verify driver transistor.
5. The programmable memory device of claim 1, wherein the verify driver transistor is configured to couple the latch circuit predetermined logic value to the shared indicator line.
6. The programmable memory device of claim 1, wherein the verify discharge transistor discharges the control input of the verify driver transistor prior to coupling the latch circuit predetermined logic value to a shared indicator line.
7. The programmable memory device of claim 1, further comprising a set and reset transistor coupled to the latch circuit and verify circuit.
8. The programmable memory device of claim 1, further comprising a bit line charge transistor coupled to the bit line and also coupled to a charge voltage source.
9. A method of controlling a programmable memory device, the method comprising: activating a verify discharge transistor; activating a DMA discharge transistor; discharging a control input of a verify driver transistor; deactivating the verify discharge transistor and the DMA discharge transistor; and activating simultaneously, the verify driver transistor and a direct memory access (DMA) pass transistor, thereby coupling a selected bit line to a shared indicator line.
10. The method of controlling a programmable memory device of claim 9, further comprising pre-charging the indicator line to a high logic state.
11. The method of controlling a programmable memory device of claim 9, further comprising sharing the verify discharge transistor, the DMA discharge transistor, and the verify driver transistor between a plurality of memory data register circuits.
12. The method of controlling a programmable memory device of claim 9, wherein discharging a verify driver transistor control input is performed by coupling the verify driver transistor control input to a ground voltage.
PCT/US2007/068947 2006-06-08 2007-05-15 Data register with efficient erase, program verify, and direct bit-line memory access features WO2007146532A3 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11422960 US7580291B2 (en) 2006-06-08 2006-06-08 Data register with efficient erase, program verify, and direct bit-line memory access features
US11/422,960 2006-06-08

Publications (2)

Publication Number Publication Date
WO2007146532A2 true true WO2007146532A2 (en) 2007-12-21
WO2007146532A3 true WO2007146532A3 (en) 2008-05-08

Family

ID=38832605

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/068947 WO2007146532A3 (en) 2006-06-08 2007-05-15 Data register with efficient erase, program verify, and direct bit-line memory access features

Country Status (2)

Country Link
US (1) US7580291B2 (en)
WO (1) WO2007146532A3 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7580291B2 (en) 2006-06-08 2009-08-25 Atmel Corporation Data register with efficient erase, program verify, and direct bit-line memory access features

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7486566B2 (en) * 2006-12-28 2009-02-03 Intel Corporation Methods, apparatus, and systems for flash memory bit line charging

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5509018A (en) * 1992-09-11 1996-04-16 International Business Machines Corporation Flash-erase-type nonvolatile semiconductor storage device
US5588112A (en) * 1992-12-30 1996-12-24 Digital Equipment Corporation DMA controller for memory scrubbing
US5701516A (en) * 1992-03-09 1997-12-23 Auspex Systems, Inc. High-performance non-volatile RAM protected write cache accelerator system employing DMA and data transferring scheme
US5822251A (en) * 1997-08-25 1998-10-13 Bit Microsystems, Inc. Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers
US6021069A (en) * 1998-09-24 2000-02-01 Macronix International Co., Ltd. Bit latch scheme for parallel program verify in floating gate memory device
US6026019A (en) * 1998-06-19 2000-02-15 International Business Machines Corporation Two square NVRAM cell
US20040013020A1 (en) * 2002-07-18 2004-01-22 Choo Yong-Jae Read only memory devices with independently precharged virtual ground and bit lines and methods for operating the same
US20060023512A1 (en) * 2004-08-02 2006-02-02 Hiroshi Maejima Semiconductor memory device
US20060092716A1 (en) * 2004-11-03 2006-05-04 Samsung Electronics Co., Ltd., Memory devices using tri-state buffers to discharge data lines, and methods of operating same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69630672D1 (en) * 1996-03-29 2003-12-18 St Microelectronics Srl Reference system for determining the programming / non-programming state of a memory cell, particularly for non-volatile memory
US5787484A (en) * 1996-08-08 1998-07-28 Micron Technology, Inc. System and method which compares data preread from memory cells to data to be written to the cells
US5956289A (en) * 1997-06-17 1999-09-21 Micron Technology, Inc. Clock signal from an adjustable oscillator for an integrated circuit
KR100324937B1 (en) 1999-06-29 2002-02-28 박종섭 Data register circuit of semiconductor memory device
DE10120672C2 (en) 2001-04-27 2003-03-20 Infineon Technologies Ag Data register with integrated signal level conversion
JP4426868B2 (en) * 2003-04-04 2010-03-03 株式会社ルネサステクノロジ Nonvolatile semiconductor memory device and a semiconductor integrated circuit device
US6741111B1 (en) 2003-04-21 2004-05-25 Pericom Semiconductor Corp. Data register for buffering double-data-rate DRAMs with reduced data-input-path power consumption
US7580291B2 (en) 2006-06-08 2009-08-25 Atmel Corporation Data register with efficient erase, program verify, and direct bit-line memory access features

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5701516A (en) * 1992-03-09 1997-12-23 Auspex Systems, Inc. High-performance non-volatile RAM protected write cache accelerator system employing DMA and data transferring scheme
US5509018A (en) * 1992-09-11 1996-04-16 International Business Machines Corporation Flash-erase-type nonvolatile semiconductor storage device
US5588112A (en) * 1992-12-30 1996-12-24 Digital Equipment Corporation DMA controller for memory scrubbing
US5822251A (en) * 1997-08-25 1998-10-13 Bit Microsystems, Inc. Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers
US6026019A (en) * 1998-06-19 2000-02-15 International Business Machines Corporation Two square NVRAM cell
US6021069A (en) * 1998-09-24 2000-02-01 Macronix International Co., Ltd. Bit latch scheme for parallel program verify in floating gate memory device
US20040013020A1 (en) * 2002-07-18 2004-01-22 Choo Yong-Jae Read only memory devices with independently precharged virtual ground and bit lines and methods for operating the same
US20060023512A1 (en) * 2004-08-02 2006-02-02 Hiroshi Maejima Semiconductor memory device
US20060092716A1 (en) * 2004-11-03 2006-05-04 Samsung Electronics Co., Ltd., Memory devices using tri-state buffers to discharge data lines, and methods of operating same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SAKUI K. ET AL.: 'A Sophisticated Bit-by-Bit Verifying scheme for NAND EEPROMs' SYMPOSIUM ON VLSI CIRCUITS DIGEST OF TECHNICAL PAPERS, [Online] 1998, Retrieved from the Internet: <URL:http://www.ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=688098> *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7580291B2 (en) 2006-06-08 2009-08-25 Atmel Corporation Data register with efficient erase, program verify, and direct bit-line memory access features

Also Published As

Publication number Publication date Type
WO2007146532A3 (en) 2008-05-08 application
US7580291B2 (en) 2009-08-25 grant
US20080005416A1 (en) 2008-01-03 application

Similar Documents

Publication Publication Date Title
US6681358B1 (en) Parallel testing of a multiport memory
US6556508B2 (en) Integrated circuit memory device having interleaved read and program capabilities and methods of operating same
US6191973B1 (en) Mram cam
US7274611B2 (en) Method and architecture to calibrate read operations in synchronous flash memory
US20050024956A1 (en) Column redundancy for digital multilevel nonvolatile memory
US20110002169A1 (en) Bad Column Management with Bit Information in Non-Volatile Memory Systems
US6865098B1 (en) Row redundancy in a content addressable memory device
US6614691B2 (en) Flash memory having separate read and write paths
US5297029A (en) Semiconductor memory device
US6515900B2 (en) Non-volatile memory with background operation function
US6421286B1 (en) Semiconductor integrated circuit device capable of self-analyzing redundancy replacement adapting to capacities of plural memory circuits integrated therein
US6178132B1 (en) Non-volatile integrated circuit having read while write capability using one address register
US20030043628A1 (en) Non-volatile semiconductor memory device with accelerated column scanning scheme
US6400624B1 (en) Configure registers and loads to tailor a multi-level cell flash design
US6507514B1 (en) Integrated circuit memory chip for use in single or multi-chip packaging
US6341090B1 (en) Method for repairing semiconductor integrated circuit device
US6888764B2 (en) Semiconductor device including semiconductor memory
US6003149A (en) Test method and apparatus for writing a memory array with a reduced number of cycles
US6307790B1 (en) Read compression in a memory
US6269016B1 (en) MRAM cam
US20060253641A1 (en) Multiple erase block tagging in a flash memory device
JP2002150789A (en) Non-volatile semiconductor memory
US7046559B2 (en) Semiconductor memory device capable of erasing or writing data in one bank while reading data from another bank
US5952833A (en) Programmable voltage divider and method for testing the impedance of a programmable element
US6101150A (en) Method and apparatus for using supply voltage for testing in semiconductor memory devices

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07783767

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase in:

Ref country code: RU

122 Ep: pct application non-entry in european phase

Ref document number: 07783767

Country of ref document: EP

Kind code of ref document: A2