WO2007140288A2 - Formation of improved soi substrates using bulk semiconductor wafers - Google Patents

Formation of improved soi substrates using bulk semiconductor wafers Download PDF

Info

Publication number
WO2007140288A2
WO2007140288A2 PCT/US2007/069720 US2007069720W WO2007140288A2 WO 2007140288 A2 WO2007140288 A2 WO 2007140288A2 US 2007069720 W US2007069720 W US 2007069720W WO 2007140288 A2 WO2007140288 A2 WO 2007140288A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor
semiconductor device
substrate
insulator
Prior art date
Application number
PCT/US2007/069720
Other languages
French (fr)
Other versions
WO2007140288A3 (en
Inventor
Dureseti Chidambarrao
William K. Henson
Hung Y. Ng
Kern Rim
Clement H. Wann
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Priority to EP07797764.3A priority Critical patent/EP2024995B1/en
Priority to CN2007800189825A priority patent/CN101454889B/en
Publication of WO2007140288A2 publication Critical patent/WO2007140288A2/en
Publication of WO2007140288A3 publication Critical patent/WO2007140288A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Definitions

  • the present invention relates to improved semiconductor-on-insulator (SOI) substrates. More specifically, the present invention relates to SOI substrates that each has one or more device regions including a semiconductor device layer that is isolated from a base substrate layer by a buried insulator layer and supported by one or more vertical insulating pillars, as well as to methods and precursor structures that can be used to form such SOI substrates.
  • SOI substrates that each has one or more device regions including a semiconductor device layer that is isolated from a base substrate layer by a buried insulator layer and supported by one or more vertical insulating pillars, as well as to methods and precursor structures that can be used to form such SOI substrates.
  • SOI substrate structure typically contains a buried insulator layer, which functions to electrically isolate a top semiconductor device layer from a base semiconductor substrate.
  • Active devices such as transistors, are typically formed in the top semiconductor device layer of the SOI substrate.
  • SOI devices i.e., SOI devices
  • SOI devices offer many advantages over their bulk counterparts, including, but not limited to: reduction of junction leakage, reduction of junction capacitance, reduction of short channel effects, better device performance, higher packing density, and lower voltage requirements.
  • One conventional method for forming a SOI substrate from a bulk silicon substrate involves selective masking of certain regions on the surface of a bulk silicon substrate, followed by anodization to form porous silicon at unmasked regions on the silicon substrate surface. Silicon at the masked regions is not porified and therefore forms solid silicon pillars. A silicon layer is subsequently grown over both the porous and non-porous portions of the silicon substrate. By forming an opening in the subsequently grown silicon layer, the porous portions of the silicon substrate become exposed and can therefore be selectively removed to form hollow regions underneath the subsequently grown silicon layer, while the non-porous silicon pillars provide the necessary structural support for the silicon layer during this process. Finally, the hollow regions can be filled with an insulator material to form a buried insulator film underneath the silicon layer, thereby resulting in a SOI substrate.
  • Figure IA shows a top view of a SOI substrate formed by the above-described conventional method
  • Figures IB and 1C respectively show cross-sectional views of such a SOI substrate along line I and line II.
  • the conventional SOI substrate comprises a device region 2 located over a base substrate 12 and encircled by trench isolation regions 20.
  • a semiconductor device layer 16 is located at the device region 2, with a gate dielectric layer 3 and gate electrodes 5 are located thereabove.
  • the semiconductor device layer 16 is separated from the base substrate 12 by a buried insulator layer 14, thereby forming a SOI configuration.
  • Silicon pillars 11 are located at edges of the device region 2, as shown in Figures IA and 1C. The silicon pillars 11 provide structural support for the semiconductor device layer 16 before the buried insulator layer 14 is formed.
  • the silicon pillars 11 in the above-described conventional SOI substrate structure extend from the base substrate 12 through the buried insulator layer 14 to overlap with portions of the semiconductor device layer 16, as shown in Figure 1C.
  • the overlap portions between the silicon pillars 11 and the semiconductor device layer 16 behave more like bulk structures than SOI structures, which undermines the advantages offered by true SOI structures.
  • the present invention relates to a semiconductor-on-insulator (SOI) substrate comprising one or more device regions, each of which comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, wherein the semiconductor device layer of each device region is supported by one or more vertical insulating pillars.
  • SOI semiconductor-on-insulator
  • the present invention relates to a precursor substrate structure comprising at least one device region having at least a base semiconductor substrate layer and a semiconductor device layer with an air gap located therebetween, wherein the semiconductor device layer is supported by one or more vertical insulating pillars.
  • the present invention relates to a method for forming a semiconductor-on-insulator (SOI) substrate, comprising: forming a substrate structure comprising at least a base semiconductor substrate layer and a semiconductor device layer with a sacrificial layer located therebetween; patterning the substrate structure to form one or more device regions defined by one or more isolation trenches, wherein each device region comprises a base semiconductor substrate layer and a semiconductor device layer with a sacrificial layer located therebetween; forming one or more insulator strips each having at least a vertical portion over a sidewall of one of the isolation trenches and a horizontal portion over an upper surface of one of the device regions; selectively removing the sacrificial layer from each device region to form an air gap between the base semiconductor substrate layer and the semiconductor device layer, wherein the vertical portions of the one or more insulator strips form vertical insulator pillars to support the semiconductor device layer; and filling the air gap within each device region with an insulator material to form a buried insulator
  • the above-described method may further comprise filling the isolation trenches with an insulating trench fill material and planarizing the substrate structure to remove the horizontal portions of the insulator strips and to form a substantially planar upper surface.
  • lateral etching is carried out after patterning of the substrate structure and before formation of the insulator strips to selectively remove a peripheral portion of the sacrificial layer in each device region.
  • the vertical portions of the subsequently formed patterned insulator strips comprise ledges that extend between the base semiconductor substrate layer and the semiconductor device layer at each device region.
  • the present invention relates to a SOI substrate comprising at least two device regions, each of which comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, and wherein the semiconductor device layers of such device regions have different thicknesses.
  • the present invention relates to a SOI substrate comprising at least two device regions, each of which comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, and wherein the semiconductor device layers of such device regions have different crystallographic orientations.
  • Figure IA shows a top view of a conventional SOI substrate structure containing silicon pillars at edges of a device region.
  • Figure IB shows a cross-sectional view of the conventional SOI substrate structure of Figure IA along line I.
  • Figure 1C shows a cross-sectional view of the conventional SOI substrate structure of Figure IA along line II.
  • Figure 2A shows a cross-sectional view of an exemplary SOI substrate structure containing vertical insulating pillars with ledges, according to one embodiment of the present invention.
  • Figure 2B shows a top view of the exemplary SOI substrate structure of Figure 2A.
  • Figures 3-11 illustrate exemplary processing steps for forming an SOI substrate structure containing vertical insulating pillars with ledges, according to one embodiment of the present invention.
  • Figure 12 shows a cross-sectional view of an exemplary SOI substrate structure containing vertical insulating pillars without ledges, according to one embodiment of the present invention.
  • Figures 13-16 illustrate exemplary processing steps for forming an SOI substrate structure containing vertical insulating pillars without ledges, according to one embodiment of the present invention.
  • Figure 17 shows a cross-sectional view of an exemplary SOI substrate structure containing semiconductor device layers of different thicknesses, while such semiconductor device layers are supported by vertical insulating pillars, according to one embodiment of the present invention.
  • Figures 18-23 illustrate exemplary processing steps that can be used for forming an SOI substrate structure containing semiconductor device layers of different thicknesses, according to one embodiment of the present invention.
  • Figure 24 shows a cross-sectional view of an exemplary SOI substrate structure containing semiconductor device layers of different crystallographic orientations, while such semiconductor device layers are supported by vertical insulating pillars, according to one embodiment of the present invention.
  • FIGS. 25-30 illustrate exemplary processing steps that can be used for forming an SOI substrate structure containing semiconductor device layers of different crystallographic orientations, according to one embodiment of the present invention.
  • substantially planar refers to the smoothness of a surface defined by surface protrusions or depressions of less than about 10 nm in height or depth.
  • each of the SOI substrates of the present invention has a substantially planar upper surface and comprises one or more device regions, each of which comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween.
  • the semiconductor device layer of each device region is supported by one or more vertical insulating pillars, which are preferably located at edges of each device region but can also locate at any other areas within each device region.
  • FIG. 2A shows a cross-sectional view of an exemplary SOI substrate structure, according to one embodiment of the present invention.
  • the SOI substrate 10 comprises three device regions 2, 4, and 6.
  • Each of the device regions 2, 4, and 6 comprises at least, from the bottom to the top, a base semiconductor substrate layer 12, a buried insulator layer 14, and a semiconductor device layer 16.
  • One or more vertical insulating pillars 22 are provided at edges of the device regions 2, 4, and 6 to provide structural support for the semiconductor device layer 16.
  • each vertical insulating pillar 22 has at least one ledge 24 that extends between the semiconductor device layer 16 and the base semiconductor substrate layer 12, as shown in Figure 2A.
  • a top view of the SOI substrate 10 along line III is provided in Figure 2B.
  • the base semiconductor substrate layer 12 may comprise any semiconductor material including, but not limited to: Si, SiC, SiGe, SiGeC, Ge alloys, GaAs, InAs, InP, other III- V or II-VI compound semiconductors, or organic semiconductor structures.
  • the base semiconductor substrate layer 12 be composed of a Si-containing semiconductor material, i.e., a semiconductor material that includes silicon.
  • the base semiconductor substrate layer 12 may be doped, undoped, or contain both doped and undoped regions therein (not shown).
  • the base semiconductor substrate layer 12 is either undoped or slightly p-doped.
  • the base semiconductor substrate layer 12 is preferably a bulk semiconductor structure, it may also include a layered structure with one or more buried insulator layers (not shown).
  • the buried insulator layer 14 may comprise any suitable insulator material(s), and it typically comprises an oxide, a nitride, or an oxynitride in either a crystalline phase or a non-crystalline phase.
  • the buried insulator layer 14 may be a homogenous, continuous layer, or it may contain relatively large cavities or micro- or nano-sized pores (not shown). Physical thickness of the buried insulator layer 14 may vary widely depending on the specific applications, but it typically ranges from about 10 nm to about 500 nm, with from about 20 nm to about 200 nm being more typical.
  • the semiconductor device layer 16 may comprise any semiconductor material including, but not limited to: Si, SiC, SiGe, SiGeC, Ge alloys, GaAs, InAs, InP, other III- V or II-VI compound semiconductors, or organic semiconductor structures. In some embodiments of the present invention, it is preferred that the semiconductor device layer 16 be composed of a Si-containing semiconductor material, i.e., a semiconductor material that includes silicon. Further, the semiconductor device layer 16 may be doped, undoped, or contain both doped and undoped regions therein (not shown). Preferably, the semiconductor device layer 16 is either undoped or slightly p-doped. Physical thickness of the semiconductor device layer 16 may vary widely depending on the specific applications, but it typically ranges from about 10 nm to about 200 nm, with from about 50 nm to about 100 nm being more typical.
  • the upper surfaces of the device regions 2, 4, and 6 are preferably coplanar with one another, thereby forming a substantially planar upper surface for the SOI structure 10.
  • An optional surface protective layer 18 may be provided over the semiconductor device layer 16 to protect layer 16 during planarization.
  • the optional surface protective layer 18 may comprise any suitable material(s) that can function as a planarization stop layer.
  • the optional surface protective layer 18 comprises silicon nitride and has a thickness ranging from about 40 nm to about 100 nm.
  • the vertical insulating pillars 22 may comprise any suitable insulator material(s), such as oxides, nitrides, or oxynitrides.
  • the vertical insulating pillars 22 comprise a conformal oxide material.
  • Such an oxide material provides excellent structural support for the semiconductor device layer 16.
  • the thermal oxide material provides the conformability required for forming pillar structures 22 that adhere well to the sidewalls of the semiconductor device layer 16 and contain the ledges 24 extending between the semiconductor device layer 16 and the base semiconductor substrate layer 12.
  • isolation regions 20 are typically formed in the SOI substrate 10 to provide isolation between adjacent device regions 2, 4, and 6.
  • the isolation regions 20 may be a trench isolation region or a field oxide isolation region.
  • the isolation regions 20 are trench isolation regions formed by a conventional trench isolation process well known to those skilled in the art. For example, lithography, etching and filling of the trench with a trench dielectric may be used in forming the trench isolation regions 20.
  • the dielectric material used for forming the trench can be any suitable dielectric material, and it is preferably a non-conformal dielectric material.
  • a liner may be formed in the trench prior to trench fill, a densification step may be performed after the trench fill and a planarization process may follow the trench fill as well.
  • the isolation regions 20 are field oxide isolation regions formed utilizing a so-called local oxidation of silicon process.
  • FIG. 3 shows a base semiconductor substrate layer 12, which may or may not contain any buried insulator layer.
  • the base semiconductor substrate layer 12 has a bulk semiconductor structure with no buried insulator layer therein and is either un-doped or slightly p-doped.
  • a dopant implantation step is then carried out to implant an n-type dopant species into an upper surface of the base semiconductor substrate layer 12, thereby forming a sacrificial layer 13 that contains n-doped semiconductor.
  • the sacrificial layer 13 can subsequently be removed by an etching step that selectively removes n-doped semiconductor over un-doped or slightly p- doped semiconductor for formation of a buried insulator layer (to be described hereinafter in greater detail).
  • the dopant implantation step is carried out at an energy level ranging from about 1 Kev to about 150 Kev and a dopant dose ranging from about 1E14 atm/cm 2 to about 1E16 atm/cm 2 .
  • Rapid thermal anneal (RTA) at an annealing temperature ranging from about 650 0 C to about 1300 0 C is subsequently performed in order to activate the dopant species in the n-doped semiconductor layer 13.
  • RTA rapid thermal anneal
  • the n-doped semiconductor layer 13 can also be formed by other doping techniques, such as solid-state diffusion from a doping layer or a vapor.
  • the n-doped semiconductor sacrificial layer 13 so formed preferably comprises an n- type dopant species, such as phosphorus (P), arsenic (As), antimony (Sb), etc., at a concentration ranging from about lx lO 19 /cm 3 to about lx lO 21 /cm 3 .
  • Physical thickness of the sacrificial layer 13 is substantially the same as the buried insulator layer 14 to be formed.
  • the sacrificial layer has a thickness ranging from about 10 nm to about 500 nm, and more preferably from about 20 nm to about 200 nm.
  • the sacrificial layer 13 is not limited to the above-described n-doped semiconductor, and it may also contain other materials that can be selectively removed over the base semiconductor substrate layer 12 underneath and the semiconductor device layer 16 to be formed atop.
  • Other removable materials that can be used to form the sacrificial layer 13 include, but are not limited to: porous semiconductor, SiGe and SiGeC.
  • the layered substrate structure 10 which comprises the base semiconductor substrate layer 12, the sacrificial layer 13, the semiconductor device layer 16, and the optional surface protective layer 18, is patterned to form one or more device regions 2, which are defined by one or more isolation trenches 30, as shown in Figure 6A.
  • a top view of the patterned substrate structure 10 is shown in Figure 6B.
  • Patterning of the layered substrate structure 10 can be carried out by first depositing a blanket dielectric hard mask layer (not shown) over the layered substrate structure 10, followed by conventional lithography and etching steps that pattern the layered substrate structure 10, as shown in Figure 6A.
  • the lithography step includes applying a photoresist (not shown) onto the upper surface of the dielectric hard mask layer, exposing the photoresist to a desired pattern of radiation and developing the exposed photoresist utilizing a conventional resist developer.
  • the pattern in the photoresist is then transferred to the dielectric mask layer and the layered substrate structure 10 utilizing one or more dry etching steps to form the one or more device regions 2 as shown in Figures 6A and 6B.
  • the patterned photoresist may be removed after the pattern has been transferred into the dielectric mask layer, and the dielectric mask layer is subsequently removed after etching of the layered substrate structure 10 has been completed. In other embodiments, the patterned photoresist and the dielectric mask layer are both removed after etching has been completed.
  • a lateral etching step is carried out to selectively remove a peripheral portion of the sacrificial layer 13 through sidewalls of the isolation trenches 30 to form recess 32 on the trench sidewalls, as shown in Figure 7.
  • the lateral etching step is preferably carried out using a plasma etching step to selectively etch the n-doped semiconductor material contained by the sacrificial layer 13 over the un-doped or slightly p-doped semiconductor material contained by the base semiconductor substrate layer 12 and the semiconductor device layer 16.
  • Chlorine- and/or bromine-based plasma chemistries can be used to achieve a selectivity of n- doped silicon over undoped or slightly p-doped silicon as high as about 500: 1.
  • An example of a plasma etch tool capable of performing such a lateral etching step is a 9400 inductively coupled plasma source (ICP) plasma etch tool manufactured by LAM Research Corp. (Fremont, California).
  • ICP inductively coupled plasma source
  • RF radio-frequency
  • Other ICP systems such as those manufactured by Applied Materials (Santa Clara, California) or Tokyo Electron Limited (Tokyo, Japan) may also be used.
  • the lateral etching step can also be carried out using wet etching for selective removal of the n-doped semiconductor material in the sacrificial layer 13.
  • a conformal insulator layer 19 is deposited over the entire structure of Figure 7, including both the sidewalls of the isolation trenches 30 and the upper surface of the device region 2. A portion of the conformal insulator layer 19 fills the recess 32 on the trench sidewalls, thereby forming a ledge-like structure between the base semiconductor substrate layer 12 and the semiconductor device layer 16, as shown in Figure 8.
  • the conformal insulator layer 19 may comprise any suitable insulator material(s), such as oxides, nitrides, or oxynitrides, and it can be formed by a thermal growth process such as, for example, oxidation, nitridation or oxynitridation.
  • the conformal insulator layer 19 can be formed by a deposition process such as, for example, chemical vapor deposition (CVD), plasma-assisted CVD, atomic layer deposition (ALD), evaporation, reactive sputtering, chemical solution deposition and other like deposition processes.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • evaporation reactive sputtering
  • chemical solution deposition chemical solution deposition and other like deposition processes.
  • the conformal insulator layer 19 comprises a conformal oxide material.
  • the conformal insulator layer 19 is then patterned by conventional lithography and etching to form one or more insulator strips 19A over each device region 2, as shown in Figure 9A.
  • the lithography step includes applying a photoresist (not shown) over the conformal insulator layer 19, exposing the photoresist to a desired pattern of radiation (which defines the areas where the insulator strips 19A are to be formed) and developing the exposed photoresist utilizing a conventional resist developer.
  • the pattern in the photoresist is then transferred to the conformal insulator layer 19 utilizing one or more wet and/or dry etching steps to form the one or more insulator strips 19A as shown in Figure 9A.
  • a wet etching solution comprising hydrofluoric acid (HF) can preferably be used to selectively remove unmasked portions of the conformal insulator layer 19 and stop at the surface protective layer 18.
  • HF hydrofluoric acid
  • Figure 9B shows a cross-sectional view of one of the device regions 2 alone Line IV that extends through one of the insulator strips 19 A.
  • the insulator strip 19A contains at least a horizontal portion that cover an upper surface of the device region 2 and at least a vertical portion that covers a sidewall of one of the isolation trenches 30, as shown in Figure 9B.
  • the vertical portion of the insulator strip 19A therefore forms at least a vertical insulator pillar 22 that adheres to sidewalls of both the semiconductor device layer 16 and the base semiconductor substrate layer 12. Further, a portion of the vertical insulator pillar 22 extends into the recess between the semiconductor device layer 16 and the base semiconductor substrate layer 12 to form a ledge 24.
  • Figure 9C shows a cross-sectional view of the device region 2 alone Line V that extends through an area that is not covered by any insulator strip.
  • the sidewalls of the semiconductor device layer 16, the sacrificial layer 13, and the base semiconductor substrate layer 12 are still exposed in this area, and the recess 32 between the semiconductor device layer 16 and the base semiconductor substrate layer 12 remains unfilled in this area.
  • an additional lateral etching step which is similar to that described hereinabove, is carried out to selectively remove the entire sacrificial layer 13 through exposed isolation trench sidewalls that are not covered by the insulator strips 19A. Consequently, an air gap 15 is formed between the base semiconductor substrate layer 12 and the semiconductor device layer 16, as shown in Figure 1OA. In this manner, the semiconductor device layer 16 becomes "floating" above the base semiconductor substrate layer 12. Structural support for the floating semiconductor device layer 16 is provided by the vertical insulator pillar 22 and its ledge 24.
  • Figure 1OB shows a three-dimensional (3D) side view of the base semiconductor substrate layer 12, the floating semiconductor device layer 16, the insulator strip 19A, and the vertical insulator pillar 22 with the ledge 24, and Figure 1OC shows a 3D elevated view of these structures.
  • the air gap 15 between the base semiconductor substrate layer 12 and the semiconductor device layer 16 is filled with an insulator material to form a buried insulator layer 14, as shown in Figure 11.
  • Any suitable insulator material such as an oxide, nitride, or oxynitride, can be used for filling the air gap 15.
  • a high aspect ratio profile material commercialized by Applied Materials (Santa Clara, CA) under the trade name of HARPTM is used to fill the air gap 15 and form a continuous, homogeneous buried insulator layer 14.
  • insulator materials of medium-to-low aspect ratio profiles can be used to form a buried insulator layer 14 with cavities therein.
  • the buried insulator layer 14 may comprise porous dielectric material(s) with micro- or nano-sized pores therein.
  • the isolation trenches 30 are filled with a trench dielectric material to form trench isolations 20, and a planarization step such as chemical mechanical polishing (CMP) is then carried out to remove excess trench isolation material located outside of the trenches 30 and to remove the horizontal portion of the insulator strip 19A, thereby forming a SOI substrate structure 10 with a substantially planar upper surface, as shown in Figure 11.
  • CMP chemical mechanical polishing
  • Figures 2-11 illustratively demonstrate exemplary SOI substrates and processing steps that can be used for forming such exemplary SOI substrates according to specific embodiments of the present invention
  • a person ordinarily skilled in the art can readily modify the substrate structures and processing steps for adaptation to specific application requirements, consistent with the above descriptions.
  • the exemplary SOI substrates as shown in Figures 2-3 and 11 contain specific numbers of vertical insulator pillars arranged in specific manners, it is readily understood that the SOI substrates of the present invention may comprise any number of vertical insulator pillars arranged in any manner.
  • Figures 3-4 shows formation of a layered substrate structure 10 by first forming a n-doped semiconductor sacrificial layer 13 via surface dopant implantation, followed by formation of the semiconductor device layer 16 via epitaxial growth of semiconductor
  • a layered substrate structure 10 may also be formed by a single in-depth dopant implantation step, which forms the n-doped semiconductor sacrificial layer 13 at a predetermined depth in a bulk semiconductor substrate.
  • the portion of the bulk semiconductor substrate located underneath the layer 13 defines the base substrate layer 12, and the portion located above the layer 13 defines the semiconductor device layer 16.
  • the subsequent epitaxial growth step is therefore not necessary.
  • Figures 2-3 and 11 show vertical insulator pillars with ledges
  • the vertical insulator pillars can also be provided without ledges in an alternative embodiment of the present invention.
  • Figure 12 shows an SOI substrate 10 having contains substantially the same structural components as that shown by Figure 2, except that the vertical insulator pillars 22 in Figure 12 do not have any ledge.
  • Figures 13-16 illustrate exemplary processing steps for forming an SOI substrate structure with such ledge-less vertical insulating pillars, according to an alternative embodiment of the present invention.
  • a conformal insulator layer 19 is deposited over the entire structure without the lateral etching step as described hereinabove in Figure 7. In this manner, no recess is formed along sidewalls of the isolation trenches 30, and the conformal insulator layer 19 does not extend between the base semiconductor substrate layer 12 and the semiconductor device layer 16, as shown in Figure 13.
  • the conformal insulator layer 19 is then patterned by conventional lithography and etching to form one or more insulator strips 19A over each device region 2, as shown in Figure 14A, similar to those descried hereinabove with reference to Figure 9A.
  • Figure 14B shows a cross-sectional view of one of the device regions 2 along Line VI that extends through one of the insulator strips 19 A.
  • the insulator strip 19A contains at least a horizontal portion that cover an upper surface of the device region 2 and at least a vertical portion that cover a sidewall of one of the isolation trenches 30, as shown in Figure 14B.
  • the vertical portion of the insulator strip 19A therefore forms at least a vertical insulator pillar 22 that adheres to sidewalls of both the semiconductor device layer 16 and the base semiconductor substrate layer 12. Note that no ledge is formed along the vertical insulator pillar 22, as shown in Figure 14 B.
  • Figure 14C shows a cross-sectional view of the device region 2 alone Line VII that extends through an area that is not covered by any insulator strip.
  • the sidewalls of the semiconductor device layer 16, the sacrificial layer 13, and the base semiconductor substrate layer 12 remain exposed in this area.
  • a lateral etching step similar to that described hereinabove is carried out to selectively remove the entire sacrificial layer 13 through exposed isolation trench sidewalls that are not covered by the insulator strips 19A. Consequently, an air gap 15 is formed between the base semiconductor substrate layer 12 and the semiconductor device layer 16, as shown in Figure 15 A. In this manner, the semiconductor device layer 16 becomes "floating" above the base semiconductor substrate layer 12. Structural support for the floating semiconductor device layer 16 is provided by the ledge-less vertical insulator pillar 22.
  • Figure 15B shows a three- dimensional (3D) side view of the base semiconductor substrate layer 12, the floating semiconductor device layer 16, the insulator strip 19A, and the ledge-less vertical insulator pillar 22, and Figure 1OC shows a 3D elevated view of these structures.
  • the air gap 15 between the base semiconductor substrate layer 12 and the semiconductor device layer 16 is filled with an insulator material to form a buried insulator layer 14, and the isolation trenches 30 are filled with a trench dielectric material to form trench isolations 20.
  • a CMP or other planarization step is carried out subsequently to remove excess trench isolation material located outside of the trenches 30 and to remove the horizontal portion of the insulator strip 19A, thereby forming a SOI substrate structure 10 with a substantially planar upper surface, as shown in Figure 16.
  • the SOI substrates of the present invention as described hereinabove provide true SOI configurations in the entire active device regions and therefore offer full advantages of SOI structures. Further, the methods for fabricating such SOI substrates do not require perfect alignment of the vertical insulator pillars. Therefore, the device performance is no longer affected by potential alignment errors.
  • the present invention in a specific embodiment provides a SOI structure that comprises two or more device regions with semiconductor device layers of different thickness, as shown in Figure 17.
  • the SOI substrate 10 comprises three device regions 2, 4, and 6, which respectfully contain semiconductor device layers 16A, 16B, and 16C and buried insulator layers 14A, 14B, and 14C.
  • the semiconductor device layers 16A and 16C have an average thickness (Ti) that is significantly larger than the average thickness (T 2 ) of layer 16B.
  • the buried insulator layers 14A and 14C are located at a depth that is larger than that of layer 16B.
  • the SOI structure of Figure 17 can be readily formed by processing steps similar to those described hereinabove, except that a slightly different dopant implantation process will be used to form an unpatterned, layered substrate structure with a semiconductor device layer of varying thicknesses.
  • the unpatterned, layered substrate structure contains an n-doped sacrificial semiconductor layer with different portions located at different depths of the substrate structure.
  • Such an unpatterned, layered substrate structure can then be patterned to form two or more device regions with semiconductor device layers of different thicknesses.
  • Figures 18-23 illustrate an exemplary dopant implantation process containing at least two dopant implantation steps for formation of an n-doped sacrificial semiconductor layer with at least two portions located at two different depths of a layered substrate structure.
  • Figure 18 shows a first masked dopant implantation step during which a first portion 13A of an n-doped sacrificial semiconductor layer is selectively formed over a first region of a base semiconductor substrate layer 12, while a second region of layer 12 is protected from the dopant implantation by a block mask 34.
  • the block mask 34 is removed after the first dopant implantation step, and epitaxial growth of semiconductor material is carried out, so that the first portion 13A of an n- doped sacrificial semiconductor layer is buried in the subsequently grown epitaxial semiconductor material, as shown in Figure 19.
  • a second masked dopant implantation step is carried out, during which the first region of the base semiconductor substrate layer 12 containing the first portion 13 A of the n-doped sacrificial semiconductor layer is covered by another block mask 36, while a second portion 13B of the n-doped sacrificial semiconductor layer is formed over the second region of the base semiconductor substrate layer 12, as shown in Figure 20.
  • the block mask 36 is then removed after the second dopant implantation step, and epitaxial growth of semiconductor material is again carried out, so that the second portion 13B of the n-doped sacrificial semiconductor layer is also buried in epitaxial semiconductor material, as shown in Figure 21.
  • the subsequently grown epitaxial semiconductor material formed over the first portion 13A of the n-doped sacrificial semiconductor layer constitute a first, thicker portion 16A of a semiconductor device layer
  • the epitaxial semiconductor material formed over the second portion 13B of the n-doped sacrificial semiconductor layer constitute a second, thinner portion 16B of the semiconductor device layer.
  • An optional surface protective layer 18 can be formed over both portions 16A and 16B of the semiconductor device layer, thereby forming an unpatterned layered substrate 10, which contains a semiconductor device layer with two different portions 16A and 16B of different thicknesses, as shown in Figure 22.
  • Such an unpatterned layered substrate 10 can then be patterned to form at least two different device regions 2 and 4 that are isolated from each other by an isolation trench 30 and contain two different semiconductor device layers 16A and 16B of different thicknesses (Ti and T 2 ), as shown in Figure 23.
  • the unpatterned layered substrate 10 of Figure 22 can also be formed by a single dopant implantation step. Specifically, a bulk semiconductor substrate is first provided, followed by selectively masking of a portion of the bulk semiconductor substrate. The thickness of the masking layer is adjusted so that it only retards the dopant implantation (i.e., reducing the implantation depth by a predetermined amount) but not completely block the dopant implantation in the remaining unmasked portion of the bulk semiconductor substrate. In this manner, a single dopant implantation step can be carried out to form an n-doped semiconductor sacrificial layer with different portions located at different depths of the bulk semiconductor substrate.
  • the present invention in a specific embodiment provides a SOI structure that comprises two or more device regions with semiconductor device layers of different thicknesses, as shown in Figure 17.
  • CMOS complementary metal oxide semiconductor
  • electrons have a high mobility along the ⁇ 100 ⁇ crystal planes of silicon, but holes have high mobility along the ⁇ 110 ⁇ crystal planes of silicon.
  • hole mobility values along the ⁇ 100 ⁇ planes are roughly about 2 to 4 times lower than the corresponding electron hole mobility values along such planes.
  • hole mobility values along the ⁇ 110 ⁇ silicon surfaces are about 2 times higher than those along the ⁇ 100 ⁇ silicon surfaces, but electron mobility along the ⁇ 110 ⁇ surfaces are significantly degraded compared to those along the ⁇ 100 ⁇ surfaces.
  • the ⁇ 110 ⁇ silicon surfaces are optimal for forming p-channel field effect transistor (p- FET) devices due to the excellent hole mobility along the ⁇ 110 ⁇ planes, which leads to higher drive currents in the p-FETs.
  • p- FET p-channel field effect transistor
  • n-FET n-channel field effect transistor
  • the ⁇ 100 ⁇ silicon surfaces instead are optimal for forming n-FET devices due to the enhanced electron mobility along the ⁇ 100 ⁇ planes, which results in higher drive currents in the n-FETs.
  • such a SOI substrate contains at least two device regions having semiconductor layers of different crystallographic orientations.
  • the different crystallographic orientations are preferably selected from the group consisting of ⁇ 100>, ⁇ 110>, and ⁇ 111> orientations of silicon.
  • Figure 24 shows such an SOI substrate 10, which comprises device regions 2, 4, and 6.
  • the base semiconductor substrate layer 12 in the SOI substrate 10 have first portions 12A of a first crystallographic orientation, which are located in device regions 2 and 6, and second portions 12B of a second, different crystallographic orientation located in device region 4.
  • the semiconductor device layer 12 in the SOI substrate 10 also comprises first portions 16A of the first crystallographic orientation located in device regions 2 and 6 and second portions 16B of the second, different crystallographic orientation located in device region 4.
  • the SOI structure of Figure 24 can be readily formed by processing steps similar to those described hereinabove, except that an unpatterned, layered substrate structure having a semiconductor device layer with different portions of different crystallographic orientations needs to be formed first, which can then be patterned to form two or more device regions with semiconductor device layers of different crystallographic orientations.
  • Such an unpatterned, layered substrate structure can be readily formed using one or more wafer bonding, dopant implantation, amorphization implantation, recrystallization, and epitaxial growth steps.
  • Figures 25-30 illustrate an exemplary process for forming an unpatterned, layered substrate structure having a semiconductor device layer with different portions of different crystallographic orientations.
  • a base semiconductor substrate layer 12 is first formed by bonding a first semiconductor layer 12A of a first crystallographic orientation onto a second semiconductor layer 12B of a second, different crystallographic orientation by known wafer bonding techniques, as shown in Figure 25.
  • a dopant implantation step is carried out to implant n-type dopant species onto an upper surface of the first semiconductor layer 12A to form an n-doped sacrificial semiconductor layer 13, as shown in Figure 26.
  • a masked amorphization implantation step is then carried out using block mask 38 to form at least one amorphous semiconductor region 40, which extends through the n- doped sacrificial semiconductor layer 13 and the first semiconductor layer 12A into the second semiconductor layer 12B, as shown in Figure 27.
  • An upper portion of the amorphous semiconductor region 40 contains n-type dopant species that have been previously implanted.
  • Recrystallization of the amorphous semiconductor region 40 over the second base semiconductor layer 12B forms a recrystallized region that is an extension of layer 12B and therefore has the same crystallographic orientation as layer 12B (i.e., the second, different crystallographic orientation).
  • An upper portion of the recrystallized region contains n-doped semiconductor of the second, different crystallographic orientation, as shown in Figure 28.
  • the block mask 40 is removed, and epitaxial growth of semiconductor is carried out to form a semiconductor device layer that contains first portions 16A grown over the first base semiconductor substrate layer 12A outside the recrystallized region 12B and a second portion 16B grown over the recrystallized region 12B.
  • the first portions 16A of the semiconductor device layer has the same crystallographic orientation as that of the first base semiconductor substrate layer 12A (i.e., the first crystallographic orientation)
  • the second portion 16B of the semiconductor device layer has the same crystallographic orientation as that of the recrystallized region 12B (i.e., the second, different crystallographic orientation), as shown in Figure 29.
  • An optional surface protective layer 18 can be formed over both portions 16A and 16B of the semiconductor device layer, thereby forming an unpatterned layered substrate 10, which contains a semiconductor device layer with two different portions 16A and 16B of different crystallographic orientations, as shown in Figure 29.
  • Such an unpatterned layered substrate 10 can then be patterned to form different device regions 2, 4, and 6 that are isolated from one another by isolation trenches 30 and contain semiconductor device layers 16A and 16B of different crystallographic orientations, as shown in Figure 30.
  • the above-described processing steps form the n-doped sacrificial semiconductor layer 13 before the amorphization and recrystallization steps, it is understood that the n-doped sacrificial semiconductor layer 13 can also be formed after the amorphization and recrystallization steps. Further, the n-doped sacrificial semiconductor layer 13 can be formed by in-depth dopant implantation after epitaxial growth of the semiconductor device layer.
  • This application finds utility in the field of semiconductor devices, and more particularly, in methods of fabricating improved semiconductor-on- insulator (SOI) substrates.
  • SOI semiconductor-on- insulator

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

The present invention relates to semiconductor-on-insulator (SOI) substrates having device regions (2, 4, 6), each comprises a base semiconductor substrate layer (12) and a semiconductor device layer (16) and a buried insulator layer (14) between. The semiconductor device layer (16) supported by vertical insulating pillars (22), each having a ledge extending between the base semiconductor substrate layer (12) and the semiconductor device layer (16). The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a 'floating' semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap (15) and is supported by the vertical insulating pillars (22). The air gap (15) is preferably formed by selective removal of a sacrificial layer (13) located between the base semiconductor substrate layer (12) and the semiconductor device layer (16).

Description

FORMATION OF IMPROVED SOI SUBSTRATES USING BULK SEMICONDUCTOR WAFERS
FIELD OF THE INVENTION
The present invention relates to improved semiconductor-on-insulator (SOI) substrates. More specifically, the present invention relates to SOI substrates that each has one or more device regions including a semiconductor device layer that is isolated from a base substrate layer by a buried insulator layer and supported by one or more vertical insulating pillars, as well as to methods and precursor structures that can be used to form such SOI substrates.
BACKGROUND OF THE INVENTION
Semiconductor-on-insulator (SOI) technology is becoming increasingly important in semiconductor processing. A SOI substrate structure typically contains a buried insulator layer, which functions to electrically isolate a top semiconductor device layer from a base semiconductor substrate. Active devices, such as transistors, are typically formed in the top semiconductor device layer of the SOI substrate.
Devices formed using SOI technology (i.e., SOI devices) offer many advantages over their bulk counterparts, including, but not limited to: reduction of junction leakage, reduction of junction capacitance, reduction of short channel effects, better device performance, higher packing density, and lower voltage requirements.
It is therefore desirable to form SOI substrates from bulk semiconductor substrates. One conventional method for forming a SOI substrate from a bulk silicon substrate involves selective masking of certain regions on the surface of a bulk silicon substrate, followed by anodization to form porous silicon at unmasked regions on the silicon substrate surface. Silicon at the masked regions is not porified and therefore forms solid silicon pillars. A silicon layer is subsequently grown over both the porous and non-porous portions of the silicon substrate. By forming an opening in the subsequently grown silicon layer, the porous portions of the silicon substrate become exposed and can therefore be selectively removed to form hollow regions underneath the subsequently grown silicon layer, while the non-porous silicon pillars provide the necessary structural support for the silicon layer during this process. Finally, the hollow regions can be filled with an insulator material to form a buried insulator film underneath the silicon layer, thereby resulting in a SOI substrate.
Figure IA shows a top view of a SOI substrate formed by the above-described conventional method, while Figures IB and 1C respectively show cross-sectional views of such a SOI substrate along line I and line II. Specifically, the conventional SOI substrate comprises a device region 2 located over a base substrate 12 and encircled by trench isolation regions 20. A semiconductor device layer 16 is located at the device region 2, with a gate dielectric layer 3 and gate electrodes 5 are located thereabove. The semiconductor device layer 16 is separated from the base substrate 12 by a buried insulator layer 14, thereby forming a SOI configuration. Silicon pillars 11 are located at edges of the device region 2, as shown in Figures IA and 1C. The silicon pillars 11 provide structural support for the semiconductor device layer 16 before the buried insulator layer 14 is formed.
However, the silicon pillars 11 in the above-described conventional SOI substrate structure extend from the base substrate 12 through the buried insulator layer 14 to overlap with portions of the semiconductor device layer 16, as shown in Figure 1C. The overlap portions between the silicon pillars 11 and the semiconductor device layer 16 behave more like bulk structures than SOI structures, which undermines the advantages offered by true SOI structures.
Further, the processing steps used for forming such a conventional SOI substrate structure inevitably involve alignment errors and process bias, which do not scale well. Therefore, when the device structure is scaled from 90 nm down to 45 nm, the device performance will be further compromised.
There is therefore a need for improved SOI substrates that can be formed using bulk semiconductor structures, without undermining the advantages of true SOI structures or compromising the device performance at device dimensions below 45 nm. There is also a need for a simple and effective method of fabricating the improved SOI substrates.
SUMMARY OF THE INVENTION
In one aspect, the present invention relates to a semiconductor-on-insulator (SOI) substrate comprising one or more device regions, each of which comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, wherein the semiconductor device layer of each device region is supported by one or more vertical insulating pillars.
In another aspect, the present invention relates to a precursor substrate structure comprising at least one device region having at least a base semiconductor substrate layer and a semiconductor device layer with an air gap located therebetween, wherein the semiconductor device layer is supported by one or more vertical insulating pillars.
In a further aspect, the present invention relates to a method for forming a semiconductor-on-insulator (SOI) substrate, comprising: forming a substrate structure comprising at least a base semiconductor substrate layer and a semiconductor device layer with a sacrificial layer located therebetween; patterning the substrate structure to form one or more device regions defined by one or more isolation trenches, wherein each device region comprises a base semiconductor substrate layer and a semiconductor device layer with a sacrificial layer located therebetween; forming one or more insulator strips each having at least a vertical portion over a sidewall of one of the isolation trenches and a horizontal portion over an upper surface of one of the device regions; selectively removing the sacrificial layer from each device region to form an air gap between the base semiconductor substrate layer and the semiconductor device layer, wherein the vertical portions of the one or more insulator strips form vertical insulator pillars to support the semiconductor device layer; and filling the air gap within each device region with an insulator material to form a buried insulator layer between the base semiconductor substrate layer and the semiconductor device layer.
The above-described method may further comprise filling the isolation trenches with an insulating trench fill material and planarizing the substrate structure to remove the horizontal portions of the insulator strips and to form a substantially planar upper surface.
Preferably, but not necessary, lateral etching is carried out after patterning of the substrate structure and before formation of the insulator strips to selectively remove a peripheral portion of the sacrificial layer in each device region. In this manner, the vertical portions of the subsequently formed patterned insulator strips comprise ledges that extend between the base semiconductor substrate layer and the semiconductor device layer at each device region.
In still another aspect, the present invention relates to a SOI substrate comprising at least two device regions, each of which comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, and wherein the semiconductor device layers of such device regions have different thicknesses.
In a still further aspect, the present invention relates to a SOI substrate comprising at least two device regions, each of which comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, and wherein the semiconductor device layers of such device regions have different crystallographic orientations.
Other aspects, features and advantages of the invention will be more fully apparent from the ensuing disclosure and appended claims. BRIEF DESCRIPTION OF THE DRAWINGS
Figure IA shows a top view of a conventional SOI substrate structure containing silicon pillars at edges of a device region.
Figure IB shows a cross-sectional view of the conventional SOI substrate structure of Figure IA along line I.
Figure 1C shows a cross-sectional view of the conventional SOI substrate structure of Figure IA along line II.
Figure 2A shows a cross-sectional view of an exemplary SOI substrate structure containing vertical insulating pillars with ledges, according to one embodiment of the present invention.
Figure 2B shows a top view of the exemplary SOI substrate structure of Figure 2A.
Figures 3-11 illustrate exemplary processing steps for forming an SOI substrate structure containing vertical insulating pillars with ledges, according to one embodiment of the present invention.
Figure 12 shows a cross-sectional view of an exemplary SOI substrate structure containing vertical insulating pillars without ledges, according to one embodiment of the present invention.
Figures 13-16 illustrate exemplary processing steps for forming an SOI substrate structure containing vertical insulating pillars without ledges, according to one embodiment of the present invention.
Figure 17 shows a cross-sectional view of an exemplary SOI substrate structure containing semiconductor device layers of different thicknesses, while such semiconductor device layers are supported by vertical insulating pillars, according to one embodiment of the present invention. Figures 18-23 illustrate exemplary processing steps that can be used for forming an SOI substrate structure containing semiconductor device layers of different thicknesses, according to one embodiment of the present invention.
Figure 24 shows a cross-sectional view of an exemplary SOI substrate structure containing semiconductor device layers of different crystallographic orientations, while such semiconductor device layers are supported by vertical insulating pillars, according to one embodiment of the present invention.
Figures 25-30 illustrate exemplary processing steps that can be used for forming an SOI substrate structure containing semiconductor device layers of different crystallographic orientations, according to one embodiment of the present invention.
DETAILED DESCRIPTIONS OF THE INVENTION, AND PREFERRED EMBODIMENTS THEREOF
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the invention.
It will be understood that when an element as a layer, region or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "beneath" or "under" another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present. The term "vertical" as used herein refers to a direction that is perpendicular to the substrate surface or a direction that deviates from such a perpendicular direction at an angle of less than 60°.
The term "substantially planar" as used herein refers to the smoothness of a surface defined by surface protrusions or depressions of less than about 10 nm in height or depth.
The present invention provides improved SOI substrates that comprise vertical insulating pillars for supporting the semiconductor device layers. Specifically, each of the SOI substrates of the present invention has a substantially planar upper surface and comprises one or more device regions, each of which comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween. The semiconductor device layer of each device region is supported by one or more vertical insulating pillars, which are preferably located at edges of each device region but can also locate at any other areas within each device region.
Figure 2A shows a cross-sectional view of an exemplary SOI substrate structure, according to one embodiment of the present invention. Specifically, the SOI substrate 10 comprises three device regions 2, 4, and 6. Each of the device regions 2, 4, and 6 comprises at least, from the bottom to the top, a base semiconductor substrate layer 12, a buried insulator layer 14, and a semiconductor device layer 16. One or more vertical insulating pillars 22 are provided at edges of the device regions 2, 4, and 6 to provide structural support for the semiconductor device layer 16. Further, each vertical insulating pillar 22 has at least one ledge 24 that extends between the semiconductor device layer 16 and the base semiconductor substrate layer 12, as shown in Figure 2A. A top view of the SOI substrate 10 along line III is provided in Figure 2B.
The base semiconductor substrate layer 12 may comprise any semiconductor material including, but not limited to: Si, SiC, SiGe, SiGeC, Ge alloys, GaAs, InAs, InP, other III- V or II-VI compound semiconductors, or organic semiconductor structures. In some embodiments of the present invention, it is preferred that the base semiconductor substrate layer 12 be composed of a Si-containing semiconductor material, i.e., a semiconductor material that includes silicon. Further, the base semiconductor substrate layer 12 may be doped, undoped, or contain both doped and undoped regions therein (not shown). Preferably, the base semiconductor substrate layer 12 is either undoped or slightly p-doped. Although the base semiconductor substrate layer 12 is preferably a bulk semiconductor structure, it may also include a layered structure with one or more buried insulator layers (not shown).
The buried insulator layer 14 may comprise any suitable insulator material(s), and it typically comprises an oxide, a nitride, or an oxynitride in either a crystalline phase or a non-crystalline phase. The buried insulator layer 14 may be a homogenous, continuous layer, or it may contain relatively large cavities or micro- or nano-sized pores (not shown). Physical thickness of the buried insulator layer 14 may vary widely depending on the specific applications, but it typically ranges from about 10 nm to about 500 nm, with from about 20 nm to about 200 nm being more typical.
The semiconductor device layer 16 may comprise any semiconductor material including, but not limited to: Si, SiC, SiGe, SiGeC, Ge alloys, GaAs, InAs, InP, other III- V or II-VI compound semiconductors, or organic semiconductor structures. In some embodiments of the present invention, it is preferred that the semiconductor device layer 16 be composed of a Si-containing semiconductor material, i.e., a semiconductor material that includes silicon. Further, the semiconductor device layer 16 may be doped, undoped, or contain both doped and undoped regions therein (not shown). Preferably, the semiconductor device layer 16 is either undoped or slightly p-doped. Physical thickness of the semiconductor device layer 16 may vary widely depending on the specific applications, but it typically ranges from about 10 nm to about 200 nm, with from about 50 nm to about 100 nm being more typical.
The upper surfaces of the device regions 2, 4, and 6 are preferably coplanar with one another, thereby forming a substantially planar upper surface for the SOI structure 10. An optional surface protective layer 18 may be provided over the semiconductor device layer 16 to protect layer 16 during planarization. The optional surface protective layer 18 may comprise any suitable material(s) that can function as a planarization stop layer. Preferably, the optional surface protective layer 18 comprises silicon nitride and has a thickness ranging from about 40 nm to about 100 nm.
The vertical insulating pillars 22 may comprise any suitable insulator material(s), such as oxides, nitrides, or oxynitrides. In a particularly preferred, but not necessary, embodiment of the present invention, the vertical insulating pillars 22 comprise a conformal oxide material. Such an oxide material provides excellent structural support for the semiconductor device layer 16. Further, the thermal oxide material provides the conformability required for forming pillar structures 22 that adhere well to the sidewalls of the semiconductor device layer 16 and contain the ledges 24 extending between the semiconductor device layer 16 and the base semiconductor substrate layer 12.
One or more isolation regions 20 are typically formed in the SOI substrate 10 to provide isolation between adjacent device regions 2, 4, and 6. The isolation regions 20 may be a trench isolation region or a field oxide isolation region. Preferably, the isolation regions 20 are trench isolation regions formed by a conventional trench isolation process well known to those skilled in the art. For example, lithography, etching and filling of the trench with a trench dielectric may be used in forming the trench isolation regions 20. The dielectric material used for forming the trench can be any suitable dielectric material, and it is preferably a non-conformal dielectric material. Optionally, a liner may be formed in the trench prior to trench fill, a densification step may be performed after the trench fill and a planarization process may follow the trench fill as well. Alternatively, the isolation regions 20 are field oxide isolation regions formed utilizing a so-called local oxidation of silicon process.
The improved SOI substrate structure as described hereinabove can be readily formed from a bulk semiconductor substrate by a simplified method at reduced costs. Such a method will be illustrated in greater details hereinafter with reference to Figures 3-11. Figure 3 shows a base semiconductor substrate layer 12, which may or may not contain any buried insulator layer. Preferably, the base semiconductor substrate layer 12 has a bulk semiconductor structure with no buried insulator layer therein and is either un-doped or slightly p-doped. A dopant implantation step is then carried out to implant an n-type dopant species into an upper surface of the base semiconductor substrate layer 12, thereby forming a sacrificial layer 13 that contains n-doped semiconductor. The sacrificial layer 13 can subsequently be removed by an etching step that selectively removes n-doped semiconductor over un-doped or slightly p- doped semiconductor for formation of a buried insulator layer (to be described hereinafter in greater detail).
In a specific, but non-limiting, example, the dopant implantation step is carried out at an energy level ranging from about 1 Kev to about 150 Kev and a dopant dose ranging from about 1E14 atm/cm2 to about 1E16 atm/cm2. Rapid thermal anneal (RTA) at an annealing temperature ranging from about 6500C to about 13000C is subsequently performed in order to activate the dopant species in the n-doped semiconductor layer 13. The n-doped semiconductor layer 13 can also be formed by other doping techniques, such as solid-state diffusion from a doping layer or a vapor. The n-doped semiconductor sacrificial layer 13 so formed preferably comprises an n- type dopant species, such as phosphorus (P), arsenic (As), antimony (Sb), etc., at a concentration ranging from about lx lO19/cm3 to about lx lO21/cm3. Physical thickness of the sacrificial layer 13 is substantially the same as the buried insulator layer 14 to be formed. Preferably, the sacrificial layer has a thickness ranging from about 10 nm to about 500 nm, and more preferably from about 20 nm to about 200 nm.
Note that the sacrificial layer 13 is not limited to the above-described n-doped semiconductor, and it may also contain other materials that can be selectively removed over the base semiconductor substrate layer 12 underneath and the semiconductor device layer 16 to be formed atop. Other removable materials that can be used to form the sacrificial layer 13 include, but are not limited to: porous semiconductor, SiGe and SiGeC. After formation of the sacrificial layer 13, a semiconductor device layer 16 is formed on top of the sacrificial layer 13 by epitaxial growth, as shown in Figure 4. Consequently, the semiconductor device layer 16 has the same crystal structure and crystal plane orientation as the substrate (i.e., the sacrificial layer 13) it is grown on. An optional surface protective layer 18 can further be formed over the semiconductor device layer 16, as shown in Figure 5.
Subsequently, the layered substrate structure 10, which comprises the base semiconductor substrate layer 12, the sacrificial layer 13, the semiconductor device layer 16, and the optional surface protective layer 18, is patterned to form one or more device regions 2, which are defined by one or more isolation trenches 30, as shown in Figure 6A. A top view of the patterned substrate structure 10 is shown in Figure 6B.
Patterning of the layered substrate structure 10 can be carried out by first depositing a blanket dielectric hard mask layer (not shown) over the layered substrate structure 10, followed by conventional lithography and etching steps that pattern the layered substrate structure 10, as shown in Figure 6A. Specifically, the lithography step includes applying a photoresist (not shown) onto the upper surface of the dielectric hard mask layer, exposing the photoresist to a desired pattern of radiation and developing the exposed photoresist utilizing a conventional resist developer. The pattern in the photoresist is then transferred to the dielectric mask layer and the layered substrate structure 10 utilizing one or more dry etching steps to form the one or more device regions 2 as shown in Figures 6A and 6B. In some embodiments, the patterned photoresist may be removed after the pattern has been transferred into the dielectric mask layer, and the dielectric mask layer is subsequently removed after etching of the layered substrate structure 10 has been completed. In other embodiments, the patterned photoresist and the dielectric mask layer are both removed after etching has been completed.
Subsequently, a lateral etching step is carried out to selectively remove a peripheral portion of the sacrificial layer 13 through sidewalls of the isolation trenches 30 to form recess 32 on the trench sidewalls, as shown in Figure 7. When the sacrificial layer 13 comprises an n-doped semiconductor material, as described hereinabove, the lateral etching step is preferably carried out using a plasma etching step to selectively etch the n-doped semiconductor material contained by the sacrificial layer 13 over the un-doped or slightly p-doped semiconductor material contained by the base semiconductor substrate layer 12 and the semiconductor device layer 16. Chlorine- and/or bromine-based plasma chemistries can be used to achieve a selectivity of n- doped silicon over undoped or slightly p-doped silicon as high as about 500: 1. An example of a plasma etch tool capable of performing such a lateral etching step is a 9400 inductively coupled plasma source (ICP) plasma etch tool manufactured by LAM Research Corp. (Fremont, California). In an ICP tool, two radio-frequency (RF) power sources are used, which include an upper power source for generating a plasma and a lower power source for maintaining etch bias. Other ICP systems such as those manufactured by Applied Materials (Santa Clara, California) or Tokyo Electron Limited (Tokyo, Japan) may also be used.
Alternatively, the lateral etching step can also be carried out using wet etching for selective removal of the n-doped semiconductor material in the sacrificial layer 13.
Next, a conformal insulator layer 19 is deposited over the entire structure of Figure 7, including both the sidewalls of the isolation trenches 30 and the upper surface of the device region 2. A portion of the conformal insulator layer 19 fills the recess 32 on the trench sidewalls, thereby forming a ledge-like structure between the base semiconductor substrate layer 12 and the semiconductor device layer 16, as shown in Figure 8.
The conformal insulator layer 19 may comprise any suitable insulator material(s), such as oxides, nitrides, or oxynitrides, and it can be formed by a thermal growth process such as, for example, oxidation, nitridation or oxynitridation. Alternatively, the conformal insulator layer 19 can be formed by a deposition process such as, for example, chemical vapor deposition (CVD), plasma-assisted CVD, atomic layer deposition (ALD), evaporation, reactive sputtering, chemical solution deposition and other like deposition processes. In a particularly preferred, but not necessary, embodiment of the present invention, the conformal insulator layer 19 comprises a conformal oxide material. The conformal insulator layer 19 is then patterned by conventional lithography and etching to form one or more insulator strips 19A over each device region 2, as shown in Figure 9A. Specifically, the lithography step includes applying a photoresist (not shown) over the conformal insulator layer 19, exposing the photoresist to a desired pattern of radiation (which defines the areas where the insulator strips 19A are to be formed) and developing the exposed photoresist utilizing a conventional resist developer. The pattern in the photoresist is then transferred to the conformal insulator layer 19 utilizing one or more wet and/or dry etching steps to form the one or more insulator strips 19A as shown in Figure 9A. When the surface protective layer 18 comprises a nitride and the conformal insulator layer comprises an oxide, a wet etching solution comprising hydrofluoric acid (HF) can preferably be used to selectively remove unmasked portions of the conformal insulator layer 19 and stop at the surface protective layer 18.
Figure 9B shows a cross-sectional view of one of the device regions 2 alone Line IV that extends through one of the insulator strips 19 A. The insulator strip 19A contains at least a horizontal portion that cover an upper surface of the device region 2 and at least a vertical portion that covers a sidewall of one of the isolation trenches 30, as shown in Figure 9B. The vertical portion of the insulator strip 19A therefore forms at least a vertical insulator pillar 22 that adheres to sidewalls of both the semiconductor device layer 16 and the base semiconductor substrate layer 12. Further, a portion of the vertical insulator pillar 22 extends into the recess between the semiconductor device layer 16 and the base semiconductor substrate layer 12 to form a ledge 24.
Figure 9C shows a cross-sectional view of the device region 2 alone Line V that extends through an area that is not covered by any insulator strip. The sidewalls of the semiconductor device layer 16, the sacrificial layer 13, and the base semiconductor substrate layer 12 are still exposed in this area, and the recess 32 between the semiconductor device layer 16 and the base semiconductor substrate layer 12 remains unfilled in this area.
Subsequently, an additional lateral etching step, which is similar to that described hereinabove, is carried out to selectively remove the entire sacrificial layer 13 through exposed isolation trench sidewalls that are not covered by the insulator strips 19A. Consequently, an air gap 15 is formed between the base semiconductor substrate layer 12 and the semiconductor device layer 16, as shown in Figure 1OA. In this manner, the semiconductor device layer 16 becomes "floating" above the base semiconductor substrate layer 12. Structural support for the floating semiconductor device layer 16 is provided by the vertical insulator pillar 22 and its ledge 24. Figure 1OB shows a three-dimensional (3D) side view of the base semiconductor substrate layer 12, the floating semiconductor device layer 16, the insulator strip 19A, and the vertical insulator pillar 22 with the ledge 24, and Figure 1OC shows a 3D elevated view of these structures.
After the additional lateral etching step, the air gap 15 between the base semiconductor substrate layer 12 and the semiconductor device layer 16 is filled with an insulator material to form a buried insulator layer 14, as shown in Figure 11. Any suitable insulator material, such as an oxide, nitride, or oxynitride, can be used for filling the air gap 15. Preferably, a high aspect ratio profile material commercialized by Applied Materials (Santa Clara, CA) under the trade name of HARP™ is used to fill the air gap 15 and form a continuous, homogeneous buried insulator layer 14. Alternatively, insulator materials of medium-to-low aspect ratio profiles can be used to form a buried insulator layer 14 with cavities therein. Further, the buried insulator layer 14 may comprise porous dielectric material(s) with micro- or nano-sized pores therein.
Next, the isolation trenches 30 are filled with a trench dielectric material to form trench isolations 20, and a planarization step such as chemical mechanical polishing (CMP) is then carried out to remove excess trench isolation material located outside of the trenches 30 and to remove the horizontal portion of the insulator strip 19A, thereby forming a SOI substrate structure 10 with a substantially planar upper surface, as shown in Figure 11.
Note that while Figures 2-11 illustratively demonstrate exemplary SOI substrates and processing steps that can be used for forming such exemplary SOI substrates according to specific embodiments of the present invention, it is clear that a person ordinarily skilled in the art can readily modify the substrate structures and processing steps for adaptation to specific application requirements, consistent with the above descriptions. For example, although the exemplary SOI substrates as shown in Figures 2-3 and 11 contain specific numbers of vertical insulator pillars arranged in specific manners, it is readily understood that the SOI substrates of the present invention may comprise any number of vertical insulator pillars arranged in any manner. For another example, although Figures 3-4 shows formation of a layered substrate structure 10 by first forming a n-doped semiconductor sacrificial layer 13 via surface dopant implantation, followed by formation of the semiconductor device layer 16 via epitaxial growth of semiconductor, it is understood that such a layered substrate structure 10 may also be formed by a single in-depth dopant implantation step, which forms the n-doped semiconductor sacrificial layer 13 at a predetermined depth in a bulk semiconductor substrate. In this manner, the portion of the bulk semiconductor substrate located underneath the layer 13 defines the base substrate layer 12, and the portion located above the layer 13 defines the semiconductor device layer 16. The subsequent epitaxial growth step is therefore not necessary.
Further, although Figures 2-3 and 11 show vertical insulator pillars with ledges, the vertical insulator pillars can also be provided without ledges in an alternative embodiment of the present invention. Figure 12 shows an SOI substrate 10 having contains substantially the same structural components as that shown by Figure 2, except that the vertical insulator pillars 22 in Figure 12 do not have any ledge.
Figures 13-16 illustrate exemplary processing steps for forming an SOI substrate structure with such ledge-less vertical insulating pillars, according to an alternative embodiment of the present invention.
Specifically, after patterning of the layered substrate structure 10, as shown in Figures 6A and 6B, a conformal insulator layer 19 is deposited over the entire structure without the lateral etching step as described hereinabove in Figure 7. In this manner, no recess is formed along sidewalls of the isolation trenches 30, and the conformal insulator layer 19 does not extend between the base semiconductor substrate layer 12 and the semiconductor device layer 16, as shown in Figure 13. The conformal insulator layer 19 is then patterned by conventional lithography and etching to form one or more insulator strips 19A over each device region 2, as shown in Figure 14A, similar to those descried hereinabove with reference to Figure 9A.
Figure 14B shows a cross-sectional view of one of the device regions 2 along Line VI that extends through one of the insulator strips 19 A. The insulator strip 19A contains at least a horizontal portion that cover an upper surface of the device region 2 and at least a vertical portion that cover a sidewall of one of the isolation trenches 30, as shown in Figure 14B. The vertical portion of the insulator strip 19A therefore forms at least a vertical insulator pillar 22 that adheres to sidewalls of both the semiconductor device layer 16 and the base semiconductor substrate layer 12. Note that no ledge is formed along the vertical insulator pillar 22, as shown in Figure 14 B.
Figure 14C shows a cross-sectional view of the device region 2 alone Line VII that extends through an area that is not covered by any insulator strip. The sidewalls of the semiconductor device layer 16, the sacrificial layer 13, and the base semiconductor substrate layer 12 remain exposed in this area.
Subsequently, a lateral etching step similar to that described hereinabove is carried out to selectively remove the entire sacrificial layer 13 through exposed isolation trench sidewalls that are not covered by the insulator strips 19A. Consequently, an air gap 15 is formed between the base semiconductor substrate layer 12 and the semiconductor device layer 16, as shown in Figure 15 A. In this manner, the semiconductor device layer 16 becomes "floating" above the base semiconductor substrate layer 12. Structural support for the floating semiconductor device layer 16 is provided by the ledge-less vertical insulator pillar 22. Figure 15B shows a three- dimensional (3D) side view of the base semiconductor substrate layer 12, the floating semiconductor device layer 16, the insulator strip 19A, and the ledge-less vertical insulator pillar 22, and Figure 1OC shows a 3D elevated view of these structures.
After the additional lateral etching step, the air gap 15 between the base semiconductor substrate layer 12 and the semiconductor device layer 16 is filled with an insulator material to form a buried insulator layer 14, and the isolation trenches 30 are filled with a trench dielectric material to form trench isolations 20. A CMP or other planarization step is carried out subsequently to remove excess trench isolation material located outside of the trenches 30 and to remove the horizontal portion of the insulator strip 19A, thereby forming a SOI substrate structure 10 with a substantially planar upper surface, as shown in Figure 16.
The SOI substrates of the present invention as described hereinabove provide true SOI configurations in the entire active device regions and therefore offer full advantages of SOI structures. Further, the methods for fabricating such SOI substrates do not require perfect alignment of the vertical insulator pillars. Therefore, the device performance is no longer affected by potential alignment errors.
In some embodiments, it is desirable to provide a SOI substrate with semiconductor device layers of different thicknesses in different device regions. Therefore, the present invention in a specific embodiment provides a SOI structure that comprises two or more device regions with semiconductor device layers of different thickness, as shown in Figure 17. Specifically, the SOI substrate 10 comprises three device regions 2, 4, and 6, which respectfully contain semiconductor device layers 16A, 16B, and 16C and buried insulator layers 14A, 14B, and 14C. As shown in Figure 17, the semiconductor device layers 16A and 16C have an average thickness (Ti) that is significantly larger than the average thickness (T2) of layer 16B. Correspondingly, the buried insulator layers 14A and 14C are located at a depth that is larger than that of layer 16B.
The SOI structure of Figure 17 can be readily formed by processing steps similar to those described hereinabove, except that a slightly different dopant implantation process will be used to form an unpatterned, layered substrate structure with a semiconductor device layer of varying thicknesses. In other words, the unpatterned, layered substrate structure contains an n-doped sacrificial semiconductor layer with different portions located at different depths of the substrate structure. Such an unpatterned, layered substrate structure can then be patterned to form two or more device regions with semiconductor device layers of different thicknesses. Figures 18-23 illustrate an exemplary dopant implantation process containing at least two dopant implantation steps for formation of an n-doped sacrificial semiconductor layer with at least two portions located at two different depths of a layered substrate structure.
Figure 18 shows a first masked dopant implantation step during which a first portion 13A of an n-doped sacrificial semiconductor layer is selectively formed over a first region of a base semiconductor substrate layer 12, while a second region of layer 12 is protected from the dopant implantation by a block mask 34.
The block mask 34 is removed after the first dopant implantation step, and epitaxial growth of semiconductor material is carried out, so that the first portion 13A of an n- doped sacrificial semiconductor layer is buried in the subsequently grown epitaxial semiconductor material, as shown in Figure 19.
Next, a second masked dopant implantation step is carried out, during which the first region of the base semiconductor substrate layer 12 containing the first portion 13 A of the n-doped sacrificial semiconductor layer is covered by another block mask 36, while a second portion 13B of the n-doped sacrificial semiconductor layer is formed over the second region of the base semiconductor substrate layer 12, as shown in Figure 20.
The block mask 36 is then removed after the second dopant implantation step, and epitaxial growth of semiconductor material is again carried out, so that the second portion 13B of the n-doped sacrificial semiconductor layer is also buried in epitaxial semiconductor material, as shown in Figure 21. The subsequently grown epitaxial semiconductor material formed over the first portion 13A of the n-doped sacrificial semiconductor layer constitute a first, thicker portion 16A of a semiconductor device layer, and the epitaxial semiconductor material formed over the second portion 13B of the n-doped sacrificial semiconductor layer constitute a second, thinner portion 16B of the semiconductor device layer. An optional surface protective layer 18 can be formed over both portions 16A and 16B of the semiconductor device layer, thereby forming an unpatterned layered substrate 10, which contains a semiconductor device layer with two different portions 16A and 16B of different thicknesses, as shown in Figure 22.
Such an unpatterned layered substrate 10 can then be patterned to form at least two different device regions 2 and 4 that are isolated from each other by an isolation trench 30 and contain two different semiconductor device layers 16A and 16B of different thicknesses (Ti and T2), as shown in Figure 23.
The unpatterned layered substrate 10 of Figure 22 can also be formed by a single dopant implantation step. Specifically, a bulk semiconductor substrate is first provided, followed by selectively masking of a portion of the bulk semiconductor substrate. The thickness of the masking layer is adjusted so that it only retards the dopant implantation (i.e., reducing the implantation depth by a predetermined amount) but not completely block the dopant implantation in the remaining unmasked portion of the bulk semiconductor substrate. In this manner, a single dopant implantation step can be carried out to form an n-doped semiconductor sacrificial layer with different portions located at different depths of the bulk semiconductor substrate.
In some embodiments, it is desirable to provide a SOI substrate with semiconductor device layers of different thicknesses in different device regions. Therefore, the present invention in a specific embodiment provides a SOI structure that comprises two or more device regions with semiconductor device layers of different thicknesses, as shown in Figure 17.
It has been recently discovered that a substrate with hybrid crystallographic orientation is particularly suitable for improving the device performance of complementary metal oxide semiconductor (CMOS) circuits. For example, electrons have a high mobility along the { 100} crystal planes of silicon, but holes have high mobility along the {110} crystal planes of silicon. On one hand, hole mobility values along the {100} planes are roughly about 2 to 4 times lower than the corresponding electron hole mobility values along such planes. On the other hand, hole mobility values along the {110} silicon surfaces are about 2 times higher than those along the { 100} silicon surfaces, but electron mobility along the {110} surfaces are significantly degraded compared to those along the { 100} surfaces. Therefore, the { 110} silicon surfaces are optimal for forming p-channel field effect transistor (p- FET) devices due to the excellent hole mobility along the {110} planes, which leads to higher drive currents in the p-FETs. However, such surfaces are completely inappropriate for forming n-channel field effect transistor (n-FET) devices. The { 100} silicon surfaces instead are optimal for forming n-FET devices due to the enhanced electron mobility along the { 100} planes, which results in higher drive currents in the n-FETs.
It is therefore desirable to provide a SOI substrate as described hereinabove but further with hybrid crystallographic orientations. Specifically, such a SOI substrate contains at least two device regions having semiconductor layers of different crystallographic orientations. When the semiconductor device layers in the at least two device regions comprise single crystal silicon, the different crystallographic orientations are preferably selected from the group consisting of <100>, <110>, and <111> orientations of silicon.
Figure 24 shows such an SOI substrate 10, which comprises device regions 2, 4, and 6. The base semiconductor substrate layer 12 in the SOI substrate 10 have first portions 12A of a first crystallographic orientation, which are located in device regions 2 and 6, and second portions 12B of a second, different crystallographic orientation located in device region 4. Correspondingly, the semiconductor device layer 12 in the SOI substrate 10 also comprises first portions 16A of the first crystallographic orientation located in device regions 2 and 6 and second portions 16B of the second, different crystallographic orientation located in device region 4.
The SOI structure of Figure 24 can be readily formed by processing steps similar to those described hereinabove, except that an unpatterned, layered substrate structure having a semiconductor device layer with different portions of different crystallographic orientations needs to be formed first, which can then be patterned to form two or more device regions with semiconductor device layers of different crystallographic orientations. Such an unpatterned, layered substrate structure can be readily formed using one or more wafer bonding, dopant implantation, amorphization implantation, recrystallization, and epitaxial growth steps.
Figures 25-30 illustrate an exemplary process for forming an unpatterned, layered substrate structure having a semiconductor device layer with different portions of different crystallographic orientations.
A base semiconductor substrate layer 12 is first formed by bonding a first semiconductor layer 12A of a first crystallographic orientation onto a second semiconductor layer 12B of a second, different crystallographic orientation by known wafer bonding techniques, as shown in Figure 25.
Next, a dopant implantation step is carried out to implant n-type dopant species onto an upper surface of the first semiconductor layer 12A to form an n-doped sacrificial semiconductor layer 13, as shown in Figure 26.
A masked amorphization implantation step is then carried out using block mask 38 to form at least one amorphous semiconductor region 40, which extends through the n- doped sacrificial semiconductor layer 13 and the first semiconductor layer 12A into the second semiconductor layer 12B, as shown in Figure 27. An upper portion of the amorphous semiconductor region 40 contains n-type dopant species that have been previously implanted.
Recrystallization of the amorphous semiconductor region 40 over the second base semiconductor layer 12B forms a recrystallized region that is an extension of layer 12B and therefore has the same crystallographic orientation as layer 12B (i.e., the second, different crystallographic orientation). An upper portion of the recrystallized region contains n-doped semiconductor of the second, different crystallographic orientation, as shown in Figure 28.
Subsequently, the block mask 40 is removed, and epitaxial growth of semiconductor is carried out to form a semiconductor device layer that contains first portions 16A grown over the first base semiconductor substrate layer 12A outside the recrystallized region 12B and a second portion 16B grown over the recrystallized region 12B. In this manner, the first portions 16A of the semiconductor device layer has the same crystallographic orientation as that of the first base semiconductor substrate layer 12A (i.e., the first crystallographic orientation), and the second portion 16B of the semiconductor device layer has the same crystallographic orientation as that of the recrystallized region 12B (i.e., the second, different crystallographic orientation), as shown in Figure 29.
An optional surface protective layer 18 can be formed over both portions 16A and 16B of the semiconductor device layer, thereby forming an unpatterned layered substrate 10, which contains a semiconductor device layer with two different portions 16A and 16B of different crystallographic orientations, as shown in Figure 29.
Such an unpatterned layered substrate 10 can then be patterned to form different device regions 2, 4, and 6 that are isolated from one another by isolation trenches 30 and contain semiconductor device layers 16A and 16B of different crystallographic orientations, as shown in Figure 30.
Note that although the above-described processing steps form the n-doped sacrificial semiconductor layer 13 before the amorphization and recrystallization steps, it is understood that the n-doped sacrificial semiconductor layer 13 can also be formed after the amorphization and recrystallization steps. Further, the n-doped sacrificial semiconductor layer 13 can be formed by in-depth dopant implantation after epitaxial growth of the semiconductor device layer.
When the above description illustrates specific embodiments of the present invention, it should be recognized that the present invention is not so limited, but rather extends in utility to any other modification, variation, application, and embodiment, and accordingly all such other modifications, variations, applications, and embodiments are to be regarded as being within the spirit and scope of the invention. INDUSTRIAL APPLICABILITY
This application finds utility in the field of semiconductor devices, and more particularly, in methods of fabricating improved semiconductor-on- insulator (SOI) substrates.

Claims

CLAIMSWhat is claimed is:
1. A method for forming a semiconductor-on-insulator (SOI) substrate (10), comprising: forming a substrate structure comprising at least a base semiconductor substrate layer (12) and a semiconductor device layer (16) with a sacrificial layer located therebetween; patterning the substrate structure to form one or more device regions (2, 4, 6) defined by one or more isolation trenches (30), wherein each device region (2, 4, 6) comprises a base semiconductor substrate layer (12) and a semiconductor device layer (16) with a sacrificial layer (13) located therebetween; forming one or more insulator strips (19A) each having at least a vertical portion over a sidewall of one of the isolation trenches (30) and a horizontal portion over an upper surface of one of the device regions (2, 4, 6); selectively removing the sacrificial layer (13) from each device region to form an air gap (15) between the base semiconductor substrate layer(12) and the semiconductor device layer (16), wherein the vertical portions of the one or more insulator strips (19A) form vertical insulator pillars (22) to support the semiconductor device layer (16); and filling the air gap (15) within each device region (16) with an insulator material to form a buried insulator layer (14) between the base semiconductor substrate layer (12) and the semiconductor device layer (16).
2. The method of claim 1, further comprising filling the isolation trenches with a trench dielectric material and planarizing the substrate structure to remove the horizontal portions of the insulator strips and to form a substantially planar upper surface.
3. The method of claim 1, wherein after patterning of the substrate structure and before formation of the insulator strips, lateral etching is carried out to selectively remove a peripheral portion of the sacrificial layer in each device region, so that the vertical portions of the subsequently formed patterned insulator strips comprise ledges that extend between the base semiconductor substrate layer and the semiconductor device layer at each device region.
4. The method of claim 1, wherein the semiconductor device layer of the unpatterned substrate structure has different portions of different thicknesses, and wherein patterning of the substrate structure thereby form at least two device regions with semiconductor device layers of different thicknesses.
5. The method of claim 4, wherein the sacrificial layer of the unpatterned substrate structure is an n-doped semiconductor layer comprising different portions located at different depths in the unpatterned substrate structure.
6. The method of claim 5, wherein two or more dopant implantation steps are carried out to form the n-doped semiconductor layer of the unpatterned substrate structure.
7. The method of claim 5, wherein a single dopant implantation step is carried out to form the n-doped semiconductor layer of the unpatterned substrate structure.
8. The method of claim 1, wherein the semiconductor device layer of the unpatterned substrate structure has different portions of different crystallographic orientations, and wherein patterning of the substrate structure form at least two device regions with semiconductor device layers of different crystallographic orientations.
9. The method of claim 8, wherein the unpatterned substrate structure is formed by a process comprising one or more steps selected from the group consisting of wafer bonding, dopant implantation, amorphization implantation, recrystallization, and epitaxial growth of semiconductor.
10. The method of claim 8, wherein the unpatterned substrate structure is formed by: forming a base semiconductor substrate layer by bonding a first semiconductor layer of a first crystallographic orientation onto a second semiconductor layer of a second, different crystallographic orientation; implanting an n-type dopant species into an upper surface of the first semiconductor layer to form an n-doped sacrificial semiconductor layer; performing masked amorphization implantation to form one or more amorphous semiconductor regions that extends through the n-doped sacrificial semiconductor layer and the first semiconductor layer into the second semiconductor layer; recrystallizing said one or more amorphous semiconductor regions to form a recrystallized region having the second, different crystallographic orientation; and epitaxially growing a semiconductor device layer over the n-doped sacrificial semiconductor layer, wherein a first portion of the semiconductor device layer located outside the recrystallized region has the first crystallographic orientation, and wherein a second portion of the semiconductor device layer located directly over the recrystallized region has the second, different crystallographic orientation.
11. The method of claim 8, wherein the unpatterned substrate structure is formed by: forming a base semiconductor substrate layer by bonding a first semiconductor layer of a first crystallographic orientation onto a second semiconductor layer of a second, different crystallographic orientation; performing masked amorphization implantation to form one or more amorphous semiconductor regions that extends through the first semiconductor layer into the second semiconductor layer; recrystallizing said one or more amorphous semiconductor regions to form a recrystallized region having the second, different crystallographic orientation; implanting an n-type dopant species into an upper surface of the base semiconductor substrate layer to form an n-doped sacrificial semiconductor layer; and epitaxially growing a semiconductor device layer over the n-doped sacrificial semiconductor layer, wherein a first portion of the semiconductor device layer located outside the recrystallized region has the first crystallographic orientation, and wherein a second portion of the semiconductor device layer located directly over the recrystallized region has the second, different crystallographic orientation.
12. The method of claim 1, wherein each of the one or more vertical insulating pillars comprises an insulator material selected from the group consisting of oxides, nitrides, and oxynitrides.
13. The method of claim 1, wherein each of the one or more vertical insulating pillars comprises an oxide material.
14. A semiconductor-on-insulator (SOI) substrate (10) comprising one or more device regions (2, 4, 6), each of which comprises at least a base semiconductor substrate layer (12) and a semiconductor device layer (16) with a buried insulator layer (14) located therebetween, wherein the semiconductor device layer of each device region (2, 4, 6) is supported by one or more vertical insulating pillars (22).
15. The SOI substrate of claim 14, wherein each of the one or more vertical insulating pillars comprises at least one ledge that extends between the semiconductor device layer and the base semiconductor substrate layer.
16. The SOI substrate of claim 14, wherein each of the one or more vertical insulating pillars comprises an insulator material selected from the group consisting of oxides, nitrides, and oxynitrides.
17. The SOI substrate of claim 14, wherein each of the one or more vertical insulating pillars comprises an oxide material.
18. The SOI substrate of claim 14, wherein said SOI substrate has a substantially planar upper surface.
19. The SOI substrate of claim 14, wherein the one or more device regions are isolated from one another by one or more trench isolation regions.
20. The SOI substrate of claim 14, comprising at least two device regions having semiconductor device layers of different thicknesses.
21. The SOI substrate of claim 14, comprising at least two device regions having semiconductor device layers of different crystallographic orientations.
22. The SOI substrate of claim 14, wherein the semiconductor device layers of said at least two device regions comprise single crystal silicon, and wherein the different crystallographic orientations are selected from the group consisting of <100>, <110>, and <111> orientations of silicon.
23. A precursor substrate structure (10) comprising at least one device region (2, 4, 6) having at least a base semiconductor substrate layer (12) and a semiconductor device layer (16) with an air gap (15) located therebetween, wherein the semiconductor device layer is supported by one or more vertical insulating pillars (22).
24. The precursor substrate structure of claim 23, wherein each of the one or more vertical insulating pillars comprises at least one ledge that extends between the semiconductor device layer and the base semiconductor substrate layer.
25. The precursor substrate structure of claim 23, wherein each of the one or more vertical insulating pillars comprises an insulator material selected from the group consisting of oxides, nitrides, and oxynitrides.
26. The precursor substrate structure of claim 23, wherein each of the one or more vertical insulating pillars comprises an oxide material.
27. The precursor substrate structure of claim 23, wherein the at least one device region further comprises a planarization stop layer located over the semiconductor device layer.
28. The precursor substrate structure of claim 23, comprising at least two device regions with semiconductor device layers of different thicknesses.
29. The precursor substrate structure of claim 23, comprising at least two device regions with semiconductor device layers of different crystallographic orientations.
PCT/US2007/069720 2006-05-25 2007-05-25 Formation of improved soi substrates using bulk semiconductor wafers WO2007140288A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP07797764.3A EP2024995B1 (en) 2006-05-25 2007-05-25 Formation of improved soi substrates using bulk semiconductor wafers
CN2007800189825A CN101454889B (en) 2006-05-25 2007-05-25 Formation of improved SOI substrate using bulk semiconductor wafer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/420,279 US7452784B2 (en) 2006-05-25 2006-05-25 Formation of improved SOI substrates using bulk semiconductor wafers
US11/420,279 2006-05-25

Publications (2)

Publication Number Publication Date
WO2007140288A2 true WO2007140288A2 (en) 2007-12-06
WO2007140288A3 WO2007140288A3 (en) 2008-04-24

Family

ID=38750048

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/069720 WO2007140288A2 (en) 2006-05-25 2007-05-25 Formation of improved soi substrates using bulk semiconductor wafers

Country Status (5)

Country Link
US (3) US7452784B2 (en)
EP (1) EP2024995B1 (en)
CN (1) CN101454889B (en)
TW (1) TWI437661B (en)
WO (1) WO2007140288A2 (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9368428B2 (en) * 2004-06-30 2016-06-14 Cree, Inc. Dielectric wafer level bonding with conductive feed-throughs for electrical connection and thermal management
US7465972B2 (en) 2005-01-21 2008-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. High performance CMOS device design
US7323392B2 (en) * 2006-03-28 2008-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. High performance transistor with a highly stressed channel
US7829429B1 (en) * 2007-09-18 2010-11-09 National Semiconductor Corporation Semiconductor device having localized insulated block in bulk substrate and related method
KR100996800B1 (en) * 2008-10-20 2010-11-25 주식회사 하이닉스반도체 Semiconductor device and manufacturing method thereof
US8395216B2 (en) * 2009-10-16 2013-03-12 Texas Instruments Incorporated Method for using hybrid orientation technology (HOT) in conjunction with selective epitaxy to form semiconductor devices with regions of different electron and hole mobilities and related apparatus
US8673703B2 (en) * 2009-11-17 2014-03-18 International Business Machines Corporation Fabrication of graphene nanoelectronic devices on SOI structures
CN102479740B (en) * 2010-11-25 2014-03-12 中芯国际集成电路制造(北京)有限公司 Deep trench isolating structure of phase change memory and manufacturing method thereof
US8647930B2 (en) * 2011-04-14 2014-02-11 Robert Bosch Gmbh Wafer with recessed plug
US8466070B2 (en) * 2011-06-02 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming semiconductor structures
JP5944149B2 (en) * 2011-12-05 2016-07-05 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US9839537B2 (en) 2012-03-07 2017-12-12 Abbott Cardiovascular Systems Inc. Bioresorbable polymer scaffold treatment of coronary and peripheral artery disease in diabetic patients
US9560765B2 (en) * 2013-12-06 2017-01-31 Infineon Technologies Dresden Gmbh Electronic device, a method for manufacturing an electronic device, and a method for operating an electronic device
US9263357B2 (en) 2013-12-06 2016-02-16 Infineon Technologies Dresden Gmbh Carrier with hollow chamber and support structure therein
US9613878B2 (en) 2013-12-06 2017-04-04 Infineon Technologies Dresden Gmbh Carrier and a method for processing a carrier
US9224858B1 (en) 2014-07-29 2015-12-29 Globalfoundries Inc. Lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a below source isolation region and a method of forming the LDMOSFET
US9755015B1 (en) * 2016-05-10 2017-09-05 Globalfoundries Inc. Air gaps formed by porous silicon removal
US10522390B1 (en) 2018-06-21 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Shallow trench isolation for integrated circuits
US11282781B2 (en) * 2019-07-22 2022-03-22 Nanya Technology Corporation Semiconductor device and method for fabricating the same
US11289330B2 (en) * 2019-09-30 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator (SOI) substrate and method for forming

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040235262A1 (en) 2003-05-20 2004-11-25 Sharp Laboratories Of America, Inc. Silicon-on-nothing fabrication process

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5490034A (en) 1989-01-13 1996-02-06 Kopin Corporation SOI actuators and microsensors
US5057450A (en) 1991-04-01 1991-10-15 International Business Machines Corporation Method for fabricating silicon-on-insulator structures
US5364800A (en) 1993-06-24 1994-11-15 Texas Instruments Incorporated Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate
EP0957515A1 (en) 1998-05-15 1999-11-17 STMicroelectronics S.r.l. Method for manufacturing an SOI wafer
FR2812764B1 (en) 2000-08-02 2003-01-24 St Microelectronics Sa METHOD FOR MANUFACTURING SUBSTRATE OF SUBSTRATE-SELF-INSULATION OR SUBSTRATE-ON-VACUUM AND DEVICE OBTAINED
US6887773B2 (en) 2002-06-19 2005-05-03 Luxtera, Inc. Methods of incorporating germanium within CMOS process
JP2004103613A (en) 2002-09-04 2004-04-02 Toshiba Corp Semiconductor device and its manufacturing method
KR20040038507A (en) 2002-11-01 2004-05-08 한국전자통신연구원 Semiconductor device having heat release structure using SOI substrate and method for fabricating the same
US6936522B2 (en) * 2003-06-26 2005-08-30 International Business Machines Corporation Selective silicon-on-insulator isolation structure and method
US7015147B2 (en) 2003-07-22 2006-03-21 Sharp Laboratories Of America, Inc. Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of Si1-xGex layer
US20050116290A1 (en) * 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
US7253034B2 (en) * 2004-07-29 2007-08-07 International Business Machines Corporation Dual SIMOX hybrid orientation technology (HOT) substrates
JP2006128428A (en) * 2004-10-29 2006-05-18 Seiko Epson Corp Semiconductor substrate, semiconductor device, manufacturing method of semiconductor substrate and manufacturing method of semiconductor device
US7235433B2 (en) * 2004-11-01 2007-06-26 Advanced Micro Devices, Inc. Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device
JP2006237455A (en) * 2005-02-28 2006-09-07 Toshiba Corp Semiconductor device and manufacturing method thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040235262A1 (en) 2003-05-20 2004-11-25 Sharp Laboratories Of America, Inc. Silicon-on-nothing fabrication process

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2024995A4

Also Published As

Publication number Publication date
EP2024995A4 (en) 2013-07-03
EP2024995A2 (en) 2009-02-18
CN101454889B (en) 2012-05-02
WO2007140288A3 (en) 2008-04-24
TW200818387A (en) 2008-04-16
US20070275537A1 (en) 2007-11-29
US7452784B2 (en) 2008-11-18
US20110147885A1 (en) 2011-06-23
US20090039461A1 (en) 2009-02-12
TWI437661B (en) 2014-05-11
EP2024995B1 (en) 2015-07-01
US7932158B2 (en) 2011-04-26
CN101454889A (en) 2009-06-10
US8268698B2 (en) 2012-09-18

Similar Documents

Publication Publication Date Title
US7452784B2 (en) Formation of improved SOI substrates using bulk semiconductor wafers
US9202864B2 (en) Integrated circuit having back gating, improved isolation and reduced well resistance and method to fabricate same
KR101124657B1 (en) Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device
US6972478B1 (en) Integrated circuit and method for its manufacture
US7687365B2 (en) CMOS structure for body ties in ultra-thin SOI (UTSOI) substrates
US10170475B2 (en) Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
US20030136985A1 (en) Field effect transistor structure with partially isolated source/drain junctions and methods of making same
US10038075B2 (en) Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region
US20060231893A1 (en) Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement
US7544548B2 (en) Trench liner for DSO integration
US8466496B2 (en) Selective partial gate stack for improved device isolation
EP2641271A1 (en) STRUCTURE AND METHOD FOR Vt TUNING AND SHORT CHANNEL CONTROL WITH HIGH K/METAL GATE MOSFETs
WO2007020287A1 (en) Dual trench isolation for cmos with hybrid orientations
US7834425B2 (en) Hybrid orientation SOI substrates, and method for forming the same
US9064972B2 (en) Method of forming a gated diode structure for eliminating RIE damage from cap removal
US9269710B2 (en) Semiconductor devices having stressor regions and related fabrication methods
US20080274594A1 (en) Step height reduction between SOI and EPI for DSO and BOS integration
US9397233B2 (en) High voltage deep trench capacitor
US7432174B1 (en) Methods for fabricating semiconductor substrates with silicon regions having differential crystallographic orientations
JP2003142694A (en) Method of element isolation of soi device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200780018982.5

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07797764

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2007797764

Country of ref document: EP